III III
2.8-GHz prescaler keeps cost down
Neil Eaton, Emsys Engineering, Peterborough, ON, Canada
H E PRESCALER in Figure 1 inexpen- these frequencies, but the submultiple is the B input. IC 3 and IC s both connect to
T sively extends the range of a fre-
quency counter by dividing the input
signal's frequency by a factor of 1000. The
inconvenient for an operator. A further
division by a factor of7,8125 (10001128)
produces a scaling factor of 1000.
the output of IC 2, so they count output
pulses, not prescaler pulses. IC s divides
the output by five to generate the divide-
guaranteed input -frequency range of the Fortunately, the frequency counter av- by-seven periods. IC 4 divides the output
input prescaler, leI' is 250 MHz to 2.8 erages its input over many cycles, so the by 16to reset the cycle upon completion.
GHz, although typical values are 100 output of the prescaler need not be ex- Without IC4 , the cycle would continue to
MHz to 3.5 GHz. The prototype operates actly 1/ 1000 of the input frequency for every divide by seven at every fifth output pulse
at frequencies well below 100 MHz, but input pulse, The 0,8125 figure is 13 di- for a ratio of7.8. The construction ofthe
its fastest generator goes only to 1.7 GHz, vided by 16. The average frequency ratio circuitry inside the dashed lines in Figure
so you cannot confirm the upper range. is therefore 7.8125 if you divide 13 out- 1 is critical. The MC 12079 is available
The input-voltage range is 400 to 1000 put pulses of 16 by eight and the re- only as a surface-mount device. In the de-
mV p-p from 250 to 500 MHz and 100 maining three by seven. For best results, sign, it and its associated passive compo-
to 1000 mV p-p for higher than 500 the divide-by-seven pulses should be as nents is mounted on a Surfboard (Capi-
MHz. IC I serves as a divide-by-128 evenly spaced as possible. The result is a tal Advanced Technologies Model 9081,
prescaler, whose output is a 1.6V p-p repeating sequence 16output pulses long available from Digikey). It is then fas-
square wave. The RC network level-shifts with the following pattern: tened, component side up, to a bare cop-
the output ofIC I to ensure that the top of
the square wave is above the 2V input Pulse number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
threshold ofIC SA' The output ofIC SA is a Divide by 8 8 8 8 7 8 8 8 8 7 8 8 8 8 7 8
5V;CMOS-compatible square wave with
a frequency of 1/ 128 of the input frequen- IC 2 divides the prescaler's output by per-clad board to create a ground plane.
cy. Most frequency counters can handle seven or eight, depending on the state of All connections to ground from the high-
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Extend your frequency-measurement capability withthis inexpensive divide-by-l000 prescaler.
146 EDN I JULY 20, 2000 W1VW.ednmag.com
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