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EC3058D-VLSI Circuits and Systems Winter Semester-2020-21

This document contains 9 problems related to VLSI circuits and systems. Problem 1 asks to calculate the Elmore delay through an RC tree. Problem 2 involves analyzing a CMOS logic circuit layout including obtaining the stick diagram and logic function. Problem 3 asks to design a complementary CMOS logic circuit and draw its stick diagram. The remaining problems involve additional circuit analysis, design and optimization tasks such as calculating logical effort, designing an SRAM cell, analyzing delays, and optimizing a transmission gate network.

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81 views2 pages

EC3058D-VLSI Circuits and Systems Winter Semester-2020-21

This document contains 9 problems related to VLSI circuits and systems. Problem 1 asks to calculate the Elmore delay through an RC tree. Problem 2 involves analyzing a CMOS logic circuit layout including obtaining the stick diagram and logic function. Problem 3 asks to design a complementary CMOS logic circuit and draw its stick diagram. The remaining problems involve additional circuit analysis, design and optimization tasks such as calculating logical effort, designing an SRAM cell, analyzing delays, and optimizing a transmission gate network.

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Gamer Anonymous
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EC3058D-VLSI Circuits and Systems

Winter Semester-2020-21
Problem Sheet-2

1. For the RC tree given in Figure calculate the Elmore delay from node A to node B using the values for the
resistors and capacitors given in the below in Table

i 1 2 3 4 5 6 7 8
Ri (Ω) 0.25 0.25 0.5 100 0.25 0.75 0.75 1000
Ci (pF ) 250 750 250 250 1000 250 500 250
2. Consider the CMOS layout of a logic circuit shown in the figure.
(a) Obtain the corresponding stick diagram.
(b) Identity the logic function Y realized.
(c) Obtain the corresponding schematic diagram.
(d) Size the transistors for obtaining the worst case delays same as that of a 2:1 inverter (Assume extrinsic
load capacitance is dominant).

3. Draw the circuit realization of the logic function F = (A + B).(C + D).E in complemenary CMOS logic
style. Using the method of Euler path, draw the stick diagram for an optimum layout of the circuit.

4. For the circuit shown

(a) Identify the logic function F. Explain its working


(b) Find the rising logical effort (gu ), falling logical effort (gd ) and average logical effort (gavg ).

5. (a) Design a 6T SRAM cell, with cell ratio (CR)=1.5 and pull-up ratio (PR)=1.5. Take (W/L) of the
access transistors to be unity.

1
(b) If VDD = 2.5V , VDSAT n = |VDSAT p | = 0.6V , VT n = |VT p | = 0.4V , find the switching threshold of
inverter(s) in the cell, when the access transistors are off. Take µn = 2µp .
6. Consider the circuit in the figure shown. Let VDD = 2.5V , Cx = 50f F , Mr has W/L = 1, Mn has
W/L = 1.5 Assume the transistors are of 0.25µm CMOS technology with γ = 0 and the output inverter
doesn’t switch until its input equals VDD /2. How long will it take Mn to pull down node x from 2.5 V to
1.25 V if Vin is at 0V and B is at 2.5V ? Hint: Use average current method

7. (a) Realize a three input NOR gate with minimum number of NMOS transistors (only).
(b) Find the value of VOL (approximate) corresponding to A = B = C = 1 if all the transistors are
identical with the following parameters: velocity saturation voltage VDSAT n = 0.6V , VT n = 0.4V and
kn = 120µAV −2 . Neglect channel length modulation and body bias effects. Take VDD = 2.5V
(c) Is the static power dissipation of the logic gate zero? If or if not why?
8. Consider the above circuit. Assume the inverter switches ideally at VDD /2, neglect body effect, channel
length modulation and all parasitic capacitance throughout this problem.
(a) What is the logic function performed by this circuit?
(b) Explain why this circuit has non-zero static dissipation.
(c) Implement the same circuit using transmission gates.
(d) Replace the pass-transistor network in figure with a pass transistor network that computes the fol-
lowing function: x = ABC at the node x. Assume you have the true and complementary versions of
the three inputs A,B and C.

9. Suppose the delay due to a series connection of n transmission gates is intolerable for a real time application.
In order to reduce delay of the network it is decided to insert buffers after every m transmission gates.
What should be the optimum value of m so that net delay is minimum if PMOS has kp = −30µAV −2 and
Vtp = −0.4V ? Assume delay due to a buffer is 10ps, the capacitance at each node of transmission gate
stack is 10f F , VOL = 0V and VOH = 2.5V for each transmission gate.

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