muh ge eet ee OR AND aah Kor are Che basic ame 1 o perabeors Oot ~ MoT gete has Orulys one ape aud) one onebpr - - FL performs a basic legc Sunchans callads eiuerseen'_ cy Gmplemueilatrens . beget Syubl tawlly table A WR 7 cpt Poet [inet [Dna | ots @_AND gel 7 rfoomB lop LL murttep leaker Sale ue has 0 01 Proeel pn auch one oulpet , bee lege ay C Toully tal ; fp ye 5 Dew AQ | Y=738 =AB 5 8 a ‘ole : ow of Me 0 oxput “ei ‘0! | abprl l Glows be xer0 » | ° oO o a 5 »y = eee = op. gate hus too or mune oe ee ~ SH poroms Legialy ateicon A poullls (able | outpal Sep bye re : ° ( { I loge Symbol Oniwr8el Gules NAN D auds Mor, ae toep poprelar logec’ gales becouse. ~— hase o unre Sal —huneleon? of Gan be wall 4o construct am BND de , OR , @ ALOT e. 02 ombcwlerns of Lere Surclong -Geue trud fob R Gee ae kwon as ‘suwrorGaly gales’ @NandD gee ") The tom mond wv a wxloarton of qeot- PND awk orapluis am PND Susatrors Bho am — Inewrlest Caco) outpul - = tle oporaleeri oS Css gece mn be omaty rad, , tary an eq aducl cevenid ab Grown w ep)» Se followed b jouw] cohas her am OND gete Po Chon)= Sf Ce viputs are A aul B, Cum tlie ovtprd ot PND goles 9-8 anny Compleat od Mat as PB=ARe® Cas Pet De-rmorpaais bn) Cqpe wont wreak Eyabol mote: om x pd ‘0’ outpat o1")@uee gee ~ The loos MR vo conrboarbans oS MOr-oR, | bud inphits oi of funcleen’ cothhy am ft werled, Chor) outa ~ the operabeen’ of uy ied vs on qu vebouc arcu Blown wi has So op Fellas by om ‘werden Oso) He eps oe 9 fad B, Gum We ontprt of op gee & P18, aud, Grapher of Gs j Bra = AB D 5 Oherhe @ Pee @wz @s—p>—_J re 3 55 AB px -OR gple C Exdlucue oR- GATE) - RX- OR operates a nol w basce operaticers : - $l wm be perfeomeds by Weng ethos bode 01 wanda, d J ratte fable ee A Dre | loge GynrbolD> | a Gantal a lll Y=@tne) Cres) = CAt8®) + CBenD > (Rie) + FP fr caeay] t fe C8] => ABPAB?+5B1B5 i tom et ae 52d e/a mm OO| oS : 6 [ater] —_— x= [pete + [sr Gm] _ SSS] 1" arGrad +(e Gra) a fp ecersa) r [er Che) - fF. civm) + [ oem) = [® Crea) + (a Crea] = AAtAGt ABH BB Pec BB=0 = Berns ——— AdConbornalleamale logec cht WY loge’ eeoeucl3 foo oe Bysloves i he Combemalcdral 03 Seq urrrbe'el, ~ tle oulpal of & Conberrateonal arcu Ceperals on ets Pocwal wsprls ouly — cmbimatemal (ertuid ontds of op uarcables , ogee gee ond oubprch rraneables . - Legual gates aueept Sagucls Toon Ge oprl andl qewrte Ggrals lo (he outprd - am Cf & - how 8 bbe andicatanals cenit «the tnt incl bean Qancables Cows ~fonv ov orlernal Gourer and, edlernal ave Oudpreh waocablis gato wv OO eye [ee wile i [ght [| sats Fp: blocs ar ed Guboaleonal- okt - = POY an onpucl uascth le, Care one 2 posse concinatcans of brian) pat ee St Guuolees Ce berg Bkps ed© preblew & Blaled, _ © the ww: of auaskbe wniprel uareabtes vel rogpesreal oft warechles & delesmuedd- © the mprel anc 2 aypbols meped weds ow OQ" G) the Conble table Wat deleammes the Tepurreds ailateowGlep bebreen ospuds ond oukpuls oi danced © the Srmptereeds boolean funtion’ bo casks ovbpusl gb obtrunud » © te Goa eter & drawn - Addoog : Dgstel Qmpuless porforre & wenartys of evsfypnesre ocmngy [asics - | the wnrost bascé avcQuwele’ oper alan vw Ge addvtem of teoo besa’ ignls - - Semple addi been ot of 4 posscble, operateen's , eet ord =O etre | peo =f ltt = (0 AL ebker _*P tet pAdes fio & aw 00 benary tpuls Cire Gury beds) als (Cy ond B) ands poeduers benabenals ctak cocll I impala auc too pay ou _ ft adds Ce, co wwp Bug) amc Gong Ce? bobs ° taubly table of pubs A ~9-090 O © l —L Blocee Pegrera outputs P Hatt Sum g) we? | 6 fea) — omy Cea S=hB+AG = AOS Gerry C0) = AB —<——.ogee daagaovens oS Mat-f adder cht 4 » A@ 8B 8 Bun (3) ) AB Grp CCD p © ! a B = parns o| « |O 0p ctabS Bs NAND ye > d A. A-AB = (8-55) (a 73) = 6 43) +6 na? =pChrs) t OC At) = pet As ——_ Catt Addex (HB) Vv ALOR ger$= ABS > | = AOpAArnGIaa = ACAI) BCATB) = (58) Cara) = ea) + CAP BD + Gra Car = Gra) CRra) Fu Adder ee = Grp Cate) ~ JLo a combenaerrial craud Cred =— adels teco beg and w coy awd outpacls a Guro bee andy @ Corry bb _ fur ctor Casts Ue. bels A oud 8 ands Cle erm, Foowo Cn prowicus column Cited, Ge Goo om CCin) be / andy ovkpuls Gum bet CGE)amd, Ge cory Bid eattedd Ce Gay Ow C Cont) ° Secs cable B gee Ge ualue of LOB of Ce Towtls tbe . Bum\ G &C a (c)= ABP AE e BC = AB -— AC = PBC p ARCS A8C FHBC = 8 c(AGrha) =ABrC (A@B)v Legee Pragran of shut 2 Actor Cet q oe |g ee - [ Laos cron Canmoy O47 | c (4) +g G WU FA coceid aa BND logee Agere B@B = ACAD 8CAB) =AGERALHB Be =ACAtB) teCAra)ifHalt Orbboactor Cus) - flO @ comberebarial cet Cat Eublvacls ome hee foom the blur ouch proctures Mie, Beiffonone « Torutls table Blocks deagnono n a deh tt, Esai g |__ ' dH = AOB borrow == 4B ] :8a) BB aeff= PO BH bortow = |G B+ CAPD Y CdcHoteue) = x ee ae x = [ps carm)+ [e+ Gre] ere eee ra Y= Cae Gas} + (8 Gr59]}. Cat i) = ARAtHBéoe yd FB os — Be has Re. = WB aChED np han Gad-v, outpet of Ahremm om oy he ee ACARD) CBCRB)) ACB) t BCABD = A CAB) + BCA) = ABtBA = AOS Gp nny xe = bi® AGBborrow Conctpret of GP MOND gl?ag % x5 = (x, (acre) —O %y = bez Bi —@ *2 = Gays; Sublctete yn@ egn@®> ty = (park; « bi boas eh = 04h; + BF —@ S Substiide vy O % = @4) C BC AB) = G@ab rb + & Cha) > @ a) bit hi # 8CAB) = COD bbb) + BCHB) = POs bith; + Fe = COB xT + aS = COE aby 2h6[HTT sfese —, yii-o es ABB Dbj- 4Bsya Siemens 2 pte Gop ots - InGlead of a fox Gu nap out Soom carl, . Poeuious Glage {We Com mMUn Re Cue, dels bp o gy a dinoclly, cody a» roo Moree, cuncesté ~ Peret woo coitd defer tooo Sunclons © Gowrebe Luncheon , Gr Gy Pocduers 1 lun Gere mul be @ ary sfeom peBiles i Ce’ when Ay awl By arc both) Rial OF B=), beck mot bolts)bets Maurin x teas Ch, = Git pier Ci= Got Po Coe Gi tp)c) @ = Git p, Cot Polo) = Git pi Got PyPoG Gat PC, Go tP2 (Git Pi Gto t o &) of predudls , i £ cokest a cp = Git Ps Cr= Got pole ane = lt la” = Ofixo=0 U er Gy = Gat P3e3 = OF /x) 1.0.8 | =y “Y AzA, A, Ao Bs Ba 8, BoA bel asteler coolly aarp lots alend -15 BINARY PARALLEL ADDER ‘inary parallel adder is a digital circuit that adds two binary numbers in parallel form and snluces the arithmetic sum of those numbers in parallel form, It consists of full adders connected ‘tachain, with the output carry from each full-adder connected to the input carry of the next full- tke in the chain, Figure 7.20 shows the interconnection of four full-adder (FA) circuits to provide a 4-bit | adder. The augend bits of A and addend bits of B are designated by subscript numbers Sonright to left, with subscript 1 denoting the lower-order bit. The carries are connected in a ia iough the full-adders. The input carry to the adder is C,, and the output carry is C,. The S ‘Qus generate the required sum bits. When the 4-bit full-adder circuit is enclosed within an IC thas four terminals for the augend bits, four terminals for the addend bits, four terminals ior & Sy Ss Ss: Figure 7.20 Logic diagram of a 4-bit binary parallel adder.1 err OP EE iba slab an havea)COMBINATIONAL LOGIC DESIGN 299 ABCD aulder citcuit must be able to opera ye ceil MUST e able to do the folowing 1. Add two 4-bit BCD code groups, using straight binary add 2, Determine, ifthe sum of this addition is greater the yon (decimal 6) to this sum and gene a ewe BCD ae, TetbY Using a4-bit binary parallel adder such as the T4LSB3 IC. Ce Treaty cee SOUPSAsA,A,A, and B,B,B,B, ae aplied to ait parallel pide adder will output SS, where S, is actually C,, the carry-out of the MSB bits The sum output S,8,8,8,S, can range anywhere from 00000 to 10010 (when both the BCD gs Tous are 1001 = 9). The circuitry for a BCD adder must include the logic needed to detect o that the ‘correction can be added in, Those cases, where ‘ceordance with the above steps, In other n , han 1001 (decimal 9); if itis, add 0110 Ye @ carry to the next decimal position. ger the sum is greater than 01001, Gesmis greater than 1001 are listed in Table 7.1 * a HHH ccocec] ece--e Woo IH oo--oo-+ __Letus define a logic output X that will go HIGH only when the sum is greater than 01001 for the cases in Table 7.1). If we examine these cases, we see that X will be HIGH for either of (sum greater than 15) __2 Whenever $, = 1 and either S, or S, or both are 1 (sums 10 to 15) __ This condition can be expressed as ip X=S, 45,5, +S) X = 1, it is necessary to add the correction factor 0110 to the sum bits, and to igure 7.28 shows the complete circuitry for a BCD adder, including the logic n for X.300 FUNDAMENTALS OF DIGITAL CIRCUITS second BCD adder, the carry-out of the second BCD adder is connected as the ¢; BCD adder and so on. ATY-in of yy 8, 8 5 8, thing next BCD adder — 4-bit parallel adder (74LS83) hs ° Correction adder Figure 7.28 Logic diagram of a BCD adder using two 4-bit adders and a correction-detector circuit.116 CODE CONVERTERS qhe availability of a large variety of codes for the same discrete elements of information results in sheuse of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two gjstems if each uses different codes for the same information. Thus a code converter is a logic circuit whose inputs are bit patterns representing numbers (or characters) in one code and whose outputs are the corresponding representations in a different code. It makes two systems compatible even though each uses a different binary code. Code converters are usually multiple output circuits. Toconvert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates. For example, a binary-to-Gray code converter has four binary input lines B,, B,, B,, and B,, and four Gray code output lines G,, G,, G,, and G,. When the input is 0010, for instance, the output should be 0011 and so forth. To design a code converter, we use a code table treating it as a tnuth table to express each output as a Boolean algebraic function of all the inputs. In this example of binary-to-gray code conversion, we can treat the binary to the Gray code lables four truth tables to derive expressions for G,, Gy, G,, and G, . Each of these four expressions Would, in general, contain all the four input variables B,, B,, B,, and B,. Thus, this code converter 'sactually equivalent to four logic circuits, one for each of the truth tables. The logic expressions derived for the code converter can be simplified using the usual ‘schniques, including ‘don’t cares’ if present. Even if the input is an unweighted code, the same cell Numbering method which we used earlier can be used, but the cell numbers must correspond ‘0 the input combinations as if they were an 8-4-2-1 weighted code. For example, in Excess-3 to Conversion, number ABCD = 0110, which represents 3,, is assigned the cell number 6 and "tthe cell number 3. Be careful to determine which input combinations, if any, will never occur can be treated as don’t cares. Of course, it is the input bit patterns, and not the output bit Patterns that determine don’t cares. came erated circuits (ICs) are available to convert data from one form to another. Binary-to-BCD. a TSions are most often encountered in connection with computer applications. Numerical data mitted in BCD form from input devices must be converted to binary, so that arithmetic306 FUNDAMENTALS OF DIGITAL ciRCUITS operations can be performed on it, The binary aes cD for transmission to output devices. Therel the major components ofthe computer system iS°" TT tables may be stored in the ROM. In some systen itself, through execution of a specially designes Dl en opposed to the hardware conversion performed by log! Gray Code Converter ster circuit is a 4-bit binary and the output is a sof 4-bit binary input and all of them are vali ponding Gray code are shown in the conversion serve that the expressions for the outputs ts of arithmetic operations must be converted ,, * conversions are often accomplished by ysing her than special converter circuits. Conversion versions are accomplished by the computey fam. This is called software conversion, a, 7.16.1. Design of a 4-bit Binary-to~ The input to the 4-bit binary-to-Gray code conve 4-bit Gray code. There are 16 possible combination: Hence no don’t cares. The 4-bit binary and the corres} table (Figure 7.32a). From the conversion table, we obs y Gy, Gy, and G, are as follows: G,= E48, 9, 10, 11, 12, 13, 14, 15) G,=Em64, 5, 6, 7, 8, 9, 10, 11) G,=Em(2, 3, 4, 5, 10, 11, 12, 13) G,=Em(1, 2,5, 6, 9, 10, 13, 14) ‘The K-maps for G,, G,, G,, and G, and their minimization are shown in Figure 7.32b, The minimal expressions for the outputs obtained from the K-map are: G, B, G,=B,B, +B,B, =B, ®B, G= B. B, + BB, =B,@B, G,=B,B, +B,B, =B, ®B, ‘2 viet Bs paises ‘can be achieved by using three X-OR gates as shown in the logic diagram 4-bit binary #olGray Cua ET ML aa acer 5% BB G&G GG 00 0 0 oo Dat rns 00 10 is 4D tasleinad Oe ela abel ceed 10 meet eh fol! ig Tp (det bad) OW His” Lomi iba Fone ial et gt ted Oc tke lade Daas oo NM ot Hovedg> ie Cre at Oia Ojo Naish stmetont0; tu tl ald 9 ea 1 teeter) rae ee slop Dcultboinos peltuig pe o Lode anoatoprd (a) Conversion table Fi ir 'gure 7-92 4-bit binary-to-Gray code converter (Contd,)COMBINATIONAL LOGIC DESIGN 307 | a of ie 10 L1} Li} ) D-6 G,=B, 2B G,=B.28, Kemap for Ge (kee | OTRREEG eae Figure 7.32. 4-bit binary-to-Gray code converter. 1182. Design of a 4-bit Gray-to-Binary Code Converter The input tothe 4-bit Gray-to-binary code converter circuit is a 4-bit Gray code and the output is ‘tit binary, There are 16 possible combinations of 4-bit Gray input and all of them are valid. ee no don't cares, The 4-bit input Gray code and the corresponding output binary numbers are ‘town in the conversion table of Figure 7.332. From the conversion table we observe that the “pressions for the outputs B,, B,, B, and B, are: B,=EZm(12, 13, 15, 14, 10, 11, 9,8) == m0B, 9, 10, 11, 12, 13, 14, 15) B,=Em(6,7,5, 4, 10, 11, 9,8) = m(4, 5, 6, 7,8, 9, 10, 11) B,=Em(3, 2, 5,4, 15, 14,9, 8)= 2 m(2, 3,4, 5, 8,9, 14, 15) B,=EZm(1, 2,7, 4, 13, 14, 11, 8)=2mU1, 2,4, 7,8 11, 13, 14) Drawing the K-maps for By, By, By and B, in terms of G,, Gy, Gy and G, as shown in we 7.335 and simplifying them, the minimal expressions for the outputs are as follows: = G, 3=G,6,+6,G,=G,®G, 3.6.6.6, +6,6,G, + 6,6,6, + 6,6, =G,G, 8 G,) + G(G, @G,) = 6, ® G; ® Ga = Bs @ Ge 3,=G,6,6,6, +6,G,6,G, +G,6,6,6, +G,6,6,6,+6,G,6,6, ___ +G,G,G,G, + G,G,G,G,+ G,G,6,G,308 FUNDAMENTALS OF DIGITAL CIRCUITS G(G OG,) + GGG OG) @G,) + 6,G,G, ® 5) + Od =G6,6,G, eecr ‘ =(G,86,\G, ®G;) + (Gr GG, NG, ® G3) G, ©G,®G, ®G, =B, OG, cae a logic circuit can be drawn as shown in Figure 7.33, Based on the above expressions, _eerGay & 6 G&G 8 % Be B 0.00 0 0 0 0 0 0007 09 0 Of eee gh a 0 ee ee oo 7 1 G,—»——_ & o 140 0 1 0 O idee ex eee eee Ome )tea0b eat Ly 010 t 0 1 1 0 By 0100 01% 18 Gs sialon Obeaestee 01100 + 40% 4001 + 41 4 4 0 1 0 8, + 410 4 01 1 Ge + 0 10 41 0 0 7 + 004 417 1 0 8, Hee vet ons MMe ee REET EEE &, (@) Conversion fable (6) Logic diagram GG, GG; GAX_0 oft 10 GeX_0__01_11_10 7—] 3a] Weel asooa | 00 ya 3-79 gu Ce a aa 9 a " 33} 7] Fg calla | —3| 7} 9 ttt to Ga a 4) B.=G, * =G, 06. K-map fc pen aGs G6, uP EBs K-map for By G,GX_00_o1 es 77 Gev_%0 01 11_ 10 09] 73a 00] i 1 0 yy of A a a 7 id or o/ Co 7 z 7 wat tat 8, =G,@G6,6G, ni K-map for By G,86,26, 26, (©) K-maps Kmap for B, Figure 7.33 4-bit Gray-to-binary code convertera COMBINATIONAL LOGIC DESIGN 309 pesign of a 4-bit Binary-to-BCD Code Converter a 4bit binary. There are 16 possible digits). the output has to be an 8-bit one; but since een ot il allbea 9 mbinations of inputs the output can be treated as a bit one The eo pesca ie i ble in Figure 7.34a, From the conversion table, we ier eee for? conversion tal i ouput ate 38 follows; ft A=Em(10, 11, 12, 13, 14, 15) B=Em@,9) C=EmG, 5, 6,7, 14, 15) D=Em(2, 3,6, 7, 12, 13) E=m(1, 3,5, 7,9, 11, 13, 15) prawing the K-maps for the outputs and minimizing them as shown in Figure 7.34c the al expressions for the BCD outputs A, B,C, D, and E in terms of the 4-bit binary inputs By dB, are as follows: A=B,B,+B,B, B=B,B,B, | C=B,B,+B,B, D=B,B,B, + B,B, E=B, logic diagram can be drawn based on the above minimal expressions. sisi ByBy amt ‘4-bit binary BCD output. Decimal 5p, BB, A B CODE jsaq4107 070K OF gO ,10,,'0).0110 1 Dy 07 0 face mgs, On 1 it JOO at OF, 4 0m OL Ot (0. ght vattigne oC 48 Al itroY OF OTT ft Aso iog 0 gies Oss Otaueen (ORs esti on? Be Ones eo 50. t 6 0, chs i Occ On Ob bs 2 7 0 S138 aie 1 opto stat 8 4+ \Oig OW Os eOlmnt 40x 0'7O 9 jade Darth gig Cute Oke. | 10 nt TOP rove eon OO i TEOMA fMFOHTO® OF 1 3 2 1 100 it : ‘alee eaPoaioaetmegero ts: 4 SOP circuit c 4 te, fe aOR 1 0150 e 15 1 (dual dats Oo1 5 (0) Block diagram (a) Conversion table Figure 7.34 4-bit binary-to-BCD code converter (Contd.)‘ALS OF DIGITAL CIRCUITS 8,8, BB, Mee. pou mo Ot 10) BN OO Ott eee easier ol | a 00 clean a on of Ot Tey vata 2} —73]] 9 1 "1 fal =o ag |e ai} a 10| [4] 10 A=B,B, + B,B, B=8,8,8, C=B,B,+8,8, K-map for A K-map for B K-map for C 8.8, BB, BB\_0 or 1110 BB\_00 or 11 __ 10 eae geal a 00 1/7 00 ce rs 7 a on i|4 ot 1 a] 5a ce ie " +i 4 oa ee aA 99 po 10 1] 4 D=8,8,8,+5,8, E=8, KemapferD 6 kcanaps Kemap for E Figure 7.34 4-bit binary-to-BCD code converter,7.18 COMPARATORS A comparator is a logic circuit used to compare the magnitudes of two binary numbers. Depending on the design, it may either simply provide an output that is active (goes HIGH for example) whe the two numbers are equal, or additionally provide outputs that signify which of the numbers greater when equality does not hold. The X-NOR gate (coincidence gate) is a basic comparator, because its output is a1 only ii ‘wo input bits are equal, ie. the output is 1 iff and only if the input bits coincide.COMBINATIONAL LOGIC DESIGN 327 binary numbers are e F nots eee cual ifand only if all their corresponding bits coincide. For example, woe aN A By This, fs uo and BBB By are equal, if and only if, A, = B,, A. . 428, and Ag= Bo, Ths, equality hols when A, coincides with B,, A, coincides with B,, A, Ades with Band Ay coincides with B,, The implementation of this logic ee EQUALITY = (A, © : / B (As OBA, OBA, OB, (A, OB,) sraightforward. It is obvious that this cieuite a 5s areata a can be expanded or compressed to accommodate ‘The block diagram of a 1-bit comparator which c: fc f target numbers is shown in Figure 7.5 is which can be used as a module for comparison of L E 6 Figure 7.55 Block diagram of a 1-bit comparator, A bit ‘comparator B Magnitude Comparator 718.1 1-1 ‘The logic for a 1-bit magnitude comparator: Let the 1-bit numbers be A= A, and B= By. IfA,= 1 and By = 0, then A> B Therefore, A>B:G= IfA)=0 and By= 1, then A 7 a eee Oi? Oe pate Beato) Diet 1 0 0 acy Onl AOE? oR } at Rel tes eae > (a) Truth table (b) Logic diagram Figure 7.56 1-bit comparator.-Latthe wo 2-bitmumbers BEA=A,Ay and Bp, 9 0, then A> B. So the logic expression for AB , Bor = Land By ee B:G=A,B, + (A; OB) AB =OandB,=1.thenA B(G) Ao: By A B, A=B(E) Ay By A B. Or 2. IfA, and B, coincide, and if A, = 1 and By = 0, then A>B. Or tt ecm aE ttt AR RhaGee 2 3 and B, coincide, and if Ay From these statements, we see that the logic expression for A > B can be written as (A> B):G=A,B, + (A, ©B)A,B, + (4 © BA, 0 BAB, + (A, OBA, OB, XA, © B,)A,!COMBINATIONAL LOGIC DESIGN 329 similarly, the logic expression for A < B can be written as (A B, A < B, and A=B. As Be A>B(G) A=B(E) By * A to Goa “3 looo Wry yr |1oo Gf tttol Neoee haere 777 1 © O | — Bevery k-mop Jor G2 GG Gra 6 a1 ul to — || GG 3 Ga . oo | ge _] — Ga r _| FAG Fa 1 7. i | 4G3Ga. “1 GBB Bae Gi@GsO G4 jaa@ ke amap for By - G24 GyG3 4290 © G4 Gs ol iW i GiGs G26 ol ID ‘oO G4 G3 Gai iG 266 A oO (i G,2,6,4) lo ©) M+ —— G,Gs G2Gi Goa G2 Gi G43 GG Bevery to Bcp ee Booey BCD oe 00000 ee 2 eo lool 01001 (010) fooo0o > 0l0F# Gdd. P/O t ase ono 10000 to oo a bow!® Ex-nog gecle - fda Spout Gpe of gos Jl am be wed Cee habf aceboy ,~fitl acleley onl Subloactoy - The exclasene omy Abo R, gate 6 abbrewabed a3 Ex Me Gete or Gometenne as X~ ALOR Ge: - jt has w opul (n> = 2) andy one outputEncoder8 and, Decoders ~ ogee gates aw he cath blocks for Combéermateniat logee curveuets — There are variow Sypes cf Combemaleeriels cll8 Guth as Encoder§ , Decoders ofe - coder ~ Am cncerer & ew combuiakerinle digataly lee eerenit Na deep am acheie lel on one of ig esprels vepresorls a deg L£CSruls as deeemol or ocbal digif) eb @nuorls tt to @ coded, ontrrel CSucls a3 Binary or BB). ~ Encoders are ahoupds & encode usriow Symbols ond alphanumenc characlerg- The process of Conctarteng From Semen gyobals mambers fo en IS fenocon as encedling . 6-to 3 bene encetler -= Thad ob toe, Somiple, ome basic emceclen N = i Fas aghts Hepes ae Tee alpha Shek code w 1 beviaay ok @ beb conde, ae soon endef Es CS arse r7 B= 2rearer? Heer t+ 3 +649 Ua above exepoess ions Bes ie inmplamaseuceel to Obtams Be oie ce Despre Soy ensodang, eathy Qeetmall bw 3-bD bere code « sh Cec. Seay.) d tH A ae — + 1a 4@ Docent lo BCD Kneeter on Decimad' 2S Bep oubpribs mpats “p \ \ if p Devimats f6 BCD Emeeden ~ Mus crewder has den puts as Sows or bps ts ay S loon un’ -fegy ~ ach, prt os for a esowals degat ona, cats ostpd 4 'S Corresponds fo (Ge. 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