Module- 7
Types of Programmable Logic Devices:
PLA, PAL, CPLD, FPGA Generic Architecture
PLD
PLA PAL CPLD FPGA
✓ The word “programming” here refers to a hardware procedure which
specifies the bits that are inserted into the hardware configuration of
the device.
✓ PLD, it is also referred fixed architecture logic device.
Comparison of PLA and PAL
PLA PAL
It is Programmable AND array and Programmable It is Programmable AND array and Fixed OR array
OR array
It is Costliest and Complex than PAL It is easier to program, Cheaper and Simple
It is Flexible It is not Flexible
PLA is used to provide control over data path. Counter
PLA is used as a counter. State machine
PLA is used as a decoder. Decoder
PLA is used as a BUS interface in programmed I/O Synchronization
Bus Interfaces
Parallel to serial
Serial to parallel
PAL
PLA
✓ Digital systems are designed with flip‐flops and gates.
✓ Since the combinational PLD consists of only gates, it is necessary to include
external flip‐flops when they are used in the design.
Sequential (or simple) programmable logic device (SPLD)
Complex programmable logic device (CPLD)
• Digital system requires the connection of several devices to produce
the complete specification.
• Collection of individual PLDs (SPLD) on a single integrated circuit.
• It consists of multiple PLDs interconnected through a programmable
switch matrix.
• Each PLD consists 8 to 16 Macrocells.
• Sometimes Macrocell programmed by flip-flop
Complex Programmable Logic Device (CPLD)
FPGA
✓ Field‐programmable gate array (FPGA) is a VLSI circuit.
✓ A typical FPGA consists of an array of millions of logic blocks, surrounded by programmable input
and output blocks and connected together via programmable interconnections.
✓ The performance of each type of device depends on the circuit contained in its logic blocks and the
efficiency of its programmed interconnections.
✓ A typical FPGA logic block consists of lookup tables, multiplexers, gates, and flip‐flops.
✓ A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions
for the logic block. These functions are realized from the lookup table.
✓ Image Processing, Artificial Intelligence, aerospace and defense.
FPGA Architecture
Implement PAL for the given expression using 4 X 3 X 4
w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)
CD CD
AB 00 01 11 10 AB 00 01 11 10
0 1 3 2 0 1 3 2
00 0 0 0 1 00 0 1 0 1
4 5 7 6 4 5 7 6
01 0 0 0 0 01 0 0 1 0
12 13 15 14 12 13 15 14
11 1 1 0 0 11 1 1 1 1
8 9 11 10 8 9 11 10
10 0 0 0 0 10 1 1 1 1
w=ABC + ABCD x = A + BCD
CD CD
AB 00 01 11 10 AB 00 01 11 10
0 1 3 2 0 1 3 2
00 1 0 1 1 00 0 1 0 1
4 5 7 6 4 5 7 6
01 1 1 1 1 01 0 0 0 0
12 13 15 14 12 13 15 14
11 0 0 1 0 11 1 1 0 0
8 9 11 10 8 9 11 10
10 1 0 1 1 10 1 0 0 0
Y = A B + CD + B D z=ABC +ABCD+ABCD+ACD
z= w +ABCD+ACD
PAL Program Table
Product Term AND Inputs Outputs
A B C D W
1 1 1 0 - -
2 0 0 1 0 - W = ABC' + A’B’CD’
3 - - - - -
4 1 - - - -
5 - 1 1 1 - X = A + BCD
6 - - - - -
7 0 1 - - -
8 - - 1 1 - Y = A'B + CD + B’D'
9 - 0 - 0 -
10 - - - - 1
11 0 0 0 1 - Z = w + A’B’C’D + AC’D’
12 1 - 0 0 -
A A’ B B’ C C’ D D’ w w’
w
A
x
B
D
Problems on PLA
+
x + 1 = x’ x + 0=x
