Jin-Fu

Ji F Li
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
` Introduction
` System-on-Chip
S t Chi (SoC),
(S C) M
Multichip
lti hi
Module(MCM), and System-in-Package (SiP)
` Testing of Bare Dies
` System
System-in-Package
in Package Testing

2
SoP SiP
Memory

Memory

uP
RF IC Opto Elec Analog/Digital IC

Passive components
RF, Filters
Decoupled Capacitors

3
SoP
SiP

4
` The system-in-package (SiP) is a single miniaturized
functional module realized byy vertical stackingg of two
or more similar or dissimilar bare or packaged chips
` Bringing the chips closer together enables the highest
level of silicon integration and are efficiency at the
lowest cost, compared to mounting them separately in
traditional was
` SiP technology allows the integration of heterogeneous
IC technologoies
` Therefore SiP technology is emerging as a strong
Therefore,
contender in a variety of applications that include cell
phones digital camera
phones, camera, PDAs
PDAs, etc
etc.
5
` Basic requirements of chip package
◦ Signal distribution
◦ Heat dissipation
◦ Power
P di
distribution
t ib ti
◦ Circuit support and protection

Plastic
Wire bond
encapsulant Chip

Lead frame

Die attach pad

6
 Level 1

Level 2
Chip
Single-chip
Single chip
package

Printed wiring board

(PCB)

Level 1
Multichip
Module (MCM)

Chi
Chips

7
` Pitch=75-130 um, Leads=1.5mm
d it 400/ 2
` I/O density=400/cm

Bonding
Chip
pad
Substrate

Chip face

8
` The flip chip assembly is much smaller than a
traditional carrier-based
carrier based system
` No leads are needed
` Pitch=75-250 um
` I/O density 1600/cm2
density=1600/cm

Chip

Substrate

Chip face

9
` Advantages
◦ The flip chip assembly is much smaller than a
traditional carrier-based system
◦ The chip sits directly on the circuit board,
board and is much
smaller than the carrier both in area and height
` Di d t
Disadvantages
◦ Not suitable for easy replacement, or manual
i
installation
ll i
◦ Require very flat surfaces to mount to
◦ Sometimes difficult to maintain as the boards heat and
cool

10
` Introduction
` Interconnection
I t ti andd Package
P k
` System on Chip (SoC), Multichip
Module(MCM), and System in Package (SiP)
` Bare Dies Testing
` System in Package Testing

11
` Mainframe computers drove MCMs in 1980s
` High-end
Hi h d networking,
t ki signal
i l processing,
i andd
digital communication demands drive SoC
` Cell phones and handsets are driving SiPs
solutions
` Some view SiP as a vertical MCM
` SoC:
S C a packaged
k d chip
hi with
ith only
l one die
di
` SiP: an assembled system composed of a
number of individual dies on a packaged chip

12
` Several components are integrated into a chip

Core
Embedded
Embedded
SRAM
SRAM
controller
CPU

Peripheral
circuit
interface

D
Data
DMAC I/O

bus
buffer
Inte

External

s
ernal bus

memory
controller

13
` Multi-chip module package
◦ Several specialized chips are also assembled in a
single ceramic package as a system solution using
traditional assembly processes
◦ The chips in an MCM are mounted on the same plane
(the ca
cavity
it ssubstrate),
bstrate) whereas
hereas SiP employs
emplo s die
stacking as its natural configuration

Source: IBM Power5 14

` SiP design and test is a viable, rapid, and cost-effective
solution to high-density
high density system integration
` SiP is more than an IC package containing multiple die
` SiP helps
h l exceedd the
th limits
li it off the
th SoC
S C designs
d i

Source: nanoamp

15
` 3D packaging is critical to integrating the multi-media
features consumers demand in smaller, lighter
products
` It can deliver the highest level of silicon integration
and area efficiency at the lowest cost

Source: ETS07
Source: Amkor

16
` Portable devices, cell phone
◦ 70~80%
70 80%
` Module integration
◦ RF cellular,
ll l RF amplifier,
lifi switch,
it h transceiver
t i
◦ Digital
◦ Memory module, DRAM, Flash
◦ WLAN, Bluetooth
` In 2008, 3.25 billion SiPs are expected to be
assembled

17
` Combining different die technologies (Si, GaAs, SiGe,
etc.))
` Combining different die geometries (180nm, 90nm,
45nm, etc.)
` Including other technologies (MEMS, optical, vision,
etc )
etc.)
` Including other components (antennas, resonators,
connectors etc.)
connectors, etc )
` Increasing circuit density and reducing PCB area
` R d i design
Reducing d i effort
ff t
` Improving performance

18
` The most critical issues are design and
t t methods
test th d andd solutions
l ti
◦ Common EDA tools are necessary y for
integrating mixed-signal and RF blocks
◦ KGD should be readily available for SiP
designers
◦ The proliferation of integrated passive devices
((IPD)) at the SiP substrate level is needed

19
` How to test chips and packages
◦ DFT,
DFT package
k test,
t t andd KGD strategies
t t i
` How to integrate
g and test different types
yp
of memories
◦ Alternative
Alt ti design
d i andd package
k options
ti
◦ Debug and yield enhancement

20
` Introduction
` Interconnection
I t ti andd Package
P k
` System on Chip (SoC), Multichip
Module(MCM), and System in Package (SiP)
` Bare Dies Testing
` System in Package Testing

21
 Memory VLSI Analog/power
chip chip chip

Wafer Wafer Wafer

test test test

KGD

Assembly Stacking
process package

Intra-system Interconnection SiP

connectivity test DFM rules

Identify the problem Post-packaging

during the packaging test

Overall SiP test

Commercial
product
22
` Die process
Die Fabrication
b

Die #i

Fci Fdi Fci: good die

Fdi: defective die

Die Test

Figo Finogo

Pass die tests Fail die tests

23
` SiP Process
F1go Fngo

.
.
.
SiP Assembly

Aci: goodd SiP

Adi: defective
Aci Adi SiP

SiP Test
Ago Anogo

Pass SiP tests Fail SiP tests

24
` If various chips are used in a chip
◦ Ym=[(p1)
[(p )A(p
(p2))B(p
(p3))C…]]
◦ Ym: yield probability for assembled chips
◦ A,
A BB, C: number of dice of each type
◦ p1: probability of die 1 being good
` Yi ld off SiP is
Yield i also
l dependent
d d t on
◦ Ps: Know-good probability of substrate
◦ Pi: Know-good probability of die interconnects
◦ Q: number of interconnects
◦ Pw: probability of assembly workmanship
◦ Ysip=YmxPsx(P( i)QxPw

25
` Definition of defect level: percentage of SiPs
shipped which passed the SiP test,
test but may be
faulty
◦ DL=1-Y
DL 1 Ysip(1-FC)
(1 FC)x100%
100%
◦ Ysip: yield of SiP
◦ FC: faulty coverage
` Defect level can be reduced by
y high
g qqualityy
bare dies and high FC

26
` The assembly process accumulates all the
problems of the individual dies
DLi (ppm) Pi (%)
Substrate 600 99.94
Die 1 4100 99.59
Die 2 35500 97.45
Die 3 1200 99.88
YSIP 96 8
96.87

27
` To test an SiP, each bare die must be tested first before
packaged in the SiP
◦ To eliminate compound yield loss
` It is performed at standard wafer sort
◦ Manufacturing defects of silicon implementation
` Known Good Dies
◦ Confidence level that bare dies are fully tested for performance
over a temperature range
◦ A bare die with the same quality after wafer test
` Mechanical probing techniques
` Electrical probing techniques

28
` Process control-based approach
◦ Improve yield through six sigma and zero defect yield
programs
` Testing-based
g approaches
pp
◦ Sampling approach
◦ Full test and burn-in approaches
pp
x Temporary pressure contacts
x Wafer-level
x Die-level
x Permanent contacts
x Semi-permanent
S i contacts
◦ Design-based approaches

29
` Require high quality functional test
` Require
R i performance
f test
t t
◦ Performance driven application (at-speed)
` Require reliability screening
◦ Wafer level burn-in
◦ Tape automated bonding (TAB)
◦ Temporary test packaging

30
` Based on statistical probability of KGD
◦ Systematic defects-
defects process or design
design-related
related
problems
` P
Process
◦ Package a sufficient sample of dies in wafer lot
◦ Perform exhaustive test and burn-in
◦ Certify entire lot if meets requires criteria
◦ Perform binning each die based on tests of nearest
neighbors
g

31
` A: Temporary pressure contacts
◦ Wafer level
x Reliability screens
x Burn-in
B i
◦ Die level
x Temporary packages, carrier
x Probe cards and techniques
q
x Membrane pressure
` B: Permanent contacts
` C: Semi-permanent contacts

32
` Full wafer contactor
` Applied High voltage and temperature
` Long term solution for KDG
Traditional back
back-end
end

Wafer Wafer Package Burn-in Final Test Know-

probe Good-
Wafer-level Burn-in and Test Package

Wafer Wafer- Wafer KGD wafer

l
level
lbburn- final test
in and test
33
` Used for many years by DRAM vendors to
reduce burn
burn-in
in time
` Often referred to as wafer-level BI
` Provides external control of array voltages
` Stresses most defects

34
Method Pitch Process Parallelism Initial Operating
p g Optimal
p
Limit complexity $ $ Value

Low-Same
Carrier >120um Med High Low Medium Low
as PLBI
Sac
High-full Medium
Metal >120um High Medium High
Wafer High
WLBI
High-
Direct
High-full Contactor
Contact <100um Low Low High
wafer
ae tooling
too g
WLBI
and NRE

Source: freescale

35
` Wafer sort using probe card is a traditional
technique
` New probe cards are required for new die
` High performance operations depends on
probe ppin
p
` ATE Limitations
◦ High I/O counts
◦ High performance devices
` For bare dies, probing technology is crucial

36
 ` The distance between the pads and the tuning
components is reduced
` The membrane offers significant advantages
f high-performance
for hi h f wafer
f ttestt
Forced-delivery
Microstrip mechanism
transmission line Terminations
Membrane

Carrier PCB
Passive die
Ground plane Membrane
Contact bumps Contact bumps

37
` Vertical probe was developed to fulfill the
requirement for array configurations
◦ Co-planarity
◦ The demand on novel and expensive probe techniques is
increased
` Solutions
◦ MEMS-based implementations of probe cards
◦ Noncontact testing
Tester

Standard Probe Card PCB

Probe Chip Mounting Substrate

Antenna
Probe chip
Wafer to be Tested

38
` Each antenna and transceiver probes one I/O on the DUT
with each I/O site on the DUT

Probe Card Device Under Test

Tx/Rx Tx/Rx
Signal
Tx/Rx Tx/Rx

Applic
Tester

Prober

Circ
Tx/Rx Tx/Rx

cation
T

cuit
P

Test
Circuits
Tx/Rx
/ Tx/Rx
/

Power

39
` Testing RF and mix-signal ICs represents a big
challenge due to the propagation of disturbed
signal
` Wideband protocols add many constraints to
the wafer probing
p g
◦ Membrane

40
` A: Temporary pressure contacts
` B:
B PPermanent contacts
◦ TAB ((Tape
p Automated Bonding)
g) lead frame
bonded
◦ Testable ribbon bonding
◦ Bare die carrier
` C: Semi-permanent contacts

41
` Minimal package permanently assembled with die
` Die bounded into low cost carrier or tape
` TAB lead frame bonded to IC
◦ Full test and burn-in is possible
◦ TAB technology is expensive
` Testable ribbon bonding
◦ Die ribbon bounded to low cost carrier
◦ After test and burn-in ribbon cut,, leavingg TAB like die
` Bare Die carrier
◦ No p
performance penalties
p
◦ Easy carrier replacement

42
` DFT
` Yield optimization loop
◦ Yield learning; detection, analysis, and correction
` Architecture of IIP
◦ Ensures manufacturability and lifetime reliability of SiP
` Embedding process monitoring IP
◦ Test vehicle or test die
` Embedded test & repair IP
◦ Embedded memory with redundancy
` Embedded debug & diagnosis IP
◦ Collect failure data and analyze obtained data by off chip

43
` Test for electrical integrity before attachment
◦ Mechanical probing
◦ Contactless electron-beam probing
` P
Prevent population
l i off defective
d f i substrates
b
◦ No possible to repair substrate
◦ Dies damaged during removal
◦ High
g cost
` Failure mechanisms
◦ Short and open

44
` Known good substrate is required prior to
bonding
` In-Process Testing
◦ Intermediate tests during fabrication to access every
wiring layer
◦ Mainly contactless probing techniques
◦ Helps
p process
p improvement
p and process
p control
` Final Testing
◦ Before populating expensive bare dies

45
` Mechanical probing – slow
◦ Bed of nails – traditional PCB testingg
◦ Moving test head
◦ Single/double point flying probes – capacitance and
resistive, open, and short testing
◦ Glow discharge – optically detect opens and shorts
` Contactless probing - fast
◦ Automatic optical testing – image analysis
◦ Electron beam testing – charge and read each pad

Bed-of-nails probing
46
` Introduction
` System
S t on Chi Chip (SoC),
(S C) MMultichip
lti hi
Module(MCM), and System in Package (SiP)
` Bare Dies Testing
` System in Package Testing

47
` Incoming bare die test
` Mounting process
◦ Mechanical placement
` SiP assembly test
◦ Parametric test
◦ Functional test
` Encapsulation
◦ Molding
g a plastic
p bodyy around substrate
` Burn-in
` Retest
` Rework

48
` Die-to-die interconnection
◦ Delay marginalities
` Die-to-die bonding
◦ Electromechanical marginalities
` Marginal
g pad
p or die placement
p on the substrate
can affect the yield
◦ Electrical effects,
effects such as crosstalk or bonding
violation
` Need microprobing and traceability

49
` Functional test
◦ Structural and performance test
◦ Check application specifications and functionality
◦ Require
R i a complex l test
t t setup
t with
ith expensive
i
instruments
◦ Long test times
i
◦ Testing full paths makes diagnostics difficult
` Access methods

50
` Accessibility
` Controllability
C t ll bilit
` Observability
` Failure localization
` Failure analysis
` Deep memory and mixed signal
` Design for test (DFT)

51
` Advantage of functional test
◦ Good correlation at the system lelvel
` Disadvantages
◦ Complex test setup with expensive instruments
◦ Long test times
◦ Diagnostic difficulty
` Example:
◦ Path-Based testing
◦ Lookback techniques

52
` Consider a system with a digital plus mixed-
signal circuitry,
circuitry an RF transceiver , and a
power amplifier dies
Receiver path

LNA ADC

Band-pass filter BPF BPF VGA DSP

LO
(BPF)

PA DAC

Transmitter path

53
` The quality of a receiver is given by its bit error rate
(BER)
` The BER test requires a lot of data to achieve the target
accuracy
` A bit-error, pe
pe = 0.5 ⋅ erfc ( Eb / N o )
Eb = C / f b
No : the noise power spectral density
Eb : the energy of the received bit
C : the power of the carrier
fb : the data rate

54
` The transmitter channel is usually tested by measuring
the error vector magnitude (EVM)
◦ V(t) represents the transmitted signal, where I(t) and Q(t) are
the data signals
v(t ) = I (t ) cos(ωc t ) + Q(t ) sin(ωc t )

( I − I ) + (Q − Q )
2 2
EVM = ref ref

Qref
Ref vector Error vector

Q
Amplitude error
Phase error

Iref I

55
` External
◦ Creating the loop between the output of PA and the
input of LNA
Loopback circuit

Down-
BP Filter LNA LP ADC
C
converter
t

External Offset Base

LO mixer Band
LO DSP
Phase/Freq.
divider
Up-
TA PA LP DAC
converter
Test
attenuator

56
` Internal
◦ Creatingg the loopp in the front-end IC
◦ Connecting the up-converter to LNA through TA, a
complementary BIST sharing the circuitry with on-chip
resources

Phase/Freq. Down-
LNA LP ADC
divider converter

Base
Test DA/AD Band
Test LO Test loop DSP
PA TA

Up-
LP DAC
converter

57
` Structural testing of interconnections between dies
` Structural or functional testing of dies themselves
` Challenge
◦ Hard to access the dies from the I/Os of the SiP
` To improve the testability, SIP test access port (TAP) is
placed on the bare dies
` To provide high quality structural test and failed
element identification capability,
capability BIST and boundary-
scan are used

58
` Features
◦ Access for die and interconnection tests
◦ SIP test enabling at system level
◦ Additional recursive test procedures during assembly
` IEEE 1149.1 and 1149.4
◦ Boundary scans are used in bare dies
◦ 1149.1 for digital dies and 1149.4 for mixed-signal or
analog dies
` IEEE 1500
◦ Designed for SoC test at system level

59
 Boundary
scan cell
IN1 OUT1
IN2 OUT2
IN3 Die Core OUT3
IN4 OUT4
Internal Scan
Boundaryy
scan path
Instruction
TCK

Controlller
Identification

TAP
TMS
TDI Bypass
TRST
TDO

60
 Digital I/O

DMB DMB DMB

Controller
Add. Boundary
scan path
Instruction
TDI Bypass
Mixed-Signal Core
TMS TAP
TAP
TCK Controller

TDO M
U
X Internal
analog bus
AT1 AB1
Analog AB2
TBIC
C
TAP
AT2 ABM ABM ABM
Test bus interface Analog
circuit boundary
Analog I/O module
61
` The assembly process may introduce additional
failures
` Intermediate tests after every die soldering may
be required
` Dies are assembled from the least to the most
expensive dies to optimize the overall SiP cost

62
` TAP must manage boundary scan resources
d i the
during th incremental
i t l tests
t t even while
hil some
dies are missing
` Two configurations are required
◦OOnee iss for
o tthee incremental
c e e ta test - sta
star
◦ One is for the end-user test - ring

63
` The star configuration attempts to facilitate
incremental testing during the assembly
◦ The link between the dies is broken during the
assembly TDI
TCK
Die2
Die1 TMS
TDO
TDO 0
TDI 1
TAP

TDI
TCK
SiP T

TCK
TMS1 Die3
TMS
TMS2 TDO
0
TMS3 1

0
1 TDI
0
TCK
1 Die4
TMS
TDO

64
` The end-user cannot detect the presence of
several
seve a dies
d es in thee ringg configuration
co gu a o
◦ Only one TMS control signal is required
TDI
TCK
Die2
Die1 TMS
TDO
TDO
O 0
TDI 1
P TAP

TDI
TCK
TCK
TMS1 Die3
SiP

TMS
TMS2 TDO
0
TMS3 1

0
1 TDI
0
TCK
1 Die4
TMS
TDO

65
` The interconnection test is performed through
boundary scan in external test mode
◦ For k wire, log2(2k+2) vectors are required to test
bridging faults
Step Die 1 Die3 Die 3
Digital
1 Reset Reset Die 1
2 PRELOAD PRELOAD Digital
Vector
3 EXTEST EXTEST
#1
Vector
4 EXTEST EXTEST
#2 Die 2
5 Reset Reset Analog/MS

Die 4

66
` External pads of an SiP are less
◦ Integrate additional DFT for testing specific dies on another
die
◦ Implement a configurable DFT with software or
programmable capabilities on another die
◦ Use the transparent mode of other dies to directly control and
observe
b f
from the
h primary
i I/O
/
` Example
◦ The embedded memories are usually packaged without BIST
circuit
◦ The
Th BIST circuit
i it has
h tot be
b implemented
i l t d in
i another
th digital
di it l core
◦ Dies without boundary scan

67
` Use a transparent mode of the other dies to
control and observe from the I/O of the package

Die 3
Digital

Die 2
Die 4 Analog/MS
RF

68
` Features
◦ Easy and fast test interoperability at the core
and subsystem layers
◦ Effective support for chip-to-chip
interconnection test
◦ Definition of a standard approach for
generating the chip-level
chip level and SiP-level
SiP level test
program

69
` A single serial line is used as the TAM
` It is useful for both chip-level
chip level and SiP-level
SiP level test
Subsystem chip

Stand-alone chip SSoC TAM 1500

CPU

DRAM
eMEM I/O
1500 1500 1500

SiP 1500
TAM
substrate

Test data Wrapper Test data

i
input
t i l
serial t t
output
control
70
` The wrapper is to provide test data to each
core and capture results and to perform data
conversion for transmission on the selected
TAM
` A six-signal
g bus allows management
g of the
wrapper serial structures by controlling data
transfers to and form each core

71
` The wrapper boundary register (WBR) is used
as a boundary scan chain at core level
` The wrapper bypass register (WBY) has a
single flip-flop to bypass test data to other
cores
` The wrapper instruction register (WIR)
receives the instruction and controls the
multiplexers

72
` Core-to-core interconnection testing

Scan chain 0
WPI[0:2]
Scan chain 1 WPO[0:2]
d[0]

d[1] q[0]
d[2] Core

q[1]
d[3]
q[2]
d[4]
clock scan

Clock
Scan WBY
Test data input WIR Test data output

Wrapper serial control

73
` Chip-to-chip interconnection testing

Scan chain 0
WPI[0:2]
Scan chain 1 WPO[0:2]
d[0]

d[1] q[0]
d[2] Core

q[1]
assume
d[3] q[1] and q[2]
assume q[2] are SSoC PO
d[4]
d[3] and d[4] clock scan
are SSoC PI
Clock
Scan WBY
Test data input WIR Test data output

Wrapper serial control

74
` Memory test time dominates product test flow
and test platform choice
◦ SoC tester and memory tester
` DFT for mixed-signal and memory is the
better solution

75
` Use dedicated chip with BIST
` Include BIST facilities in neighboring dice

SRAM DRAM

Control
User
Address
Logic
Data

MBIST SRAM DRAM

TAP

76
` Use boundary scan chain of neighboring ASIC
◦ Memory arrays,
arrays glue logic,
logic etc.
etc
` Use dedicated boundary scan parts to create
virtual boundary scan
◦ Probe chip, octals, etc.

77
` Effective self-test in autonomous manner
` Test controller embedded in SiP,SiP instead of
external test processor
` Embedded
E b dd d ASIC bl blockk or ddedicated
di t d chip
hi
` SiP technology drivers
◦ High quality test
x BIST
S can pprovide high
g test coverage
g
◦ Performance test
x BIST runs at system speed
◦ Reliability test
x BIST runs during
d i burn-in
b i
78
` Challenges
◦ Cost reduction of the required test equipment
◦ Difficult to access the dies after assembly process
` Analog, mixed signals, and RF circuits require long
functional test time
` Approaches
pp
◦ Move tester functions onto the chip itself - BIST
◦ Convert analog signals on-chip to timing delay information
for ATE measurement
◦ Use DFT techniques to internally transform the analog signals
t digital
to di it l signals
i l
` Only digital signals are externally observed by less-
expensive
i digital
di i l tester
79
` Assume that DACs and ADCs are available
` Input and output signals are fully digital
` Both DAC-to-ADC and analog blocks paths can be
tested I1I2I3 O1O2 O3
01101 01101
11010 DAC ADC 11010
10101 1 1 10101
11101 11101
01101 01101
11010 DAC ADC 11010
10101 2 2 10101
11101 11101
. .
. ∑ .
. .
01101 01101
DAC ADC 11010
11010 10101
10101 n n
11101
ANC 11101

80
` Test equipment is a problem for MEMS testing
` Two
T approachesh
◦ Perform an indirect structural or functional test
◦ Implement DFT circuitry to convert the physical
signal to an electrical signal
` Significant package influence is another
challenge for MEMS testing
◦ Hard to detect defective MEMS before packaging

81
` The classical problems are more serious
◦ Adjacent dies might disturb and modify the MEMS quality
◦ The test needs to generate and observe various nonelectrical
signals for several MEMS in the same SiP
` The alternative techniques with only electrical signals
are the only
y viable option
p

Source: ETS07

82