Chapter 2

BJT BIASING CIRCUIT

Introduction – Biasing
The analysis or design of a transistor amplifier requires knowledge of both the
dc and ac response of the system. In fact, the amplifier increases the strength
of a weak signal by transferring the energy from the applied DC source to the
weak input ac signal The analysis or design of any electronic amplifier therefore
has two components:
•The dc portion and
•The ac portion
During the design stage, the choice of parameters for the required dc levels
will affect the ac response.
What is biasing circuit?
Biasing: Application of dc voltages to establish a fixed level of current and
voltage.
Purpose of the DC biasing circuit
• To turn the device “ON”
• To place it in operation in the region of its characteristic where the device
operates most linearly .
•Proper biasing circuit which it operate in linear region and circuit
have centered Q-point or midpoint biased
•Improper biasing cause Improper biasing cause
•„Distortion in the output signal
•„Produce limited or clipped at output signal

Important basic relationship

I=
E IC + I B
IC
β =
IB
I E  = ( β + 1)I B ≅ I C

V=
CB V CE −V BE
Operating Point

•Active or Linear Region Operation

Base – Emitter junction is forward biased
Base – Collector junction is reverse biased
Good operating point

•Saturation Region Operation

Base – Emitter junction is forward biased
Base – Collector junction is forward
biased
•Cutoff Region Operation
Base – Emitter junction is reverse biased
 BJT
Analysis

DC AC
analysis analysis

Calculate gains of the

Calculate the DC Q-point amplifier

solving input and Graphical

output loops Method

DC Biasing Circuits
•Fixed-bias circuit
•Emitter-stabilized bias circuit
•Collector-emitter loop
•Voltage divider bias circuit
•DC bias with voltage feedback
FIXED BIAS CIRCUIT

 This is common emitter (CE)

configuration
 1st step: Locate capacitors and
replace them with an open
circuit
 2nd step: Locate 2 main loops
which;
 BE loop (input loop)
 CE loop(output loop)
 FIXED BIAS CIRCUIT

 1st step: Locate capacitors and replace them with an open

circuit
 FIXED BIAS CIRCUIT

 2nd step: Locate 2 main loops.

BE Loop CE Loop

2
1 2
 FIXED BIAS CIRCUIT

 BE Loop Analysis
■ From KVL;
1
−V CC + I B R B +V BE =
0
IB V CC −V BE A
∴I B =
RB
 FIXED BIAS CIRCUIT

 CE Loop Analysis
■ From KVL;
−V CC + I C RC +V CE =
0
IC ∴V CE = V CC − I C RC
■ As we known;
2 I C = βI B B
■ Substituting A with B

 V − VBE 
I C = β DC  CC 
 RB 
Note that RC does not affect the value of Ic
 FIXED BIAS CIRCUIT

 DISADVANTAGE
 Unstable – because it is too dependent on β and produce
width change of Q-point
 For improved bias stability , add emitter resistor to dc bias.
Collector–Emitter Loop
The collector–emitter section of the network appears in Fig. 4.5 with the indicated
direction of current IC and the resulting polarity across RC. The magnitude of the col-
lector current is related directly to IB through
IC ⫽ ␤IB (4.5)

It is interesting to note that since the base current is controlled by the level of RB
and IC is related to IB by a constant ␤, the magnitude of IC is not a function of the Figure 4.5 Collector–emitter
resistance RC. Change RC to any level and it will not affect the level of IB or IC as loop.
long as we remain in the active region of the device. However, as we shall see, the
level of RC will determine the magnitude of VCE, which is an important parameter.
Applying Kirchhoff’s voltage law in the clockwise direction around the indicated
closed loop of Fig. 4.5 will result in the following:
VCE ⫹ ICRC ⫺ VCC ⫽ 0
and VCE ⫽ VCC ⫺ ICRC (4.6)

which states in words that the voltage across the collector–emitter region of a tran-
sistor in the fixed-bias configuration is the supply voltage less the drop across RC.
As a brief review of single- and double-subscript notation recall that

VCE ⫽ VC ⫺ VE (4.7)

where VCE is the voltage from collector to emitter and VC and VE are the voltages
from collector and emitter to ground respectively. But in this case, since VE ⫽ 0 V,
we have

VCE ⫽ VC (4.8)

In addition, since

VBE ⫽ VB ⫺ VE (4.9)
and VE ⫽ 0 V, then

VBE ⫽ VB (4.10)

Keep in mind that voltage levels such as VCE are determined by placing the red Figure 4.6 Measuring VCE and
VC.
(positive) lead of the voltmeter at the collector terminal with the black (negative) lead
at the emitter terminal as shown in Fig. 4.6. VC is the voltage from collector to ground
and is measured as shown in the same figure. In this case the two readings are iden-
tical, but in the networks to follow the two can be quite different. Clearly under-
standing the difference between the two measurements can prove to be quite impor-
tant in the troubleshooting of transistor networks.

Determine the following for the fixed-bias configuration of Fig. 4.7. EXAMPLE 4.1
(a) IBQ and ICQ.
(b) VCEQ.
(c) VB and VC.
(d) VBC.

4.3 Fixed-Bias Circuit 147

 Figure 4.7 dc fixed-bias cir-
cuit for Example 4.1.

Solution
VCC ⫺ VBE 12 V ⫺ 0.7 V
(a) Eq. (4.4): IBQ ⫽ ᎏ ᎏ ⫽ ᎏᎏ ⫽ 47.08 ␮A
RB 240 k⍀
Eq. (4.5): ICQ ⫽ ␤IBQ ⫽ (50)(47.08 ␮A) ⫽ 2.35 mA
(b) Eq. (4.6): VCEQ ⫽ VCC ⫺ ICRC
⫽ 12 V ⫺ (2.35 mA)(2.2 k⍀)
⫽ 6.83 V
(c) VB ⫽ VBE ⫽ 0.7 V
VC ⫽ VCE ⫽ 6.83 V
(d) Using double-subscript notation yields
VBC ⫽ VB ⫺ VC ⫽ 0.7 V ⫺ 6.83 V
⫽ ⴚ6.13 V
with the negative sign revealing that the junction is reversed-biased, as it should be
for linear amplification.

Transistor Saturation
The term saturation is applied to any system where levels have reached their maxi-
mum values. A saturated sponge is one that cannot hold another drop of liquid. For
a transistor operating in the saturation region, the current is a maximum value for the
particular design. Change the design and the corresponding saturation level may rise
or drop. Of course, the highest saturation level is defined by the maximum collector
current as provided by the specification sheet.
Saturation conditions are normally avoided because the base–collector junction is
no longer reverse-biased and the output amplified signal will be distorted. An oper-
ating point in the saturation region is depicted in Fig. 4.8a. Note that it is in a region
where the characteristic curves join and the collector-to-emitter voltage is at or be-
low VCEsat. In addition, the collector current is relatively high on the characteristics.
If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick,
direct method for determining the saturation level becomes apparent. In Fig. 4.8b, the
current is relatively high and the voltage VCE is assumed to be zero volts. Applying
Ohm’s law the resistance between collector and emitter terminals can be determined
as follows:
V E 0V
RCE ⫽ ᎏCᎏ ⫽ ᎏᎏ ⫽ 0 ⍀
IC ICsat

148 Chapter 4 DC Biasing—BJTs

 EMITTER-STABILIZED BIAS CIRCUIT

 An emitter resistor, RE is
added to improve stability
 1st step: Locate capacitors and
replace them with an open
circuit
 2nd step: Locate 2 main loops
which;
 BE loop
Resistor, RE added  CE loop
 EMITTER-STABILIZED BIAS CIRCUIT

 1st step: Locate capacitors and replace them with an open

circuit
 EMITTER-STABILIZED BIAS CIRCUIT

 2nd step: Locate 2 main loops.

BE Loop CE Loop

2
1 2
 EMITTER-STABILIZED BIAS CIRCUIT

 BE Loop Analysis

1
■ From kvl;
−V CC + I B R B +V BE + I E R E =
0

Recall; I E = ( β + 1) I B
Substitute for IE
−V CC + I B R B +V BE + ( β + 1)I B R E =
0
V CC −V BE
∴I B =
R B + ( β + 1)R E
 EMITTER-STABILIZED BIAS CIRCUIT

 CE Loop Analysis
■ From KVL;
−V CC + I C RC +V CE + I E R E =
0
■ Assume;
2 I E ≈ IC
■ Therefore;
∴VCE = VCC − I C ( RC + RE )
 Improved Bias Stability
The addition of the emitter resistor to the dc bias of the BJT provides improved
stability, that is, the dc bias currents and voltages remain closer to where they
were set by the circuit when outside conditions, such as temperature, and
transistor beta, change.

Without Re With Re

V CC −V BE   V CC −V BE 
Ic =  β Ic =  β
 RB 
 R B + ( β + 1)R E 

Note :it seems that beta in numerator canceled with beta in

denominator
For the emitter bias network of Fig. 4.22, determine: EXAMPLE 4.4
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.

Figure 4.22 Emitter-stabilized

bias circuit for Example 4.4.

Solution
VCC ⫺ VBE 20 V ⫺ 0.7 V
(a) Eq. (4.17): IB ⫽ ᎏ ᎏ ⫽ ᎏᎏᎏ
RB ⫹ (␤ ⫹ 1)RE 430 k⍀ ⫹ (51)(1 k⍀)
19.3 V
⫽ ᎏᎏ ⫽ 40.1 ␮A
481 k⍀
(b) IC ⫽ ␤IB
⫽ (50)(40.1 ␮A)
⬵ 2.01 mA
(c) Eq. (4.19): VCE ⫽ VCC ⫺ IC (RC ⫹ RE)
⫽ 20 V ⫺ (2.01 mA)(2 k⍀ ⫹ 1 k⍀) ⫽ 20 V ⫺ 6.03 V
⫽ 13.97 V
(d) VC ⫽ VCC ⫺ ICRC
⫽ 20 V ⫺ (2.01 mA)(2 k⍀) ⫽ 20 V ⫺ 4.02 V
⫽ 15.98 V
(e) VE ⫽ VC ⫺ VCE
⫽ 15.98 V ⫺ 13.97 V
⫽ 2.01 V
or VE ⫽ IERE ⬵ ICRE
⫽ (2.01 mA)(1 k⍀)
⫽ 2.01 V
(f) VB ⫽ VBE ⫹ VE
⫽ 0.7 V ⫹ 2.01 V
⫽ 2.71 V
(g) VBC ⫽ VB ⫺ VC
⫽ 2.71 V ⫺ 15.98 V
⫽ ⴚ13.27 V (reverse-biased as required)

4.4 Emitter-Stabilized Bias Circuit 155

 VOLTAGE DIVIDER BIAS CIRCUIT
 Provides good Q-point stability with a single polarity supply voltage
 This is the biasing circuit wherein, ICQ and VCEQ are almost independent of
beta.
 The level of IBQ will change with beta so as to maintain the values of ICQ and
VCEQ almost same, thus maintaining the stability of Q point.
 Two methods of analyzing a voltage divider bias circuit are:
 Exact method : can be applied to any voltage divider circuit
 Approximate method : direct method, saves time and energy,
 1st step: Locate capacitors and replace them with an open circuit
 2nd step: Simplified circuit using Thevenin Theorem
 3rd step: Locate 2 main loops which;
 BE loop
 CE loop
 VOLTAGE DIVIDER BIAS CIRCUIT
■ 2nd step: : Simplified circuit using Thevenin Theorem

From Thevenin Theorem;

Thevenin Theorem;
R1 × R2
RTH = R1 // R2 =
R1 + R2
R2
VTH = VCC
R1 + R2

Simplified Circuit
 VOLTAGE DIVIDER BIAS CIRCUIT
 2nd step: Locate 2 main loops.

BE Loop CE Loop

2
2

1 1
 VOLTAGE DIVIDER BIAS CIRCUIT

 BE Loop Analysis
■ From KVL;
−V TH + I B RTH +V BE + I E R E =
0

Recall; I E = ( β + 1) I B
Substitute for IE
1
−V TH + I B RTH +V BE + ( β + 1)I B R E =
0
V −V BE
∴ I B = TH
R RTH + ( β + 1)R E
 VOLTAGE DIVIDER BIAS CIRCUIT

 CE Loop Analysis
■ From KVL;
−V CC + I C RC +V CE + I E R E =
0
■ Assume;
I E ≈ IC
2
■ Therefore;
∴VCE = VCC − I C ( RC + RE )
 RTh: The voltage source is replaced by a short-circuit equivalent as shown in
Fig. 4.28. R1

R2
RTh ⫽ R1储R2 (4.28) R Th

ETh: The voltage source VCC is returned to the network and the open-circuit
Thévenin voltage of Fig. 4.29 determined as follows:
Figure 4.28 Determining RTh.
Applying the voltage-divider rule:
R2VCC
ETh ⫽ VR2 ⫽ ᎏ ᎏ (4.29)
R1 ⫹ R2
R1 + +
The Thévenin network is then redrawn as shown in Fig. 4.30, and IBQ can be de- VCC R2 VR E Th
2
termined by first applying Kirchhoff’s voltage law in the clockwise direction for the
loop indicated: – –
ETh ⫺ IBRTh ⫺ VBE ⫺ IERE ⫽ 0
Substituting IE ⫽ (␤ ⫹ 1)IB and solving for IB yields
Figure 4.29 Determining ETh.
ETh ⫺ VBE
IB ⫽ ᎏ ᎏ (4.30)
RTh ⫹ (␤ ⫹ 1)RE

Although Eq. (4.30) initially appears different from those developed earlier, note
that the numerator is again a difference of two voltage levels and the denominator is
RTh
the base resistance plus the emitter resistor reflected by (␤ ⫹ 1)—certainly very sim- B
ilar to Eq. (4.17). +
Once IB is known, the remaining quantities of the network can be found in the IB VBE – E
ETh
same manner as developed for the emitter-bias configuration. That is, RE
VCE ⫽ VCC ⫺ IC (RC ⫹ RE) (4.31)

which is exactly the same as Eq. (4.19). The remaining equations for VE, VC, and VB Figure 4.30 Inserting the
are also the same as obtained for the emitter-bias configuration. Thévenin equivalent circuit.

Determine the dc bias voltage VCE and the current IC for the voltage-divider config- EXAMPLE 4.7
uration of Fig. 4.31.

Figure 4.31 Beta-stabilized

circuit for Example 4.7.

4.5 Voltage-Divider Bias 159

 Solution

Eq. (4.28): RTh ⫽ R1储R2

(39 k⍀)(3.9 k⍀)
⫽ ᎏᎏ ⫽ 3.55 k⍀
39 k⍀ ⫹ 3.9 k⍀
R2VCC
Eq. (4.29): ETh ⫽ ᎏ ᎏ
R1 ⫹ R2
(3.9 k⍀)(22 V)
⫽ ᎏᎏ ⫽ 2 V
39 k⍀ ⫹ 3.9 k⍀
ETh ⫺ VBE
Eq. (4.30): IB ⫽ ᎏᎏ
RTh ⫹ (␤ ⫹ 1)RE
2 V ⫺ 0.7 V 1.3 V
⫽ ᎏᎏᎏ ⫽ ᎏᎏᎏ
3.55 k⍀ ⫹ (141)(1.5 k⍀) 3.55 k⍀ ⫹ 211.5 k⍀
⫽ 6.05 ␮A
IC ⫽ ␤IB
⫽ (140)(6.05 ␮A)
⫽ 0.85 mA
Eq. (4.31): VCE ⫽ VCC ⫺ IC (RC ⫹ RE)
⫽ 22 V ⫺ (0.85 mA)(10 k⍀ ⫹ 1.5 k⍀)
⫽ 22 V ⫺ 9.78 V
⫽ 12.22 V

Approximate Analysis
The input section of the voltage-divider configuration can be represented by the net-
work of Fig. 4.32. The resistance Ri is the equivalent resistance between base and
ground for the transistor with an emitter resistor RE. Recall from Section 4.4 [Eq.
(4.18)] that the reflected resistance between base and emitter is defined by Ri ⫽
(␤ ⫹ 1)RE. If Ri is much larger than the resistance R2, the current IB will be much
smaller than I2 (current always seeks the path of least resistance) and I2 will be ap-
proximately equal to I1. If we accept the approximation that IB is essentially zero am-
peres compared to I1 or I2, then I1 ⫽ I2 and R1 and R2 can be considered series ele-

Figure 4.32 Partial-bias circuit

for calculating the approximate
base voltage VB.

160 Chapter 4 DC Biasing—BJTs

Approximate analysis:

Ri  R2 → I R 2  I b
( β + 1)R E  R 2 ⇒ β R E > 10R 2
If this condition applied then you can use approximation
method .
This makes IB to be negligible. Thus I1 through R1 is
almost same as the current I2 through R2.
Thus R1 and R2 can be considered as in series.
Voltage divider can be applied to find the voltage across
R2 ( VB)
 Approximate Analysis
When βRE > 10R2 , Then IB << I2 and I1 ≅ I2 :

R 2 VCC
VB = VE = VB − VBE
R1 + R 2
VE
IE =
RE
From Kirchhoff’s voltage law:
VCE = VCC − I C R C − I E R E
IE ≅ IC This is a very stable bias
VCE = V CC −I C (R C + R E ) circuit. The currents and
voltages are nearly
independent of any
variations in β.
 R2VCC
VB ⫽ ᎏ ᎏ (4.32)
R1 ⫹ R2

Since Ri ⫽ (␤ ⫹ 1)RE ⬵ ␤RE the condition that will define whether the approxi-
mate approach can be applied will be the following:
␤RE ⱖ 10R2 (4.33)

In other words, if ␤ times the value of RE is at least 10 times the value of R2, the ap-
proximate approach can be applied with a high degree of accuracy.
Once VB is determined, the level of VE can be calculated from
VE ⫽ VB ⫺ VBE (4.34)

and the emitter current can be determined from

VE
IE ⫽ ᎏᎏ (4.35)
RE

and ICQ ⬵ IE (4.36)

The collector-to-emitter voltage is determined by

VCE ⫽ VCC ⫺ ICRC ⫺ IERE
but since IE ⬵ IC,

VCEQ ⫽ VCC ⫺ IC (RC ⫹ RE) (4.37)

Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that ␤
does not appear and IB was not calculated. The Q-point (as determined by ICQ and
VCEQ) is therefore independent of the value of ␤.

Repeat the analysis of Fig. 4.31 using the approximate technique, and compare solu- EXAMPLE 4.8
tions for ICQ and VCEQ.

Solution
Testing:
␤RE ⱖ 10R2
(140)(1.5 k⍀) ⱖ 10(3.9 k⍀)
210 k⍀ ⱖ 39 k⍀ (satisfied)
R2VCC
Eq. (4.32): VB ⫽ ᎏ ᎏ
R1 ⫹ R2
(3.9 k⍀)(22 V)
⫽ ᎏᎏ
39 k⍀ ⫹ 3.9 k⍀
⫽2V

4.5 Voltage-Divider Bias 161

 Note that the level of VB is the same as ETh determined in Example 4.7. Essen-
tially, therefore, the primary difference between the exact and approximate techniques
is the effect of RTh in the exact analysis that separates ETh and VB.
Eq. (4.34): VE ⫽ VB ⫺ VBE
⫽ 2 V ⫺ 0.7 V
⫽ 1.3 V
VE 1.3 V
ICQ ⬵ IE ⫽ ᎏᎏ ⫽ ᎏᎏ ⫽ 0.867 mA
RE 1.5 k⍀
compared to 0.85 mA with the exact analysis. Finally,
VCEQ ⫽ VCC ⫺ IC(RC ⫹ RE)
⫽ 22 V ⫺ (0.867 mA)(10 kV ⫹ 1.5 k⍀)
⫽ 22 V ⫺ 9.97 V
⫽ 12.03 V
versus 12.22 V obtained in Example 4.7.
The results for ICQ and VCEQ are certainly close, and considering the actual vari-
ation in parameter values one can certainly be considered as accurate as the other.
The larger the level of Ri compared to R2, the closer the approximate to the exact so-
lution. Example 4.10 will compare solutions at a level well below the condition es-
tablished by Eq. (4.33).

EXAMPLE 4.9 Repeat the exact analysis of Example 4.7 if ␤ is reduced to 70, and compare solu-
tions for ICQ and VCEQ.

Solution
This example is not a comparison of exact versus approximate methods but a testing
of how much the Q-point will move if the level of ␤ is cut in half. RTh and ETh are
the same:
RTh ⫽ 3.55 k⍀, ETh ⫽ 2 V
ETh ⫺ VBE
IB ⫽ ᎏ ᎏ
RTh ⫹ (␤ ⫹ 1)RE
2 V ⫺ 0.7 V 1.3 V
⫽ ᎏᎏᎏ ⫽ ᎏᎏᎏ
3.55 k⍀ ⫹ (71)(1.5 k⍀) 3.55 k⍀ ⫹ 106.5 k⍀
⫽ 11.81 ␮A
ICQ ⫽ ␤IB
⫽ (70)(11.81 ␮A)
⫽ 0.83 mA
VCEQ ⫽ VCC ⫺ IC(RC ⫹ RE)
⫽ 22 V ⫺ (0.83 mA)(10 k⍀ ⫹ 1.5 k⍀)
⫽ 12.46 V

162 Chapter 4 DC Biasing—BJTs

 DC Bias with Voltage Feedback

Another way to
improve the stability
of a bias circuit is to
add a feedback path
from collector to
base.

In this bias circuit

the Q-point is only
slightly dependent on
the transistor beta, β.
 Base-Emitter Loop
From Kirchhoff’s voltage law:
-VCC + I′C R C +I B R B +VBE +I E R E = 0

Where IB << IC:

I' = I + I ≅ I
C C B C

Knowing IC = βIB and IE ≅ IC, the loop

equation becomes:
VCC – β I B R C − I B R B − VBE − β I B R E = 0

Solving for IB:

VCC − VBE
IB =
R B + β(R C + R E )
 Collector-Emitter Loop

Applying Kirchoff’s voltage law:

IE + VCE + I’CRC – VCC = 0

Since I′ C ≅ IC and IC = βIB:

IC(RC + RE) + VCE – VCC =0

Solving for VCE:

VCE = VCC – IC(RC + RE)