Advanced Microcontrollers

By
Mrs. Chaitali K Kulkarni
Assistant Professor,
Department of Electronics and Telecommunication Engineering
 Syllabus
Module. Details
no
1 Introduction to 16 bit microcontrollers
2 MSP430 GPIO, Timer and On-chip Peripherals
3 Introduction to 32bit microcontrollers
4 ARM LPC2148: Overview and interfacing
5 Mini project on MSP430/LPC 2148
 Recommended books
Sr. Name/s of Author/s Title of Book Name of
No. Publisher with
country

1 John Davies MSP430 Microcontroller Basics Newnes publishers,

USA
2 Chris Nagy Embedded Systems Design Using the Newnes publishers,
TI MSP430 Series USA
3 Andrew Sloss, Dominic ARM System Developer’s Guide Morgan Kaufmann
Symes, and Chris Wrigh Publisher

4 James A. Lang brid ge Professional Embedded Arm Wrox, John Wiley

Development Brand& Sons
Chapter 1
What is Microcontroller?
 Introduction to 16 bit microcontrollers

1.1
Features and Different families and nomenclature of
MSP430
1.2
Functional block diagram, pin out, memory, memory-
Mapped Input and Output, Clock Generator
 Introduction to MSP 430

Introduced in 1990s
Offers a wide variety of 16-bit MCUs with ultra-low-power
Integrated analog and digital peripherals for sensing and
measurement applications
Mixed Signal processing capability
It can be employed in several applications like spirometers, pulse
oximeters, blood pressure monitors and heartbeat monitors
 Architecture features
It follows RISC architecture
Von Neumann architecture
MSP430 controller consists of a 16-bit RISC CPU, clocking devices and
some other peripherals
Maximum code efficiency is obtained because of very powerful 16-bit
RISC CPU, 16- bit registers, constant generators etc.
The DCO offers switching between different modes with in 6µs
interval.
 CISC and RISC architecture
• Complex Instruction Set Computer
• Reduced Instruction Set Computer
 MSP430 generations/families
There are six general generations of MSP430 processors
Such as 3xx generation, 1xx generation, the '4xx generation, the '2xx
generation, the '5xx generation, and the '6xx generation
The 3xx and 1xx generations are limited to a 16-bit address space
 In the later generations this was expanded to include '430X'
instructions that allow a 20-bit address space
 Continued………..
• MSP430x1xxseries
It is the basic generation without an embedded LCD controller. They are
generally smaller than the '3xx generation. These flash- or ROM-based
ultra-low-power MCUs offer 8 MIPS, 1.8–3.6 V operation, up to 60 KB flash,
and a wide range of analog and digital peripherals.
• MSP430F2xx series
• The are similar to the '1xx generation, but operate at even lower power,
support up to 16 MHz operation, and have a more accurate (±2%) on-chip
clock that makes it easier to operate without an external crystal. These
flash-based ultra-low power devices offer 1.8–3.6 V operation. Includes the
very-low power oscillator (VLO), internal pull-up/pull-down resistors, and
low-pin count options.
Continued………..
MSP430G2xx series
The MSP430G2xx Value Series features flash-based Ultra-Low Power MCUs up to 16
MIPS with 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-
up/pull-down resistors, and low-pin count options, at lower prices than the MSP430F2xx
series.

• MSP430x3xx series
• It is the oldest generation, designed for portable instrumentation with an
embedded LCD controller. This also includes a frequency-locked loop oscillator
that can automatically synchronize to a low-speed (32 kHz) crystal. This
generation does not support EEPROM memory, only mask ROM and UV-
eraseable and one-time programmable EPROM Later generations provide only
flash memory and mask ROM options. These devices offer 2.5–5.5 V operation,
up to 32 KB ROM.
 Continued………..
.
MSP430x4xx series
These are similar to the '3xx generation, but include an integrated LCD controller,
and are larger and more capable. These flash or ROM based devices offers 8–16
MIPS at 1.8–3.6 V operation, with FLL, and SVS. Ideal for low power metering and
medical applications
MSP430x5xx series
They are able to run up to 25 MHz, have up to 512 KB flash memory and up to 66
KB RAM. This flash-based family features low active power consumption with up to
25 MIPS at 1.8–3.6 V operation (165 uA/MIPS). Includes an innovative power
management module for optimal power consumption and integrated USB.

Source: WWW.TI.COM
 Functional block diagram

CPU and its supporting hardware, including the clock generator

The emulation, JTAG interface and Spy-Bi-Wire are used to
communicate with a desktop computer when downloading a program
and for debugging
The main blocks are linked by the memory address bus (MAB) and
memory data bus (MDB)
These devices have flash memory, 1KB in the F2003 or 2KB in the
F2013, and 128 bytes of RAM
 Continued………………….
Six blocks are shown for peripheral functions (there are many more in
larger devices).
All MSP430s include input/output ports, Timer_A, and a watchdog
timer, although the details differ. The universal serial interface (USI)
and sigma–delta analog-to-digital converter (SD16_A) are particular
features of this device.
 The brownout protection comes into action if the supply voltage
drops to a dangerous level. Most devices include this but not some of
the MSP430x1xx family.
• MSP430F2003 and F201

• Source:MSP430 Microcontroller Basics by John Davies

 Memory

• memory address bus is 16 bits wide so there are 216 = 65,536 = 64K
• Uses Little endian style
 Brief description
• Special function registers: Mostly concerned with enabling functions of
Some modules and enabling and signaling interrupts from peripherals.
• Peripheral registers with byte access and peripheral registers with word
access:
• Provide the main communication between the CPU and peripherals.
Some must be accessed as words and others as bytes. They are grouped
in this way to avoid wasting addresses. If the bytes and words were
mixed, numerous unused bytes would be needed to ensure that the
words were correctly aligned on even addresses.
Continued……………..
• Random access memory: Used for variables. This always starts at
address 0x0200 and the upper limit depends on the size of the RAM
• Bootstrap loader: Contains a program to communicate using a
standard serial protocol, often with the COM port of a PC
• Information memory: A 256B block of flash memory that is intended
for storage of nonvolatile data
• Code memory: Holds the program, including the executable code
itself and any constant data
• Interrupt and reset vectors: Used to handle “exceptions,” when
normal operation of the processor is interrupted or when the device
is reset. This table was smaller and started at 0xFFE0 in earlier devices
 Central Processing Unit
It includes the arithmetic logic unit (ALU), which performs computation,
a set of 16 registers designated
R0–R15 and the logic needed to decode the instructions and
implement them.
The CPU can run at a maximum clock frequency fMCLK of 16MHz in the
MSP430F2xx family and some newer MSP430x4xx devices, and 8MHz in
the others.
•F
Fig: Registers in the
CPU of the MSP 430
 Continued………………….
• Program counter( PC):
• This contains the address of the next instruction to be executed

• Stack pointer, SP:

• When a subroutine is called, the CPU jumps to the subroutine,
executes the code there, then returns to the instruction after the call.
It must therefore keep track of the contents of the PC before jumping
to the subroutine, so that it can return afterward.
• This is the primary purpose of the stack.
 Continued………………….
• Status register (SR):
• This contains a set of flags (single bits), whose functions fall into three
categories. The most commonly used flags are C, Z, N, and V, which
give information about the result of the last arithmetic or logical
operation
• Constant generator:
• This provides the six most frequently used values so that they need
not be fetched from memory whenever they are needed. It uses both
R2 and R3 to provide a range of useful values by exploiting the CPU’s
addressing modes.
 Memory-Mapped Input and Output
• The MSP430, in common with most processors, uses memory-
mapped input and output
• This means that the ports simply appear to the CPU as particular
memory registers called peripheral registers
• Each port is associated with a byte and each bit corresponds to a pin
on the package (if implemented)
• These registers can be read, written, and modified in almost the same
way as simple registers in RAM.
Continued……………..
• Port P1 input, P1IN:
Reading returns the logical values on the inputs if they are
configured for digital input and output. This register is read-only.
It is also volatile, which means that it may change at a time that a program
cannot predict. This is of course why the input port is there, so that the MCU
can react to its surroundings. You want to know when a user presses a
button, for instance. This is a reminder that P1IN is not just a simple memory
and that some care is needed when programming in C
• Port P1 output, P1OUT:
Writing sends the value to be driven onto the pin if it is configured as a
digital output. If the pin is not currently an output, the value is stored in a
buffer and appears on the pin if it is later switched to be an output
• Port P1 direction, P1DIR: A bit of 0 configures the pin as an input, which is
the default. Writing a 1 switches the pin to become an output
 Clock Generator
• Basically the clock signal is a square wave whose edges trigger
hardware throughout the device so that the changes in different
components are synchronized
• A fast clock to drive the CPU, which can be started and stopped
rapidly to conserve energy but usually need not be particularly
accurate
• A slow clock that runs continuously to monitor real time, which must
therefore use little power and may need to be accurate
• These are the internal clocks, which are the same in all devices:
• Master clock, (MCLK)
Is used by the CPU and a few peripherals
• Subsystem master clock, (SMCLK)
Is distributed to peripherals
• Auxiliary clock, (ACLK)
Is also distributed to peripherals
Pin out of
MSP430
• VCC and VSS are the supply voltage and ground for the whole device
(the analog and digital supplies are separate in the 16-pin package)
• P1.0–P1.7, P2.6, and P2.7 are for digital input and output, grouped
into ports P1 and P2
• Timers pins
TACLK can be used as the clock input to the timer
TA0,TA1 can be either inputs or outputs
Continued……….
• ADC signals
• A0−, A0+, and so on, up to A4±, are inputs to the analog-to-digital
converter. It has four differential channels, each of which has negative
and positive inputs.
• VREF is the reference voltage for the converter
Continued……….
• ACLK and SMCLK are outputs for the microcontroller’s clock signals.
These can be used to supply a clock to external components or for
diagnostic purposes
• SCLK, SDO, and SCL are used for the universal serial interface, which
communicates with external devices using the serial peripheral
interface (SPI) or inter-integrated circuit (I2C) bus
• XIN and XOUT are the connections for a crystal, which can be used to
provide an accurate, stable clock frequency
• RST is an active low reset signal. Active low means that it remains high near
VCC
for normal operation and is brought low near VSS to reset the chip.
Alternative
• Notations to show the active low nature are _RST and /RST.
• NMI is the non maskable interrupt input, which allows an external signal to
• interrupt the normal operation of the program.
• TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used to
program and debug the device
• SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to
the usual JTAG connection that saves pins.
Spi bi wire and JTAG
• JTAG: (Joint test access group)
is an industry standard for verifying designs and testing printed circuit
boards after manufacture
Debugging
Storing firmware
Boundary scan testing
Continued……………..
• Spy-Bi-Wire is a serialised JTAG protocol developed by Texas
Instruments for their MSP430 microcontrollers
• The two connections are a bidirectional data output, and a clock
• The clocking signal is split into a period of three clock pulses, for each
clock pulse the TDI, TDO and TMS signals are passed on the micro
controller via the bidirectional data
Low-Power Modes of Operation of MSP430
• The MSP430 was designed from the outset for low power and this is
reflected in a range of low-power modes of operation
• SCG0, SCG1, CPUOFF, and OSCOFF in the status register can be used
to control
Active CPU, all clocks, and enabled modules are active, I ≈ 300A. The MSP430
mode starts up in this mode, which must be used when the CPU is required.
An interrupt automatically switches the device to active mode. The
current can be reduced by running the MSP430 at the lowest supply
voltage consistent with the frequency of MCLK; VCC can be lowered to
1.8V for fDCO = 1MHz, giving I ≈ 200A

LPM0 CPU and MCLK are disabled, SMCLK and ACLK remain active, I ≈ 85A.
This is used when the CPU is not required but some modules require a
fast clock from SMCLK and the DCO.
LPM3 CPU, MCLK, SMCLK, and DCO are disabled; only ACLK remains active; I
≈ 1A. This is the standard low-power mode when the device must
wake itself at regular intervals and therefore needs a (slow) clock.
It is also required if the MSP430 must maintain a real-time clock. The
current can be reduced to about 0.5Aby using the VLO instead of an
external crystal in a MSP430F2xx if fACLK need not be accurate
LPM4 CPU and all clocks are disabled, I ≈ 0.1A. The device can be wakened
only by an external signal. This is also called RAM retention mode
Waking from a Low-Power Mode
• An interrupt is needed to awaken the MSP430. The processor handles
an interrupt from a low-power mode in almost the same way as in
active mode. The only difference is that MCLK must first be started so
that the CPU can handle the interrupt;
• this replaces the first step when the CPU is active, which is to
complete the current instruction. MCLK is started automatically by
the hardware for servicing interrupts and requires no intervention
from the programmer.
•
Continued…………
• Remember that the status register is cleared when an interrupt is
accepted, which puts the processor into active mode. Similarly, MCLK
is automatically turned off at the end of the ISR if the MSP430 returns
to a low-power mode when the status register is restored
• Thus interrupts from low-power modes are written in exactly the
same way as those from active mode. This has the attractive feature
that low-power modes fit naturally into the structure of many
programs
Digitally Controlled Oscillator( DCO)
• One of the aims of the original design of the MSP430 was that it
should be able to start rapidly at full speed from a low-power mode,
without waiting a long time for the clock to settle
• Highly controllable RC circuit
• ACLK-32KHZ
• SMCLK-1MHZ
__enable _interrupt (); // Enable interrupts (intrinsic)
for (;;) { // Loop forever doing nothing
__low_power_mode_0 (); // Enter low power mode LPM0
} // Interrupts do the work
}
// ----------------------------------------------------------------------
// Interrupt service routine for Timer A channel 0
// Processor returns to LPM0 automatically after ISR
// ----------------------------------------------------------------------
#pragma vector = TIMERA0_VECTOR
__interrupt void TA0_ISR (void)
{
P2OUT ˆ= LED1|LED2; // Toggle LEDs
 Addressing Modes

• The MSP430 architecture has seven possibilities to address its

operands
• Four of them are implemented in the CPU, two of them result from
the use of the program counter (PC) as a register, and a further one is
claimed by indexing a register that always contains a zero (status
register)
• The single operand instructions can use all of the seven addressing
modes, the double operand instructions can use all of them for the
source operand, and four of them for the destination operand
In brief about ……………
• Double Operand Instructions
• Mnemonic Source, Destination

• Single Operand Instructions

• Mnemonic Destination
• Jumps
• The jump to the destination rather than its absolute address, in other
words the offset that must be added to the program counter.
Register Addressing
Indexed Addressing
Symbolic Mode
Indirect Register Addressing
Absolute Mode
SP-Relative Mode
Continued……………..
• Register Addressing
• The operand is contained in one of the registers R0 to R15
• This is the fastest addressing mode and the one that needs the least
memory

• Example:
• Add the contents of R7 to the contents of R8
• ADD R7,R8 ; (R7) + (R8) → (R8)
 • Indexed Addressing
• The address of the operand is the sum of the index and the contents
of the register used.
• The index is contained in an additional word located after the
instruction word.
• Example:
• Compare the 2nd byte of a table addressed by R5 with the low Byte
of R15. Result to the Status Register SR
• CMP.B 1(R5),R15 ; (R15) – (1 + (R5)) ;
• If the register in use is the program counter then two additional,
important addressing modes
Symbolic Mode (PC Relative)
• In this case the program counter PC is used as the base address, so
the constant is the offset to the data from the PC
• It is used by writing the symbol for a memory location without any
prefix

• Example
• mov.w LoopCtr ,R6 ; load word LoopCtr into R6 , symbolic mode
• LoopCtr= pc
 Absolute Mode
• The constant in this form of indexed addressing is the absolute
address of the data
• This is already the complete address required so it should be added to
a register that contains 0
• Absolute addressing is shown by the prefix & and should be used for
special function and peripheral registers, whose addresses are fixed in
the memory map

• Mov b & p1in ,r6 load byte p1 in into r6

 SP-Relative Mode
• The stack pointer SP can be used as the register in indexed mode like
any other
• SP points to (holds the address of) the most recently added word
• Suppose that we wanted to copy the value that had been pushed
onto the stack before the most recent one
• Example
• mov.w 2(SP),R6 ; copy most recent word but one from stack
• Indirect Register Addressing
• The register used contains the address of the operand
• The operand can be located anywhere in the entire memory space
(64K)

• Example:
• Add the byte addressed by R8 to the contents of R9
• ADD.B @R8,R9 ; ((R8)) + (R9) → (R9)
 Indirect Autoincrement Register Mode
• Again this is available only for the source and is shown by the symbol
@ in front of a register with a + sign after it
• Autoincrement is usually called post increment addressing because
many processors have a complementary predecrement addressing
mode, equivalent to *--c in C, but the MSP430 does not.
• An important feature of the addressing modes is that all operations
on the first address are fully completed before the second address is
evaluated
 Example
• mov.w @R5+,R6

• It uses the value in R5 as a pointer and automatically increments it

afterward by 1 if a byte has been fetched or by 2 for a word
• Suppose yet again that R5 contains the value 4 before this instruction
• A word is loaded from address 4 into R6 and the value in R5 is
incremented to 6 because a word (2 bytes) was fetched
 Immediate Mode
• This is a special case of autoincrement addressing that uses the
program counter PC.
• Example:

• mov.w @PC+,R6 ; load immediate word into R6

• The PC is automatically incremented after the instruction is fetched

and therefore points to the following word. The instruction loads this
word into R6 and increments PC to point to the next word, which in
this case is the next instruction
 Status Register
15-9 8 7 6 5 4 3 2 1 0
Reserved V SCG1 SCG0 OSC OFF CPU OFF GIE N Z C
Flags
• C:
• carry bit C is to flag that the result of an arithmetic operation is too
large to fit in the space allocated
• The carry flag also takes part in rotations and shifts. It is sometimes
used as temporary storage to pass a bit from one register to another
or to a subroutine
Continued…………….
• Z:
• The zero flag Z is set when the result of an operation is 0. A common
application is to check whether two values are equal
• They are subtracted and the Z bit is tested to see whether the result is
0

• N:
• The negative flag N is made equal to the msb of the result, which
indicates a negative number if the values are signed
• V:
• The signed overflow flag V is set when the result of a signed operation
has overflowed, even though a carry may not be generated.