FOLLOWING QUESTIONS ARE MEANT FOR SOME IDEA ABOUT THE TYPE OF QUESTIONS.
THE STUDENTS MUST NOT TAKE IT AS SUGGESTION/PROBABLE QUESTIONS. THESE ARE
SOME MODEL QUESTIONS
Short answer type questions:
1. Differentiate between static and dynamic branch prediction approaches.
2. What is fine-grained multithreading and what is the advantage and
disadvantages of fine-grained multithreading?
3. What is a VLIW processor? What are advantages and disadvantages of a VLIW processor.
4. What do you mean by write-through and write-back in cache memory.
5. Define and explain MIPS, MFLOPS, SPEC ratings. Compare the respective advantages and
disadvantages.
6. Compare and contrast scalar, vector and array processors.
7. Compare between RISC and CISC processor architecture
8. What do you mean by branch prediction buffer?
9. What do you mean by cache miss and cache hit?
10. Define and explain Gustafson’s law.
11. Compare and contrast superscalar and super-pipelined architecture
12. Differentiate between static and dynamic branch prediction approaches
13. State the key features of a superscalar architecture
14. What do you mean by in-order and out-of-order execution?
15. What are the dependencies of ILP?
16. List the levels of branch prediction
17. What are the block-replacement strategies used on a cache miss?
18. What is miss penalty in cache? What is the relation between memory-stall-cycle and miss penalty?
19. What is the distinction between instruction-level parallelism and machine parallelism?
20. What are the differences among sequential access, direct access, and random access?
21. What is the general relationship among access time, memory cost, and capacity?
22. How does the principle of locality relate to the use of multiple memory levels?
23. What are the differences among direct mapping, associative mapping, and setassociative
mapping?
24. For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and
define the three fields.
Long answer type questions:
25. What do you mean by ILP (Instruction level parallelism)? List and briefly explain the three types of
superscalar instruction issue policies. What are the key elements of a superscalar processor
organization? 2+8+5=15
26. Define speedup factor and efficiency for ‘equal duration model’ and ‘parallelcomputation with serial
section model’.
Consider an algorithm in which (1/a) th of the time is spent executing computations that must be done in a serial fashion.
What is the maximum speedup achievable by a parallel form of the algorithm?
5+5+5=15
27. A. When parallelizing an application, the ideal speedup is speeding up with the number of processors.
This is limited by two things: percentage of application that can be parallelized and the cost of
communication. Amdahl’s law takes account of the former not the latter. Answer the following
questions
i. What is the speeding up with N processors if 80% of the application is parallelizable, ignoring
the cost of communication
ii. What is the speedup with 8 processors, if, for every processor added, the communication
overhead is 0.5% of the original execution time?
Compare and contrast Amdahl’s law and Gustafson’s law
28. Define and explain the following term: pipeline throughput, pipeline efficiency, minimum average latency.
Design and explain an arithmetic pipeline for 6 bit integer multiplication using CSA and CPA. What is the use of
composite reservation table?
6(2X3) +6+2=15
29. Briefly describe the classification of pipeline processors. What do you mean by reservation table? Design and
explain a schematic diagram of the floating point division pipeline structure of IBM 360/91 where δ 32 hasbeen
considered as zero within the limit of the machine precision.
4+2+9=15
30. Explain with an example the method of multiplication of two 3x3 matrix using multifunction array pipeline.
Briefly describe the key design issues of a pipeline processor.
The inner loop of a certain program is completed to perform the following operations in sequence:
a. R0← (M1) (fetch)
b. R0← (R0) + (M2) (add)
c. R0← (R0) * (M3) (multiply)
d. M4 ← R0 (store)
Show that internal forwarding technique minimizes memory references for the above code.
31. A. For the following reservation table of a pipeline processor, give the forbidden list of avoided latencies F, the
collision vector, the state diagram, the MAL and all greedy cycles (time is on columns [t 0->t8]; states are on rows)
X X
X X X
X
X X
X X
b. A certain dynamic pipeline with the four segments S 1, S2,S3,S4 is characterized by the following reservation table
(time is on columns [t0->t7]; states are on rows)
X X
X X
X X
X X
i. determine latencies in the forbidden list F and the collision vector C
ii. determine the minimum constant latency L by checking the forbidden list
iii. draw the state diagram for this pipeline. Determine the MAL the maximum throughput of this pipeline
c. The following overlayed reservation table corresponds to a two-function pipeline:
A B B A
A B A
B A
B
List all four cross forbidden lists of latencies and corresponding combined cross-collision matrices. Draw the
state diagram for the two-functional pipeline
32. Briefly explain the different memory interleaving techniques. Compare those techniques with aleast
three features.
33. Briefly explain the Flynn’s classification of computer architecture. Describe MIMD array processor.
What are the differences between array processor and vector processors?
34. Explain Feng’s classification of computer architecture. Distinguish between the following
a. Data processing and information processing
b. Batch processing, multiprogramming, time sharing and multiprocessing
c. Parallelism and pipelining
35. Briefly describe the different hazards encountered by the pipeline processor. Suggest solution for the
following:
a. Data hazards
b. Control hazards
c. Branch hazards
36. Briefly describe the MIPS architecture and pipeline implementation on MIPS
