4Table of Contents VLSI Technology & Design (GTU)

Introduction to VLSI 1-1 to 1-114

Chapter 1:
Historical Perspective. ... 1-2
1.1
* ********* 1-5
1.2 Design Methodology.. ***''*

1.2.1 Full Custom Design.. .1-5

Semicustom Design..... 1-5

1.2.2
1.2.2.1 Standard Cell. 1-6
1.2.2.2 Gate Array.** ********* ***°*************** 1 6

1.2.2.3 Programmable Logic Devices (PLD). . 1-7

.1-7
1.3 Abstraction Levels in Digital Circuits..
****.... 1-8
Concepts of Regularity, Modularity and Locality.
1.4 VLSI Design Flow - Y- Chart Representation. 1-8
1.5
.. 1-11
1.6 Package Technology
Through Hole Package... 1-11
1.6.1
Surface Mount Package . 1-11
1.6.2
1-12
1.6.3 Contactless Packages.
Use of CAD Tools for Layout and Simulation. 1-12
1.7
1-14
4 1.8 University Questions and Answers

Process 2-1 to 2-83

Chapter 2: Semiconductor Manufacturing
2.1 Wafer Processing. .2-2
Crystal Growth . 2-2
2.1.1
2-4
2.1.2 Silicon Shaping..
. -4
2.1.2.1 Shaping...
Surface Grinding. .2-4
2.1.2.2
2.1.2.3 Slicing.. . 2-5
.2-5
2.1.3 Etching. 2-6
2.1.4 Polishing and Wafer Cleaning..
2-6
2.2 Oxidation..
2.2.1 Thermal Growth. .2-6
.2-9
2.2.2 CVD Oxides.
2-9
)2.3 Diffusion...
2.3.1 Constant Total Dopant... 2-10
2.3.2 Constant Surface Concentration Diffusions.. 2-12
2.4 2-13
lonImplantation.. 2-13
2.4.1 Ion Implantation Equipment....
2.5 2-14
Epitaxy.... . . 2-15
2.5.1 Vapour Phase Epitaxy.
2-16
2.5.2 Liquid Phase Epitaxy.
2-166
2.5.3 Molecular Beam Epitaxy.
2.6 Metallization.... 2-17
**

2.7 2-20
Lithography.
Mask Generation.
2-24
2.7.1
*****

2.8 2-26
Process to Pattern SiO

Jenil Thakkar
 Introduction to VLSI

Syllabus
Overview of VLSI design methodology, VLSI design flow, Design hierarchy, Concept
Package
of regularity, Modularity and Locality, VLSI design style, Design quality,
technology, Computer aided design technology.

Page No.
Content

1-2
1.1 Historical Perspective
1-5
1.2 Design Methodology
Circuits 1-7
1.3 Abstraction Levels in digital
1-8
1.4 Concepts of Regularity, Modularity and Locality
1-8
1.5 VLSI Design Flow Y- Chart Representation
-

1-11
1.6 Package Technology
Simulation 1-12
1.7 Use of CAD Tools for Layout and
1-14
1.8 University Questions and Answers

Jenil Thakkar
 1-2
Introduction to VLa Spee

Technology& Design
(GTU) hast
4PVLSI

1 . 1H i s t o r i c a lP e r s p e c t i v e :

Circuits. 1C is a complete microelectronic

microele diss
form for Integrated fabricated on extren

IC is the
abbreviated
components
are inseparably remely pro

active and passive

which both bec
circuit, in

single tiny chip of

silicon.
almost every aspect of
our daily life. The loC
today have touched
Integrated circuits
complex and flexible devices that ar
re
fabricate
made it possible to design and
technology has electronic active device technolog
for users. Until 1950's, the
highly intelligent and adaptable revolution in the field of electronics
tubes. There significant
was
was dominated by vacuum
Walter H. Brattain and John
after the invention of bipolar transistor by William B. Shockley,
of integrated
telephone laboratories. It was followed by the development
Bardeen of Bell
in two broad categories: Bipolar and MOS.
circuit(1C). IC technology is classified mainly
uses MOSFET as an
active device and MOS technology
Bipolar technology uses BJT as an
active device. IC classification is shown in Fig. 1.1.1.
Today IC technology is almost completely dominated by MOS process, the prime
reason being the scaling ability of MOSFET device and low power consumption.
Reasons for MOSFET being preferred over BITs is given below

Sr. No. MOS Technology BJT Technology

1.
High input impedance Low input impedance

2. Low power consumption

High power dissipation
3. High noise margin Low noise margin
4. Could be scaled down easily Limitation in scaling
5. High packing density Low packing density
Although MOSFETs has several benefits over
BJT, but BJTs are not still absolute the
reason is that BJTs are faster
than MOSFET. Thus /O
circuits usually utilize BJTs.
The basic concept behind
MOSFET transistor was
Insufficient knowledge
of materials and gate proposed by J. Lilienfield in 1925.
usability of the device for a long time. Once stability
problems, however delayed the practica
these were solved,
off in full swing in the MOS digital ICs started to take
early 1970's. The first
beginning of 1960. It practical MOS IC
implemented in pMOS only logic and
was was
implemented at the
such as calculators. First were used in
1974
microprocessor was introduced by intel in applications
(8080 processor). These processors were
1972 (4004
processor) ano
implemented in nMOS only logic,
Jenil Thakkar that has tne
 Introduction to VLSI
4PVLSI Technology &Design (GTU) 1-3

nMOS is electron that

speed advantage (faster pMOS only logic since current carrier in
than

has higher mobility

than current carriers holes of pMOS device).
of power
In late 1970's nMOS only logic started to suffer from the same problem
became
dissipation that has made bipolar logic unattractive. CMOS that consumes less power
the IC field. CMOS that consumes less power
prominent in the market and is still dominating
and
came prominent in the market and
is still dominating the IC field. Integration density
over few decades of time. Integrated
circuit has gone
performance of ICs has grown rapidly
LSI and VLSI.
through several generation since then : SSI, MSI,
scale integration
The of commercially available ICs are still called small
simplest types
(SS) and contain the equivalent of 1 to 20 gates
medium scale integration (MSI)
The next larger commercially available ICs are called
and contain the equivalent of about 20 to 200 gates. An
MSI IC typically contains a
functional building block, such as a decoder, register or counter.

2000 gates or more and include small

LSI ICs contain the equivalent of 200 to

memories, microprocessor etcC.

scale integration) is fuzzy and tends

The dividing line between LSI and VLSI (very large
of transistor count rather then gate count.
to be stated in terms
includes most
Any IC with over 1,000,000 definitely VLSI and
transistors is

microprocessor and memories as well as larger programmable

logic device.
Table below gives the level of integration in ICC
Table 1.1.1

SSI MSI LSI VLSI

Level of integration

Number of gates/chip 1-20 20-200 200-2000|>1,000,000 transistors

and later cofounder of India in 1960,
Gordon Moore, then with Fairchild corporation
that can be implemented per chip doubles every
predicted that the number of transistor
size and growing die size. Such progress is
1% years because of the shrinking feature
circuits on a single chip
highlighted by the in which number of transistor are integrated in
way
has grown.

Jenil Thakkar
42VLSI Technology &Design (GTU 1-4
Introduction to VLSI
Silicon 1C Technology

Bipolar MOS

NMOS PMOS CMOS

Fig. 1.1.1: Silicon IC technology classification

100M
64M
A Memory
(rate of increase =x 1.5/ year)
16
Microprocessor
10M (rate of increase =x 1.25/year)

4M
Pentium
1M DEC Alpha
1M
80486 68040
250K 80860

68030

80386
880200
100K
64K**** 80286
32A
68000
16K
8086
4K
8048
10K
8085
K1K 8080
8008 Source: Intel Corp.
4004
1K

70 75 80 85 90 95 2000

Year
Fig. 1.1.2: Level of integration versus time for memory chips and logic cnips
It can be observed
(Fig. 1.1.2) that in terms of transistor count, logic
significantly fewer transistors in any cnp
given year mainly due to large consumption of chip
for complex interconnects. Memory circuits be
are highly regular, and thus more celd
a
integrated with much less area of
interconnects. This has also been one of the ua easo

why the rate of increase of chip complexity (transistor count Is consistently higher
for memory circuits.
per chip) 1s CoO

To continue growth in this field it will be v e the

technology
both.
necessary to improve current ICs are
terms of scaling and processirg.
Although the large majority of the cu
Jenil Thakkar
 1-5 Introduction to VLSI*
4VLSI Technology &Design (GTU)
implemented in MOS technology, other technologies comc into play when very high
that combines
performance is concerned. As an example of this is BICMOS technology
on the same dic.
bipolar and MOS devices
1.2 esign Methodology:
uns
At an early stage of design, the designer needs to make the decision of which
available
methodology should be adopted for designing. The choice is normally based on

design time, cost and the functionality of the circuit. The basic options available to any
designer are: standard cells based design, full custom design and semi custom design.

1.2.1 Full Custom Design: 2 ml GTU-May 2012

In a full custom design layout, the geometry, orientation, and placement of every
transistor is done individually by the designer. Design productivity is usually very

low-typically a few tens of transistors per day per design. The entire mask is produced without
use of any library. Thus the development cost of such a design style is becoming prohibitively

high. Also time to market is more Thus, the concept of design reuse is becoming popular in
order to reduce design cycle time and development cost.

Advantages:
1. High performance

Disadvantages
1. High cost
2 Larger time to market

1.2.2 Semicustom Design GTU-May 2012

The second approach is the semi custom design methodology which reduces both cost
and timeto market but its performance is not better than full custom design. There are several
semi custom design methods like standard cell, gate array and programmable logic devices.
in
Semi-oustom
ea
be
Standard cell Gate array Programmable
ns

er
logic devices
PLI
SPLD CPLD FPGA

in Fig. 1.2.1: Semi-custom approach classification

are
Jenil Thakkar
VLSI Technology & Design(GTU) 1-6
Introduction to VLS
1.2.2.1 Standard Cell

In this design style, all of the commonly used

logic cells are developed, characterized
and stored in the standard
cell library. A typical library may contain a few hundred cell
including inverters, NAND gates, NOR gates, complex AO/OALgates, D-Latches
and counter. Each flip-flops
gate type can be implemented in several versions to provide adequate
driving capability for example; an inverter gate canhave standard size, double size
and
quadruple size so that the chip
designer can choose the proper size to achieve
speed and layout density. Designer sends the high current
schematic to the fabricator who
mask if the cells are from his prepares the
library. Hence it is captivated by the company.
the larger the cost.
Standard cell
Larger the library.
guarantees
that it will work.
Advantages:
More compact design (less routing area, improved
speed).
Sophisticated systems can be built easily.
Flexible to include digital as well as
analog functions.
Disadvantage:
Mask cost.
1.2.2.2 Gate Array:

A gate array circuit is a

prefabricated circuit with no particular function in
transistors and other active devices are which
placed (unconnected)) at regular
and manufactured on wafer.
Only masks for metallization need to be predefined positions
created.
VDD Interconnect
lines

Vss- 2

Fig. 1.2.2 : Gate array (2

input NAND gate)

Jenil Thakkar
4VLSITechnology &Design (GTU) 1-7 Introduction to VLSI*

Advantages
Reduces mask since fewer custom masks need to be
cost
produced.
Less time to market. Fastest logic implementation compared to full custom approach and
standard ccll approach.

Disadvantages
Size is fixed.
Number of transistors are fixed.
Metalheight is fixed (Supply and ground lines are fixed).
2 Metal layers are possible.
Low efficiency. Most of the transistors may not be in use.
Suitable for low production volumes.

1.2.2.3 Programmable Logic Devices (PLD):

There are varieties of IC's available in the market that could be programmed according
to user's Specification. Such IC's that allow it to be programmed after they are manufactured
are called programmable logic devices. Programmable logic device has an undefined function
at the time of manufacture and it behaves in a desired manner once it is programmed. PLD's
consists of configurable logics and flip-flops linked together with programmable interconnect.
There are few major programmable logic architecture available today that includes Simple
Programmable Logic Devices( SPLD), Complex Programmable Logic Devices( CPLD), Field
Programmable gate array( FPGA).
Advantages
Very short terms around time.
Suitable for fast prototyping and for small volume production ofas ASIC chips.

1.3 Abstraction Levels in Digital Circuitss

Time to market is of prime concern to every designer and this has lead to the rapid
evolution in the design technology. Designers need to cope up with time to market by being
adhered to rigid design methodologies and strategics that are friendlier to design automation.
The hierarchical design approach is adopted allowing reuse of cells thereby reducing design
effort and increasing the chances for first time working implementation. This is possible as
digital systems can be represented in different levels of abstraction. At each design level, the
internal details for complex module can be abstracted away and replaced by a black box view
or model. This model contains virtually all the information needed to deal with the block at the

next level of hierarchy. For example, once a designer has implemented for an adder module,
itS performance can be defined very accurately and can be captured in model. For all purpose,
can be considered a black box with known characterises. As it is not required for
the system
itdesigner to look inside this box; hence design complex is substantially reduced.
Jenil Thakkar
PVLSI Technology &Design (GTU) 1-8
Introduction to VLS
Typically used abstraction levels in digital circuit design are in
order of increasin
abstraction, the device, the circuit, gate, functional module
(example adder) and svstem le
(example processor). The circuit designer will never seriously consider
increasin
the solid state level
equation (device level) governing the behaviour phvsi
devices when of the designing a digital gate
1.4 Concepts of Regularity, Modularity and Locality

Hierarchy: GTU-Dec. 201

The use of hierarchy involves dividing
submodule repeatedly until the
a
complex design
into various modules
and
detail.
complexity of the submodule is at an
understandable level of
Regularity:
Using regularitythe designer
attempts to divide the hierarchy into a set of
building blocks. Example of regularity is the similar
cells such as a design of array structures consisting of
parallel multiplication
array, Regularity can exist at all levels
identical
For example, at the transistor
level, identical gate structures can be used or of abstraction.
optimized transistor in several places in using uniformly
a design.
Modularity:
Modularity in design means that the various functional
largersystem must have well defined functions and interfaces so blocks which makes up the
and tested that they be
separately, All the blocks can be combined easily at the end of can
implemented
to form a large the design process.
system.
Locality
Locality
ensures that the internals of
modules
This enables the outside world are not visible to any exterior interface.
and outputs.
to treat cach module as a black box with well defined
inputs
1,5 VLSI Design Flow Y- Chart
Representation
The design flow starts with GTU May 2011, Dec. 2011
a given set of
specification requirements. The system is
designed as per the specifications. At the end when the desired
or

design has to be modifíed and

re-checked several times specifications are not met,
until it meets the
the
specificatious. required
The design description for a VLSI circuit may be
namely:
described in forms of three domains
1. Behavioural domain
2. Structural domain
Physical domain.

Jenil Thakkar
VLSI Technology& Design(GTU) 1-9 Introduction to VLSI

Structural
domain Behavioral
domain

9 System
Algorithm /program
FTEDT Finite
state machine Fm
Register/
adder Modula
descripon PA
Logic gate
Boolean
equation
FM
Transistopr

Masks

Cell
placement

Modules
placement
C m c

PM Cmn PhysicalChip
domain floor plan

Fig. 1.5.1: Y - Chart representation of design flow

Fig. 1.5.1 shows the design flow for most logic chips, using design activities on three
different axes (domains) which resemble the letter Y.
The design flow begins with the specifications that describe the behaviour of the target
chip. The architecture of the system is correspondingly than dcfined and is henceforth mapped
onto the chip surface by floor planning.
In the, next lower level of abstraction the design in the behavioural domain can be
defined using finite state machines (FSMs) which are structurally implemented with functional
modules such as registers and combinational logic units. Using automatic module placement

Jenil Thakkar
2VLSI Technology& Design (GTU 1-10
Introductition to
feature of CAD tools these modules then
Vis
are
geometrically placed onto the chip
chip
followed by routing. surface. It i
The next evolution starts with module description. Individual modules are then
implemented using logical gates, which are placed and interconnected by usina
a
placement and routing program. The last evolution involves description of gates using hool.cel
equations that is
implemented by employing transistors at transistor level olea
gates and finally mask is generated which is implementation
required by the various processing steps. in t
fabrication process. A simplified view of this h
design flow is shown in Fig. 1.5.2.

Design
Specification

Architecture design/
System level design

Gate level design

C Circuit level design

HDLcoding

Simulation

Verification

Meets
No Specification?

Yes

Fabrication

Fig. 1.5.2: Simplified view of

VLSIdesign flow

Jenil Thakkar
 Introduction to VLSI
4VLSITechnology& Design (GTU) 1-11

1.6 Package Technology:

IC's contain several active and passive components on a single tiny silicon
semiconductor that are inseparable from each other. The circuits contained in IC's differ in
their complexity. It may vary from simple circuit comprising of two transistors to very
complex circuits consisting of millions of transistors. Whatever may be the complexity of the
IC, all IC packages are categorized into 3 types : Through hole, surface mount and contact-less

packages.
1.6.1 Through Hole Package:
In through hole package one or more rows of leads or pins are available that are
designed to go through the holes of printed circuit board (PCB) and are soldered underneath.
Body of through hole packages are made from either plastic or ceramic. The number of leads
on a through hole package may vary from 3 to 64. IC package having single row of leads is
called single in line package (SIP), while with two rows of leads is called dual in line package
(DIP). DIP's are mostly encountered in educational institutes. IC having grid arrangement of
lead is called as pin grid aray (PGA). They offer more number of pin counts (more than
400 pins ) and are better than DIP's in terms of thermal conductivity and power dissipation
characteristics.

Celeron
pGA
uP

(a) DIP Package (b) PGA Package

Fig. 1.6.1

1.6.2 Surface Mount Package:

Unlike through hole package, the leads of surface mount packages are mounted directly
on the surface of printed circuit boards (PCBs). They do not go through holes or fit into a

socket. The leads of surface mount packages except ball grid array (BGA) are bent at an angle
near the foot to aid soldering to the surface of the circuit board. Ball grid array packages on the

other hand do not have solderable leads instead their leads are ball shaped and are arranged in
a grid pattern underneath the package. BGA IC's are held against contacts on the board with

pressure. They are constructed from either plastic or ceramic and have leads varying from 56
to 1312.

Jenil Thakkar
4PVLSITechnology &Design (GTU) 1-12
Introduction to V
Surface mount package are made up of ceramic,
plastic, metals or combination off
three and has leads ranging from I to 1312. Small outline
package (SO) with a single rowa
leads and flat package (FP), which has leads on 2 or 4 sides of
the
ow
package are common tvoe
of surface mount
packages.

Fig. 1.6.2 : surface mount package

1.6.3 Contactless Packages:

ContactlesS packages do not come into direct physical contact with a circuit board. They
are scanned to provide information to other devices wirelessly. They have no leads and are
made only with plastic bodies.

1.7 Use of CAD Tools for Layout and Simulation :

Pattern generator
Design entry
files

Design verification
DRC, Simulation etc. Produce masks

Pattem generation For each layer

wafer processing
deposit, expose, develop
IC design process etch, bake

Package

Test

IC fabrication process
Fig. 1.7.1: IC design and fabrication process
Jenil Thakkar
 Introduction to VLSI
4VLSI Technology &Design(GTU) 1-13

Complexity of IC"'s is increasing exponentially over the years (Moore's Law).

Designing error free VLSI circuits that consist of nillions of transistors per chip is far beyond

human ability requires computer to check layout, circuit performance, process design etc.
and
VLSI circuit
So, computers are used extensively to aid in the design and optimization process.
designers are normally given a set of design rules based on a particular technology and a
technology files in order to do their work.
Thedesign phase involves
Design capture:
The behaviour and/ or siructure of a system may be captured in a hardware description
language such as VHDL, verilog etc. The system could also be entered through schematic
capture using schematic editors.

Synthesis
Synthesis is the process of converting the high level description of the system into lower
gate level circuit. ie. Once the system specification is entered designer need not bother for
selecting and interconnecting at the gate level. Only the library and optimization criteria
power or speed) need to be specified and the synthesis tool does the remaining. Most
synthesis tools support a large range of FPGA and CPLD device vendors.

Layout
The physical layout may be generated either automatically from a high level description
or may be hand edited using a layout editor (MAGIC or MICROWIND).

Design verification:
To verify the design simulation is done. Simulation tool is a software timing program
used to verify the functionality or timing of the circuit. Various simulators may be used at the
logic, circuit or layout level (SPICE, IRSIM etc.). These simulators perform functional, timing
and other tests. Layout needs to run through get another type of verification tool called Design
Rule Checker (DRC) which checks for design rule violations. Design rules specify various
layout rules such as the optimum width and spacing between various layers.

Pattern generation
It generates the database suitable for manufacturer. Translators are available to translate
the design from a standard layout format like Callech Intermediae Format (CIF) to the pattern
generation format. That is, on completion of design and layout, the system design is contained
in system layout files in intermediate form. These files are converted to pattern generator files,
to be sent to the mask making facility. Once the masks are manufactured, the semi conductor

Jenil Thakkar
 1-14
VLSI Technology &Design(GTU) Introduction to VLS
device fabrication starts which after several processing steps becomes a fully phveia

component.
ysical 1C
Based on a typical VLSI design work flow, a good VLSI CAD tool must sn
pport the
followingfeatures
1) Physical design layout editor, circuit schematics design.
2) Physical verification Must contain DRC, circuit extractor, capability to plot ut
and /or display for visual checking.
3) Behavioural verification.

Oral Questions
Q. 1 Why MOS technology has become dominant technology in IC market. (Section 1.1)
Q.2 Differentiate full custom and semicustom design approach. (Section 1.2)
Q.3 Explain VLSI design flow. (Section 1.5)
Q. 4 What is importance of CAD tools in VLSI. (Section 1.7)
a.5 Differentiate between LSI, MSI and VLSI circuit. (Section 1.1)
Q.6 State Moore's law. (Section 1.1)
1.8 University Questions and Answers

May 2011
Q. 1 Discuss VLSI design flow in detail. (Section 1.5)
(4 Marks)
Dec. 2011
Q. 2 Explain VLSI design flow using Y-chart. (Section 1.5) (7 Marks)
May 2012
Q. 3 Answer the following : Compare Semi-custom and
Full custom VLSI design style
(Section 1.2.1 and 1.2.2)
(3% Marks)

Dec. 2012
Q. 2 Discuss following approaches (with examples) used to reduce complexity of
design: 1. Hierarchy, 3. Modularity, and 4. Locality. (7 Marks)
(Section 1.4)
O00
Jenil Thakkar