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Latching and Unlatching

The document discusses the SET and RESET instructions in ladder logic and function block diagram (FBD) programming for a Siemens S7-1200 PLC. It provides examples of how SET sets an output to 1 and RESET sets an output to 0. An exercise shows how to use SET and RESET to latch and unlatch two outputs using inputs in ladder logic and FBD. Wiring and I/O configuration for the S7-1200 CPU are also shown.

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OJ AC
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517 views12 pages

Latching and Unlatching

The document discusses the SET and RESET instructions in ladder logic and function block diagram (FBD) programming for a Siemens S7-1200 PLC. It provides examples of how SET sets an output to 1 and RESET sets an output to 0. An exercise shows how to use SET and RESET to latch and unlatch two outputs using inputs in ladder logic and FBD. Wiring and I/O configuration for the S7-1200 CPU are also shown.

Uploaded by

OJ AC
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Siemens S7-1200

CPU 1212C AC/DC/Relay

Bit Logic Operations


• SET and RESET Instructions

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• Exercise Example

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Bit Logic Instructions in LAD – SET and RESET (1)
SET Instruction
Symbol

When S (Set) is activated, then the data value at the OUT address is
set to 1. When S is not activated, OUT is not changed.

RESET Instruction

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Symbol
When R (Reset) is activated, then the data value at the OUT address
is set to 0. When R is not activated, OUT is not changed.

Example
SET RESET OUT
I0.0 I0.1 Q0.0
0 0 Last State
0 1 0
1 0 1
1 1 0
Exercise Example in Ladder
Write a Logic to latch two outputs Q0.0 & Q0.1 with I0.0 and unlatch it using I0.1
Ladder Solution PLC Wiring

X10

X11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3

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L1 N L+ M 1M 2M 0 1

0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
120-240 24VDC Analog
24VDC Inputs
VAC Inputs

SIEMENS
SIMATIC
S7-1200 Relay Outputs

Required Condition X1 P1 1L 2L

0.0
0.1
0.2
0.3

0.4
0.5
X12
1 2 3 4 5 6 7 8
I0.0 I0.1 Q0.0 Q0.1
Profinet (LAN)
0 0 Last State Last State Ethernet Port

0 1 0 0
1 0 1 1
1 1 0 0
Bit Logic Instructions in FBD- SET & RESET (1)
SET Instruction
Symbol

When S (Set) is activated, then the data value at the OUT


address is set to 1. When S is not activated, OUT is not
changed.
RESET Instruction

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Symbol
When R (Reset) is activated, then the data value at the OUT
address is set to 0. When R is not activated, OUT is not
changed.

Example
SET RESET OUT
I0.0 I0.1 Q0.0
0 0 Last State
0 1 0
1 0 1
1 1 0
Exercise Example in FBD
Write a Logic to latch two outputs Q0.0 & Q0.1 with I0.0 and unlatch it using I0.1
FBD Solution Required Condition
I0.0 I0.1 Q0.0 Q0.1
0 0 Last State Last State
0 1 0 0
1 0 1 1

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1 1 0 0

PLC Wiring

X10

X11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3

L1 N L+ M 1M 2M 0 1

0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
120-240 24VDC Analog
24VDC Inputs
VAC Inputs

SIEMENS
SIMATIC
S7-1200 Relay Outputs

X1 P1 1L 2L

0.0
0.1
0.2
0.3

0.4
0.5
X12
1 2 3 4 5 6 7 8

Profinet (LAN)
Ethernet Port
Bit Logic Instructions in LAD – SET and RESET (Field)
SET Instruction
Symbol

When SET_BF is activated, a data value of 1 is assigned to "n“ bits


starting at address tag OUT. When SET_BF is not activated, OUT is not
changed
RESET Instruction

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Symbol

RESET_BF writes a data value of 0 to "n" bits starting at address tag OUT.
When RESET_BF is not activated, OUT is not changed.

Example SET RESET OUT 1 OUT 2 OUT 3


I0.0 I0.1 Q0.0 Q0.1 Q0.2
0 0 Last State Last State Last State
0 1 0 0 0
1 0 1 1 0
1 1 0 0 0
Exercise Example in LADDER
1. Write a Logic to latch three outputs Q0.0 ~ Q0.2 with I0.0 and unlatch all using I0.1

Ladder Solution PLC Wiring

X10

X11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3

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L1 N L+ M 1M 2M 0 1

0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
120-240 24VDC Analog
24VDC Inputs
VAC Inputs
Required Condition SIEMENS
SIMATIC
I0.0 I0.1 Q0.0 Q0.1 Q0.2
S7-1200 Relay Outputs
0 0 Last State Last State Last State
X1 P1 1L 2L

0.0
0.1
0.2
0.3

0.4
0.5
0 1 0 0 0

X12
1 2 3 4 5 6 7 8
1 0 1 1 1
Profinet (LAN)
1 1 0 0 0 Ethernet Port
Bit Logic Instructions in FBD- SET & RESET (Field)
SET Instruction
Symbol

When SET_BF is activated, a data value of 1 is assigned to "n“ bits


starting at address tag OUT. When SET_BF is not activated, OUT is not
changed
RESET Instruction

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Symbol

RESET_BF writes a data value of 0 to "n" bits starting at address tag OUT.
When RESET_BF is not activated, OUT is not changed.

Example SET RESET OUT 1 OUT 2 OUT 3


I0.0 I0.1 Q0.0 Q0.1 Q0.2
0 0 Last State Last State Last State
0 1 0 0 0
1 0 1 1 0
1 1 0 0 0
Exercise Example in FBD
Write a Logic to latch three outputs Q0.0 ~ Q0.2 with I0.0 and unlatch all using I0.1
FBD Solution Required Condition
I0.0 I0.1 Q0.0 Q0.1 Q0.2
0 0 Last State Last State Last State
0 1 0 0 0
1 0 1 1 1

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1 1 0 0 0

PLC Wiring

X10

X11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3

L1 N L+ M 1M 2M 0 1

0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
120-240 24VDC Analog
24VDC Inputs
VAC Inputs

SIEMENS
SIMATIC
S7-1200 Relay Outputs

X1 P1 1L 2L

0.0
0.1
0.2
0.3

0.4
0.5
X12
1 2 3 4 5 6 7 8

Profinet (LAN)
Ethernet Port
Bit Logic Instructions in FBD- SET Dominant & RESET Dominant
SET/ Reset Flip Flop Truth Table
Symbol SET RESET OUT 1
I0.0 I0.1 Q0.0
SR is a reset dominant latch where 0 0 Last State
the reset dominates. If the set (S) 0 1 0
and reset (R1) signals are both
1 0 1
true, the value at address Q0.0 will

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1 1 0
be 0.

Reset/ SET Flip Flop Truth Table


Symbol RESET SET OUT 1
I0.0 I0.1 Q0.0
RS is a set dominant latch where 0 0 Last State
the set dominates. If the set (S1) 0 1 1
and reset (R) signals are both
1 0 0
true, the value at address Q0.0
1 1 0
will be 1.
Exercise Example in FBD
Write a Logic to latch the Motor Q0.0 with I0.0 (PB) and include two emergency switches
I0.2 and I0.3 to unlatch it. Which Flip Flop you will use?
PLC Wiring Required Condition
Contacts Description
I0.0 Start the Motor
I0.2 Emergency Stop

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I0.3 Emergency Stop

X10

X11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3

L1 N L+ M 1M 2M 0 1 Q0.0 Motor

0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
120-240 24VDC Analog
24VDC Inputs
VAC Inputs

SIEM ENS FBD Solution


SIMATIC
S7-1200 Relay Outputs

X1 P1 1L 2L

0.0
0.1
0.2
0.3

0.4
0.5
X12
1 2 3 4 5 6 7 8

Pr ofinet (LAN)
Ether net Por t
What did we learn in this lesson?

 The SET & RESET Bit instruction is used to latch


or unlatch only one bit.
 The SET & RESET Field instruction is used to
latch or unlatch multiple bits.
 In SET/RESET Flip Flop the OUTPUT will be
FALSE if both the inputs are HIGH

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 In RESET/SET Flip Flop the OUTPUT will be
TRUE if both the inputs are HIGH

Thank you
Get copy of this presentation
in the course!

Code and Compile


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