COM-3011 [20 MHz –3 GHz] Receiver /

SDR Platform

Key Features  Selectable internal 100 MHz / external

ADC sampling clock (to synchronize
multiple receivers).
 [20-3000 MHz] receiver
 Software-programmable channel filter
 Input level: bandwidth: 2 KHz to 40 MHz
-65 dBm to –20 dBm (<200 MHz)
-60 dBm to –20 dBm (<1 GHz)  ARM processor and FPGA can be used for
-55 dBm to –20 dBm (<3 GHz) custom software-defined radio applications.
 Frequency synthesizer can be tuned over o LPC1759 120 MHz 32-bit ARM
entire range by steps of 1Hz or less. Cortex-M3.
 External 10 or 20 MHz frequency reference o Xilinx Spartan-6 LX16 FPGA.
can be used to achieve higher frequency
stability.  ComScope –enabled: key internal
signals can be captured in real-time and
 8 preset frequencies for fast (<2ms) local
displayed on host computer.
oscillator frequency tuning.
 SMA connectors. Single 5V supply.
Connectorized 3”x 3” module for ease of
prototyping.

For the latest data sheet, please refer to the ComBlock

web site: www.comblock.com/download/com3011.pdf.
These specifications are subject to change without notice.

For an up-to-date list of ComBlock modules, please

refer to http://www.comblock.com/product_list.html .

COM-3011 (shown without shield)



MSS • 845-N Quince Orchard Boulevard • Gaithersburg, Maryland 20878 • U.S.A.

Telephone: (240) 631-1111 Facsimile: (240) 631-1676 www.ComBlock.com
© MSS 2017 Issued 7/24/2017
 LPF
power detection gain control bandwidth

IF1 125 MHz IF2 25 MHz DATA_I_OUT(11:0)

40 MHz
Bandwidth
RF IN
A/D
10bit
20 - 3000 MHz
DATA_Q_OUT(11:0)

Frequency
Synthesizer 100 MHz
Oscillator 90deg
0deg

20 MHz
Oscillator NCO

optional freq.
higher-stability selection
external frequency
reference (10/20 MHz)

Functional block diagram

USB

32-bit
frequency selection
120 MHz
ARM
gain control Cortex-M3 AGC
processor IN
power detection 40-pin 2mm connector

Image-rejection
BPF
DATA_I_OUT
RF IN
Xilinx
A/D
XC6SLX16
10bit
FPGA DATA_Q_OUT
20 - 3000 MHz

EXT_ADC_CLK
Frequency
Synthesizer

100 MHz
Oscillator
20 MHz
Oscillator

frequency selection
optional
higher-stability
external frequency
reference (10/20 MHz)
Hardware block diagram

Electrical Interface

Inputs / Outputs
2
 internal ADC clock)
Inputs Definition AGC_IN Input signal to control the analog
RF_IN 20 - 3000 MHz. gain prior to A/D conversion. Can
SMA male connector (J3). be digital (pulse-width
50 Ohm impedance. modulated) or analog.
Receiver sensitivity:
-65 dBm (< 200 MHz) The purpose is to use the
-60 dBm (< 1 GHz) maximum dynamic range while
-55 dBm(<3 GHz) preventing saturation at the A/D
Maximum input (linear): converter. 0 is the maximum gain,
-20 dBm +3V is the minimum gain.
Maximum input (no damage):
+10 dBm Without any subsequent module,
EXT_FREQ_REF Optional input. External 10 or 20 the COM-3011’s gain is set at its
MHz frequency reference for maximum and may thus saturate.
frequency synthesis.
Sinewave, clipped sinewave or Control Lines Definition
squarewave. PLL_STROBE Low-voltage (3.3V / 0V) TTL
SMA male connector (J8). input control.
Input is AC coupled. Used to increment the modulo-
Minimum level 0.6Vpp. Nfreq frequency pointer (where
Maximum level: 3.3Vpp. Nfreq is defined in Register 67) in a
round-robin sequence.
EXT_ADC_CLK Optional input. Externally Rising edge triggered.
supplied Analog-to-Digital Minimum pulse width: 10 sec.
converter sampling clock. Connector J6 Pin A3.
Enabled or disabled by software USB Monitoring & Mini-USB connector
control. LVTTL 0 – 3.3V. Control Type AB
Selecting sampling rates less than Full speed / Low Speed
half the baseband filter bandwidth Power Interface 4.9 – 5.25VDC. Terminal block.
may result in aliasing. Power consumption is 700 mA.
EXT_LO Optional input. Externally
generated RF carrier for
frequency down-conversion, thus Absolute Maximum Ratings
bypassing the internal frequency
synthesizer. Enabled or disabled Supply voltage -8V min,
by moving two SMT capacitors +6.5V max
soldered on the board. AC EXT_FREQ_REF, -0.3V min, +3.6V max
coupled, 50 Ohm impedance. PLL_PROBE,
EXT_ADC_CLK, AGC_IN
Input level: -10 to
+ 10 dBm. RF_IN, EXT_LO +10 dBm
Digital Output Definition
Signals
DATA_I_OUT[11:0] In-phase baseband signal.
12-bit digital samples.
Unsigned (straight offset binary)
0x800 = 0V value
0xFFF= most positive value
0x000 = most negative value
DATA_Q_OUT[11:0] Quadrature baseband signal.
Same format as DATA_I_OUT.
CLK_OUT Digital clock. 40 or 100
Msamples/s if internal selection,
otherwise EXT_ADC_CLK’s
frequency.
Read the samples at the rising
edge of CLK_OUT.
ADC_CLK_OUT ADC clock (100 MHz when using

3
Configuration
An entire ComBlock assembly comprising several
ComBlock modules can be monitored and
controlled centrally over a single connection with a
host computer. Connection types include built-in
types:
 USB (requires a mini-USB cable)
or connections via adjacent ComBlocks:
 USB
 TCP-IP/LAN,
 Asynchronous serial (DB9)
 PC Card (CardBus, PCMCIA).

The module configuration is stored in non-volatile

memory.

Configuration (Basic)
The easiest way to configure the COM-3011 is to
use the ComBlock Control Center software
supplied with the module on CD. In the ComBlock
Control Center window detect the ComBlock
module(s) by clicking the Detect button, next
click to highlight the COM-3011 module to be
configured and click the Settings button to
display the Basic Settings window shown below.
Basic Settings Window
Up to eight frequencies can be stored within each
module at any given time. The current frequency is
selected by an index in the range 0 to 7.
Frequencies are expressed in Hz.
Configuration (Advanced)
Alternatively, users can access the full set of
A basic frequency hopping scheme can be enabled configuration features by specifying 8-bit control
by registers as listed below. These control registers can
(a) enabling the external trigger be set manually through the ComBlock Control
(b) entering the number of frequency hopping Center or by software using the ComBlock API (see
steps in the round-robin arrangement. www.comblock.com/download/M&C_reference.pdf)
For example, by specifying 4 steps, the receiver
center frequency will follow the following index All control registers are read/write.
sequence: 0,1,2,3,0,1,2,3,0,1, etc., the index being
incremented at the rising edge of each external Undefined control registers or register bits are for
PLL_STROBE pulse. backward software compatibility and/or future use.
They are ignored in the current firmware version.

Programmers developing custom applications

(using the ComBlock API instead of the supplied
ComBlock control center graphical user interface)
should know that frequency changes are enacted
upon (re-)writing to the last register (REG71).

4
 1 = ADC sampling rate (100
Parameters Configuration Msamples/s typ.)
RF to IF1 Preselected frequency translation 0. REG6(3)
frequency Valid range 137.5 MHz – 4.4 GHz, Frequency Use to switch local oscillator
translation expressed in Hz. selection frequency among preselected values.
f0 Range 0 through 7
Select a frequency f0 such that either REG6(7:5)
fRF – f0 = 125 MHz (approxim.) or RF to IF1 Seven additional preselected frequency
fRF + f0 = 125 MHz frequency translations from RF to IF1.
where fRF is the RF input signal center translation x = 1 through 7
frequency. fx Same format as f0.
REG(3+4*x): bits 7:0 (LSB)
125 MHz is the IF1 band-pass filter REG(4+4*x): bits 15:8
center frequency. REG(5+4*x): bits 23:16
REG(6+4*x): bits 31:24 (MSB)
This only includes the RF frequency Number of RF Each time a PLL_STROBE pulse is
synthesizer. An additional frequency frequencies Nfreq received, the frequency pointer
translation is performed digitally by an in the scanning increments modulo Nfreq.
list
NCO, as specified by control registers Nfreq is in the range 1 – 8.
REG36 and above. REG35: bit 7:0.
IF2 to Baseband Eight preselected NCO frequency
REG0: bit 7:0 (LSB) frequency translations from IF2 to baseband..
REG1: bit 15:8 translation x = 0 through 7
REG2: bit 23:16 fncox Format: fncox * 232 / fADC where fADC is
REG3: bit 31:24 (MSB) the fADC sampling clock frequency (100
LPF bandwidth Programmable low-pass filter (one- MHz internal or TBD external)
sided) bandwidth expressed in KHz.
Valid range 1KHz – 20 MHz. Double REG(36+4*x): bits 7:0 (LSB)
this value to get the total bandwidth. REG(37+4*x): bits 15:8
REG4: (LSB) REG(38+4*x): bits 23:16
REG5: (MSB) REG(39+4*x): bits 31:24 (MSB)
Internal/External Enable or disable the RF frequency AGC loops 0 = open loops. RF and baseband gains
RF carrier synthesizer. are fixed.
generation 0 = internal RF carrier generation. 1 = local RF and baseband AGC loops.
1 = external RF carrier . An Out-of-range conditions at the RF
unmodulated RF signal must be mixer, A/D converter and digital
supplied through J6. The RF frequency output are detected and corrected
settings are thus ignored. A minor locally, without involving any external
hardware modification must be module.
performed prior to using the external 2 = external baseband AGC loop.
RF carrier. See below for details. Follow-on module (demodulator for
REG6(0) example) detects out-of-range
Internal/External Select the external ADC sampling conditions and adjusts the baseband
ADC sampling clock EXT_ADC_CLK or the internal gain accordingly using the AGC_IN
clock fclk 100 MHz sampling clock. pin. The RF AGC loop is still local as
Selecting sampling rates less than half per 1.
the baseband filter bandwidth may REG69(7:6)
result in aliasing. RF Gain Initial receiver RF gain (before the
0 = internal 100 MHz ADC clock AGC takes over). 12-bit.
1 = external ADC clock. 0 for the minimum gain, 4095 for the
REG6(1) maximum gain.
External controls Enable or disable the PLL_STROBE REG68: bits 7:0 (LSB)
enabled/disabled external control on the J6 connector. REG69(3:0): bits 11:8
0 = external control disabled Baseband Gain Initial receiver baseband gain (before
1 = external control enabled the baseband AGC takes over). 16-bit.
REG6(2) 0 for the minimum gain, 0xFFFF for
Output sampling Output sampling rate at the 40-pin the maximum gain.
rate connector. REG70: (LSB)
0 = 40 MSamples/s REG71: (MSB)
5
 Test Points
Monitoring Test points are provided for easy access by an
Parameters Monitoring oscilloscope probe.
PLL lock status Indicates the RF synthesizer lock Test Point Definition
(PLL_LOCK) status: locked to the frequency PLL_LOCK Frequency synthesizer PLL lock status.
reference (1) or unlocked (0). Active low: ‘1’ when locked. This
SREG0 bit 0 information is also available in status
FPGA programmed ‘1’ when the FPGA is programmed register SREG0
with a valid configuration file. CLK_REF 20 MHz frequency reference clock (after
SREG0 bit 1 doubling when supplying a 10 MHz
Power good for ‘1’ when the supply voltage is external frequency reference)
various internal within a normal range. See ADC_IN IF1 (125 MHz intermediate frequency)
supply voltages schematics for supply voltages signal prior to A/D conversion.
names. The nominal amplitude is 0.5Vpp when
the AGC loop is closed with the following
SREG0 bit 3: D_+3.3V demodulator (COM-1001,1202,1418,1027
SREG0 bit 4: AMP1_+3V or equivalent).
SREG0 bit 5: A_+4.75V TP1 / Selected ADC sampling clock.
(unreliable) ADC_CLK
SREG0 bit 6: CLK_+3.3V DONE ‘1’ indicates proper FPGA configuration.
SREG0 bit 7: SYNTH_+3.3V
Current receiver RF Range 0 – 4095
gain (RF AGC loop) SREG1: bits 7:0 LSB
SREG2(3:0): bits(11:8)
Current receiver Range 0 – 65535
baseband gain SREG3: LSB
(baseband AGC SREG4: MSB
loop)
RF power detection Range 0 – 4095
at the RF mixer SREG5: bits 7:0 LSB
SREG6(3:0): bits(11:8)
Sampling clock Sampling clock frequency fclk in
frequency Hz, measured every second using
the internal 20 MHz or external
10/20 MHz frequency reference.
SREG7: LSB
SREG8
SREG9
SREG10: MSB

6
ComScope Monitoring
Key FPGA internal signals can be captured in real-
time and displayed on a host computer using the
ComScope feature of the ComBlock Control
Center. The COM-3011 signal traces and trigger are
defined as follows:
Trace 1 signals Format Nominal Capture
sampling length
rate (samples)
1: I signal after 8-bit fclk 512
frequency signed
translation to
baseband and
image-rejection
filtering

Trace 2 signals Format Nominal Capture

sampling length
rate (samples)
1: Q signal after 8-bit fclk 512
frequency signed
translation to
baseband and
image-rejection
filtering

Trace 3 signals Format Nominal Capture

sampling length
rate (samples)
1: Input signal 8-bit fclk 512
(Intermediate signed
frequency IF2 25
MHz)
A/D converter
output
Trigger Signal Format
N/A 1-bit

The sampling rate fclk is the ADC sampling rate.

The ComScope user manual is available at
www.comblock.com/download/comscope.pdf.

ComScope Window Sample: showing ADC samples

(green), and output samples after final frequency
down-conversion to baseband (blue = I, red = Q)
7
Operations the R43 and R38 pads respectively, as illustrated
below:
Receiver Center Frequency
The receiver translates the received signal
frequency to (near-zero) baseband in three steps:
1) A programmable RF frequency synthesizer
fed to a RF mixer translates the signal
center frequency from RF to a + or - 125
MHz intermediate frequency (IF1).
2) The IF1 signal undergoes IF undersampling
at the Analog-to-Digital converter, in effect
translating the center frequency to a 25
MHz intermediate frequency (IF2). The
frequency translation equals the ADC
sampling clock frequency (100 MHz when
using the internal ADC sampling clock).
3) A programmable numerically controlled
oscillator further translates the IF2 signal
frequency to baseband.

In order to minimize noise when an external RF

Internal vs External Frequency carrier is used, it is recommended to switch off the
Reference built-in RF frequency synthesizer by software (see
control register REG6(0)).
An external 10 or 20 MHz frequency reference can
be used when the user application requires high
frequency stability. In this case, simply connect a AGCs
10 or 20 MHz sinewave, clipped sinewave or
square wave to the J8 connector. Detection is The COM-3011 comprises two independent AGC
automatic, thus no configuration change is needed. loops:
Upon removal of the external frequency reference  The RF AGC loop’s objective is to prevent any
signal, the COM-3011 reverts to the internal saturation up between the RF input and the A/D
frequency reference. converter. It automatically adjusts the RF gain
based on two sensors: power detection at the
RF mixer (i.e. before the IF bandpass filter) and
Internal vs External ADC sampling out-of-range condition at the A/D converter (i.e
clock after the IF bandpass filter).
The source for the Analog to Digital converter  The baseband AGC loop’s objective is to
clock can be selected to be internal (fixed 100 maximize the amplitude of the digital output
Msamples/s) or external (up to 105 Msamples/s) by samples while avoiding saturation. It
software command. automatically adjusts the digital baseband gain
based on out-of-range condition at the digital
output (i.e. after the baseband low-pass filters).
External RF carrier
Phase-synchronized operation of multiple units is
possible by suppling an externally-generated RF FPGA Customization (optional)
carrier for frequency upconversion via the J6 The FPGA can be reprogrammed with user-specific
EXT_LO SMA connector. This configuration is not code. Use of the FPGA is at the user’s discretion.
software configurable: the RF carrier path is altered The FPGA is pre-programmed with all basic
by moving the R42 and R39 resistors 90 degrees to functions described in this specification document.

8
FPGA: Xilinx Spartan-6 XC6SLX.
Performance
When generating the bit file using Xilinx ISE, the
bitstream compression option (-g Compress) must
be enabled.
Internal Clock Reference
The internal crystal performance is as follows:
Flash memory size limitation: one FPGA  tolerance:  10 ppm max @25C
configuration, maximum size 425984 bits.  temperature stability (-10C to +60C):  50 ppm
max
FPGA configuration time at power up: < 150 ms  aging: 5ppm/year max @25C

Band Pass Filter

The A/D converter is preceeded by a band-pass
filter centered at 125 MHz. The one-sided -3 dB
cutoff frequency is 25 MHz. Within the [0-20 MHz]
band, the maximum in-band ripple ± 0.2 dB.

10

0
dB (Out/In)

-1 0

-20

-30

-40
40 60 80 1 00 1 20 1 40 1 60 1 80 200 220 240 260

freq, MHz
COM-3011 anti-aliasing bandpass

Phase Noise
Typical phase noise of the RF synthesizer is:
fRF =300 MHz
-76 dBc/Hz @ 1 KHz, typ.
-84 dBc/Hz @ 10 KHz, typ.
fRF =3 GHz
-67 dBc/Hz @ 1 KHz, typ.
-73 dBc/Hz @ 10 KHz, typ.

Other Specifications
Input noise figure: 7 dB typ.
LO Out-of-band spectral spurious lines: < - 55 dBc.
Spurious signals at RF_IN input (other than LO):
< -80 dBm

9
Timing
Output Connector J5
Output 40-pin (2 rows x 20) 2mm male connector.

B1
A1
Output data is generated at
the falling edge of CLK_OUT CLK_OUT
DATA_I_OUT(11) DATA_I_OUT(10)
DATA_I_OUT(9) DATA_I_OUT(8)
DATA_I_OUT(7) DATA_I_OUT(6)
DATA_I_OUT(5) GND
CLK_OUT DATA_I_OUT(4) DATA_I_OUT(3)
DATA_I_OUT(2) DATA_Q_OUT(11)
SAMPLE_CLK_OUT DATA_Q_OUT(10) DATA_Q_OUT(9)
DATA_OUT DATA_Q_OUT(8) DATA_Q_OUT(7)
DATA_Q_OUT(6) GND
DATA_Q_OUT(5) DATA_Q_OUT(4)
Best time to read data DATA_Q_OUT(3) DATA_Q_OUT(2)
is at the rising edge ADC_CLK_OUT AGC_IN
of CLK_OUT EXT_ADC_CLK DATA_I_OUT(1)
DATA_I_OUT(0) GND
DATA_Q_OUT(1) DATA_Q_OUT(0)
Mechanical Interface
corner (3.000", 3.000") M&C TX M&C RX
5VDC Power Mounting hole
Mounting hole Terminal
J1
(2.840", 2.840") GND
(0.160",2.840") Block, 90 deg

B20
A20
Mini-USB
GND +5V
J3 J2 JP1
B1
A1

RS-232 male
J8
(0.280", 1.750") header

Connector J7
RF_IN A1 pin (2.900", 2.250")
SMA male, 90deg Output A
J5 2 rows x 20 pin

Top view
DONE
male, 90 deg
12-pin (2 rows x 6) 2mm through-hole connector.

B1
A1
EXT_LO ADC_IN
B20

PLL
A20

Optional external LO CLK GND

LOCK
SMA female edge REF
GND
(0.160",0.160") J7 J8
EXT
B1 B6
A1 A6
REF PLL_STROBE
2 rows x 6 pin 10/20 MHz Ref Input Mounting hole M&C TX M&C RX
Corner(0.000", 0.000") male, 90 deg SMA female edge (2.840", 0.160")

GND
Mounting hole diameter: 0.125"
B6
A6

A1 pin height: 0.039"

Maximum height 0.500"

Pinout

Mini USB Connector, J1

The COM-3011 is a USB device with a mini type
AB connector. (G = GND)

5V D- D+ ID G
1

10
I/O Compatibility List
(not an exhaustive list)
Output
COM-1800 FPGA (XC7A100T) +
ARM + DDR3 SODIMM socket + GbE
DEVELOPMENT PLATFORM 1
COM-1806 Wideband signal capture and playback2
COM-1202 PSK/QAM/APSK modem
COM-1518 DS Spread-Spectrum demodulator 22 Mchips
COM-1827 Continuous phase demodulator (MSK, etc)
COM-2001 Dual D/A converter (baseband)
COM-1524 Channel emulator

Configuration Management
This specification is to be used in conjunction with
FPGA VHDL software revision 4.
ARM microcontroller software revision 3.01.

ComBlock Ordering Information

COM-3011 [20-3000 MHz] receiver / SDR

platform

ECCN: 5A991.g

MSS • 845-N Quince Orchard Boulevard•

Gaithersburg, Maryland 20878-1676 • U.S.A.
Telephone: (240) 631-1111
Facsimile: (240) 631-1676
E-mail: sales@comblock.com

1
98-pin to 40-pin adapters to interface with other
Comblocks are supplied free of charge. Please let us
know about your interface requirements at the time of
order.
2
98-pin to 40-pin adapters to interface with other
Comblocks are supplied free of charge. Please let us
know about your interface requirements at the time of
order.

11