Lecture 19:
SRAM
Outline
Memory Arrays
SRAM Architecture
– SRAM Cell
– Decoders
– Column Circuitry
19: SRAM CMOS VLSI Design 4th Ed. 2
Memory Arrays
19: SRAM CMOS VLSI Design 4th Ed. 3
Array Architecture
2n words of 2m bits each
If n >> m, fold by 2k into fewer rows of more columns
Good regularity – easy to design
Very high density if good cells are used
19: SRAM CMOS VLSI Design 4th Ed. 4
6T SRAM Cell
Cell size accounts for most of array size
– Reduce cell size at expense of complexity
6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
Read:
– Precharge bit, bit_b
– Raise wordline
Write:
– Drive data onto bit, bit_b
– Raise wordline
19: SRAM CMOS VLSI Design 4th Ed. 5
SRAM Read
Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
Read stability
– A must not flip
– N1 >> N2
19: SRAM CMOS VLSI Design 4th Ed. 6
SRAM Write
Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
Writability
– Must overpower feedback inverter
– N2 >> P1
19: SRAM CMOS VLSI Design 4th Ed. 7
SRAM Sizing
High bitlines must not overpower inverters during
reads
But low bitlines must write new value into cell
19: SRAM CMOS VLSI Design 4th Ed. 8
SRAM Column Example
Read Write
19: SRAM CMOS VLSI Design 4th Ed. 9
SRAM Layout
Cell size is critical: 26 x 45 λ (even smaller in industry)
Tile cells sharing VDD, GND, bitline contacts
19: SRAM CMOS VLSI Design 4th Ed. 10
Thin Cell
In nanometer CMOS
– Avoid bends in polysilicon and diffusion
– Orient all transistors in one direction
Lithographically friendly or thin cell layout fixes this
– Also reduces length and capacitance of bitlines
19: SRAM CMOS VLSI Design 4th Ed. 11
Commercial SRAMs
Five generations of Intel SRAM cell micrographs
– Transition to thin cell at 65 nm
– Steady scaling of cell area
19: SRAM CMOS VLSI Design 4th Ed. 12
Decoders
n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory
– Build AND from NAND or NOR gates
Static CMOS Pseudo-nMOS
19: SRAM CMOS VLSI Design 4th Ed. 13
Decoder Layout
Decoders must be pitch-matched to SRAM cell
– Requires very skinny gates
19: SRAM CMOS VLSI Design 4th Ed. 14
Large Decoders
For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
19: SRAM CMOS VLSI Design 4th Ed. 15
Predecoding
Many of these gates are redundant
– Factor out common
gates into predecoder
– Saves area
– Same path effort
19: SRAM CMOS VLSI Design 4th Ed. 16
Column Circuitry
Some circuitry is required for each column
– Bitline conditioning
– Sense amplifiers
– Column multiplexing
19: SRAM CMOS VLSI Design 4th Ed. 17
Bitline Conditioning
Precharge bitlines high before reads
Equalize bitlines to minimize voltage difference when
using sense amplifiers
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Sense Amplifiers
Bitlines have many cells attached
– Ex: 32-kbit SRAM has 128 rows x 256 cols
– 128 cells on each bitline
tpd ∝ (C/I) ΔV
– Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)
– Discharged slowly through small transistors
(small I)
Sense amplifiers are triggered on small voltage
swing (reduce ΔV)
19: SRAM CMOS VLSI Design 4th Ed. 19
Differential Pair Amp
Differential pair requires no clock
But always dissipates static power
19: SRAM CMOS VLSI Design 4th Ed. 20
Clocked Sense Amp
Clocked sense amp saves power
Requires sense_clk after enough bitline swing
Isolation transistors cut off large bitline capacitance
19: SRAM CMOS VLSI Design 4th Ed. 21
