simplifying Learning

CM O S I C L ay o u t D e s i g n C o u r s e O u t l i n e
To proliferate the cutting edge technologies to Indian Engineers
with detailed overview, imparting in-depth skills to make Indian
engineers ready for tomorrow’s Semiconductor Industry.

Tr a i n i n g o n
CMOS IC
Layout
Design

At XXXXXXXXX
Team is highly skilled at :

 CMOS Layout
 Analog Layout
 Standard Cell Layout Design
 Memory Layout technology
consulting
 Physical Design
 Physical Verification etc .,.
technology
co n s u l t i n g
 Training solutions that work for your Career Development.
N U R T U R I N G M I N D S T O G R E AT TA L E N T S - R E A D Y F O R C O R E S E M I C O N I N D U S T R Y

Flexible training model for today’s engineers

on Custom IC Layout Design L A B E X E R CI S E
Project 1 : Design Standard Cell Library
T RA I N I N G S OL U TI O N S CO U RS E O U T L I N E
• CMOS CUSTOM LAYOUT. Course structure involves revisiting the topics Implement Schematic, Layout and Clean -
IC Design Flow
• PHYSICAL DESIGN. needed for impoving the skill-set required for
Custom IC Design Flow - Topologies         
UP the DRC and LVS for Below Cells with
• DESIGN VERIFICATION. entering core semiconductor industry.
• PHYSICAL VERIFICATION Custom Layout Considerations Fixed Heights.
Basic MOSFET
. P RE - RE Q U I SI T E S MOS Sharing, MOS Variant Structures with
MOSFET Operation – NMOS, VT, Regions of INV 1X, 2X, 4X, 8X, 16X, 32X, NAND1X,
• CMOS FUNDAMENTALS BackGate, MOS Fingers, Multipliers, Effects of
Operation, Drain Current equations - different 2X, 4X, NOR1X, 2X, 4X, AOI, OAI, D-
• VLSI FUNDAMENTALS MOS Sharing - R, C, LOD, Inverter Layout
regions, Mobility - Channel Resistance
• LINUX BASIC COMMANDS Charter plan for Designing Standard Cell Design LATCH - P, N, D-FLOP
• BASIC SPICE COMMANDS (OPTIONAL) Geometric Scaling
Library Cleaning up DRC Violations Project 2 : Implementation of OTA
CMOS Inverter Design
CMOS Failure Mechanisms
Inverter Circuit – Explaination, Inverter Project 3 : Implementation of LDO /
DRC Clean up, Latch-UP, GuardRings, EM, ESD,
Switching Characteristics -  RC Modelling, Comparator
SH, Deep N-Well, NAC / ANT, Cross Talk,
High2Low and Low2High Time, Switching Time,
Parasitics - Different Types
Maximum Switching Frequency, Miller Effect,
Analog Layout Concepts
Propagation Delay, VTC, Gain, MOS as an
Variations in Polysilicon Etch Rate, Gradient
Amplifier
Effects, LOD, WPE, STI, Interdigitization Layout
Power Dissipation : Leakage Power & Dynamic
Techniques, Common Centroid Layout
Power
Techniques
CMOS Fabrication Process Flow
Need for dummies, WPE in detail, Rules for
Wafer Processing, Oxide, PolySilicon, Doping &
matching, Shielding
ION Implantation, Metal Layers, MOSFET
Dimensions, Design Rules & its Types

W E ’ V E W O R K E D W I T H A DI V E R S E C U S TO ME R B A S E. H O W C A N W E H E L P Y O U ?