Verification of New IP in Legacy SOC using SystemVerilog/VMM

Paul Howard, TI Jiri Prevratil, Synopsys Praveen Devulapalli, Synopsys

This Thi presentation is b t ti i based on d the Electronic Design article Verify SoCs Faster And More Predictably With SystemVerilog and Constrainted Random Stimuli
Authors: Asad Khan, TI Paul Howard, TI Jiri Prevratil, Synopsys Praveen Devulapalli, Synopsys y g Henry Angulo, TI David Kimble, TI

Purpose p
Present a strategy for verifying new IP in a 2nd gy y g generation SOC.
Identify the verification challenges Migration path using SystemVerilog VMM to support Constrained random & directed stimuli F Functional coverage ti l Reference model automated checking

Outline
Verification Challenges g Verification Methodology Selection Legacy vs New Environment Implementation Phases TSB43DA42 VMM Verification Environment Functional Coverage and Test cases Conclusions

Device Description p

Verification Challenges g
New packet cipher feature: p p
Data paths supported either packet encryption or packet decryption. Variations in packet format, length, and timing created a large set of corner cases cases. Debugging cipher defects in silicon or FPGA would be gg g p extremely time-consuming. Most effective way to debug : SIMULATION ff S O

Verification Challenges (cont.)

Legacy environment used traditional verification methodology:
Verilog language Custom bus-functional models (BFMs) for each interface Scoreboards for end-to-end checking end to end Large number of directed test cases to achieve code coverage

C Capabilities d i d to verify new f bili i desired if features

constrained random and functional coverage driven methodology support for reference model integration pp g provisioning for verification IP (VIP) support block level to top level test back compatibility industry standard methodology concise test cases

Verification Methodology Selection

Methodology shift f f from a f fragmented f format to a more unified f f format

Verification Methodology Selection (Cont.) (Cont )

Goals
Test new packet cipher functionality using constrainedrandom testing with functional coverage. Add new verification methodology without starting from scratch. Improve run-time performance run time performance. Minimize risk of adopting new methodology and tools. Bottom Line - Meet Schedule

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Verification Methodology Selection (Cont.) (Cont )

Plan
Maintain legacy environment as-is to support existing functionality. d Create 2nd DV environment to test new cipher functionality Adopt SystemVerilog and VMM Leverage building-blocks from legacy environment building blocks Build a foundation for future derivative products Small, but non-trivial opportunity to evaluate new non trivial methodology without being in critical-path.

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Verification Methodology Selection (Cont.) (Cont )

Tests

Targeted Testbench T dT b h

Transactor

Self Check

Checker

Driver

Monitor

Assertions DUT

DUT Monitor

Bus Protocol

System RFM

Func ctional Co overage

VMM Approach Supports the targeted Testbench functionality

Generator

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Verification Methodology Selection (Cont.)

Tests Verification IP

Targeted Testbench T dT b h

VMM Approach in Action

Transactor

Self Check

Checker

Driver

Monitor

Assertions DUT

DUT Monitor

Bus Protocol

System RFM

Func ctional Co overage

Generator

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Legacy Environment g y
Legacy Test Environment that needed update for the new Enhanced Security IP during integration was as follows:
Packet Drives

CFG Reg Model

Score Board
HSDI_1 BFM

Test Support Tasks

HSDI PKT GEN OBJ HSDI PKT GEN OBJ

HSDI_2 BFM

Directed Test Cases

DUT
1394 PKT GEN OBJ EXCPU PKT GEN OBJ 1394 BFM

TSB43DA42

EXCPU BFM

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Legacy Environment Mapped to VMM

Legacy Test Environment components mapped to VMM Layers
Packet Drives

Mapped to VMM Transaction Layer

Mapped to VMM Test, Scenario, and Transaction Layers

Test Support pp Tasks

CFG Reg Model

Score Board B d
HSDI_1 BFM

HSDI PKT GEN OBJ

HSDI PKT GEN OBJ Directed Test Cases 1394 PKT GEN OBJ EXT CPU PKT GEN OBJ

HSDI_2 BFM

TSB43DA42
1394 BFM

DUT

EXCPU BFM

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Implementation Phases p
Phase I Simple HSDI external loop back test p p
Defined/validated the basic HSDI packet data class generation in the VMM starter kit Mapped the legacy verilog packet generation object tasks to VMM transactors (HSDI only) Run a simple loop back with the data generated by constrained random VMM generator

Phase II HSDI internal loop back test p

Enabled DUT configuration Used Legacy 1394 BFM to drive back the data to second HSDI port S This is the first test exercising the new cipher IP block

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Implementation Phases p
Phase III Complete environment p
Extension of scoreboard interface to incorporate the new IP functionality Integrated both c and verilog predictors Added 1394 VMM generation
Enhanced Security Verilog Cipher Predictor
Enhanced Security C-Model For KEYOUT compares

Enhanced Security Verilog Inverse Cipher Predictor

SystemVerilog INTERFACE

DUT

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Implementation Phases p
Phase IV Functional Coverage & Regressions g g
Add functional covergroups Created regression environment Ran regressions with multiple seeds and collected the coverage Ran directed random testcases to close coverage directed-random

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TSB43DA42 (Enhanced Security) VMM Verification Environment: I

TEST

DATA CLASS
MPEG

systest_sv.sv

Generator

Master
(HSDI)

Scoreboard

Monitor

I N T E R F A C E

HSDI0 BFM

HSDI1 BFM

L HSDI O Port0 O P B A HSDI C Port1 K

F I F O

1394 Port

CPU BFM

DUT

vmm_env

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TSB43DA42 (Enhanced Security) VMM Verification Environment: II

TEST

DATA CLASS
MPEG

systest_sv.sv

Generator

Master
(HSDI)

Scoreboard

Monitor

I N T E R F A C E

HSDI0 BFM

HSDI Port0

HSDI1 BFM

HSDI Port1

F I F O

1394 BFM (LPBK)

1394 Port

CPU BFM

DUT

vmm_env

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TSB43DA42 (Enhanced Security) VMM Verification Environment: III

TEST

DATA CLASS
MPEG 1394 etc

systest_sv.sv

Config Class I N T E R F A C E
HSDI0 BFM

Generator

Master
(HSDI, 1394)

HSDI1 BFM

L HSDI O Port0 O P B A HSDI C Port1 K

F I F O

Scoreboard +
C and Verilog Models

1394 BFM (LPBK)

1394 Port

Monitor

CPU BFM

DUT

vmm_env

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TSB43DA42 (Enhanced Security) VMM Verification Environment: IV

TEST

DATA CLASS
MPEG 1394 etc

systest_sv.sv

Config Class I N T E R F A C E
HSDI0 BFM

Generator

Master
(HSDI, 1394)

HSDI1 BFM

L HSDI O Port0 O P B A HSDI C Port1 K

F I F O

Scoreboard +
C and Verilog Models

1394 BFM (LPBK)

1394 Port

Monitor Coverage

CPU BFM

DUT

vmm_env

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Functional Coverage and Testcases g

Example of Functional Coverage collected over 300 random seed runs using VCS URG tool is as shown:

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Functional Coverage and Testcases

//---------- Constraints for 1394 iso-cip mpeg packet ------------------constraint iso_cip_mpeg_pkt::test_specific { // iso receive path select iso_path_select inside {[ISO_PATH_0 : ISO_PATH_1]}; // iso-cip mpeg class class_mpeg inside {[3:7]};

The final Test Case looked like a control panel where constraints can be changed without deep knowledge of implementation details as shown:

// Mpeg cell1 ctl field constraints adaptation_field_control1 adaptation field control1 inside {[2'b00 : 2'b11]}; {[2 b00 2 b11]}; transport_scrambling_control1 inside {[2'b00 : 2'b11]}; adaptation_field_length1 inside {[0 : 182 ]}; pid1 == 0; // Mpeg cell2 ctl field constraints adaptation_field_control2 inside {[2'b00 : 2'b11]}; transport_scrambling_control2 transport scrambling control2 inside {[2 b00 : 2'b11]}; {[2'b00 2 b11]}; adaptation_field_length2 inside {[0 : 182 ]}; pid2 == 0; // Mpeg cell3 ctl field constraints adaptation_field_control3 inside {[2'b00 : 2'b11]}; transport_scrambling_control3 inside {[2'b00 : 2'b11]}; adaptation_field_length3 p _ _ g inside {[0 : 182 ]}; {[ pid3 == 0; // Mpeg cell4 ctl field constraints adaptation_field_control4 inside {[2'b00 : 2'b11]}; transport_scrambling_control4 inside {[2'b00 : 2'b11]}; adaptation_field_length4 inside {[0 : 182 ]}; pid4 == 0; // Mpeg cell5 ctl field constraints adaptation_field_control5 inside {[2'b00 : 2'b11]}; transport_scrambling_control5 inside {[2'b00 : 2'b11]}; adaptation_field_length5 inside {[0 : 182 ]}; pid5 == 0; };

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Conclusions
Legacy test environments need methodology upgrade g y gy pg to eliminate directed test overload, and to boost efficiency SystemVerilog and VMM proved to be valuable in upgrading the legacy test environment without starting from scratch t ti f t h SystemVerilog random generation and structured VMM implementation allowed parallel runs to achieve 100% functional coverage DPI allowed direct integration of C Reference Models in SystemVerilog

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Conclusions (cont.) ( )
Project Summary
Verification of new cipher functionality effectively found corner-case defects. Functional coverage provided effective test plan tracking After verification, FPGA emulation ran smoothly 1st silicon showed no issues. Verification was completed on-schedule.

Future Plans
Ad t S t V il & VMM on f t Adopt SystemVerilog future projects j t Leverage available VIP cores Utilize same verification approach for other derivative devices.

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Questions & Answers