OZ813

Ultra High Efficiency Dual DC-DC Controller

FEATURES GENERAL DESCRIPTION
• Dual DC-DC SMPS controller with OZ813 is a DC/DC controller specially developed to design
integrated drivers power supplies for next generation microprocessors, their
• Two constant ripple-current controllers peripherals and chipsets. OZ813 steps down the high battery
• Constant ripple-current control allows voltage to low output voltages in the range of 0.5V to 2.75V.
optimum inductor size High efficiency, DC accuracy and excellent transient response
• High full load efficiency; up to 94% make OZ813 suitable for supplying low voltage CPU
• High light load efficiency; >85% at 100mA peripherals, chipset cores, and graphics processors. OZ813
• Vout accuracy; 1% or better has two independent constant ripple-current buck controllers
• Input voltage; from 3V to 26V with powerful integrated drivers able to drive output currents
up to 15A.
• Output voltage – adj. from 0.5V to 2.75V
Voltage Feed-Forward compensation assures high rejection of
• Output current - up to 15A
input voltage transients typically occurring when the AC
• Independent adapter is plugged in or removed.
o Power Good signals Over Voltage Protection (OVP) acts when the output voltage
o ON/SKIP signals exceeds the set voltage by more than 125mV. This protection
• Soft-Start at start-up condition is latched and initiates a ramp down of the output
• Soft-stop at shutdown voltage.
• Voltage Feed-Forward Compensation Under Voltage Protection (UVP) acts when the output voltage
• User adjustable operating frequency falls below the set voltage by more than 133mV. This
• Dynamic voltage change support protection condition is latched and initiates a ramp down of
• Output Protection: the output voltage.
o Latched Over Voltage Protection After an OVP or UVP event, the ON/SKIP pin should be
o Latched Under Voltage Protection toggled or VDDA/VIN cycled to restart the circuit.
o Valley type Over Current Both outputs are protected against overload by individual,
Protection valley current type, cycle-by-cycle (Over Current Protection)
• Input Protection: OCP circuits.
o Under Voltage Lock Out on VDDA The Under Voltage Lock Out circuit monitors both, VDDA and
o Under Voltage Lock Out on VIN VIN and lets the controller operate only if VDDA > 4.3V and
VIN > 2.5V.
APPLICATIONS The Power Good signal is high as long as the output voltage
Power Supplies for Notebook CPU and Peripherals
is within +125mV/-133mV of the set voltage. At startup the
ORDERING INFORMATION output voltage ramps up in a controlled manner with a typical
Part Number Temp Range Package slew rate of 1V/ms and at shutdown the output voltage is
OZ813LN o o
0 C to 85 C QFN24 Lead-Free ramped down in a controlled manner with the same slew rate.

SIMPLIFIED APPLICATION DIAGRAM PIN DIAGRAM

VSET2

HDR2
PGD2
CS2N

CS2P

LX2

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VSET1

PGD1

LX1

HDR1
CS1N

CS1P

07/31/08 OZ813-SF-v1.3 Page 1

Copyright © 2004-2008 by O2Micro All Rights Reserved
Patents #6,965,221; 7,202,650; 6,844,710; 7,098,642 and others pending
 OZ813
PIN DESCRIPTION
No. Name I/O Type Description
Enables Channel 2 operation.
If VON/SKIP2 > 0.6V, the Vout2 voltage ramps up to the voltage set on
VSET2 pin with a slew rate of 1V/ms. If VON/SKIP2 > 2.1V the controller
enters skip mode of operation. If both ON/SKIP1 and ON/SKIP2 pins are
1 ON/SKIP2 I Digital
< 0.4V the chip is disabled and enters a very low consumption mode <
1µA. To re-enable the controller the voltage on at least one of the
ON/SKIP pins need to exceed 1V. Once the chip is enabled the conditions
above applies.
Input voltage sense. Used for feed-forward compensation. Also monitored
2 VIN I Analog by the Under Voltage Lock Out circuit. Let the controller operate only if
Vin > 2.5V. Must be connected to the input voltage of the power stage.
2.75V +/- 1% precision reference voltage. A 0.1µF should be placed from
3 VREF O Analog
VREF to GNDA.
Adjust the Ton of the controller according to the formula:
4 TSET P Power Ton = (1.6µs*VTSET)/(Vin-Vout)
A 0.1µF capacitor must be placed from TSET to GNDA.
+5V supply for the controller analog circuits. A 1µF capacitor should be
5 VDDA P Power
placed from VDDA to GNDA.
Enables Channel 1 operation.
If VON/SKIP1 > 0.6V, the Vout1 voltage ramps up to the voltage set on
VSET1 pin with a slew rate of 1V/ms. If VON/SKIP1 > 2.1V the controller
enters skip mode of operation. If both ON/SKIP1 and ON/SKIP2 pins are
6 ON/SKIP1 I Digital
< 0.4V the chip is disabled and enters a very low consumption mode <
1µA. To re-enable the controller the voltage on at least one of the
ON/SKIP pins need to exceed 1V. Once the chip is enabled the conditions
above applies.
Sets the Vout1 output voltage of the first controller.
7 VSET1 I Analog
Uses a resistor divider from the reference voltage.
8 CS1N I Analog Inverting current sense pin for channel 1.
9 CS1P I Analog Non-inverting current sense pin for channel 1.
Power Good output for Vout1.
10 PGD1 O Digital It is an open drain output asserted high when the output voltage Vout1 is
within +125mV/-133mV of the set value.
11 LX1 P Power Inductor switching node for channel 1.
12 HDR1 O Digital Output of the high side driver for channel 1.
Positive supply for the high side driver of channel 1. A 0.1µF capacitor
13 BST1 P Power
should be placed between BST1 and LX1.
14 LDR1 O Digital Output of the low side driver for channel 1.
15 GNDP P Power Power Ground.
Positive supply for the low side driver. A 1µF capacitor should be placed
16 VDDP P Power
from VDDP to GNDP.
17 LDR2 O Digital Output of the low side driver for channel 2.
Positive supply for the high side driver of channel 2. A 0.1µF capacitor
18 BST2 P Power
should be placed between BST2 and LX2.
19 HDR2 O Digital Output of the high side driver for channel 2.
20 LX2 P Power Inductor switching node for channel 2.
Power Good output for Channel2.
21 PGD2 O Digital It is an open drain output asserted high when output voltage Vout2 is
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within +125mV/-133mV of the set value.
22 CS2P I Analog Non-inverting current sense pin for channel 2.
23 CS2N I Analog Inverting current sense pin for channel 2.
Sets the Vout2 output voltage of the second controller.
24 VSET2 I Analog
Uses a resistor divider from the reference voltage.
25 GNDA P Power Ground for the controller analog circuits.

OZ813-SF-v1.3 Page 2
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OZ813
TYPICAL APPLICATION SCHEMATIC
+3V3
+VDC

+5V
R21 +VDC

1k9
CIN2
PGD2
CS2N
10uF_25V 1.5V/5A
CS2P L2
LX2
VSET2 HDR2 3.3uH/5A 28mohm
M2
1 8 R24
C21 2 S1 D1 7 COUT2
G1 D1 51
R02 0.1uF 3 6 2x100uF_6V

25

24
23
22
21
20
19
22 U1 LDR2 4 S2 D2 5 R22 100k R23 60k
BST2 G2 D2

GNDA

CS2P
VSET2

PGD2
LX2
HDR2
CS2N
Si4830DY
+VDC C22 3.3nF
CS2P
1 18 D2
ON/SKIP2 2 ON/SKIP2 BST2 17 MBR0540 CIN1 CS2N
VREF 3 VIN LDR2 16 +5V 10uF_25V
4 VREF OZ813 VDDP 15 D1 C23 C24
VDDA 5 TSET GNDP 14 MBR0540
6 VDDA QFN24 LDR1 13 22pF 1nF
ON/SKIP1 ON/SKIP1 BST1 C03
1uF M1 1.7V/5A
VSET1

HDR1
PGD1
CS1N
CS1P
C01 1 8
C02 LX1 BST1 2 S1 D1 7 L1
0.1uF R03 1uF 3 G1 D1 6
LDR1 4 S2 D2 5 3.3uH/5A 28mohm
G2 D2
10
11
12

105k
7
8
9

C11 Si4830DY R14

VSET1 0.1uF 51 COUT1
HDR1 2x100uF_6V
C04 LX1 R12 100k R13 60k
R04 CS1P
1nF CS1N
20k C12 3.3nF
CS1P
+3V3 VSET2
Single point ground connection CS1N

R05 C13 C14

R11 C05 R01
150k 22pF 1nF
1k9 1nF
0

PGD1 Signal Ground Power Ground

Figure 16. Typical Chipset Power Supply Schematic

OZ813-SF-v1.3 Page 3
 OZ813
BILL OF MATERIALS
Item Qty Reference Value Vendor Part Number PCB Footprint
Taiyo-Yuden TMK325BJ106MM-B
1 2 CIN1, CIN2 10u/25V Johanson Dielectrics 250S41X106M 1210
TDK C3225X7R1E106M
Taiyo-Yuden JMK325BJ107MY-T
2 2 COUT1, COUT2 2x100uF/6V Johanson Dielectrics 6R3S41X107M 1210
TDK C3225X5R0J107M
3 3 C02, C11, C21 0.1uF/10V Any Ceramic – X7R or X5R 0603
Taiyo-Yuden EMK107BJ105KA-B
4 2 C01, C03 1uF/10V Johanson Dielectrics 100R14X105M 0603
TDK C1608X5R1A105K
5 2 C12, C22 3.3nF/25V Any Ceramic – X7R or X5R 0603
6 4 C04, C05, C14, C24 1nF/6V Any Ceramic – X7R or X5R 0603
7 2 C13, C23 22pF Any Ceramic 0603
8 1 R01 0 Any 0603
9 1 R02 22 Any 0603
10 1 R03 105k 1% Any 0603
11 1 R04 20k 1% Any 0603
12 1 R05 150k 1% Any 0603
13 2 R11, R21 1k9 Any 0603
14 2 R12, R22 100k 1% Any 0603
15 2 R13, R23 60k 1% Any 0603
16 2 R14, R24 51 Any 0603
17 2 D1, D2 NONE Vishay MBR0540 SOD-123
Vishay Si4830DY
18 2 M1, M2 NONE SO-8
Fairchild FDS6982S
Vishay IHLP2525CZ-01
19 2 L1, L2 3.3u/5A 2525
TOKO FDV0630 3R3
20 1 U1 OZ813 O2Micro, Inc. OZ813 QFN24

COMPONENT SUPPLIERS
Contact Information
Manufacturer
Phone Website
Power MOSFETs
Vishay 1-402-563-6866 www.vishay.com
Fairchild 1-703-478-5800 www.fairchildsemi.com
Inductors
Vishay 1-402-563-6866 www.vishay.com
TOKO 1-408-432-8281 www.toko.com
Diode
Vishay 1-402-563-6866 www.vishay.com
Fairchild 1-703-478-5800 www.fairchildsemi.com
Capacitors
Taiyo-Yuden www.t-yuden.com
Johanson Dielectrics 1-818-364-9800 www.johansondielectrics.com
TDK 1-800-344-2112 www.tdk.com
Resistors
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Vishay 1-402-563-6866 www.vishay.com
TDK 1-800-344-2112 www.tdk.com

OZ813-SF-v1.3 Page 4
 OZ813
PACKAGE INFORMATION
Exposed pad at bottom is GNDA (pin 25) and must be fully soldered to PCB

PIN 1 ID

1 1
2 2
3 PIN 1 ID
3

TOP VIEW BOTTOM VIEW

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Rth j-a (QFN-24 4x4mm package) = 38°C/W

Rth j-c (QFN-24 4x4mm package) = 4.8°C/W

OZ813-SF-v1.3 Page 5
 OZ813
DIMENSION TABLE

SYMBOL SPECIFICATION
Pitch 0.50 Min Nom Max
A 0.90
B 4.00
C 4.00
D 0.18 .25 .30
E .50
L 0.30 0.40 0.50
P 2.80
D1 0.25
E1 0.50
L1 0.80
P1 2.50
F 3.20

Notes:
1. Controlling dimensions are in millimeters (mm).
2. Pin #1 count orientation shall be in a counterclockwise
direction as viewed in live-bug position.

LANDING PATTERN

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OZ813-SF-v1.3 Page 6
 OZ813
PACKAGE MARKING (QFN24 PACKAGE)

813L _

Mark Function
N Lead-Free Package

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OZ813-SF-v1.3 Page 7
 OZ813
IMPORTANT NOTICE
No portion of O2Micro specifications/datasheets or any of its subparts may be reproduced in any form, or by any means,
without prior written permission from O2Micro.

O2Micro and its subsidiaries reserve the right to make changes to their datasheets and/or products or to discontinue any
product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and
conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent
infringement, and limitation of liability.

O2Micro warrants performance of its products to the specifications applicable at the time of sale in accordance with
O2Micro’s standard warranty. Testing and other quality control techniques are utilized to the extent O2Micro deems
necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.

Customer acknowledges that O2Micro products are not designed, manufactured or intended for incorporation into any
systems or products intended for use in connection with life support or other hazardous activities or environments in which
the failure of the O2Micro products could lead to death, bodily injury, or property or environmental damage (“High Risk
Activities”). O2Micro hereby disclaims all warranties, and O2Micro will have no liability to Customer or any third party,
relating to the use of O2Micro products in connection with any High Risk Activities.

Any support, assistance, recommendation or information (collectively, “Support”) that O2Micro may provide to you
(including, without limitation, regarding the design, development or debugging of your circuit board or other application) is
provided “AS IS.” O2Micro does not make, and hereby disclaims, any warranties regarding any such Support, including,
without limitation, any warranties of merchantability or fitness for a particular purpose, and any warranty that such Support
will be accurate or error free or that your circuit board or other application will be operational or functional. O2Micro will have
no liability to you under any legal theory in connection with your use of or reliance on such support.

COPYRIGHT © 2004-2008, O2Micro International Limited

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OZ813-SF-v1.3 Page 8