DOCUMENT NUMBER

Freescale Semiconductor, Inc. 9S12H256BDGV1/D

MC9S12H256
Device User Guide
V01.18

Covers also MC9S12H128

Freescale Semiconductor, Inc...

Original Release Date: 29 SEP 2000

Revised: 13 AUG 2003

Motorola, Inc

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.

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 DOCUMENT NUMBER
Freescale Semiconductor, Inc. 9S12H256BDGV1/D

Revision History

Version Revision Effective Author Description of Changes

Number Date Date
07 MAR 03 APR
V01.00 Initial version.
2001 2001
- Minor formal corrections
10 MAI 10 MAY
V01.01 - Changed ATD coupling ratio to10-2
2001 2001
- Changed VDD5 to 4.5V
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- Removed 112-pin package references

14 MAY 14 MAY
V01.02 - Changed ATD Electrical Characteristics separate coupling ratio for
2001 2001
positive and negative bulk current injection
30 MAY 30 MAY
V01.03 - Reinserted 112-pin package information.
2001 2001
11 JUN 11 JUN - Removed SRSv2 comment from preface
V01.04
2001 2001 - Corrected RESET pin to active low in table 2-1
- Adapted style and wording to 9DP256 device user guide
18 JUN 18 JUN
V01.05 - Minor format and wording improvements
2001 2001
- Added SRAM data retention disclaimer
- Changed Oscillator Characteristics tCQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
28 JUN 28 JUN
V01.06 - Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
- Changed IDDPS (RTI and COP disabled) to 400µA
2001 2001
- Corrected typo in Figure 2-1 pin 76: PK3 -> PK2
- Added tEXTR and tEXTF to Oscillator Characteristics
- Added typ value for tUPOSC
12 JUL 12 JUL
V01.07 - Corrected tEXTL and tEXTH values
2001 2001
- Updated thermal resistances as per Thermal Simulation Report,
July 10, 2001
16 JUL 16 JUL - updated EEPROM size
V01.08
2001 2001 - added DC cutoff capacitor into layout proposals
03 AUG 03 AUG
V01.09 - minor updates
2001 2001
29 AUG 29 AUG
V01.10 - updated electrical spec
2001 2001

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.

For More Information On This Product,

Go to: www.freescale.com
 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

Version Revision Effective Author Description of Changes

Number Date Date
11 OCT 11 OCT - Replaced references w.r.t. new family name HCS12.
V01.11
2001 2001 - Corrected XCLKS reference in CRG electrical spec.
07 NOV 07 NOV
V01.12 - added ‘powered by’ column in pin list table
2001 2001
- new document numbering
- removed document order number except from cover sheet
- updated min VDD, VDDPLL
08 MAR 08 MAR
V01.13 - updated currents on VOH,VOL for standard pins
2002 2002
- updated CIN, IDDS, IREF, CINS, TEXTL, TEXTH
- included missing lcd electrical spec
- updated NVM spec
- updated input leakage
- updated slew rate spec on PU,PV, PW
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16 DEC 16 DEC
V01.14 - updated supply currents
2002 2002
- included 1K78X
- added detailed register map
31 MAR 31 MAR - added K1 max value
V01.15
2003 2003 - added chragepump current min/max values
05 NOV 05 NOV
V01.16 - corrected pinout problem in LQFP112 layout proposal
2003 2003
04 AUG 04 AUG
V01.17 - added MC9S12H128
2004 2004
13 AUG 13 AUG
V01.18 - added Internal Pull Resistor columns to signal properties table
2004 2004

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MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.
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MC9S12H256 Device User Guide — V01.18

Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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2.2 Signal Properties Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.3 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin. . . . . . . . . . . . . 60
2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . 60
2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 61
2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.13 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.14 PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.16 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.17 PE0 / XIRQ — Port E Input Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.18 PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.19 PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.20 PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.22 PL[7:4] / FP[31:28] — Port L I/O Pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.23 PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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2.3.24 PM5 / TXCAN1 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.25 PM4 / RXCAN1 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.26 PM3 / TXCAN0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.27 PM2 / RXCAN0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.28 PM1 / SCL — Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.29 PM0 / SDA — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.30 PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.31 PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.32 PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.33 PS6 / SCK — Port S I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.34 PS5 / MOSI — Port S I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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2.3.35 PS4 / MISO — Port S I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3.36 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.37 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.38 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.39 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.40 PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . 65
2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0] . . . . . . . . . . . . . . . . 66
2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4] . . . . . . . . . . . . . . . 66
2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0] . . . . . . . . . . . . . . . 66
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.1 VDDR — External Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins . . . . . . . . . . . . . . . 66
2.4.3 VDD1, VSS1, VSS2 — Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.5 VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . 67
2.4.6 VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.7 VLCD — Power Supply Reference Pin for LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.8 VRH, VRL — ATD Reference Voltage Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.9 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Section 3 System Clock Description

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3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.1 Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2.2 Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.2.3 Test Operating Mode (Motorola Use Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Section 5 Resets and Interrupts

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Section 6 HCS12 Core Block Description

Section 7 Clock and Reset Generator (CRG) Block Description

7.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1.1 XCLKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Section 8 Timer (TIM) Block Description

Section 9 Analog to Digital Converter (ATD) Block Description

Section 10 Inter-IC Bus (IIC) Block Description

Section 11 Serial Communications Interface (SCI) Block Description

Section 12 Serial Peripheral Interface (SPI) Block Description

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Section 13 Pulse Width Modulator (PWM) Block Description

Section 14 Flash EEPROM 256K Block Description

Section 15 EEPROM 4K Block Description

Section 16 RAM Block Description

Section 17 Liquid Crystal Display Driver (LCD) Block Description

Section 18 MSCAN Block Description

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Section 19 PWM Motor Control (MC) Block Description

Section 20 Port Integration Module (PIM) Block Description

Section 21 Voltage Regulator (VREG) Block Description

21.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.2 Recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Appendix A Electrical Characteristics

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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A.2.3 ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A.3.1 NVM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.4 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.4.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.4.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A.4.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
A.5 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
A.6 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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A.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

A.7 LCD_32F4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.8.1 General Muxed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Appendix B Package Information

B.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
B.2 112-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
B.3 144-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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Figure 1-1 MC9S12H256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 1-2 MC9S12H128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 1-3 MC9S12H256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 1-4 MC9S12H128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128 . . . . . . . . . . 56
Figure 2-2 Pin Assignments in 144-pin LQFP for MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 3-1 Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21-1 LQFP112 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 21-2 LQFP144 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Figure A-3 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-6 SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure A-8 SPI Slave Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure A-9 General External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . 126
Figure B-2 144-pin LQFP mechanical dimensions (case no. 918-03) . . . . . . . . . . . . . . . . . . . . . 127

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Table 0-1 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 1-1 Device Memory Map MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-2 Device Memory Map MC9S12H128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 44
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 46
Table 1-5 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 1-6 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5-1 Reset and Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 21-1 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table A-2 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table A-13 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-14 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-15 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-16 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-17 SPI Master Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table A-18 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LCD_32F4B Driver Electrical Characteristics 119
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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MC9S12H256 Device User Guide — V01.18

Preface

The Device User Guide provides information about the MC9S12H256 and MC9S12H128 device made up
of standard HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an
effort to reduce redundancy all module specific information is located only in the respective Block User
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
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Table 0-1 Document References

User Guide Version Document Order Number
HCS12 V1.5 Core User Guide 1.2 HCS12COREUG
CRG Block User Guide V02 S12CRGV2/D
TIM_16B8C Block User Guide V01 S12TIM16B8CV1/D
ATD_10B16C Block User Guide V02 S12ATD10B16CV2/D
IIC Block User Guide V02 S12IICV2/D
SCI Block User Guide V02 S12SCIV2/D
SPI Block User Guide V02 S12SPIV2/D
PWM_8B6C Block User Guide V01 S12PWM8B6CV1/D
FTS256K Block User Guide V02 S12FTS256KV2/D
EETS4K Block User Guide V02 S12EETS4KV2/D
LCD_32F4B Block User Guide V01 S12LCD32F4BV1/D
MSCAN Block User Guide V02 S12MSCANV2/D
MC_10B12C Block User Guide V02 S12MC10B12CV2/D
PIM_9H256 Block User Guide V01 S12PIMH256V1/D
VREG Block User Guide V01 S12VREGV1/D

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MC9S12H256 Device User Guide — V01.18

Section 1 Introduction

1.1 Overview
The MC9S12H256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit
analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
The MC9S12H128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 6K
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bytes of RAM, 2K bytes of EEPROM, one asynchronous serial communications interface (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 8-channel, 10-bit
analog-to-digital converter (ATD), a two-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
In addition, it features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width
modulator (MC) consisting of 24 high current outputs suited to drive up to 6 stepper motors. System
resource mapping, clock generation, interrupt control, and bus interfacing are managed by the HCS12
Core.
The MC9S12H256 has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 12 general purpose I/O pins are available with interrupt and wake-up capability
from STOP or WAIT mode.

1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. 20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)

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– BDM (Background Debug Mode)

• CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
• 8-bit and 4-bit ports with interrupt functionality
– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 128K, 256K Flash EEPROM
– 2K, 4K byte EEPROM
– 6K, 12K byte RAM
• Analog-to-Digital Converter
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– 8, 16 channels, 10-bit resolution

– External conversion trigger capability
• Two 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
• 2, 6 PWM channels
– Programmable period and duty cycle
– 8-bit 2, 6-channel or 16-bit 1, 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
• Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Synchronous Serial Peripheral Interface (SPI)

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– Inter-Integrated Circuit interface (IIC)

• Liquid Crystal Display driver with variable input voltage
– Configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output
– 5 modes of operation allow for different display sizes to meet application requirements
– Unused frontplane and backplane pins can be used as general purpose I/O
• 16, 24 high current drivers suited for PWM motor control
– Each PWM channel switchable between two drivers in an H-bridge configuration
– Left, right and center aligned outputs
– Support for sine and cosine drive
– Dithering
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– Output slew rate control

• 144-Pin or 112-Pin LQFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 32MHz equivalent to 16MHz Bus Speed
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints

1.3 Modes of Operation

User modes
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola Use Only)
– Special Peripheral Mode (Motorola Use Only)
Low power modes

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• Stop Mode
• Pseudo Stop Mode
• Wait Mode

1.4 Block Diagram

Figure 1-1 is a block diagram of the MC9S12H256 device.
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VDDR VDDA VDDA

VSSA VSSA
VDD1 Voltage Regulator VRH VRH
VSS1,VSS2 VRL VRL
AN00 PAD00
256k Bytes Flash EEPROM AN01 PAD01
4k Bytes EEPROM AN02 PAD02
Analog to AN03 PAD03
12K Bytes RAM AN04 PAD04
Digital
AN05 PAD05
Single-wire Background Converter AN06 PAD06
BKGD (ATD)

PTAD
Debug Module CPU12 AN07 PAD07
XFC AN08 PAD08
VDDPLL Clock and Periodic Interrupt AN09 PAD09
VSSPLL Reset AN10 PAD10
PLL COP Watchdog AN11 PAD11
EXTAL Generation
XTAL Module Clock Monitor AN12 PAD12
Breakpoints AN13 PAD13
RESET AN14 PAD14
TEST AN15 PAD15

PE0 XIRQ Integration PW0 PP0

DDRE

PE1 IRQ Module Pulse PW1 PP1

PTE

DDRP
PE4 ECLK PW2 PP2

PTP
Width
PE5 MODA PW3 PP3
PE6 MODB Modulator PW4 PP4
(PWM) PW5 PP5
VLCD VLCD
RXD0
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SCI0 PS0
XADDR14 PK0 BP0 PIX0 TXD0 PS1

PPAGE
DDRK
PTK

XADDR15 PK1 BP1 PIX1

XADDR16 PK2 BP2 PIX2 RXD1 PS2
SCI1

DDRS
TXD1 PS3

PTS
XADDR17 PK3 BP3 PIX3
SDI/MISO PS4
DATA0 PB0 FP0 ADDR0 SDO/MOSI PS5
DATA1 PB1 FP1 ADDR1 SPI
SCK PS6
DATA2 PB2 FP2 ADDR2 SS PS7
Multiplexed Address/Data Bus
DDRB

DATA3 PB3 FP3 ADDR3

PTB

LCD
DATA4 PB4 FP4 Driver ADDR4 SDA PM0
DATA5 PB5 FP5 ADDR5 IIC SCL PM1
DATA6 PB6 FP6 ADDR6

DDRM
DATA7 PB7 FP7 ADDR7 RXCAN0 PM2

PTM
CAN0 TXCAN0 PM3
DATA0 DATA8 PA0 FP8 ADDR8
DATA1 DATA9 PA1 FP9 ADDR9 RXCAN1 PM4
CAN1 TXCAN1 PM5
DATA2 DATA10 PA2 FP10 ADDR10
DDRA
PTA

DATA3 DATA11 PA3 FP11 ADDR11

VDDM1
DATA4 DATA12 PA4 FP12 ADDR12 MOTOR0 and MOTOR1 Supply
DATA5 DATA13 PA5 FP13 ADDR13 VSSM1
DATA6 DATA14 PA6 FP14 ADDR14 M0C0M PU0
DATA7 DATA15 PA7 FP15 ADDR15 PWM0 M0C0P PU1
MOTOR0
Multiplexed Multiplexed M0C1M PU2
PL0 FP16 PWM1

DDRU
Narrow Wide M0C1P PU3

PTU
PL1 FP17
Bus Bus PL2 FP18 M1C0M PU4
PWM2 M1C0P PU5
DDRL

PL3 FP19
PTL

MOTOR1
PL4 FP28 M1C1M PU6
PL5 FP29 PWM3 M1C1P PU7
PL6 FP30
PL7 FP31 VDDM2
MOTOR2 and MOTOR3 Supply
VSSM2
PE2 FP20 M2C0M PV0
DDRE

R/W PWM4
PTE

PE3 FP21 M2C0P PV1

LSTRB/TAGLO MOTOR2
PE7 FP22 NOACC/XCLKS M2C1M PV2
PWM5

DDRV
M2C1P PV3

PTV
DDRK

M3C0M PV4
PTK

PK7 FP23 ECS/ROMONE PWM6 M3C0P PV5

MOTOR3
M3C1M PV6
PWM7 M3C1P PV7
NOTE: Not all PT0 FP24 IOC0
PT1 FP25 IOC1
functionality shown PT2 FP26 IOC2
VDDM3
in this block MOTOR4 and MOTOR5 Supply
PT3 FP27 IOC3 VSSM3
DDRT
PTT

diagram is M4C0M PW0

available in all PT4 IOC4 PWM8 M4C0P PW1
PT5 IOC5 Input Capture and MOTOR4
packages! M4C1M PW2
PT6 IOC6 Output Compare PWM9
DDRW

M4C1P PW3
PTW

PT7 IOC7 Timer

M5C0M PW4
PWM10 M5C0P PW5
PH0 KWH0 MOTOR5
PH1 KWH1 M5C1M PW6
PH2 KWH2 PWM11 M5C1P PW7
DDRH

PH3 KWH3
PTH

PH4 KWH4 Supply pins Internal Logic 2.5V I/O Driver 5V

PH5 KWH5 Pin VDD1 VDDX1,2
PH6 KWH6
Interrupt VSS1,2
PH7 KWH7 A/D Converter 5V & VSSX1,2
Logic
PJ0 Voltage Regulator
KWJ0
PJ1 KWJ1 Reference PLL 2.5V
DDRJ

VREG Input 5V
PTJ

PJ2 KWJ2 VDDR

VDDA VDDPLL
PJ3 KWJ3
VSSA VSSPLL

Figure 1-1 MC9S12H256 Block Diagram

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Figure 1-2 is a block diagram of the MC9S12H128 device.

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VDDR VDDA VDDA

VSSA VSSA
VDD1 Voltage Regulator VRH VRH
VSS1,VSS2 VRL VRL
AN00 PAD00
128k Bytes Flash EEPROM AN01 PAD01
2k Bytes EEPROM AN02 PAD02

PTAD
Analog to AN03 PAD03
6K Bytes RAM AN04 PAD04
Digital
AN05 PAD05
Single-wire Background Converter AN06 PAD06
BKGD (ATD)
Debug Module CPU12 AN07 PAD07
XFC AN08
VDDPLL Clock and Periodic Interrupt
VSSPLL Reset
PLL COP Watchdog
EXTAL Generation
XTAL Module Clock Monitor
RESET Breakpoints
TEST

PE0 XIRQ Integration PW0 PP0

DDRE

PE1 IRQ Module Pulse PW1 PP1

PTE

DDRP
PE4 ECLK PW2 PP2

PTP
Width
PE5 MODA PW3 PP3
PE6 MODB Modulator PW4 PP4
(PWM) PW5 PP5
VLCD VLCD
RXD0
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SCI0 PS0
XADDR14 PK0 BP0 PIX0 TXD0 PS1

PPAGE
DDRK
PTK

XADDR15 PK1 BP1 PIX1

XADDR16 PK2 BP2 PIX2

DDRS
PTS
XADDR17 PK3 BP3 PIX3
SDI/MISO PS4
DATA0 PB0 FP0 ADDR0 SDO/MOSI PS5
DATA1 PB1 FP1 ADDR1 SPI
SCK PS6
DATA2 PB2 FP2 ADDR2 SS PS7
Multiplexed Address/Data Bus
DDRB

DATA3 PB3 FP3 ADDR3

PTB

LCD
DATA4 PB4 FP4 Driver ADDR4 SDA PM0
DATA5 PB5 FP5 ADDR5 IIC SCL PM1
DATA6 PB6 FP6 ADDR6

DDRM
DATA7 PB7 FP7 ADDR7 RXCAN0 PM2

PTM
CAN0 TXCAN0 PM3
DATA0 DATA8 PA0 FP8 ADDR8
DATA1 DATA9 PA1 FP9 ADDR9 RXCAN1 PM4
CAN1 TXCAN1 PM5
DATA2 DATA10 PA2 FP10 ADDR10
DDRA
PTA

DATA3 DATA11 PA3 FP11 ADDR11

VDDM1
DATA4 DATA12 PA4 FP12 ADDR12 MOTOR0 and MOTOR1 Supply
DATA5 DATA13 PA5 FP13 ADDR13 VSSM1
DATA6 DATA14 PA6 FP14 ADDR14 M0C0M PU0
DATA7 DATA15 PA7 FP15 ADDR15 PWM0 M0C0P PU1
MOTOR0
Multiplexed Multiplexed M0C1M PU2
PL0 FP16 PWM1

DDRU
Narrow Wide M0C1P PU3

PTU
PL1 FP17
Bus Bus PL2 FP18 M1C0M PU4
PWM2 M1C0P PU5
DDRL

PL3 FP19
PTL

MOTOR1
M1C1M PU6
PWM3 M1C1P PU7
VDDM2
MOTOR2 and MOTOR3 Supply
VSSM2
PE2 FP20 M2C0M PV0
DDRE

R/W PWM4
PTE

PE3 FP21 M2C0P PV1

LSTRB/TAGLO MOTOR2
PE7 FP22 NOACC/XCLKS M2C1M PV2
PWM5

DDRV
M2C1P PV3

PTV
DDRK

M3C0M PV4
PTK

PK7 FP23 ECS/ROMONE PWM6 M3C0P PV5

MOTOR3
M3C1M PV6
PWM7 M3C1P PV7
NOTE: Not all PT0 FP24 IOC0
PT1 FP25 IOC1
functionality shown PT2 FP26 IOC2
VDDM3
in this block MOTOR4 and MOTOR5 Supply
PT3 FP27 IOC3 VSSM3
DDRT
PTT

diagram is M4C0M PW0

available in all PT4 IOC4 PWM8 M4C0P PW1
PT5 IOC5 Input Capture and MOTOR4
packages! M4C1M PW2
PT6 IOC6 Output Compare PWM9
DDRW

M4C1P PW3
PTW

PT7 IOC7 Timer

M5C0M PW4
PWM10 M5C0P PW5
MOTOR5
M5C1M PW6
PWM11 M5C1P PW7

Supply pins Internal Logic 2.5V I/O Driver 5V

VDD1 VDDX1,2
VSS1,2 VSSX1,2
A/D Converter 5V &
Voltage Regulator
Reference PLL 2.5V VREG Input 5V
VDDA VDDPLL VDDR
VSSA VSSPLL

Figure 1-2 MC9S12H128 Block Diagram

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1.5 Device Memory Map

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MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

Table 1-1 and Figure 1-3 show the device memory map of the MC9S12H256.
Table 1-1 Device Memory Map MC9S12H256
Size
Address Module (Bytes)
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID register (PARTID) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Mode) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 – $006F Standard Timer Module 16-bit 8 channels (TIM) 48
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$0070 – $007F Reserved 16

$0080 – $00AF Analog to Digital Converter 10-bit 16 channels (ATD) 48
$00B0 – $00BF Reserved 16
$00C0 – $00C7 Inter Integrated Circuit (IIC) 8
$00C8 – $00CF Serial Communications Interface 0 (SCI0) 8
$00D0 – $00D7 Serial Communications Interface 1 (SCI1) 8
$00D8 – $00DF Serial Peripheral Interface (SPI) 8
$00E0 – $00FF Pulse Width Modulator 8-bit 6 channels (PWM) 32
$0100 – $010F Flash control registers 16
$0110 – $011B EEPROM control registers 12
$011C – $011F Reserved 4
$0120 – $0137 Liquid Crystal Display Driver 32x4 (LCD) 24
$0140 – $017F Motorola Scalable Controller Area Network 0 (MSCAN0) 64
$0180 – $01BF Motorola Scalable Controller Area Network 1 (MSCAN1) 64
$01C0 – $01FF Motor Control Module (MC) 64
$0200 – $027F Port Integration Module (PIM) 128
$0280 – $03FF Reserved 384
$0000 – $0FFF EEPROM array 4096
$1000 – $3FFF RAM array 12288
Fixed Flash EEPROM array
$4000 – $7FFF 16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 – $BFFF Flash EEPROM Page Window 16384
Fixed Flash EEPROM array
$C000 – $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end 16384
and 256 bytes of Vector Space at $FF80 – $FFFF

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$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0000 4K Bytes EEPROM
$0800 initially overlapped by register space
$1000 $0FFF Mappable to any 4K Boundary
$1000 12K Bytes RAM
Alignable to top ($1000 – $3FFF)
or bottom ($0000 – $2FFF)
$4000 $3FFF Mappable to any 16K Boundary
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000
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16K Page Window

Sixteen * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED* SPECIAL

SINGLE CHIP SINGLE CHIP * Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode

Figure 1-3 MC9S12H256 Memory Map

Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128.
Table 1-2 Device Memory Map MC9S12H128
Size
Address Module (Bytes)
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID register (PARTID) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Mode) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 – $006F Standard Timer Module 16-bit 8 channels (TIM) 48
$0070 – $007F Reserved 16
$0080 – $00AF Analog to Digital Converter 10-bit 16 channels (ATD) 48
$00B0 – $00BF Reserved 16
$00C0 – $00C7 Inter Integrated Circuit (IIC) 8

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Table 1-2 Device Memory Map MC9S12H128

Size
Address Module (Bytes)
$00C8 – $00CF Serial Communications Interface 0 (SCI0) 8
$00D0 – $00D7 Reserved 8
$00D8 – $00DF Serial Peripheral Interface (SPI) 8
$00E0 – $00FF Pulse Width Modulator 8-bit 6 channels (PWM) 32
$0100 – $010F Flash control registers 16
$0110 – $011B EEPROM control registers 12
$011C – $011F Reserved 4
$0120 – $0137 Liquid Crystal Display Driver 32x4 (LCD) 24
$0140 – $017F Motorola Scalable Controller Area Network 0 (MSCAN0) 64
$0180 – $01BF Motorola Scalable Controller Area Network 1 (MSCAN1) 64
$01C0 – $01FF Motor Control Module (MC) 64
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$0200 – $027F Port Integration Module (PIM) 128

$0280 – $03FF Reserved 384
$0000 – $07FF EEPROM array 2048
$1000 – $3FFF RAM array 12288
Fixed Flash EEPROM array
$4000 – $7FFF 16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 – $BFFF Flash EEPROM Page Window 16384
Fixed Flash EEPROM array
$C000 – $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end 16384
and 256 bytes of Vector Space at $FF80 – $FFFF

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$0000 1K Register Space

$0000 $03FF Mappable to any 2K Boundary

$0400 $0000 2K Bytes EEPROM
initially overlapped by register space
$0800
$07FF Mappable to any 4K Boundary
$2800 6K Bytes RAM
$2800
Alignable to top ($2800 – $3FFF)
or bottom ($0000 – $17FF)
$4000 $3FFF Mappable to any 16K Boundary
$4000 0.5K, 1K, 2K or 4K Protected Sector

16K Fixed Flash EEPROM

$7FFF

$8000
$8000
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16K Page Window

Sixteen * 16K Flash EEPROM Pages
EXT

$BFFF

$C000 $C000 16K Fixed Flash EEPROM

$FFFF 2K, 4K, 8K or 16K Protected Boot Sector

$FF00
BDM
$FF00 (If Active)
$FFFF VECTORS VECTORS VECTORS $FFFF

NORMAL EXPANDED* SPECIAL

SINGLE CHIP SINGLE CHIP * Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode

Figure 1-4 MC9S12H128 Memory Map

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1.5.1 Detailed Register Map

$0000 - $000F MEBI map 1 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0000 PORTA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0001 PORTB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0002 DDRA Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0003 DDRB Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0 0 0 0 0 0 0
$0004 Reserved
Write:
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Read: 0 0 0 0 0 0 0 0
$0005 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0006 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0007 Reserved
Write:
Read: Bit 1 Bit 0
$0008 PORTE Bit 7 6 5 4 3 2
Write:
Read: 0 0
$0009 DDRE Bit 7 6 5 4 3 Bit 2
Write:
Read: 0 0 0
$000A PEAR NOACCE PIPOE NECLK LSTRE RDWE
Write:
Read: 0 0
$000B MODE MODC MODB MODA IVIS EMK EME
Write:
Read: 0 0 0 0
$000C PUCR PUPKE PUPEE PUPBE PUPAE
Write:
Read: 0 0 0 0
$000D RDRIV RDPK RDPE RDPB RDPA
Write:
Read: 0 0 0 0 0 0 0
$000E EBICTL ESTR
Write:
Read: 0 0 0 0 0 0 0 0
$000F Reserved
Write:

$0010 - $0014 MMC map 1 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0010 INITRM RAM15 RAM14 RAM13 RAM12 RAM11 RAMHAL
Write:
Read: 0 0 0 0
$0011 INITRG REG14 REG13 REG12 REG11
Write:
Read: 0 0 0
$0012 INITEE EE15 EE14 EE13 EE12 EEON
Write:
Read: 0 0 0 0
$0013 MISC EXSTR1 EXSTR0 ROMHM ROMON
Write:
MTST0 Read: Bit 7 6 5 4 3 2 1 Bit 0
$0014
Test Only Write:

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$0015 - $0016 INT map 1 of 2 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$0015 ITCR WRINT ADR3 ADR2 ADR1 ADR0
Write:
Read:
$0016 ITEST INTE INTC INTA INT8 INT6 INT4 INT2 INT0
Write:

$0017 - $0017 MMC map 2 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MTST1 Read: Bit 7 6 5 4 3 2 1 Bit 0
$0017
Test Only Write:
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$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-5)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0018 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0019 Reserved
Write:
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
$001A PARTIDH
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
$001B PARTIDL
Write:

$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-6)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
$001C MEMSIZ0
Write:
Read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0
$001D MEMSIZ1
Write:

$001E - $001E MEBI map 2 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0
$001E INTCR IRQE IRQEN
Write:

$001F - $001F INT map 2 of 2 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0
$001F HPRIO PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
Write:

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$0020 - $0027 Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0020 - Read: 0 0 0 0 0 0 0 0
Reserved
$0027 Write:

$0028 - $002F BKP (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0
$0028 BKPCT0 BKEN BKFULL BKBDM BKTAG
Write:
Read:
$0029 BKPCT1 BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Write:
Read: 0 0
$002A BKP0X BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
Write:
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Read:
$002B BKP0H Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$002C BKP0L Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 0
$002D BKP1X BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
Write:
Read:
$002E BKP1H Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$002F BKP1L Bit 7 6 5 4 3 2 1 Bit 0
Write:

$0030 - $0031 MMC map 4 of 4 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0030 PPAGE PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
Write:
Read: 0 0 0 0 0 0 0 0
$0031 Reserved
Write:

$0032 - $0033 MEBI map 3 of 3 (Core User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0032 PORTK Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0033 DDRK Bit 7 6 5 4 3 2 1 Bit 0
Write:

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$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0034 SYNR SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
Write:
Read: 0 0 0 0
$0035 REFDV REFDV3 REFDV2 REFDV1 REFDV0
Write:
CTFLG Read: 0 0 0 0 0 0 0 0
$0036
TEST ONLY Write:
Read: 0 LOCK TRACK SCM
$0037 CRGFLG RTIF PORF LOCKIF SCMIF
Write:
Read: 0 0 0 0 0
$0038 CRGINT RTIE LOCKIE SCMIE
Write:
Read:
$0039 CLKSEL PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Write:
Read: 0
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$003A PLLCTL CME PLLON AUTO ACQ PRE PCE SCME

Write:
Read: 0
$003B RTICTL RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
Write:
Read: 0 0 0
$003C COPCTL WCOP RSBCK CR2 CR1 CR0
Write:
FORBYP Read: 0 0 0 0 0 0 0 0
$003D
TEST ONLY Write:
CTCTL Read: 0 0 0 0 0 0 0 0
$003E
TEST ONLY Write:
Read: 0 0 0 0 0 0 0 0
$003F ARMCOP
Write: Bit 7 6 5 4 3 2 1 Bit 0

$0040 - $006F TIM (Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0040 TIOS IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
Read: 0 0 0 0 0 0 0 0
$0041 CFORC
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
$0042 OC7M OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
Read:
$0043 OC7D OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
$0044 TCNT (hi)
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$0045 TCNT (lo)
Write:
Read: 0 0 0 0
$0046 TSCR1 TEN TSWAI TSFRZ TFFCA
Write:
Read:
$0047 TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Write:
Read:
$0048 TCTL1 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Write:
Read:
$0049 TCTL2 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Write:

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$0040 - $006F TIM (Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$004A TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Read:
$004B TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Read:
$004C TIE C7I C6I C5I C4I C3I C2I C1I C0I
Write:
Read: 0 0 0
$004D TSCR2 TOI TCRE PR2 PR1 PR0
Write:
Read:
$004E TFLG1 C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Read: 0 0 0 0 0 0 0
$004F TFLG2 TOF
Write:
Read:
$0050 TC0 (hi) Bit 15 14 13 12 11 10 9 Bit 8
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Write:
Read:
$0051 TC0 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0052 TC1 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0053 TC1 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0054 TC2 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0055 TC2 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0056 TC3 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0057 TC3 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0058 TC4 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$0059 TC4 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005A TC5 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005B TC5 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005C TC6 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005D TC6 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$005E TC7 (hi) Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$005F TC7 (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0
$0060 PACTL PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Write:
Read: 0 0 0 0 0 0
$0061 PAFLG PAOVF PAIF
Write:
Read:
$0062 PACNT (hi) Bit 7 6 5 4 3 2 1 Bit 0
Write:

34

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MC9S12H256 Device User Guide — V01.18

$0040 - $006F TIM (Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0063 PACNT (lo) Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$0064 Reserved
Write:
Read:
$0065 Reserved
Write:
Read:
$0066 Reserved
Write:
Read:
$0067 Reserved
Write:
Read:
$0068 Reserved
Write:
Read:
$0069 Reserved
Freescale Semiconductor, Inc...

Write:
Read:
$006A Reserved
Write:
Read:
$006B Reserved
Write:
Read:
$006C Reserved
Write:
TIMTST Read: 0 0 0 0 0 0
$006D TCBYP PCBYP
Test Only Write:
Read:
$006E Reserved
Write:
Read:
$006F Reserved
Write:

$0070 - $007F Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0070 - Read: 0 0 0 0 0 0 0 0
Reserved
$007F Write:

$0080 - $00AF ATD (Analog to Digital Converter 10 Bit 16 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$0080 ATDCTL0
Write:
Read: 0 0 0 0 0 0 0 0
$0081 ATDCTL1
Write:
Read: ASCIF
$0082 ATDCTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
Write:
Read: 0
$0083 ATDCTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0
Write:
Read:
$0084 ATDCTL4 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Write:
Read:
$0085 ATDCTL5 DJM DSGN SCAN MULT CD CC CB CA
Write:

35

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$0080 - $00AF ATD (Analog to Digital Converter 10 Bit 16 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0
$0086 ATDSTAT0
Write:
Read: 0 0 0 0 0 0 0 0
$0087 Reserved
Write:
Read: SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2
$0088 ATDTEST0
Write:
Read: SAR1 SAR0 0 0 0 ATDCLK
$0089 ATDTEST1 RST SC
Write:
Read: CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8
$008A ATDSTAT2
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
$008B ATDSTAT1
Write:
Read:
$008C ATDDIEN0 Bit 15 14 13 12 11 10 9 Bit 8
Freescale Semiconductor, Inc...

Write:
Read:
$008D ATDDIEN1 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$008E PORTAD0
Write:
Read: Bit7 6 5 4 3 2 1 BIT 0
$008F PORTAD1
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0090 ATDDR0H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$0091 ATDDR0L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0092 ATDDR1H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$0093 ATDDR1L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0094 ATDDR2H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$0095 ATDDR2L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0096 ATDDR3H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$0097 ATDDR3L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$0098 ATDDR4H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$0099 ATDDR4L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009A ATDDR5H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$009B ATDDR5L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009C ATDDR6H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$009D ATDDR6L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$009E ATDDR7H
Write:

36

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$0080 - $00AF ATD (Analog to Digital Converter 10 Bit 16 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: Bit7 6 5 4 3 2 1 Bit0
$009F ATDDR7L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00A0 ATDDR8H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00A1 ATDDR8L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00A2 ATDDR9H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00A3 ATDDR9L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00A4 ATDDR10H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00A5 ATDDR10L
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Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00A6 ATDDR11H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00A7 ATDDR11L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00A8 ATDDR12H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00A9 ATDDR12L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00AA ATDDR13H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00AB ATDDR13L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00AC ATDDR14H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00AD ATDDR14L
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
$00aE ATDDR15H
Write:
Read: Bit7 6 5 4 3 2 1 Bit0
$00AF ATDDR15L
Write:

$00B0 - $00BF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$00B0 - Read: 0 0 0 0 0 0 0 0
Reserved
$00BF Write:

$00C0 - $00C7 IIC (Inter IC Bus)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00C0 IBAD ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
Write:
Read:
$00E1 IBFD IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
Write:

37

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MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$00C0 - $00C7 IIC (Inter IC Bus)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$00C2 IBCR IBEN IBIE MS/SL TX/RX TXAK IBSWAI
Write: RSTA
Read: TCF IAAS IBB 0 SRW RXAK
$00C3 IBSR IBAL IBIF
Write:
Read:
$00C4 IBDR D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: 0 0 0 0 0 0 0 0
$00C5 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00C6 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00C7 Reserved
Write:
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$00C8 - $00CF SCI0 (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$00C8 SCI0BDH SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Read:
$00C9 SCI0BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Read:
$00CA SCI0CR1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
Write:
Read:
$00CB SCI0CR2 TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
$00CC SCI0SR1
Write:
Read: 0 0 0 0 0 RAF
$00CD SCI0SR2 BRK13 TXDIR
Write:
Read: R8 0 0 0 0 0 0
$00CE SCI0DRH T8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
$00CF SCI0DRL
Write: T7 T6 T5 T4 T3 T2 T1 T0

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) only on MC9S12H256

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0
$00D0 SCI1BDH SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Read:
$00D1 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Read:
$00D2 SCI1CR1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
Write:
Read:
$00D3 SCI1CR2 TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
$00D4 SCI1SR1
Write:

38

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) only on MC9S12H256

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 RAF
$00D5 SCI1SR2 BRK13 TXDIR
Write:
Read: R8 0 0 0 0 0 0
$00D6 SCI1DRH T8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
$00D7 SCI1DRL
Write: T7 T6 T5 T4 T3 T2 T1 T0

$00D8 - $00DF SPI0 (Serial Peripheral Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00D8 SPI0CR1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write:
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Read: 0 0 0 0
$00D9 SPI0CR2 MODFEN BIDIROE SPISWAI SPC0
Write:
Read: 0 0
$00DA SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
Write:
Read: SPIF 0 SPTEF MODF 0 0 0 0
$00DB SPI0SR
Write:
Read: 0 0 0 0 0 0 0 0
$00DC Reserved
Write:
Read:
$00DD SPI0DR Bit7 6 5 4 3 2 1 Bit0
Write:
Read: 0 0 0 0 0 0 0 0
$00DE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$00DF Reserved
Write:

$00E0 - $00FF PWM (Pulse Width Modulator 8 Bit 6 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$00E0 PWME PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
Write:
Read: 0 0
$00E1 PWMPOL PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Write:
Read: 0 0
$00E2 PWMCLK PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
Write:
Read: 0 0
$00E3 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0
Write:
Read: 0 0
$00E4 PWMCAE CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
Write:
Read: 0 0 0
$00E5 PWMCTL CON45 CON23 CON01 PSWAI PFRZ
Write:
PWMTST Read: 0 0 0 0 0 0 0 0
$00E6
Test Only Write:
PWMPRSC Read: 0 0 0 0 0 0 0 0
$00E7
Test Only Write:
Read:
$00E8 PWMSCLA Bit 7 6 5 4 3 2 1 Bit 0
Write:

39

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$00E0 - $00FF PWM (Pulse Width Modulator 8 Bit 6 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$00E9 PWMSCLB Bit 7 6 5 4 3 2 1 Bit 0
Write:
PWMSCNTA Read: 0 0 0 0 0 0 0 0
$00EA
Test Only Write:
PWMSCNTB Read: 0 0 0 0 0 0 0 0
$00EB
Test Only Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EC PWMCNT0
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00ED PWMCNT1
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EE PWMCNT2
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00EF PWMCNT3
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Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00F0 PWMCNT4
Write: 0 0 0 0 0 0 0 0
Read: Bit 7 6 5 4 3 2 1 Bit 0
$00F1 PWMCNT5
Write: 0 0 0 0 0 0 0 0
Read:
$00F2 PWMPER0 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F3 PWMPER1 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F4 PWMPER2 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F5 PWMPER3 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F6 PWMPER4 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F7 PWMPER5 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F8 PWMDTY0 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00F9 PWMDTY1 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FA PWMDTY2 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FB PWMDTY3 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FC PWMDTY4 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$00FD PWMDTY5 Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read: 0 PWM5IN
$00FE PWMSDN PWMIF PWMIE PWMRSTRT PWMLVL PWM5INL PWM5ENA
Write:
Read: 0 0 0 0 0 0 0 0
$00FF Reserved
Write:

40

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$0100 - $010F Flash Control Register (fts256k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: FDIVLD
$0100 FCLKDIV PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
Write:
Read: KEYEN NV6 NV5 NV4 NV3 NV2 SEC1 SEC0
$0101 FSEC
Write:
Read: 0 0 0
$0102 Reserved 0 0 0 WRALL 0
Write:
Read: 0 0 0
$0103 FCNFG CBEIE CCIE KEYACC BKSEL1 BKSEL0
Write:
Read:
$0104 FPROT FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write:
Read: CCIF 0 0 0
$0105 FSTAT CBEIF PVIOL ACCERR BLANK
Write:
Read: 0 0 0 0
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$0106 FCMD CMDB6 CMDB5 CMDB2 CMDB0

Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0107
Factory Test Write:
Read: 0
$0108 FADDRHI Bit 14 13 12 11 10 9 Bit 8
Write:
Read:
$0109 FADDRLO Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$010A FDATAHI Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$010B FDATALO Bit 7 6 5 4 3 2 1 Bit 0
Write:
$010C - Read: 0 0 0 0 0 0 0 0
Reserved
$010F Write:

$0110 - $011B EEPROM Control Register (eets4k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: EDIVLD
$0110 ECLKDIV PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
Write:
Read: 0 0 0 0 0 0 0 0
$0111 Reserved
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0112
Factory Test Write:
Read: 0 0 0 0 0 0
$0113 ECNFG CBEIE CCIE
Write:
Read:
$0114 EPROT EPOPEN NV6 NV5 NV4 EPDIS EP2 EP1 EP0
Write:
Read: CCIF 0 0 0
$0115 ESTAT CBEIF PVIOL ACCERR BLANK
Write:
Read: 0 0 0 0
$0116 ECMD CMDB6 CMDB5 CMDB2 CMDB0
Write:
Reserved for Read: 0 0 0 0 0 0 0 0
$0117
Factory Test Write:
Read: 0 0 0 0 0
$0118 EADDRHI 10 9 Bit 8
Write:

41

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$0110 - $011B EEPROM Control Register (eets4k)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0119 EADDRLO Bit 7 6 5 4 3 2 1 Bit 0
Write:
Read:
$011A EDATAHI Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read:
$011B EDATALO Bit 7 6 5 4 3 2 1 Bit 0
Write:

$011C - $011F Reserved for RAM Control Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$011C - Read: 0 0 0 0 0 0 0 0
Reserved
$011F Write:
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$0120 - $0137 LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0
$0120 LCDCR0 LCDEN LCLK2 LCLK1 LCLK0 BIAS DUTY1 DUTY0
Write:
Read: 0 0 0 0 0 0
$0121 LCDCR1 LCDSWAI LCDRPSTP
Write:
Read:
$0122 FPENR0 FPEN7 FPEN6 FPEN5 FPEN4 FPEN3 FPEN2 FPEN1 FPEN0
Write:
Read:
$0123 FPENR1 FPEN15 FPEN14 FPEN13 FPEN12 FPEN11 FPEN10 FPEN9 FPEN8
Write:
Read:
$0124 FPENR2 FPEN23 FPEN22 FPEN21 FPEN20 FPEN19 FPEN18 FPEN17 FPEN16
Write:
Read:
$0125 FPENR3 FPEN31 FPEN30 FPEN29 FPEN28 FPEN27 FPEN26 FPEN25 FPEN24
Write:
Read: 0 0 0 0 0 0 0 0
$0126 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0127 Reserved
Write:
Read:
$0128 LCDRAM0 FP1BP3 FP1BP2 FP1BP1 FP1BP0 FP0BP3 FP0BP2 FP0BP1 FP0BP0
Write:
Read:
$0129 LCDRAM1 FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 FP2BP1 FP2BP0
Write:
Read:
$012A LCDRAM2 FP5BP3 FP5BP2 FP5BP1 FP5BP0 FP4BP3 FP4BP2 FP4BP1 FP4BP0
Write:
Read:
$012B LCDRAM3 FP7BP3 FP7BP2 FP7BP1 FP7BP0 FP6BP3 FP6BP2 FP6BP1 FP6BP0
Write:
Read:
$012C LCDRAM4 FP9BP3 FP9BP2 FP9BP1 FP9BP0 FP8BP3 FP8BP2 FP8BP1 FP8BP0
Write:
Read:
$012D LCDRAM5 FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0
Write:
Read:
$012E LCDRAM6 FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0
Write:
Read:
$012F LCDRAM7 FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0
Write:

42

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MC9S12H256 Device User Guide — V01.18

$0120 - $0137 LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0130 LCDRAM8 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0
Write:
Read:
$0131 LCDRAM9 FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0
Write:
Read:
$0132 LCDRAM10 FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0
Write:
Read:
$0133 LCDRAM11 FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0
Write:
Read:
$0134 LCDRAM12 FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0
Write:
Read:
$0135 LCDRAM13 FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0
Write:
Read:
$0136 LCDRAM14 FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0
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Write:
Read:
$0137 LCDRAM15 FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0
Write:

$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0140 CAN0CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0141 CAN0CTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0142 CAN0BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0143 CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0144 CAN0RFLG WUPIF CSCIF OVRIF RXF
Write:
Read:
$0145 CAN0RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Read: 0 0 0 0 0
$0146 CAN0TFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0147 CAN0TIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0148 CAN0TARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0149 CAN0TAAK
Write:
Read: 0 0 0 0 0
$014A CAN0TBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$014B CAN0IDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$014C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$014D Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$014E CAN0RXERR
Write:

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MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$014F CAN0TXERR
Write:
$0150 - CAN0IDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0153 CAN0IDAR3 Write:
$0154 - CAN0IDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0157 CAN0IDMR3 Write:
$0158 - CAN0IDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$015B CAN0IDAR7 Write:
$015C - CAN0IDMR4 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$015F CAN0IDMR7 Write:
$0160 - Read: FOREGROUND RECEIVE BUFFER see Table 1-3
CAN0RXFG
$016F Write:
$0170 - Read:
CAN0TXFG FOREGROUND TRANSMIT BUFFER see Table 1-3
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$017F Write:

Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
$0160 Standard ID Read: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CAN0RIDR0 Write:
Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
$0161 Standard ID Read: ID2 ID1 ID0 RTR IDE=0
CAN0RIDR1 Write:
Extended ID Read: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
$0162 Standard ID Read:
CAN0RIDR2 Write:
Extended ID Read: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
$0163 Standard ID Read:
CAN0RIDR3 Write:
$0164- CAN0RDSR0 - Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$016B CAN0RDSR7 Write:
Read: DLC3 DLC2 DLC1 DLC0
$016C CAN0RDLR
Write:
Read:
$016D Reserved
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$016E CAN0RTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$016F CAN0RTSRL
Write:
Extended ID Read:
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CAN0TIDR0 Write:
$0170
Standard ID Read:
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
Write:
Extended ID Read:
ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
CAN0TIDR1 Write:
$0171
Standard ID Read:
ID2 ID1 ID0 RTR IDE=0
Write:

44

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read:
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
CAN0TIDR2 Write:
$0172
Standard ID Read:
Write:
Extended ID Read:
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
CAN0TIDR3 Write:
$0173
Standard ID Read:
Write:
$0174- CAN0TDSR0 - Read:
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$017B CAN0TDSR7 Write:
Read:
$017C CAN0TDLR DLC3 DLC2 DLC1 DLC0
Write:
Read:
$017D CON0TTBPR PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Freescale Semiconductor, Inc...

Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$017E CAN0TTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$017F CAN0TTSRL
Write:

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXACT SYNCH
$0180 CAN1CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ
Write:
Read: 0 SLPAK INITAK
$0181 CAN1CTL1 CANE CLKSRC LOOPB LISTEN WUPM
Write:
Read:
$0182 CAN1BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Write:
Read:
$0183 CAN1BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0
$0184 CAN1RFLG WUPIF CSCIF OVRIF RXF
Write:
Read:
$0185 CAN1RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Read: 0 0 0 0 0
$0186 CAN1TFLG TXE2 TXE1 TXE0
Write:
Read: 0 0 0 0 0
$0187 CAN1TIER TXEIE2 TXEIE1 TXEIE0
Write:
Read: 0 0 0 0 0
$0188 CAN1TARQ ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
$0189 CAN1TAAK
Write:
Read: 0 0 0 0 0
$018A CAN1TBSEL TX2 TX1 TX0
Write:
Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0
$018B CAN1IDAC IDAM1 IDAM0
Write:
Read: 0 0 0 0 0 0 0 0
$018C Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$018D Reserved
Write:

45

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
$018E CAN1RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$018F CAN1TXERR
Write:
$0190 - CAN1IDAR0 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$0193 CAN1IDAR3 Write:
$0194 - CAN1IDMR0 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$0197 CAN1IDMR3 Write:
$0198 - CAN1IDAR4 - Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
$019B CAN1IDAR7 Write:
$019C - CAN1IDMR4 - Read:
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
$019F CAN1IDMR7 Write:
$01A0 - Read: FOREGROUND RECEIVE BUFFER see Table 1-3
CAN1RXFG
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$01AF Write:
$01B0 - Read:
CAN1TXFG FOREGROUND TRANSMIT BUFFER see Table 1-3
$01BF Write:

Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
$01A0 Standard ID Read: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CAN1RIDR0 Write:
Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
$01A1 Standard ID Read: ID2 ID1 ID0 RTR IDE=0
CAN1RIDR1 Write:
Extended ID Read: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
$01A2 Standard ID Read:
CAN1RIDR2 Write:
Extended ID Read: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
$01A3 Standard ID Read:
CAN1RIDR3 Write:
$01A4- CAN1RDSR0 - Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
$01AB CAN1RDSR7 Write:
Read: DLC3 DLC2 DLC1 DLC0
$01AC CAN1RDLR
Write:
Read:
$01AD Reserved
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$01AE CAN1RTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$01AF CAN1RTSRL
Write:
Extended ID Read:
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CAN1TIDR0 Write:
$01B0
Standard ID Read:
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
Write:

46

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read:
ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
CAN1TIDR1 Write:
$01B1
Standard ID Read:
ID2 ID1 ID0 RTR IDE=0
Write:
Extended ID Read:
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
CAN1TIDR2 Write:
$01B2
Standard ID Read:
Write:
Extended ID Read:
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
CAN1TIDR3 Write:
$01B3
Standard ID Read:
Write:
$01B4- CAN1TDSR0 - Read:
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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$01BB CAN1TDSR7 Write:

Read:
$01BC CAN1TDLR DLC3 DLC2 DLC1 DLC0
Write:
Read:
$01BD CON1TTBPR PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
$01BE CAN1TTSRH
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
$01BF CAN1TTSRL
Write:

$01C0 - $01FF MC (Motor Controller 10bit 12 channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$01C0 MCCTL0 MCPRE1 MCPRE0 MCSWAI FAST DITH MCTOIF
Write:
Read: 0 0 0 0 0 0
$01C1 MCCTL1 RECIRC MCTOIE
Write:
Read: 0 0 0 0 0
$01C2 MCPER (hi) P10 P9 P8
Write:
Read:
$01C3 MCPER (lo) P7 P6 P5 P4 P3 P2 P1 P0
Write:
Read: 0 0 0 0 0 0 0 0
$01C4 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01C5 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01C6 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01C7 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01C8 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01C9 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01CA Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01CB Reserved
Write:

47

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$01C0 - $01FF MC (Motor Controller 10bit 12 channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$01CC Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01CD Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01CE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01CF Reserved
Write:
Read: 0 0
$01D0 MCCC0 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D1 MCCC1 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D2 MCCC2 OM1 OM0 AM1 AM0 CD1 CD0
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Write:
Read: 0 0
$01D3 MCCC3 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D4 MCCC4 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D5 MCCC5 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D6 MCCC6 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D7 MCCC7 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D8 MCCC8 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01D9 MCCC9 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01DA MCCC10 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0
$01DB MCCC11 OM1 OM0 AM1 AM0 CD1 CD0
Write:
Read: 0 0 0 0 0 0 0 0
$01DC Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01DD Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01DE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01DF Reserved
Write:
Read: S S S S
$01E0 MCDC0 (hi) S D10 D9 D8
Write:
Read:
$01E1 MCDC0 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01E2 MCDC1 (hi) S D10 D9 D8
Write:
Read:
$01E3 MCDC1 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01E4 MCDC2 (hi) S D10 D9 D8
Write:

48

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$01C0 - $01FF MC (Motor Controller 10bit 12 channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$01E5 MCDC2 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01E6 MCDC3 (hi) S D10 D9 D8
Write:
Read:
$01E7 MCDC3 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01E8 MCDC4 (hi) S D10 D9 D8
Write:
Read:
$01E9 MCDC4 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01EA MCDC5 (hi) S D10 D9 D8
Write:
Read:
$01EB MCDC5 (lo) D7 D6 D5 D4 D3 D2 D1 D0
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Write:
Read: S S S S
$01EC MCDC6 (hi) S D10 D9 D8
Write:
Read:
$01ED MCDC6 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01EE MCDC7 (hi) S D10 D9 D8
Write:
Read:
$01EF MCDC7 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01F0 MCDC8 (hi) S D10 D9 D8
Write:
Read:
$01F1 MCDC8 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01F2 MCDC9 (hi) S D10 D9 D8
Write:
Read:
$01F3 MCDC9 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01F4 MCDC10 (hi) S D10 D9 D8
Write:
Read:
$01F5 MCDC10 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: S S S S
$01F6 MCDC11 (hi) S D10 D9 D8
Write:
Read:
$01F7 MCDC11 (lo) D7 D6 D5 D4 D3 D2 D1 D0
Write:
Read: 0 0 0 0 0 0 0 0
$01F8 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01F9 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01FA Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01FB Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01FC Reserved
Write:

49

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$01C0 - $01FF MC (Motor Controller 10bit 12 channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0 0 0 0 0
$01FD Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01FE Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$01FF Reserved
Write:

$0200 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0200 PTT PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Write:
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Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0

$0201 PTIT
Write:
Read:
$0202 DDRT DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Write:
Read:
$0203 RDRT RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
$0204 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Write:
Read:
$0205 PPST PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Write:
Read: 0 0 0 0 0 0 0 0
$0206 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0207 Reserved
Write:
Read:
$0208 PTS PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
Write:
Read: PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
$0209 PTIS
Write:
Read:
$020A DDRS DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
Write:
Read:
$020B RDRS RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read:
$020C PERS PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
Write:
Read:
$020D PPSS PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
Write:
Read:
$020E WOMS WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
Write:
Read: 0 0 0 0 0 0 0 0
$020F Reserved
Write:
Read: 0 0
$0210 PTM PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
Write:
Read: 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
$0211 PTIM
Write:
Read: 0 0
$0212 DDRM DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Write:

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$0200 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0
$0213 RDRM RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Write:
Read: 0 0
$0214 PERM PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Write:
Read: 0 0
$0215 PPSM PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Write:
Read: 0 0
$0216 WOMM WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Write:
Read: 0 0 0 0 0 0 0 0
$0217 Reserved
Write:
Read: 0 0
$0218 PTP PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Write:
Read: 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
$0219 PTIP
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Write:
Read: 0 0
$021A DDRP DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Write:
Read: 0 0
$021B RDRP RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Write:
Read: 0 0
$021C PERP PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Write:
Read: 0 0
$021D PPSP PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0
Write:
Read: 0 0 0 0 0 0 0 0
$021E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$021F Reserved
Write:
Read:
$0220 PTH PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
Write:
Read: PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
$0221 PTIH
Write:
Read:
$0222 DDRH DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Write:
Read:
$0223 RDRH RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
Write:
Read:
$0224 PERH PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Write:
Read:
$0225 PPSH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
Write:
Read:
$0226 PIEH PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
Write:
Read:
$0227 PIFH PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
Write:
Read: 0 0 0 0
$0228 PTJ PTJ3 PTJ2 PTJ1 PTJ0
Write:
Read: 0 0 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0
$0229 PTIJ
Write:
Read: 0 0 0 0
$022A DDRJ DDRJ3 DDRJ2 DDRJ1 DDRJ0
Write:
Read: 0 0 0 0
$022B RDRJ RDRJ3 RDRJ2 RDRJ1 RDRJ0
Write:

51

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 Freescale
MC9S12H256 Device User Guide — V01.18 Semiconductor, Inc.

$0200 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read: 0 0 0 0
$022C PERJ PERJ3 PERJ2 PERJ1 PERJ0
Write:
Read: 0 0 0 0
$022D PPSJ PPSJ3 PPSJ2 PPSJ1 PPSJ0
Write:
Read: 0 0 0 0
$022E PIEJ PIEJ3 PIEJ2 PIEJ1 PIEJ0
Write:
Read: 0 0 0 0
$022F PIFJ PIFJ3 PIFJ2 PIFJ1 PIFJ0
Write:
Read:
$0230 PTL PTL7 PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0
Write:
Read: PTIL7 PTIL6 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0
$0231 PTIL
Write:
Read:
$0232 DDRL DDRL7 DDRL7 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0
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Write:
Read:
$0233 RDRL RDRL7 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0
Write:
Read:
$0234 PERL PERL7 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0
Write:
Read:
$0235 PPSL PPSL7 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0
Write:
Read: 0 0 0 0 0 0 0 0
$0236 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0237 Reserved
Write:
Read:
$0238 PTU PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0
Write:
Read: PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0
$0239 PTIU
Write:
Read:
$023A DDRU DDRU7 DDRU7 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
Write:
Read:
$023B SRRU SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0
Write:
Read:
$023C PERU PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0
Write:
Read:
$023D PPSU PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0
Write:
Read: 0 0 0 0 0 0 0 0
$023E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$023F Reserved
Write:
Read:
$0240 PTV PTV7 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0
Write:
Read: PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTIV1 PTIV0
$0241 PTIV
Write:
Read:
$0242 DDRV DDRV7 DDRV7 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0
Write:
Read:
$0243 SRRV SRRV7 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0
Write:
Read:
$0244 PERV PERV7 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0
Write:

52

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 Freescale Semiconductor, Inc.
MC9S12H256 Device User Guide — V01.18

$0200 - $027F PIM (Port Integration Module)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read:
$0245 PPSV PPSV7 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0
Write:
Read: 0 0 0 0 0 0 0 0
$0246 Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$0247 Reserved
Write:
Read:
$0248 PTW PTW7 PTW6 PTW5 PTW4 PTW3 PTW2 PTW1 PTW0
Write:
Read: PTIW7 PTIW6 PTIW5 PTIW4 PTIW3 PTIW2 PTIW1 PTIW0
$0249 PTIW
Write:
Read:
$024A DDRW DDRW7 DDRW7 DDRW5 DDRW4 DDRW3 DDRW2 DDRW1 DDRW0
Write:
Read:
$024B SRRW SRRW7 SRRW6 SRRW5 SRRW4 SRRW3 SRRW2 SRRW1 SRRW0
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Write:
Read:
$024C PERW PERW7 PERW6 PERW5 PERW4 PERW3 PERW2 PERW1 PERW0
Write:
Read:
$024D PPSW PPSW7 PPSW6 PPSW5 PPSW4 PPSW3 PPSW2 PPSW1 PPSW0
Write:
Read: 0 0 0 0 0 0 0 0
$024E Reserved
Write:
Read: 0 0 0 0 0 0 0 0
$024F Reserved
Write:
$0250 - Read: 0 0 0 0 0 0 0 0
Reserved
$027F Write:

$0280 - $03FF Reserved

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0280 - Read: 0 0 0 0 0 0 0 0
Reserved
$03FF Write:

1.6 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL at addresses $001A,$001B,
respectively. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the
assigned part ID numbers.

Table 1-5 Assigned Part ID Numbers

Device Mask Set Number Part ID1
MC9S12H256 0K78X $1000
MC9S12H256 1K78X $1001

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NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-6 shows the read-only values of these registers. Refer to section Module
Mapping and Control (MMC) of HCS12 Core User Guide for further details.

Table 1-6 Memory size registers

Register name Value
MEMSIZ0 $25
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MEMSIZ1 $81

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Section 2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.

2.1 Device Pinout

The MC9S12H256 is available in a 112-pin and 144-pin quad flat pack (LQFP), the MC9S12H128 is
available in a 112-pin quad flat pack (LQFP). Most pins perform two or more functions, as described in
the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.

NOTE: In expanded narrow modes the lower byte data is multiplexed with higher byte data
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through pins 64-71 on the 112-pin LQFP or through pins 111-118 on the 144-pin
LQFP version.

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PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PK7/ECS/ROMONE/FP23

PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PE2/R/W/FP20
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
VDDX1
VSSX1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
M0C0M/PU0 1 84 PB5/ADDR5/DATA5/FP5
M0C0P/PU1 2 83 PB4/ADDR4/DATA4/FP4
M0C1M/PU2 3 82 PB3/ADDR3/DATA3/FP3
M0C1P/PU3 4 81 PB2/ADDR2/DATA2/FP2
VDDM1 5 80 PB1/ADDR1/DATA1/FP1
VSSM1 6 79 PB0/ADDR0/DATA0/FP0
7 78 PK0/XADDR14/BP0
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M1C0M/PU4
M1C0P/PU5 8 77 PK1/XADDR15/BP1
M1C1M/PU6 9 76 PK2/XADDR16/BP2
M1C1P/PU7 10 75 PK3/XADDR17/BP3
M2C0M/PV0 11 74 VLCD
M2C0P/PV1 12 73 VSS1
M2C1M/PV2 13 72 VDD1
M2C1P/PV3 14 MC9S12H-Family 71 PAD07/AN07
VDDM2 15 112 LQFP 70 PAD06/AN06
VSSM2 16 69 PAD05/AN05
M3C0M/PV4 17 68 PAD04/AN04
M3C0P/PV5 18 67 PAD03/AN03
M3C1M/PV6 19 66 PAD02/AN02
M3C1P/PV7 20 65 PAD01/AN01
M4C0M/PW0 21 64 PAD00/AN00
M4C0P/PW1 22 63 VDDA
M4C1M/PW2 23 62 VRH
M4C1P/PW3 24 61 VRL
VDDM3 25 60 VSSA
VSSM3 26 59 PE0/XIRQ
M5C0M/PW4 27 58 PE4/ECLK
M5C0P/PW5 28 57 PE6/IPIPE1/MODB
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
RXCAN1/PM4
TXCAN1/PM5
MODA/IPIP0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1

Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128

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PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PE7/NOACC/XCLKS/FP22
PK7/ECS/ROMONE/FP23

PE3/LSTRB/TAGLO/FP21

PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24

PE2/R/W/FP20
PJ3/KWJ3
PJ2/KWJ2
PJ1/KWJ1
PJ0/KWJ0

PL7/FP31
PL6/FP30
PL5/FP29
PL4/FP28
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4

PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
VDDX1
VSSX1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
M0C0M/PU0 1 108 PB5/ADDR5/DATA5/FP5
M0C0P/PU1 2 107 PB4/ADDR4/DATA4/FP4
M0C1M/PU2 3 106 PB3/ADDR3/DATA3/FP3
M0C1P/PU3 4 105 PB2/ADDR2/DATA2/FP2
VDDM1 5 104 PB1/ADDR1/DATA1/FP1
VSSM1 6 103 PB0/ADDR0/DATA0/FP0
M1C0M/PU4 7 102 PK0/XADDR14/BP0
M1C0P/PU5 8 101 PK1/XADDR15/BP1
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M1C1M/PU6 9 100 PK2/XADDR16/BP2

M1C1P/PU7 10 99 PK3/XADDR17/BP3
KWH0/PH0 11 98 VLCD
KWH1/PH1 12 97 VSS1
KWH2/PH2 13 96 VDD1
KWH3/PH3 14 95 PAD15/AN15
M2C0M/PV0 15 94 PAD07/AN07
M2C0P/PV1 16 93 PAD14/AN14
M2C1M/PV2 17 MC9S12H-Family 92 PAD06/AN06
M2C1P/PV3 18 91 PAD13/AN13
VDDM2 19 144 LQFP 90 PAD05/AN05
VSSM2 20 89 PAD12/AN12
M3C0M/PV4 21 88 PAD04/AN04
M3C0P/PV5 22 87 PAD11/AN11
M3C1M/PV6 23 86 PAD03/AN03
M3C1P/PV7 24 85 PAD10/AN10
KWH4/PH4 25 84 PAD02/AN02
KWH5/PH5 26 83 PAD09/AN09
KWH6/PH6 27 82 PAD01/AN01
KWH7/PH7 28 81 PAD08/AN08
M4C0M/PW0 29 80 PAD00/AN00
M4C0P/PW1 30 79 VDDA
M4C1M/PW2 31 78 VRH
M4C1P/PW3 32 77 VRL
VDDM3 33 Pins shown in BOLD are not available in the 112 LQFP package 76 VSSA
VSSM3 34 75 PE0/XIRQ
M5C0M/PW4 35 74 PE4/ECLK
M5C0P/PW5 36 73 PE6/IPIPE1/MODB
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
PWM2/PP2
PWM3/PP3
PWM4/PP4
PWM5/PP5
RXD0/PS0
TXD0/PS1
RXD1/PS2
TXD1/PS3
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SDA/PM0
SCL/PM1
RXCAN0/PM2
TXCAN0/PM3
RXCAN1PM4
TXCAN1/PM5
MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1

Figure 2-2 Pin Assignments in 144-pin LQFP for MC9S12H256

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2.2 Signal Properties Summary

Table 2-1 summarizes all pin functions.

NOTE: Bold entries determine pins not available on 112-pin LQFP.

Table 2-1 Signal Properties

Internal Pull
Pin Name Pin Name Pin Name Pin Name Powered Resistor
Description
Function 1 Function 2 Function 3 Function 4 by Reset
CTRL State
EXTAL — — — VDDPLL
Oscillator Pins
XTAL — — — VDDPLL
RESET — — — VDDX2 None None External Reset Pin
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TEST — — — VDDX2 Test Input

XFC — — — VDDPLL PLL Loop Filter
Always Background Debug, Tag High, Mode
BKGD TAGHI MODC — VDDX2 Up
Up Pin
PAD[7:0] AN[7:0] — — VDDA Port AD Inputs, Analog Inputs (ATD)
None None Port AD Inputs, Analog Inputs
PAD[15:8] AN[15:8] — — VDDA
(ATD)
ADDR[15:8]/ PUCR/
PA[7:0] FP[15:8] — VDDX1 Down Port A I/O, Multiplexed Address/Data
DATA[15:8] PUPAE
ADDR[7:0]/ PUCR/
PB[7:0] FP[7:0] — VDDX1 Down Port B I/O, Multiplexed Address/Data
DATA[7:0] PUPBE
PUCR/ Port E I/O, Access, Clock Select,
PE7 FP22 XCLKS NOACC VDDX1 Down
PUPEE LCD driver
PE6 IPIPE1 MODB — VDDX2 While RESET pin is Port E I/O, Pipe Status, Mode Input
PE5 IPIPE0 MODA — VDDX2 low: Down Port E I/O, Pipe Status, Mode Input
PE4 ECLK — — VDDX2 Port E I/O, Bus Clock Output
Mode de- Port E I/O, LCD driver, Byte Strobe,
PE3 FP21 LSTRB TAGLO VDDX1
PUCR/ pendent Tag Low
PE2 FP20 R/W — VDDX1 PUPEE Port E I/O, R/W in expanded modes
PE1 IRQ — — VDDX2 Port E Input, Maskable Interrupt
Up
PE0 XIRQ — — VDDX2 Port E Input, Non Maskable Interrupt
PERH/
PH[7:0] KWH[7:0] — — VDDM Disabled Port H I/O, Interrupts
PPSH
PERJ/
PJ[3:0] KWJ[3:0] — — VDDX1 Disabled Port J I/O, Interrupts
PPSJ
Port K I/O, Emulation Chip Select,
PK7 FP23 ECS ROMONE VDDX1
PUCR/ ROM On Enable
Down
PUPKE Port K I/O, LCD driver, Extended
PK[3:0] BP[3:0] XADDR[17:14] — VDDX1
Addresses
PL[3:0] FP[19:16] — — VDDX1 PERL/ Port L I/O, LCD drivers
Down
PL[7:4] FP[31:28] — — VDDX1 PPSL Port L I/O, LCD drivers

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Internal Pull
Pin Name Pin Name Pin Name Pin Name Powered Resistor
Description
Function 1 Function 2 Function 3 Function 4 by Reset
CTRL State
PM5 TXCAN1 — — VDDX2 Port M I/O, TX of CAN1
PM4 RXCAN1 — — VDDX2 Port M I/O, RX of CAN1
PM3 TXCAN0 — — VDDX2 PERM/ Port M I/O, TX of CAN0
Disabled
PM2 RXCAN0 — — VDDX2 PPSM Port M I/O, RX of CAN0
PM1 SCL — — VDDX2 Port M I/O, SCL of IIC
PM0 SDA — — VDDX2 Port M I/O, SDA of IIC
PP[5:2] PWM[5:2] — — VDDX2 PERP/ Port P I/O, PWM channels
Disabled
PP[1:0] PWM[1:0] — — VDDX2 PPSP Port P I/O, PWM channels
PS7 SS — — VDDX2 Port S I/O, SS of SPI
PS6 SCK — — VDDX2 Port S I/O, SCK of SPI
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PS5 MOSI — — VDDX2 Port S I/O, MOSI of SPI

PS4 MISO — — VDDX2 PERS/ Port S I/O, MISO of SPI
Disabled
PS3 TXD1 — — VDDX2 PPSS Port S I/O, TXD of SCI1
PS2 RXD1 — — VDDX2 Port S I/O, RXD of SCI1
PS1 TXD0 — — VDDX2 Port S I/O, TXD of SCI0
PS0 RXD0 — — VDDX2 Port S I/O, RXD of SCI0
PT[7:4] IOC[7:4] — — VDDX1 Port T I/O, Timer channels
PERT/
Down Port T I/O, Timer channels, LCD
PT[3:0] IOC[3:0] FP[27:24] — VDDX1 PPST
driver
M0C0M
M0C0P
PU[3:0] — — VDDM Port U I/O, Motor0 of MC
M0C1M
M0C1P PERU/
Disabled
M1C0M PPSU
M1C0P
PU[7:4] — — VDDM Port U I/O, Motor1 of MC
M1C1M
M1C1P
M2C0M
M2C0P
PV[3:0] — — VDDM Port V I/O, Motor2 of MC
M2C1M
M2C1P PERV/
Disabled
M3C0M PPSV
M3C0P
PV[7:4] — — VDDM Port V I/O, Motor3 of MC
M3C1M
M3C1P
M4C0M
M4C0P
PW[3:0] — — VDDM Port W I/O, Motor4 of MC
M4C1M
M4C1P PERW/
Disabled
M5C0M PPSW
M5C0P,
PW[7:4] — — VDDM Port W I/O, Motor5 of MC
M5C1M
M5C1P

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2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.

2.3.3 TEST — Test Pin

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This pin is reserved for test.

NOTE: The TEST pin must be tied to VSS in all applications.

2.3.4 XFC — PLL Loop Filter Pin

Dedicated pin used to create the PLL loop filter.

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.

2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]

PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.

NOTE: These pins are not available in the 112-pin LQFP version.

2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]

PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.

2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.

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2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.

2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7

PE7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP22
of the LCD module. The XCLKS signal selects between an external clock or oscillator configuration
during reset.
The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is
latched at the rising edge of RESET. If the input is a logic high the EXTAL pin is configured for an
external clock drive. If input is a logic low an oscillator circuit is configured on EXTAL and XTAL. Since
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this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration
is an oscillator circuit on EXTAL and XTAL.
During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the
current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.

2.3.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.13 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.

2.3.14 PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3

PE3 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP21
of the LCD module. In MCU expanded modes of operation, LSTRB is used for the low-byte strobe
function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the
low half of the instruction word being read into the instruction queue.

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2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2

PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20
of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal
for the external bus. It indicates the direction of data on the external bus.

2.3.16 PE1 / IRQ — Port E Input Pin 1

PE1 is a general purpose input pin and also the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.17 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means
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of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.18 PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]

PH7-PH0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.

NOTE: These pins are not available in the 112-pin LQFP version.

2.3.19 PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]

PJ3-PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.and are shared with the interrupt function.

NOTE: These pins are not available in the 112-pin LQFP version.

2.3.20 PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7

PK7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP23
of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip
select signal (ECS). During reset of the MCU to normal expanded modes of operation, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.

2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0]

PK3-PK0 are general purpose input or output pins. They can be configured as backplane segment driver
outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the
expanded address XADDR[17:14] for the external bus.

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2.3.22 PL[7:4] / FP[31:28] — Port L I/O Pins [7:4]

PL7-PL4 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP31-FP28 of the LCD module.

NOTE: These pins are not available in the 112-pin LQFP version.

2.3.23 PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]

PL3-PL0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP19-FP16 of the LCD module.

2.3.24 PM5 / TXCAN1 — Port M I/O Pin 5

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PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the
Motorola Scalable Controller Area Network controller 1 (CAN1)

2.3.25 PM4 / RXCAN1 — Port M I/O Pin 4

PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN1 of the
Motorola Scalable Controller Area Network controller 1 (CAN1)

2.3.26 PM3 / TXCAN0 — Port M I/O Pin 3

PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the
Motorola Scalable Controller Area Network controller 0 (CAN0)

2.3.27 PM2 / RXCAN0 — Port M I/O Pin 2

PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN0 of the
Motorola Scalable Controller Area Network controller 0 (CAN0)

2.3.28 PM1 / SCL — Port M I/O Pin 1

PM1 is a general purpose input or output pin. It can be configured as the serial clock pin SCL of the
Inter-IC Bus Interface (IIC).

NOTE: This pin is not available in the 112-pin LQFP version.

2.3.29 PM0 / SDA — Port M I/O Pin 0

PM0 is a general purpose input or output pin. It can be configured as the serial data pin SDA of the Inter-IC
Bus Interface (IIC).

NOTE: This pin is not available in the 112-pin LQFP version.

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2.3.30 PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2]

PP5-PP2 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM5-PWM2.

NOTE: These pins are not available in the 112-pin LQFP version.

2.3.31 PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0]

PP1-PP0 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM1-PWM0.

2.3.32 PS7 / SS — Port S I/O Pin 7

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PS7 is a general purpose input or output pin. It can be configured as slave select pin SS of the Serial
Peripheral Interface (SPI).

2.3.33 PS6 / SCK — Port S I/O Pin 6

PS6 is a general purpose input or output pin. It can be configured as serial clock pin SCK of the Serial
Peripheral Interface (SPI).

2.3.34 PS5 / MOSI — Port S I/O Pin 5

PS5 is a general purpose input or output pin. It can be configured as the master output (during master
mode) or slave input (during slave mode) pin MOSI of the Serial Peripheral Interface (SPI).

2.3.35 PS4 / MISO — Port S I/O Pin 4

PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output (during slave mode) pin MISO for the Serial Peripheral Interface (SPI).

2.3.36 PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general purpose input or output pin. It can be configured as transmit pin TXD1 of the Serial
Communication Interface 1 (SCI1).

NOTE: This pin is not available in the 112-pin LQFP version.

2.3.37 PS2 / RXD1 — Port S I/O Pin 2

PS2 is a general purpose input or output pin. It can be configured as receive pin RXD1 of the Serial
Communication Interface 1 (SCI1).

NOTE: This pin is not available in the 112-pin LQFP version.

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2.3.38 PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general purpose input or output pin. It can be configured as transmit pin TXD0 of the Serial
Communication Interface 0 (SCI0).

2.3.39 PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general purpose input or output pin. It can be configured as receive pin RXD0 of the Serial
Communication Interface 0 (SCI0).

2.3.40 PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4]

PT7-PT4 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC4 of the Timer (TIM).
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2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]

PT3-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC3-IOC0 of the Timer (TIM). They can be configured as frontplane segment driver
outputs FP27-FP24 of the LCD module.

2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4]

PU7-PU4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on
M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM
output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high
state.

2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0]

PU3-PU0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on
M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM
output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high
state.

2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4]

PV7-PV4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on
M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM
output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high
state.

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2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0]

PV3-PV0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on
M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM
output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high
state.

2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4]

PW7-PW4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on
M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM
output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high
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state.

2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0]

PW3-PW0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on
M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM
output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high
state.

2.4 Power Supply Pins

MC9S12H256 power and ground pins are described below.

NOTE: All VSS pins must be connected together in the application (21.2 Recommended
PCB layout).

Because fast signal transitions place high, short-duration current demands on the
power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily
the MCU pins are loaded (Table 21-1).

2.4.1 VDDR — External Power Pin

VDDR is the power supply pin for the internal voltage regulator.

2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins

VDDX1, VDDX2, VSSX1 and VSSX2 are the power supply and ground pins for input/output
drivers.VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.

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2.4.3 VDD1, VSS1, VSS2 — Core Power Pins

VDD1, VSS1 and VSS2 are the core power and ground pins and related to the voltage regulator output.
These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally connected.

NOTE: No load allowed except for bypass capacitors.

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog to digital
converter.

2.4.5 VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5

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VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U,V and W. VDDM1, VDDM2 and
VDDM3 are internally connected.

2.4.6 VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5

VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U,V and W. VSSM1, VSSM2 and VSSM3
are internally connected.

2.4.7 VLCD — Power Supply Reference Pin for LCD driver

VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the
display contrast.

2.4.8 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the voltage reference pins for the analog to digital converter.

2.4.9 VDDPLL, VSSPLL — Power Supply Pins for PLL

VDDPLL and VSSPLL are the PLL supply pins and serve as connection points for external loop filter
components.

NOTE: No load allowed except for bypass capacitors.

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Section 3 System Clock Description

3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.

S12_CORE
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core clock

Flash

RAM

EEPROM

EXTAL TIM

ATD

bus clock PWM

CRG
SCI0, SCI1
oscillator clock
XTAL SPI

CAN0, CAN1

IIC

MC

LCD

PIM

Figure 3-1 Clock Connections

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Section 4 Modes of Operation

4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.

4.2 Modes of Operation

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
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mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.

Table 4-1 Mode Selection

MODC MODB MODA Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
0 0 0
other modes but a serial command is required to make BDM active.
0 0 1 Emulation Expanded Narrow, BDM allowed
0 1 0 Special Test (Expanded Wide) (Motorola Use Only), BDM allowed
0 1 1 Emulation Expanded Wide, BDM allowed
1 0 0 Normal Single Chip, BDM allowed
1 0 1 Normal Expanded Narrow, BDM allowed
Peripheral (Motorola Use Only); BDM allowed but bus operations
1 1 0
would cause bus conflicts (must not be used)
1 1 1 Normal Expanded Wide, BDM allowed

There are two basic types of operating modes:

1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched

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even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.

4.2.1 Normal Operating Modes

These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.

4.2.1.1 Normal Single-Chip Mode

There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups
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enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.

4.2.1.2 Normal Expanded Wide Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit

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would need to be set before any attempt to write to an external location. If there are no writable resources
in the external system, PE2 can be left as a general purpose I/O pin. The
Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in
PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not
needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as
a constant speed clock for use in the external application system.

4.2.1.3 Normal Expanded Narrow Mode

This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such
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systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of
additional external memory devices.
Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility
is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.
Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired
states during the single allowed write.
The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it
is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port
E bit 3 cannot be reconfigured as the LSTRB output.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system
activity. Development systems where pipe status signals are monitored would typically use special
expanded wide mode or occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be
reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded
narrow system includes external devices that can be written such as RAM, the RDWE bit would need to
be set before any attempt to write to an external location. If there are no writable resources in the external
system, PE2 can be left as a general purpose I/O pin.

4.2.1.4 Internal Visibility

Internal visibility is available when the MCU is operating in expanded wide modes or special narrow
mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is
enabled by setting the IVIS bit in the MODE register.

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If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their
previous state.

4.2.1.5 Emulation Expanded Wide Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. These signals allow external memory and peripheral devices
to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of
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application programs.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.

4.2.1.6 Emulation Expanded Narrow Mode

Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for
lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal
resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,
PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external
words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports. During external accesses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.

4.2.2 Special Operating Modes

There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.

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4.2.2.1 Special Single-Chip Mode

When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to
the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.
All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance
inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
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The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.

4.2.2.2 Special Test Mode (Motorola Use Only)

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.

4.2.3 Test Operating Mode (Motorola Use Only)

There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.

4.2.3.1 Peripheral Mode

This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an
external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In
effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster
testing of on-chip memory and peripherals than previous testing methods. Since the mode control register
is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a
different mode. Background debugging should not be used while the MCU is in special peripheral mode
as internal bus conflicts between BDM and the external master can cause improper operation of both
functions.

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4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
• Protection of the contents of FLASH,
• Protection of the contents of EEPROM,
• Operation in single-chip mode,
• Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
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of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.

4.3.1 Securing the Microcontroller

Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.

4.3.2 Operation of the Secured Microcontroller

4.3.2.1 Normal Single Chip Mode

This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.

4.3.2.2 Executing from External Memory

The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.

4.3.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program

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completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.

4.4 Low Power Modes

Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop,
and Wait Mode.
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Section 5 Resets and Interrupts

5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.

5.2 Vectors
5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.
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Table 5-1 Reset and Interrupt Vector Table

CCR HPRIO Value
Vector Address Interrupt Source Local Enable
Mask to Elevate
$FFFE, $FFFF External or Power On Reset None None -
$FFFC, $FFFD Clock Monitor fail reset None COPCTL (CME, FCME) -
$FFFA, $FFFB COP failure reset None COP rate select -
$FFF8, $FFF9 Unimplemented instruction trap None None -
$FFF6, $FFF7 SWI None None -
$FFF4, $FFF5 XIRQ X-Bit None -
$FFF2, $FFF3 IRQ I-Bit INTCR (IRQEN) $F2
$FFF0, $FFF1 Real Time Interrupt I-Bit RTICTL (RTIE) $F0
$FFEE, $FFEF Timer channel 0 I-Bit TIE (C0I) $EE
$FFEC, $FFED Timer channel 1 I-Bit TIE (C1I) $EC
$FFEA, $FFEB Timer channel 2 I-Bit TIE (C2I) $EA
$FFE8, $FFE9 Timer channel 3 I-Bit TIE (C3I) $E8
$FFE6, $FFE7 Timer channel 4 I-Bit TIE (C4I) $E6
$FFE4, $FFE5 Timer channel 5 I-Bit TIE (C5I) $E4
$FFE2, $FFE3 Timer channel 6 I-Bit TIE (C6I) $E2
$FFE0, $FFE1 Timer channel 7 I-Bit TIE (C7I) $E0
$FFDE, $FFDF Timer overflow I-Bit TSCR2 (TOI) $DE
$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI I-Bit SP0CR1 (SPIE) $D8
SC0CR2
$FFD6, $FFD7 SCI0 I-Bit $D6
(TIE, TCIE, RIE, ILIE)
SC1CR2
$FFD4, $FFD5 SCI1 I-Bit $D4
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $D2
$FFD0, $FFD1 Reserved
$FFCE, $FFCF Port J I-Bit PTJIF (PTJIE) $CE
$FFCC, $FFCD Port H I-Bit PTHIF (PTHIE) $CC
$FFCA, $FFCB Reserved

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Table 5-1 Reset and Interrupt Vector Table

CCR HPRIO Value
Vector Address Interrupt Source Local Enable
Mask to Elevate
$FFC8, $FFC9 Reserved
$FFC6, $FFC7 CRG PLL lock I-Bit CRGINT (LOCKIE) $C6
$FFC4, $FFC5 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4
$FFC2, $FFC3 Reserved
$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0
$FFBE, $FFBF Reserved
$FFBC, $FFBD Reserved
$FFBA, $FFBB EEPROM I-Bit EECTL (CCIE, CBEIE) $BA
$FFB8, $FFB9 FLASH I-Bit FCTL (CCIE, CBEIE) $B8
$FFB6, $FFB7 CAN0 wake-up I-Bit CAN0RIER (WUPIE) $B6
CAN0RIER (CSCIE,
$FFB4, $FFB5 CAN0 errors I-Bit $B4
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OVRIE)
$FFB2, $FFB3 CAN0 receive I-Bit CAN0RIER (RXFIE) $B2
$FFB0, $FFB1 CAN0 transmit I-Bit CAN0TIER (TXEIE[2:0]) $B0
$FFAE, $FFAF CAN1 wake-up I-Bit CAN0RIER (WUPIE) $AE
CAN1RIER (CSCIE,
$FFAC, $FFAD CAN1 errors I-Bit $AC
OVRIE)
$FFAA, $FFAB CAN1 receive I-Bit CAN1RIER (RXFIE) $AA
$FFA8, $FFA9 CAN1 transmit I-Bit CAN1TIER (TXEIE[2:0]) $A8
$FF98 to
Reserved
$FFA7
$FF96, $FF97 Motor Control Timer Overflow I-Bit MCCTL1 (MCOCIE) $96
$FF9E to
Reserved
$FF95
$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN(PWMIE) $8C
$FF80 to
Reserved
$FF8B

5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.

5.3.1 I/O pins

Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.

NOTE: For devices assembled in 112-pin LQFP packages all non-bonded out pins should
be configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.

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5.3.2 Memory

Refer to Table 1-1 for locations of the memories depending on the operating mode after reset
The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description

Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).

Section 7 Clock and Reset Generator (CRG) Block

Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
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7.1 Device-specific information

7.1.1 XCLKS

The XCLKS input signal is active high (see 2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7).

Section 8 Timer (TIM) Block Description

Consult the TIM_16B8C Block User Guide for information about the Timer module.

Section 9 Analog to Digital Converter (ATD) Block

Description

Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter
module.

Section 10 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 11 Serial Communications Interface (SCI) Block

Description

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There are two Serial Communications Interfaces (SCI0 and SCI1) implemented on the MC9S12H256
device and one SCI (SCI0) on MC9S12H128. Consult the SCI Block User Guide for information about
each Serial Communications Interface module.

Section 12 Serial Peripheral Interface (SPI) Block

Description

Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.

Section 13 Pulse Width Modulator (PWM) Block

Description
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Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator module.

Section 14 Flash EEPROM 256K Block Description

Consult the FTS256K Block User Guide for information about the flash module.

Section 15 EEPROM 4K Block Description

Consult the EETS4K Block User Guide for information about the EEPROM module.

Section 16 RAM Block Description

The RAM module does not contain any control registers. Thus no Block User Guide is available.
This module supports single-cycle misaligned word accesses without wait states.

Section 17 Liquid Crystal Display Driver (LCD) Block

Description

Consult the LCD_32F4B Block User Guide for information about the Liquid Crystal Display Driver
module.

Section 18 MSCAN Block Description

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There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult
the MSCAN Block User Guide for information on each MSCAN.

Section 19 PWM Motor Control (MC) Block Description

Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.

Section 20 Port Integration Module (PIM) Block Description

Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.
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Section 21 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.

21.1 Device-specific information

21.1.1 VREGEN

There is no VREGEN pin implemented on this device.

21.1.2 Modes of Operation

21.1.2.1 Run Mode

VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating
loops operate in Run mode with full performance.

21.1.2.2 Standby Mode

VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of
the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes
quiescent current drawn by the voltage regulator block.

21.1.2.3 Shutdown Mode

VREG Shutdown mode is not available on MC9S12H family devices.

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21.2 Recommended PCB layout

Figure 21-1 LQFP112 recommended PCB layout

C8
VSSX1
VDDX1

VDDM1

C7
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VSSM1

VSS1
C1

VDD1
VDDM2

C6
VSSM2

VDDA

VDDM3
C2
C5 VSSA
VSSM3
C3
C4

VDDR/
C14
C9

C10

C11

VDDX2

Q1
C12

C13

VSSPLL
VDDPLL
R1

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Figure 21-2 LQFP144 recommended PCB layout

C8
VSSX1
VDDX1

VDDM1

C7
VSSM1
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VSS1
C1

VDD1

VDDM2

C6
VSSM2

VDDA

VDDM3
C2
C5 VSSA
VSSM3
C3
C4

VDDR/
C9

VDDX2
C14

C10

C11

Q1
C12

C13

VSSPLL
VDDPLL
R1

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Table 21-1 Recommended Components

Component Purpose Type Value
C1 VDD1 filter cap ceramic X7R 100 .. 220nF

C2 VDDA filter cap X7R/tantalum >=100nF

C3 VDDX2 filter cap X7R/tantalum >=100nF

C4 VDDR filter cap X7R/tantalum >=100nF

C5 VDDM3 filter cap X7R/tantalum >=100nF

C6 VDDM2 filter cap X7R/tantalum >=100nF

C7 VDDM1 filter cap X7R/tantalum >=100nF

C8 VDDX1 filter cap X7R/tantalum >=100nF

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C9 VDDPLL filter cap ceramic X7R 100nF .. 220nF

C10 OSC load cap

C11 OSC load cap

C12 PLL loop filter cap

C13 PLL loop filter cap See CRG Block User Guide

C14 DC cutoff cap

R1 PLL loop filter res

Q1 Quartz/Resonator

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible
to the corresponding pins(C1 – C9).
• Central point of the ground star should be the VSS1 pin.
• Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and
VSSM1,2,3.
• VSSPLL must be directly connected to VSS1.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10,
C11, C14 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.

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Appendix A Electrical Characteristics

A.1 General
This supplement contains the most accurate electrical information for the MC9S12H256 and
MC9S12H128 microcontroller available at the time of publication.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.

A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
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customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.

NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.

P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.

A.1.2 Power Supply

The MC9S12H256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PH, PU, PV and PW. VDDR
supplies the internal voltage regulator.
VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PH, PU, PV and PW.

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VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator
and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by
anti-parallel diodes for ESD protection.

NOTE: In the following context VDD5 is used for either VDDA, VDDM, VDDR and
VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM
and VDDR pins.
VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
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A.1.3 Pins

There are four groups of functional pins.

A.1.3.1 5V I/O pins

Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.

A.1.3.2 Analog Reference

This group is made up by the VRH and VRL pins.

A.1.3.3 Oscillator

The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.

A.1.3.4 TEST

This pin is used for production testing only.

A.1.4 Current Injection

Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the

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greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.

A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
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Table A-1 Absolute Maximum Ratings1

Num Rating Symbol Min Max Unit
1 I/O, Regulator and Analog Supply Voltage VDD5 –0.3 6.0 V

2 Digital Logic Supply Voltage 2 VDD –0.3 3.0 V

3 PLL Supply Voltage 2 VDDPLL –0.3 3.0 V

Voltage difference VDDX1 to VDDX2 to VDDM and

4 ∆VDDX –0.3 0.3 V
VDDA
5 Voltage difference VSSX to VSSR and VSSA ∆VSSX –0.3 0.3 V

6 Digital I/O Input Voltage VIN –0.3 6.0 V

7 Analog Reference VRH, VRL –0.3 6.0 V

8 XFC, EXTAL, XTAL inputs VILV –0.3 3.0 V

9 TEST input VTEST –0.3 10.0 V

Instantaneous Maximum Current
10 Single pin limit for all digital I/O pins except PU, PV ID –25 +25 mA
and PW 3
Instantaneous Maximum Current
11 I –55 +55 mA
D
Single pin limit for Port PU, PV and PW 4
Instantaneous Maximum Current
12 IDL –25 +25 mA
Single pin limit for XFC, EXTAL, XTAL5
Instantaneous Maximum Current
13 IDT –0.25 0 mA
Single pin limit for TEST 6

14 Storage Temperature Range T

stg – 65 155 °C

NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2, VSSM and VDDM or VSSA and VDDA.
4. Ports PU, PV, PW are internally clamped to VSSM and VDDM.

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5. Those pins are internally clamped to VSSPLL and VDDPLL.
6. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.

A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
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Model Description Symbol Value Unit

Series Resistance R1 1500 Ω
Storage Capacitance C 100 pF
Human Body
Number of Pulse per pin –
positive – 3
negative 3

Series Resistance R1 0 Ω
Storage Capacitance C 200 pF
Machine
Number of Pulse per pin –
positive – 3
negative 3
Minimum input voltage limit –2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table A-3 ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) VHBM 2000 – V

2 C Machine Model (MM) VMM 200 – V

3 C Charge Device Model (CDM) VCDM 500 – V

Latch-up Current at TA = 125°C
4 C positive ILAT +100 – mA
negative –100
Latch-up Current at TA = 27°C
5 C positive ILAT +200 – mA
negative –200

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A.1.7 Operating Conditions

This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.

NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature TA and the junction temperature TJ. For power dissipation
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating Symbol Min Typ Max Unit
I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V
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Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V

PLL Supply Voltage 2 VDDPLL 2.35 2.5 2.75 V

Voltage Difference VDDX to VDDR and VDDA ∆VDDX –0.1 0 0.1 V

Voltage Difference VSSX to VSSR and VSSA ∆VSSX –0.1 0 0.1 V

Oscillator fosc 0.5 – 16 MHz

Bus Frequency fbus 0.5 – 16 MHz

MC9S12H256C, MC9S12H128C

Operating Junction Temperature Range TJ –40 – 100 °C

Operating Ambient Temperature Range 2 T

A –40 27 85 °C

MC9S12H256V, MC9S12H128V

Operating Junction Temperature Range TJ –40 – 120 °C

Operating Ambient Temperature Range 2 TA –40 27 105 °C

MC9S12H256M, MC9S12H128M

Operating Junction Temperature Range T

J –40 – 140 °C

Operating Ambient Temperature Range 2 TA –40 27 125 °C

NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-
tion between ambient temperature TA and device junction temperature TJ.

A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:

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T J = T A + ( P D • Θ JA )

T J = Junction Temperature, [°C ]

T A = Ambient Temperature, [°C ]

P D = Total Chip Power Dissipation, [W]

Θ JA = Package Thermal Resistance, [°C/W]

The total power dissipation can be calculated from:

P D = P INT + P IO

P INT = Chip Internal Power Dissipation, [W]

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P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA

∑ RDSON ⋅ IIOi
2
P IO =
i

PIO is the sum of all output currents on I/O ports associated with VDDX1,2 and VDDM1,2,3.

Table A-5 Thermal Package Characteristics1

Num C Rating Symbol Min Typ Max Unit
1 T Thermal Resistance LQFP112, single sided PCB2 θJA – – 54 oC/W

Thermal Resistance LQFP112, double sided PCB

2 T θJA – – 41 oC/W
with 2 internal planes3

3 T Thermal Resistance LQFP 144, single sided PCB θJA – – 45 oC/W

Thermal Resistance LQFP 144, double sided PCB

4 T θJA – – 37 oC/W
with 2 internal planes
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7

A.1.9 I/O Characteristics

This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.

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Table A-6 5V I/O Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage V 0.65*VDD5 – VDD5 + 0.3 V
IH

2 P Input Low Voltage V VSS5 – 0.3 – 0.35*VDD5 V

IL

3 C Input Hysteresis V 250 mV

HYS

Input Leakage Current except PU, PV, PW (pins in

4 P high impedance input mode)1 Iin –1.0 – 1.0 µA
Vin = VDD5 or VSS5

Input Leakage Current PU, PV, PW (pins in high

5 P impedance input mode)2 Iin –2.5 – 2.5 µA
Vin = VDD5 or VSS5
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Output High Voltage (pins in output mode, except PU,

PV and PW)
6 P Partial Drive I VOH VDD5 – 0.8 – – V
OH = –1.0mA
Full Drive IOH = –10mA

Output Low Voltage (pins in output mode except PU,

PV and PW)
7 P Partial Drive I V – – 0.8 V
OL = +1.0mA OL

Full Drive IOL = +10mA

Output High Voltage (pins PU, PV and PW in output

8 P mode) I V VDD5 – 0.32 VDD5 – 0.2 – V
OH
OH = –20mA
Output Low Voltage (pins PU, PV and PW in output
9 P mode) I V – .2 0.32 V
OL
OL = +20mA
Output Rise Time (pins PU, PV and PW in output
10 P mode with slew control enabled) VDD5=5V, tr 60 100 130 ns
Rload=1KΩ, 10% to 90% of VOH

Output Fall Time (pins PU, PV and PW in output

11 P mode with slew control enabled) VDD5=5V, tf 60 100 130 ns
Rload=1KΩ, 10% to 90% of VOH

Internal Pull Up Device Current,

12 P tested at V Max. IPUL – – –130 µA
IL

Internal Pull Up Device Current,

13 P tested at V Min. IPUH –10 – – µA
IH

Internal Pull Down Device Current,

14 P tested at V Min. IPDH – – 130 µA
IH

Internal Pull Down Device Current,

15 P tested at V Max. IPDL 10 – – µA
IL

16 D Input Capacitance Cin 6 – pF

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Table A-6 5V I/O Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Injection current3
17 T Single Pin limit IICS –2.5 – 2.5 mA
Total Device Limit. Sum of all injected currents IICP –25 25

18 P Port H, J Interrupt Input Pulse filtered4 tPULSE 3 µs

19 P Port H, J Interrupt Input Pulse passed4 tPULSE 10 µs

NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
3. Refer to Section A.1.4 Current Injection, for more details
4. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.

A.1.10.1 Measurement Conditions

All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.

A.1.10.2 Additional Remarks

In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be

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given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
Run supply currents
1 P mA
Single Chip, Internal regulator enabled IDD5 65
Wait Supply current
2 P All modules enabled, PLL on IDDW 40 mA
P only RTI enabled 1 5

Pseudo Stop Current (RTI and COP disabled) 1, 2

C –40°C 360
P 27°C 420 520
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C 70°C 760
C 85°C 800
3 IDDPS µA
P C Temp Option 100°C 950 2000
C 105°C 1000
P V Temp Option 120°C 1500 3300
C 125°C 1700
P M Temp Option 140° C 2500 4800

Pseudo Stop Current (RTI and COP enabled) 1, 2

C –40°C 420
C 27°C 480
C 70°C 820
4 IDDPS µA
C 85°C 860
C 105°C 1050
C 125°C 1700
C 140°C 2500

Stop Current 2
C –40°C 20
P 27°C 40 100
C 70°C 200
C 85°C 300
5 IDDS µA
P C Temp Option 100°C 550 1500
C 105°C 700
P V Temp Option 120°C 1200 2900
C 125°C 1400
P M Temp Option 140°C 2200 4500

NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed

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A.2 ATD Characteristics

This section describes the characteristics of the analog to digital converter.

A.2.1 ATD Operating Characteristics

The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
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Conditions are shown in Table A-4 unless otherwise noted

Num C Rating Symbol Min Typ Max Unit
Reference Potential
1 D Low VRL VSSA VDDA/2 V
High VRH VDDA/2 VDDA V
2 C Differential Reference Voltage1 VRH–VRL 4.50 5.00 5.25 V
3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz
ATD 10-Bit Conversion Period
4 D Clock Cycles2 NCONV10 14 28 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 7 14 µs
ATD 8-Bit Conversion Period
5 D Clock Cycles2 NCONV8 12 26 Cycles
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV8 6 13 µs
6 D Stop Recovery Time (VDDA=5.0 Volts) tSR 20 µs
7 P Reference Supply current IREF 0.375 mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.

A.2.2 Factors influencing accuracy

Three factors – source resistance, source capacitance and current injection – have an influence on the
accuracy of the ATD.

A.2.2.1 Source Resistance:

Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or

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operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.

A.2.2.2 Source Capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS– CINN).

A.2.2.3 Current Injection

There are two cases to consider.

1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
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VRL unless the current is higher than specified as disruptive condition.

2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 C Max input Source Resistance RS – – 1 KΩ

Total Input Capacitance

2 T Non Sampling CINN 10 pF
Sampling CINS 22

3 C Disruptive Analog Input Current INA –2.5 2.5 mA

4 C Coupling Ratio positive current injection Kp 10–4 A/A

5 C Coupling Ratio negative current injection Kn 10–2 A/A

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A.2.3 ATD accuracy

Table A-10 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH – VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C Rating Symbol Min Typ Max Unit
1 P 10-Bit Resolution LSB 5 mV
2 P 10-Bit Differential Nonlinearity DNL –1 1 Counts
3 P 10-Bit Integral Nonlinearity INL –2.5 ±1.5 2.5 Counts
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4 P 10-Bit Absolute Error1 AE –3 ±2.0 3 Counts

5 P 8-Bit Resolution LSB 20 mV

6 P 8-Bit Differential Nonlinearity DNL –0.5 0.5 Counts
7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts

8 P 8-Bit Absolute Error1 AE –1.5 ±1.0 1.5 Counts

NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.

For the following definitions see also Figure A-1.

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
Vn – V0
INL ( n ) = ∑ DNL ( i ) = -------------------- – n
1LSB
i=1

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DNL

LSB 10-Bit Absolute Error Boundary

Vi–1 Vi

$3FF
8-Bit Absolute Error Boundary
$3FE

$3FD

$3FC $FF

$3FB
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$3FA

$3F9

$3F8 $FE

$3F7

$3F6

$3F5
10-Bit Resolution

8-Bit Resolution
$3F4 $FD

$3F3

9
Ideal Transfer Curve
8 2

6
10-Bit Transfer Curve
5

4 1

2
8-Bit Transfer Curve
1

0
5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV

Figure A-1 ATD Accuracy Definitions

NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.

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MC9S12H256 Device User Guide — V01.18

A.3 NVM, Flash and EEPROM

NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.

A.3.1 NVM timing

The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
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using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.

A.3.1.1 Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1 1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ----------
f NVMOP f bus

A.3.1.2 Burst Programming

This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1 1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ----------
f NVMOP f bus

The time to program a whole row is:

t brpgm = t swpgm + 31 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.

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A.3.1.3 Sector Erase

Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:

1
t era ≈ 4000 ⋅ ---------------------
f NVMOP
The setup time can be ignored for this operation.

A.3.1.4 Mass Erase

Erasing a NVM block takes:

1
t mass ≈ 20000 ⋅ ---------------------
f NVMOP
The setup time can be ignored for this operation.
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Table A-11 NVM Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 D External Oscillator Clock fNVMOSC 0.5 32 1 MHz

2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 MHz

3 D Operating Frequency fNVMOP 150 200 kHz

4 P Single Word Programming Time tswpgm 46 2 74.5 3 µs

5 D Flash Burst Programming consecutive word 4 tbwpgm 20.4 2 31 3 µs

6 D Flash Burst Programming Time for 32 Words 4 tbrpgm 678.4 2 1035.5 3 µs

7 P Sector Erase Time tera 20 5 26.7 3 ms

8 P Mass Erase Time tmass 100 5 133 3 ms

NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.

3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. urst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.

A.3.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.

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The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Data Retention
Num C Rating Cycles Unit
Lifetime
1 C Flash/EEPROM (-40˚C to +125˚C) 10 15 Years

2 C EEPROM (-40˚C to +125˚C) 10,000 5 Years

NOTE: Flash cycling performance is 10 cycles at -40˚C to +125˚C. Data retention is

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specified for 15 years.

NOTE: EEPROM cycling performance is 10K cycles at -40˚C to 125˚C. Data retention is
specified for 5 years on words after cycling 10K times. However if only 10 cycles
are executed on a word the data retention is specified for 15 years.

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A.4 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).

A.4.1 Startup

Table A-13 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table A-13 Startup Characteristics

Conditions are shown in Table A-4 unless otherwise noted
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Num C Rating Symbol Min Typ Max Unit

1 T POR release level VPORR 2.07 V

2 T POR assert level VPORA 0.97 V

3 D Reset input pulse width, minimum input time PWRSTL 2 tosc

4 D Startup from Reset nRST 192 196 nosc

5 D Interrupt pulse width, IRQ edge-sensitive mode PWIRQ 20 ns

6 D Wait recovery startup time tWRS 14 tcyc

A.4.1.1 POR

The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.

A.4.1.2 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.

A.4.1.3 External Reset

When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.

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A.4.1.4 Stop Recovery

Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.

A.4.1.5 Pseudo Stop and Wait Recovery

The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.

A.4.2 Oscillator

The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
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oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.
Table A-14 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 C Crystal oscillator range fOSC 0.5 16 MHz

2 P Startup Current iOSC 100 µA

3 D Oscillator start-up time from POR or STOP nUPOSC 4100 cycOSC

4 C Oscillator start-up time tUPOSC 81 1002 ms

5 D Clock Quality check time-out tCQOUT 0.45 2.5 s

6 P Clock Monitor Failure Assert Frequency fCMFA 50 100 200 KHz

7 P External square wave input frequency3 fEXT 0.5 32 MHz

8 D External square wave pulse width low tEXTL 15 ns

9 D External square wave pulse width high tEXTH 15 ns

10 D External square wave rise time tEXTR 1 ns

11 D External square wave fall time tEXTF 1 ns

12 D Input Capacitance EXTAL pin CIN 9 pF

13 D Input Capacitance XTAL pin CIN 13 pF

DC Operating Bias in Colpitts Configuration on
14 C VDCBIAS 1.1 V
EXTAL Pin
NOTES:
1. fosc = 4MHz, C = 22pF.
2. Maximum value is for extreme cases using high Q, low frequency crystals

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3. XCLKS =1 during reset

A.4.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.

A.4.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

VDDPLL
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Cs Cp

R
Phase VCO
fosc 1 fref fvco
∆ KΦ KV
refdv+1
Detector
fcmp

Loop Divider
1 1
synr+1 2

Figure A-2 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-15.
The VCO Gain at the desired VCO output frequency is approximated by:
( f 1 – f vco )
-----------------------
K 1 ⋅ 1V
KV = K1 ⋅ e
The phase detector relationship is given by:

K Φ = i ch ⋅ K V
ich is the current in tracking mode.

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The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.

2 ⋅ ζ ⋅ f ref 1 f ref
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
2 50 4 ⋅ 50

π⋅ ζ+ 1+ζ
 
And finally the frequency relationship is defined as

f VCO
n = ------------- = 2 ⋅ ( synr + 1 )
f ref
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With the above inputs the resistance can be calculated as:

2 ⋅ π ⋅ n ⋅ fC
R = -----------------------------
KΦ

The capacitance Cs can now be calculated as:

2
2⋅ζ 0.516
C s = ---------------------- ≈ --------------- ;( ζ = 0.9 )
π ⋅ fC ⋅ R fC ⋅ R

The capacitance Cp should be chosen in the range of:

C s ⁄ 20 ≤ C p ≤ C s ⁄ 10
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).

A.4.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.

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0 1 2 3 N–1 N

tmin1
tnom
tmax1

tminN
tmaxN
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Figure A-3 Jitter Definitions

The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
 t max ( N ) t min ( N ) 
J ( N ) = max  1 – --------------------- , 1 – --------------------- 
 N ⋅ t nom N ⋅ t nom 

For N < 100, the following equation is a good fit for the maximum jitter:

j1
J ( N ) = -------- + j 2
N

J(N)

1 5 10 20 N

Figure A-4 Maximum bus clock jitter approximation

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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.

Table A-15 PLL Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Self Clock Mode frequency fSCM 1 5.5 MHz

2 D VCO locking range fVCO 8 32 MHz

Lock Detector transition from Acquisition to Tracking
3 D |∆trk| 3 4 %1
mode

4 D Lock Detection |∆Lock| 0 1.5 %1

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5 D Un-Lock Detection |∆unl| 0.5 2.5 %1

Lock Detector transition from Tracking to Acquisition
6 D |∆unt| 6 8 %1
mode

7 C PLLON Total Stabilization delay (Auto Mode) 2 tstab 0.5 ms

8 D PLLON Acquisition mode stabilization delay 2 tacq 0.3 ms

9 D PLLON Tracking mode stabilization delay 2 tal 0.2 ms

10 P Fitting parameter VCO loop gain3 K1 –120 -224 MHz/V

11 D Fitting parameter VCO loop frequency f1 75 MHz

12 P Charge pump current acquisition mode | ich | 20 38.5 60 µA

13 P Charge pump current tracking mode | ich | 2 3.5 6 µA

14 C Jitter fit parameter 12 j1 1.1 %

15 C Jitter fit parameter 22 j2 0.13 %

NOTES:
1. % deviation from target frequency
2. fREF = 4MHz, fBUS = 16MHz equivalent fVCO = 32MHz: REFDV = #$03, SYNR = #$0F, Cs = 4.7nF, Cp = 470pF, Rs = 10KΩ.
3. K1 is measured with VXFC = 1.4V and VXFC = 1.7V @ VDD5 = 5.25V

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A.5 MSCAN
Table A-16 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P MSCAN Wake-up dominant pulse filtered tWUP 2 µs

2 P MSCAN Wake-up dominant pulse pass tWUP 5 µs

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A.6 SPI
A.6.1 Master Mode

Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS1
(OUTPUT)

2 1 11 3
SCK 4
(CPOL = 0)
(OUTPUT) 4
12
SCK
(CPOL = 1)
(OUTPUT)
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5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

9 9 10

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure A-5 SPI Master Timing (CPHA = 0)

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SS1
(OUTPUT)
1
2 12 11 3
SCK
(CPOL = 0)
(OUTPUT)
4 4 11 12
SCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

9 10
MOSI
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(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA

1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure A-6 SPI Master Timing (CPHA =1)

Table A-17 SPI Master Mode Timing Characteristics1

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs

Num C Rating Symbol Min Typ Max Unit

1 P Operating Frequency fop DC 1/4 fbus

1 P SCK Period tsck = 1./fop tsck 4 2048 tbus

2 D Enable Lead Time tlead 1/2 — tsck

3 D Enable Lag Time tlag 1/2 tsck

4 D Clock (SCK) High or Low Time twsck tbus − 30 1024 tbus ns

5 D Data Setup Time (Inputs) tsu 25 ns

6 D Data Hold Time (Inputs) thi 0 ns

9 D Data Valid (after SCK Edge) tv 25 ns

10 D Data Hold Time (Outputs) tho 0 ns

11 D Rise Time Inputs and Outputs tr 25 ns

12 D Fall Time Inputs and Outputs tf 25 ns

NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.

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A.6.2 Slave Mode

Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS
(INPUT)

1 12 11 3
SCK
(CPOL = 0)
(INPUT)
2 4 4
11 12
SCK
(CPOL = 1)
(INPUT) 8
7 9 10 10
MISO
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(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

Figure A-7 SPI Slave Timing (CPHA = 0)

SS
(INPUT)
1 3
2 12 11
SCK
(CPOL = 0)
(INPUT)
4 4 11 12
SCK
(CPOL = 1)
(INPUT)
9 10 8
MISO
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

Figure A-8 SPI Slave Timing (CPHA =1)

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Table A-18 SPI Slave Mode Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C Rating Symbol Min Typ Max Unit
1 P Operating Frequency fop DC 1/4 fbus

1 P SCK Period tsck = 1./fop tsck 4 2048 tbus

2 D Enable Lead Time tlead 1 tcyc

3 D Enable Lag Time tlag 1 tcyc

4 D Clock (SCK) High or Low Time twsck tcyc − 30 ns

5 D Data Setup Time (Inputs) tsu 25 ns

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6 D Data Hold Time (Inputs) thi 25 ns

7 D Slave Access Time ta 1 tcyc

8 D Slave MISO Disable Time tdis 1 tcyc

9 D Data Valid (after SCK Edge) tv 25 ns

10 D Data Hold Time (Outputs) tho 0 ns

11 D Rise Time Inputs and Outputs tr 25 ns

12 D Fall Time Inputs and Outputs tf 25 ns

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MC9S12H256 Device User Guide — V01.18

A.7 LCD_32F4B
Table A.7-19 LCD_32F4B Driver Electrical Characteristics
Characteristic Symbol Min. Typ. Max. Unit
LCD Supply Voltage VLCD -0.25 - VDDX + 0.25 V
LCD Output Impedance(BP[3:0],FP[31:0])
for outputs to charge to higher voltage level or to ZBP/FP - - 5.0 kOhm
GND 1
LCD Output Current (BP[3:0],FP[31:0])
for outputs to discharge to lower voltage level IBP/FP 50 - - uA
except GND 2
NOTES:
1. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
2. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
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MC9S12H256 Device User Guide — V01.18

A.8 External Bus Timing

A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-20. All major bus signals are included in the diagram. While both a data write
and data read cycle are shown, only one or the other would occur on a particular bus cycle.

A.8.1 General Muxed Bus Timing

The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
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1, 2
3 4

ECLK
PE4

5 6 16 10
9 15 11
Addr/Data
data addr data
(read)
PA, PB
7
8

12 14 13
Addr/Data
data addr data
(write)
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PA, PB

17 18 19
Non-Multiplexed
Addresses
PK5:0

20 21 22 23
ECS
PK7

24 25 26
R/W
PE2

27 28 29
LSTRB
PE3

30 31 32
NOACC
PE7

33 34 35 36
IPIPO0
IPIPO1, PE6,5

Figure A-9 General External Bus Timing

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Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

1 P Frequency of operation (E-clock) fo 0 16.0 MHz

2 P Cycle time tcyc 62.5 ns

3 D Pulse width, E low PWEL 30 ns

4 D Pulse width, E high1 PWEH 30 ns

5 D Address delay time tAD 8 ns

6 D Address valid time to E rise (PWEL–tAD) tAV 22 ns

7 D Muxed address hold time tMAH 2 ns

tAHDS
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8 D Address hold to data valid 7 ns

9 D Data hold to address tDHA 2 ns

10 D Read data setup time tDSR 24 ns

11 D Read data hold time tDHR 0 ns

12 D Write data delay time tDDW 7 ns

13 D Write data hold time tDHW 2 ns

14 D Write data setup time1 (PWEH–tDDW) tDSW 23 ns

15 D Address access time1 (tcyc–tAD–tDSR) tACCA 30 ns

16 D E high access time1 (PWEH–tDSR) tACCE 6 ns

17 D Non-multiplexed address delay time tNAD 6 ns

18 D Non-muxed address valid to E rise (PWEL–tNAD) tNAV 26 ns

19 D Non-multiplexed address hold time tNAH 2 ns

20 D Chip select delay time tCSD 6 + tcyc/4 ns

21 D Chip select access time1 (tcyc–tCSD–tDSR) tACCS tcyc/4 – 2 ns

22 D Chip select hold time tCSH 2 ns

23 D Chip select negated time tCSN 8 ns

24 D Read/write delay time tRWD 7 ns

25 D Read/write valid time to E rise (PWEL–tRWD) tRWV 25 ns

26 D Read/write hold time tRWH 2 ns

27 D Low strobe delay time tLSD 7 ns

28 D Low strobe valid time to E rise (PWEL–tLSD) tLSV 25 ns

29 D Low strobe hold time tLSH 2 ns

30 D NOACC strobe delay time tNOD 7 ns

31 D NOACC valid time to E rise (PWEL–tNOD) tNOV 25 ns

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Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF

Num C Rating Symbol Min Typ Max Unit

32 D NOACC hold time tNOH 2 ns

33 D IPIPO[1:0] delay time tP0D 2 7 ns

34 D IPIPO[1:0] valid time to E rise (PWEL–tP0D) tP0V 22 ns

35 D IPIPO[1:0] delay time1 (PWEH–tP1V) tP1D 2 25 ns

36 D IPIPO[1:0] valid time to E fall tP1V 22 ns

NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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MC9S12H256 Device User Guide — V01.18

Appendix B Package Information

B.1 General
This section provides the physical dimensions of the MC9S12H256 and MC9S12H128 packages.
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B.2 112-pin LQFP package

4X 0.20 T L-M N 4X 28 TIPS 0.20 T L-M N J1 4X P

PIN 1
112 85
IDENT J1

1 84
CL

VIEW Y X
108X G
X=L, M OR N

VIEW Y
B V

L M
B1 J AA
V1
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28 57 F BASE
METAL
D
29 56
0.13 M T L-M N
N
SECTION J1-J1
A1 ROTATED 90 ° COUNTERCLOCKWISE

S1 NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
S 3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
C2 VIEW AB 6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
C 0.050 θ2 PROTRUSION SHALL NOT CAUSE THE D
0.10 T 112X DIMENSION TO EXCEED 0.46.

SEATING MILLIMETERS
PLANE
DIM MIN MAX
θ3 A 20.000 BSC
T A1 10.000 BSC
B 20.000 BSC
B1 10.000 BSC
C --- 1.600
C1 0.050 0.150
C2 1.350 1.450
θ D 0.270 0.370
E 0.450 0.750
F 0.270 0.330
G 0.650 BSC
J 0.090 0.170
R R2
K 0.500 REF
P 0.325 BSC
R1 0.100 0.200
R R1 0.25 R2 0.100 0.200
S 22.000 BSC
GAGE PLANE S1 11.000 BSC
V 22.000 BSC
V1 11.000 BSC
Y 0.250 REF
(K) Z 1.000 REF
C1 θ1 AA 0.090 0.160
E θ 0° 8 °
(Y) θ1 3 ° 7 °
θ2 11 ° 13 °
(Z) θ3 11 ° 13 °
VIEW AB

Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)

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B.3 144-pin LQFP package

4X 0.20 T L-M N 4X 36 TIPS 0.20 T L-M N

PIN 1 144 109

IDENT

1 108
J1 4X P

J1
L M
CL

B V X
X=L, M OR N
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140X G
B1 V1 VIEW Y
VIEW Y

36 73 NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
37 72 3. DATUMS L, M, N TO BE DETERMINED AT THE
N SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
A1 5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
S1 PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
A AND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
S PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.

VIEW AB

C 0.1 T 144X MILLIMETERS

θ2 DIM MIN MAX
A 20.00 BSC
SEATING A1 10.00 BSC
PLANE B 20.00 BSC
θ2 B1 10.00 BSC
C 1.40 1.60
T C1 0.05 0.15
C2 1.35 1.45
D 0.17 0.27
E 0.45 0.75
PLATING F 0.17 0.23
J F AA C2 G 0.50 BSC
J 0.09 0.20
0.05 K 0.50 REF
R2 P 0.25 BSC
θ R1 0.13 0.20
R2 0.13 0.20
R1 S 22.00 BSC
S1 11.00 BSC
V 22.00 BSC
BASE 0.25 V1 11.00 BSC
D METAL
GAGE PLANE Y 0.25 REF
0.08 M T L-M N Z 1.00 REF
AA 0.09 0.16
θ 0°
SECTION J1-J1 (K) θ1 0° 7°
(ROTATED 90 ° )
144 PL C1 θ2 11° 13 °
E
(Y) θ1 CASE 918-03
(Z) ISSUE C
VIEW AB

Figure B-2 144-pin LQFP mechanical dimensions (case no. 918-03)

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User Guide End Sheet

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