Digital Integrated Circuit (IC) Layout and
Design - Week 10, Lecture 20
Midterm Due in Class
Dynamic Logic
SRAM
Wrap up
EE134 1
Clocked CMOS Logic (C2MOS)
Clocked CMOS Register (Positive Edge)
φ1 low:
• Master enabled. N1 = D. M1 & M3 on.
• Slave latched. M6 and M7 off. Output Q is
in charge storage mode (floating). Hi-Z
state (high impedance).
φ1 high:
• Master Hi-Z state (N1 floating Dn).
• Slave enabled. Qn+1 = Dn.
CLK
N1 Q
EE134 2
1
C2MOS: Precharge – Evaluate (PE) Logic
General Concept Specific Example
VDD VDD
Clk Mp off
Clk Mp on
Z 1
Out
In1 CL (AB+C)
In2 PDN A
In3 C
B
Clk Me
off
Clk Me on
CLK = 0: Precharge output Z = VDD.
Me off; Mp on. Z = VDD.
CLK = 1: Evaluate. Mp off. Me on. CLK = 0: Precharge Z = 1
Pull down Z (or not) depending on CLK = 1: Evaluate. Z = (AB + C)
logic implemented in PDN.
EE134 3
Domino Logic
Like falling dominoes.
VDD VDD
Clk Mp Clk Mp
1→1
Out1
1→0
0→0
In1 0→1
In2 PDN In4 PDN
In3 In5
Clk Me Clk Me
CLK=0: Precharge
CLK=1: Logic propagates thru series of gates like dominoes falling.
EE134 4
2
Domino Logic with Keeper at output
Use small Mkp
VDD VDD
Clk Mp Clk Mp Mkp
1→1
Out1 Out2
1→0
0→0
In1 0→1
In2 PDN In4 PDN
In3 In5
Clk Me Clk Me
EE134 5
Dynamic Shift Register
Non-overlapping clock
φ1 high φ1 high
φ2 high φ2 high
∆1 ∆2
EE134 6
3
Non-Overlapping CLK
∆2
1
0 0 1 0 1
1 1 0 1 0
0 1 0 1
1
0
1
1 1 1 0
0 1
0 0 0 1 0
1 1 0 1 0
0
∆1
Initially, CLK=1 (Black). φ1 =1 & φ2 =0.
CLK Î 0 (Red)
CLK Î 1 (Blue)
EE134 7
Static RAM (SRAM)
SRAM Cell: Simple D-FF (Latch)
BIT BIT
M3 / M4
M5 M6
M1 / M2
WORD
• Word line low
• Pass transistors M5 and M6 off.
• Data latched in inverter pair. D-FF (Latch)
• Word line high: Writing / Reading
• Writing: Write by force.
• Reading: BIT and BIT precharged to either VDD or VDD/2. Read.
EE134 8
4
SRAM at transistor level
WL
VDD
M2 M4
Q
M5 Q M6
M1 M3
BL BL
EE134 9
EE134 Summary
Major Challenges
Cost
Power Consumption
Robustness
Complexity
Some new circuit solutions and design
methodologies are coming.
EE134 10
5
Technology Scaling
SRC
EE134 11
Research Roadmap
EE134 12
6
Device Evolution
EE134 13
25 nm FinFET
EE134 14
7
Cost
Mask cost in 90nm technology is over $1M.
Bugs are very expensive.
Design effort increases in DSM.
Cost of new tools.
Non-recurring costs dominate the price
effectiveness of low-volume ASICs.
Need to have a product that can fit multiple
applications, customers (flexibility).
EE134 15
Power has become a Problem
EE134 16
8
The Productivity Gap
EE134 17
Challenges in Digital Design
The Deep Submicron (DSM) Effect
∝ DSM ∝ 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.
Everything Looks a Little
Different …and There’s a Lot of Them!
EE134 18
9
ABET Evaluation: Course Objectives
Things that you should have learned in EE134.
Course Objective Very Very
Poorly Well
1 Understand the device model for a modern short- 1 2 3 4 5
channel FET.
2 Understand the parasitic diodes and capacitors of 1 2 3 4 5
an inverter.
3 Ability to layout, DRC, and LVS a CMOS digital 1 2 3 4 5
IC.
4 Calcuate delay times through inverters and logic 1 2 3 4 5
gates.
5 Size a chain of inverters to drive a large 1 2 3 4 5
capacitive load.
6 Design static CMOS logic gates. 1 2 3 4 5
7 Understand CMOS transmisison gates. 1 2 3 4 5
8 Understand CMOS transmission gate latches and 1 2 3 4 5
registers.
EE134 19
ABET: Program Outcomes
Attribute Very Very
Poorly Well
a An ability to apply knowledge of mathematics, 1 2 3 4 5
science, and engineering
b An ability to design and conduct experiments, as 1 2 3 4 5
well as to analyze and interpret data
c An ability to design a system, component, or 1 2 3 4 5
process to meet desired needs
d An ability to function on multi-disciplinary teams 1 2 3 4 5
e An ability to identify, formulate, and solve 1 2 3 4 5
engineering problems
f An understanding of professional ethical 1 2 3 4 5
responsibility
g An ability to communicate effectively 1 2 3 4 5
h The broad education necessary to understand the 1 2 3 4 5
impact of engineering solutions in a global and
societal context
i A recognition of the need for, and an ability to 1 2 3 4 5
engage in life-long learning
j A knowledge of contemporary issues 1 2 3 4 5
k An ability to use the techniques, skills, and 1 2 3 4 5
modern engineering tools necessary for
EE134engineering practice 20
10
EE134 21
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