To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.

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April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
HAT2068R
Silicon N Channel Power MOS FET
Power Switching
REJ03G1176-0500
(Previous: ADE-208-1225C)
Rev.5.00
Sep 07, 2005

Features
• Capable of 4.5 V gate drive
• Low drive current
• High density mounting
• Low on-resistance
RDS (on) = 7 mΩ typ. (at VGS = 10 V)

Outline

RENESAS Package code: PRSP0008DD-D

(Package name: SOP-8 <FP-8DAV> )
5 6 7 8
D D D D

65
87 4 1, 2, 3 Source
G 4 Gate
5, 6, 7, 8 Drain
34
12

S S S
1 2 3

Rev.5.00 Sep 07, 2005 page 1 of 6

HAT2068R

Absolute Maximum Ratings

(Ta = 25°C)
Item Symbol Value Unit
Drain to source voltage VDSS 30 V
Gate to source voltage VGSS ±20 V
Drain current ID 14 A
Note 1
Drain peak current ID (pulse) 112 A
Body-drain diode reverse drain current IDR 14 A
Note 2
Channel dissipation Pch 2.5 W
θ ch-a °C/W
Note 2
Channel to ambient thermal impedance 50
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s

Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V (BR) DSS 30 — — V ID = 10 mA, VGS = 0
Gate to source breakdown voltage V (BR) GSS ±20 — — V IG = ±100 µA, VDS = 0
Gate to source leak current IGSS — — ±10 µA VGS = ±16 V, VDS = 0
Zero gate voltage drain current IDSS — — 1 µA VDS = 30 V, VGS = 0
Gate to source cutoff voltage VGS (off) 1.0 — 2.5 V VDS = 10 V, ID = 1 mA
Note 3
Static drain to source on state resistance RDS (on) — 7 9 mΩ ID = 7 A, VGS = 10 V
Note 3
RDS (on) — 11 16 mΩ ID = 7 A, VGS = 4.5 V
Note 3
Forward transfer admittance |yfs| 16 28 — S ID = 7 A, VDS = 10 V
Input capacitance Ciss — 1650 — pF VDS = 10 V
Output capacitance Coss — 400 — pF VGS = 0
Reverse transfer capacitance Crss — 220 — pF f = 1 MHz
Total gate charge Qg — 26 — nC VDD = 10 V
Gate to source charge Qgs — 5 — nC VGS = 10 V
Gate to drain charge Qgd — 5 — nC ID = 14 A
Turn-on delay time td (on) — 15 — ns VGS = 10 V, ID = 7 A
Rise time tr — 30 — ns VDD ≈ 10 V
Turn-off delay time td (off) — 50 — ns RL = 1.43 Ω
Fall time tf — 10 — ns Rg = 4.7 Ω
Note 3
Body-drain diode forward voltage VDF — 0.80 1.10 V IF = 14 A, VGS = 0
Body-drain diode reverse recovery time trr — 50 — ns IF = 14 A, VGS = 0
diF/dt = 50 A/µs
Note: 3. Pulse test

Rev.5.00 Sep 07, 2005 page 2 of 6

HAT2068R

Main Characteristics

Power vs. Temperature Derating Maximum Safe Operation Area

4.0 500
Test Condition:
Pch (W)

When using the glass epoxy board

100 10
(FR4 40 × 40 × 1.6 mm), PW ≤ 10 s µs

ID (A)
10
3.0 0µ
s
DC PW 1m
10 s
Op =1
Channel Dissipation

era 0m

Drain Current
tio s
2.0 n(
PW N
1 Operation in ≤ 1 ote 4
this area is 0s
)
limited by RDS (on)
1.0 0.1
Ta = 25°C
1 shot Pulse
0 0.01
0 50 100 150 200 0.1 0.3 1 3 10 30 100

Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V)

Note 4:
When using the glass epoxy board
(FR4 40 × 40 × 1.6 mm)
Typical Output Characteristics Typical Transfer Characteristics
50 50
10 V Pulse Test VDS = 10 V
4.5 V Pulse Test
(A)
(A)

40 40
4V 3.5 V
ID
ID

30 30
Drain Current
Drain Current

20 20
VGS = 3 V
25°C
Tc = 75°C
10 10
–25°C

0 0
0 2 4 6 8 10 0 1 2 3 4 5

Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V)

Drain to Source Saturation Voltage vs. Static Drain to Source on State Resistance
Gate to Source Voltage vs. Drain Current
VDS (on) (V)

0.20 100
RDS (on) (mΩ)
Drain to Source on State Resistance

Pulse Test Pulse Test

50
0.16

20
Drain to Source Voltage

0.12 VGS = 4.5 V

10
0.08
ID = 10 A 5 10 V

0.04 5A
2
2A
0 1
0 4 8 12 16 20 0.1 0.2 0.5 1 2 5 10 20 50 100

Gate to Source Voltage VGS (V) Drain Current ID (A)

Rev.5.00 Sep 07, 2005 page 3 of 6

HAT2068R

Static Drain to Source on State Resistance Forward Transfer Admittance vs.

vs. Temperature Drain Current

RDS (on) (mΩ)

Static Drain to Source on State Resistance

Forward Transfer Admittance |yfs| (S)

50 100
Pulse Test
30 Tc = –25°C
40

10 75°C
30
3
ID = 2 A, 5 A 25°C
20 10 A
1
VGS = 4.5 V
10
0.3
VDS = 10 V
10 V 2 A, 5 A, 10 A Pulse Test
0 0.1
–40 0 40 80 120 160 0.1 0.3 1 3 10 30 100

Case Temperature Tc (°C) Drain Current ID (A)

Body-Drain Diode Reverse Typical Capacitance vs.

Recovery Time Drain to Source Voltage
100 10000
Reverse Recovery Time trr (ns)

3000
Capacitance C (pF)
Ciss
50
1000

Coss
300

100 Crss
20

di / dt = 50 A / µs 30
VGS = 0
VGS = 0, Ta = 25°C f = 1 MHz
10 10
0.1 0.2 0.5 1 2 5 10 20 0 10 20 30 40 50

Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V)

Dynamic Input Characteristics Switching Characteristics

50 20 200
VDS (V)

VGS (V)

ID = 14 A
VGS 100
16
Switching Time t (ns)

40
td(off)
VDD = 25 V 50 tf
Drain to Source Voltage

Gate to Source Voltage

30 10 V 12 tr
VDS 5V
20 td(on)
20 8
10

10 VDD = 25 V 4 5
10 V VGS = 10 V, VDS = 10 V
5V Rg = 4.7 Ω, duty ≤ 1 %
0 0 2
0 20 40 60 80 100 0.1 0.2 0.5 1 2 5 10 20

Gate Charge Qg (nc) Drain Current ID (A)

Rev.5.00 Sep 07, 2005 page 4 of 6

HAT2068R

Reverse Drain Current vs.

Source to Drain Voltage
50

Reverse Drain Current IDR (A)

10 V
40

5V
30
VGS = 0

20

10

Pulse Test
0
0 0.4 0.8 1.2 1.6 2.0

Source to Drain Voltage VSD (V)

Normalized Transient Thermal Impedance vs. Pulse Width

Normalized Transient Thermal Impedance γ s (t)

10

D=1
1

0.5
0.2
0.1 0.1
0.05 θch – f (t) = γ s (t) • θch – f
0.02 θch – f = 83.3°C/W, Ta = 25°C
0.01 When using the glass epoxy board
0.01
(FR4 40 × 40 × 1.6 mm)

lse PW
pu PDM D=
t T
0.001 ho
1s
PW
T

0.0001
10 µ 100 µ 1m 10 m 100 m 1 10 100 1000 10000

Pulse Width PW (S)

Switching Time Test Circuit Switching Time Waveform

90%
Vin Monitor Vout
Monitor
D.U.T. Vin 10%
Rg RL
Vout 10% 10%

Vin VDS
10 V = 10 V 90% 90%

td(on) tr td(off) tf

Rev.5.00 Sep 07, 2005 page 5 of 6

HAT2068R

Package Dimensions
JEITA Package Code RENESAS Code Package Name MASS[Typ.]
P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-D FP-8DAV 0.085g

*1 D

F
5 bp
8

*2 E

HE

c
Index mark

1 4 Terminal cross section

NOTE)
1. DIMENSIONS "*1(Nom)" AND "*2"
Z (Ni/Pd/Au plating)
DO NOT INCLUDE MOLD FLASH.
*3 bp 2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
x M
e
Reference Dimension in Millimeters
Symbol
Min Nom Max
D 4.90 5.3
L1
E 3.95
A2
A1 0.10 0.14 0.25
A 1.75
bp 0.34 0.40 0.46
A

b1
A1

c 0.15 0.20 0.25

L c1

0° 8°
y HE 5.80 6.10 6.20
Detail F e 1.27
x 0.25
y 0.1
Z 0.75
L 0.40 0.60 1.27
L1 1.08

Ordering Information
Part Name Quantity Shipping Container
HAT2068R-EL-E 2500 pcs Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.

Rev.5.00 Sep 07, 2005 page 6 of 6

 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.

Colophon .3.0