Department of Information Technology
Digital Electronics [KOE 039] Question Bank
[Unit-1]
Short Answer Questions [2 Marks]
Qns 1
(a) The solution to the quadratic equation k2-11k+22=0 are x=3 and x=6. What is the base of the
number system
(b) Determine the value of base x, if: (193)x = (623)8
(c) What is (33)6 + (45)6
(d) Convert the following
(i) (562.13)7 = (?)10
(ii) (467.342)8 = (?)10
(e) Perform 2’s complement subtraction of 010110 – 100101
(f) Convert the following numbers as indicated:
(i) (BC64)16 = ( )10 = ( )2
(ii) (111011)2 = ( )5
Long Answer Questions [10 Marks]
Qns 2 Given two Boolean functions
𝑓1 = 𝐵̅ 𝐷 + 𝐷(𝐴̅ + 𝐵)
𝑓2 = (𝐴 + 𝐵̅ + 𝐶)(𝐴 + 𝐶̅ + 𝐷
̅ )(𝐴̅ + 𝐵 + 𝐶 + 𝐷
̅)
Find (i) 𝑓1 + 𝑓2 (ii) 𝑓1 . 𝑓2 (iii) 𝑓̅1 . 𝑓2 (iv) 𝑓1 + 𝑓̅2
Qns 3 Simplify the following Boolean function by using the tabulation method (Quine McCluskey
method) and also implement.
𝑓(𝑤, 𝑥, 𝑦, 𝑧) = ∏𝑀(2,7,9,10,11,12,14,15). 𝑑(0,4,6,8) 𝑨𝒏𝒔. 𝑧(𝑤
̅ + 𝑥)(𝑥̅ + 𝑦̅)
Qns 4 Reduce the following expression using K-Map
F(A, B,C,D,E) =∑m(6,9,13,18,19,25,27,29,31)+d(2,3,11,15,17,24,28)
Qns 5 Reduce the following expression using K-Map
𝐹(𝐴, 𝐵, 𝐶, 𝐷, 𝐸) = ∏ (0,1,4,5,7,8,10,12,14,16,20,21,22,23,26,30). 𝑑(2,3,11,15,17,24,28)
𝑀
[Unit-2]
Short Answer Questions [2 Marks]
Qns 1
(a) Implement 4:1 MUX using 2:1 MUX.
(b) Demultiplexer is decoder circuit with an additional enabling input. Do you agree with the above
statement?
(c) Implement 16:1 MUX using 8:1 MUX.
(d) Explain how BCD addition is carried out.
(e) How many unused input combinations are there in a BCD adder?
(f) Construct half Subtractor using logic gates.
Long Answer Questions [10 Marks]
Qns 2 Design a combinational circuit that compares the magnitude of two 4 bit numbers and its output
indicates whether A>B, A=B, A<B.
Qns 3 Construct a BCD to excess 3 code converter with a 4-bit adder. What must be done to change the
circuit to an excess 3 to BCD code converter?
Qns 4 Construct BCD adder using two 4-bit binary parallel adder and logic gates. Explain its working for two 4-bit
binary numbers.
Qns 5 Design 5:32 Decoder using 3:8 Decoder.
Qns 6 Implement and design the following Boolean function
𝒇(𝑨, 𝑩, 𝑪, 𝑫) = ∑𝒎(𝟎, 𝟏, 𝟑, 𝟒, 𝟕, 𝟖, 𝟗, 𝟏𝟏, 𝟏𝟒, 𝟏𝟓) using
(i) 4:1 MUX and
(ii) 2:1 MUX.
[Unit-3]
Short Answer Questions [2 Marks]
Qns 1
(a) Discus the Race Around Condition in JK Flip Flops and how it can be resolve?
(b) What is the difference between Flip-Flop and Latch?
(c) Discuss the Difference between Asynchronous Counter and Synchronous Counter?
(d) Give the difference between positive and negative edge triggering. Also discuss how the ripple
counters are differing from synchronous counters?
(e) A ripple counter having 5 flip-flops (10 ns time delay each). Then determine (i) No. of Mods (ii)
fout when fclk=16 MHz (iii) Total time delay of counter (iv) Maximum allowed clock frequency
Long Answer Questions [10 Marks]
Qns 2 Design and implement a 3-bit up/down counter with direction control Mode M, using T FF.
Qns 3 Explain 4-bit Johnson counter with circuit diagram and waveform.
Qns 4 Design and Implement the MOD 6 Asynchronous up counter using JK flip flop.
Qns 5 Design a universal shift register that performs HOLD, SHIFT RIGHT, SHIFT LEFT, & LOAD.
Qns 6 Convert SR Flip Flop to JK Flip Flop.
Qns 7 Draw the logic diagram of a 4-bit binary ripple counter using flip flops that trigger on the positive
edge transition.
[Unit-4]
Short Answer Questions [2 Marks]
Qns 1
(a) Define critical race, non-critical race & Hazards in logic circuits. And also discuss, how we can
design a circuit Hazards free.
(b) Discuss the design procedure for analyzing an asynchronous sequential circuit with SR latches.
(c) What is the significance of state assignment?
(d) Define fundamental mode operation.
(e) Explain the difference between stable and unstable states.
(f) What is the difference between an internal state and a total state?
(g)
Long Answer Questions [10 Marks]
Qns 2 Derive the state table and state diagram for given sequential circuits
Qns 3 Derive the state table and state diagram for given sequential circuits
Qns 4 Derive the transition table for the asynchronous sequential circuit shown in given figure. Determine
the sequence of internal states Y1Y2 for the following sequence of inputs x1x2: 00,10,11,01,11,10,00.
Qns 5 Derive the transition table for the asynchronous sequential circuit as shown in figure
Qns 6 Design a gated latch circuit with two inputs G (gate) and D (data) and one output Q. Binary
information present at the D input is transferred to the Q output when G is equal to 1. The Q output will
follow the D input as long as G = 1. When G goes to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q output. The gated latch is a memory element that
accepts the value of D when G = 1 and retains this value after G goes to 0. Once G = 0, a change in D
does not change the value of the output Q.
Qns 7 Distinguish between critical and non-critical race condition. How will you determine race
conditions in circuits and how we can reduce it from the circuits?
Qns 8 (i)Distinguish between static and dynamic hazard. How will you determine hazard in
combinational circuits? (ii)Draw the logic diagram of the product-of-sums expression Y= (x1+x2’)
(x2+x3) Show that there is a static 0-hazard when x1 and x3 are equal to 0 and x2 goes from 0 to 1. Find a
way to remove the hazard by adding one more OR gate.
[Unit-5]
Short Answer Questions [2 Marks]
Qns 1
(a) What is logic family? Give the classification of logic families in brief.
(b) Describe Fan Out, Fan in & figure of merit of a logic family. Also Compare PLA and PAL logic
devices.
(c) Why is ECL logic faster than TTL?
(d) Compare static RAM and dynamic RAM.
Long Answer Questions [10 Marks]
Qns 2 Define the following characteristics of a digital logic IC/family
(a) Propagation Delay
(b) Fan-in/Fan-out
(c) Noise Margin/noise immunity
(d) Figure of Merit
Qns 3 With the help of neat diagram, explain the working of following logic TTL NOR Gate family.
Qns 4 Differentiate between PLA and PAL. Realize the full adder circuit using PAL.
Qns 5 With the help of neat diagram, explain the working of following logic CMOS NAND Gate family.
