Analog-to-Digital Converter Survey and Analysis

Chintan Undhad
Information and Communication
Technology
Marwadi University
Rajkot, India
chintan.undhad107901@marwadiunive
rsity.ac.in

Abstract—Analog-to-digital converters (ADC’s) are mechanisms limit achieved SNR: input-referred circuit noise
ubiquitous, critical components of software radio and other (equivalent thermal noise), aperture uncertainty, and
signal processing systems. This paper surveys the state-of-the- comparator ambiguity.
art of ADC’s, including experimental converters and
commercially available parts. The distribution of resolution
versus sampling rate provides insight into ADC performance
limitations. At sampling rates below 2 million samples per
second (Ms/s), resolution appears to be limited by thermal noise.
At sampling rates ranging from 2 Ms/s to 4 giga samples per
second (Gs/s), resolution falls off by 1 bit for every doubling of
the sampling rate. This behavior may be attributed to
uncertainty in the sampling instant due to aperture jitter. For
ADC’s operating at multi-Gs/s rates, the speed of the device
technology is also a limiting factor due to comparator
ambiguity. Many ADC architectures and integrated circuit
technologies have been proposed and implemented to push back
these limits. The recent trend toward single-chip ADC’s brings
lower power dissipation. However, technological progress as
measured by the product of the ADC resolution (bits) times the
sampling rate is slow. Average improvement is only 1.5 bits for
any given sampling frequency over the last six–eight
years.Keywords—Analog-to-digital converters, aperture jitter,
comparator ambiguity, input-referred noise, signal-to-noise
ratio, spurious-free dynamic range.

I. INTRODUCTION
During the past two decades, the rapid evolution of digital
integrated circuit technologies has led to ever more
sophisticated signal processing systems. One of the keys to the
success of these systems has been the advance in analog-to-
digital converters (ADC’s) which convert the continuous-time
signals to discrete-time, binary-coded form. More generally,
the large number of signal types to be digitized has led to a
diverse selection of data converters in terms of architectures,
resolution, and sampling rates. An analysis of SNR shows that
the 1-bit per octave slope is related to the sample-to-sample
variation of the instant in time at which sampling occurs
IV. HIGH-PERFORMANCE ADC ARCHITECTURES
II. ADC CHARACTERIZATION

The ADC’s of the preceding figures include architectures

This paper focuses on determining the resolution in bits for ranging from flash, a parallel technique, which is the fastest,
a given sampling rate. Quasi-static measures include through integrating which is probably the most accurate but
differential nonlinearity (DNL) and integral nonlinearity which also is the slowest. The fastest ADC reported is the 3-
(INL). This study focuses on SNR and SFDR because bit, 8 Gs/s Nyquist flash converter cited above. This ADC had
dynamic performance is most important for high-speed a maximum sampling rate of 14 Gs/s. In addition, the
applications and SNR and SFDR provide a more accurate separation of adjacent reference voltages grows smaller
measure of ADC performance than the stated-number-of-bits exponentially. Most flash converters available today have 8-
bit resolution. In order to overcome these problems, variations
III. PERFORMANCE ANALYSIS on the flash architecture have been developed which use
For a better understanding of ADC performance limits, it relatively few comparators yet retain good speed. Examples
is helpful to plot the effective resolution as determined from capable of Gs/s rates are the folded-flash and pipelined
SFDR and SNR. Many factors and loss mechanisms affect architectures. The reported ADC achieves ps aperture jitter,
ADC performance. Aside from quantization noise, three but requires two hybrids, each with five LSI
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 An architecture that trades speed for resolution combines
delta–sigma modulation with digital decimation filtering.
Delta–sigma converters sample the analog input signal at a
rate which is many times the Nyquist output rate. Delta–
sigma modulators may be designed with a bandpass
characteristic.This is useful when a relatively narrow band of
intermediate frequencies contains the signal to be digitized

V. LOW-POWER ADC ARCHITECTURES

Generally the highest performing converters also

dissipate the most power.

ACKNOWLEDGMENT
The mentoring support given by Vishalsir Assistant
The refrigeration overhead was not included in the Professor at Marwadi University and technical support given
determination of F for this circuit. Most of these very by Marwadi University.
efficient converters have been reported within the last six
years. REFERENCES
The template will number citations consecutively within
brackets [1]. The sentence punctuation follows the bracket [2].
VI. ADC PERFORMANCE OVER TIME Refer simply to the reference number, as in [3]—do not use
“Ref. [3]” or “reference [3]” except at the beginning of a
Improvement has been made over the last six–eight sentence: “Reference [3] was the first ...”
years or so. From the scatter in the data it is also evident that Number footnotes separately in superscripts. Place the
the improvement is quite sporadic. A similar lack of actual footnote at the bottom of the column in which it was
advancement for SFDR-bits also holds The scatter in the cited. Do not put footnotes in the abstract or reference list. Use
data emphasizes the sporadic nature of improvement in P letters for table footnotes.
however, a least squares fit through the logs of the very best
yearly data values indicates a gradual improvement over Unless there are six authors or more give all authors’
time. ) few application drivers that push the state-of-the-art. names; do not use “et al.”. Papers that have not been
published, even if they have been submitted for publication,
should be cited as “unpublished” [4]. Papers that have been
VII. SUMMARY accepted for publication should be cited as “in press” [5].
Capitalize only the first word in a paper title, except for proper
nouns and element symbols.
The SNR data show that converter performance is
limited by input-referred noise, aperture uncertainty and
comparator ambiguity. The best results have been achieved [1] R. H. Walden, A. E. Schmitz, A. R. Kramer, L. E. Larson, and J.
Pasiecznik, “A deep-submicrometer analog-to-digital converter using
for flash, folded-flash, pipelined, and time-interleaved focused-ion-beam implants,” IEEE J. Solid-State Circuits, vol. 25, pp.
architectures. 562–571, Apr. 1990
[2] T. B. Cho and P. R. Gray, “A 10b, 20 Msample/s, 35 mW pipeline A/D
converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar.
1995.
[3] K. Kusumoto, A. Matsuzawa, and K. Murata, “A 10-b, 20-MHz, 30
mW pipelined interpolating CMOS ADC,” IEEE J. Solid-State
Circuits, vol. 28, pp. 1200–1206, Dec. 1993.
[4] E. Stebbins and P. Bradley, “Hypres flash ADC program report,”
Hypres, Inc., 1993.
[5] G. Yin and W. Sansen, “A high-frequency and high-resolution
fourthorder SD A/D converter in BiCMOS technology,” IEEE J. Solid-
State Circuits, vol. 29, pp. 857–865, Aug. 1994.