8 7 6 5 4 3 2 1

CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
X1782 MLB SCHEMATIC 5 0021434873 ENGINEERING RELEASED
DATE
2019-12-20

PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 61 67 KEYBOARD & TRACKPAD 1 X1412_SHAN 05/17/2019
2 2 SYSTEM PCB SUMMARY 62 68 KEYBOARD & TRACKPAD 2 D
D 3 4 PD PARTS 63 69 BATTERY CONN, 3V3 G3H RTC VR
4 5 CPU GFX 64 70 PBUS SUPPLY & BATTERY CHARGER
5 6 CPU MISC/JTAG/CFG/RSVD 65 71 VR CORE & SA IMVP CTRL
6 7 CPU LPDDR3 INTERFACE 66 72 VR CORE & SA IMVP
7 8 CPU & PCH POWER 67 74 VR GT & GTX IMVP
8 9 CPU & PCH GROUNDS 68 76 VR 5V, 3V3
9 10 CPU CORE DECOUPLING 69 77 VR EOPIO EDRAM
10 11 CPU GT DECOUPLING 70 78 PMIC BUCKS AND SWS
11 12 PCH DECOUPLING 71 79 PMIC LDOS
12 13 PCH AUDIO/LPC/SPI/SMBUS 72 80 PMIC GPIOS & CONTROL
13 14 PCH POWER MANAGEMENT 73 81 VR VDDQ VCCIO
14 15 PCH PCIE/USB/CLKS 74 82 POWER FETS
15 16 PCH SPI/UART/GPIO 75 84 LCD BACKLIGHT DRIVER
16 18 CPU/PCH MERGED XDP 76 85 EDP DISPLAY CONNECTOR
17 19 CHIPSET SUPPORT 1 77 86 S4E<0>
18 20 CHIPSET SUPPORT 2 78 87 S4E<1>
19 22 LPDDR3 VREF MARGINING 79 88 S4E<2>
C 20 23 LPDDR3 DRAM CHANNEL A (00-31) 80 89 S4E<3> C
21 24 LPDDR3 DRAM CHANNEL A (32-63) 81 90 OCARINA PMIC & NAND VCC VR & VDDIO1 SWCH
22 25 LPDDR3 DRAM CHANNEL B (00-31) 82 96 SSD SUPPORT
23 26 LPDDR3 DRAM CHANNEL B (32-63) 83 124 FCT
24 27 LPDDR3 DRAM TERMINATION 84 125 PROBE POINTS
25 28 USB-C HIGH SPEED 1 85 135 DESENSE 1
26 29 USB-C HIGH SPEED 2 86 136 DESENSE 2
27 30 USB-C SUPPORT 87 137 DESENSE 3
28 31 USB-C PORT CONTROLLER A 88 138 DESENSE 4
29 32 USB-C PORT CONTROLLER B 89 140 DEV SUPPORT 1
30 33 USB-C CONNECTOR A 90 141 DEV SUPPORT 2
31 36 WIFI/BT SUPPORT J223_METE 05/14/2019 91 400 BOM CONFIGURATION
32 37 WIFI/BT MODULE 1 J223_METE 05/14/2019 92 401 BOM CONFIGURATION
33 38 WIFI/BT MODULE 2 J223_METE 05/14/2019 93 403 BOM GROUPS
34 39 SOC GPIO/SEP/USB/DDR/TEST 94 405 BOM VARIANT TABLES
35 40 SOC AOP/AON/SMC 95 406 BOM VARIANT TABLES
36 41 SOC ISP/I2C/UART/SPI/I2S 96 407 BOM VARIANT TABLES
37 42 SOC PCIE 97 410 BOM ALTERNATES
B 38 43 SOC POWER 1 98 500 BOARD RULES
B
39 44 SOC POWER 2
40 45 SOC POWER 3
41 46 SOC GROUND
42 47 SOC SHARED SUPPORT
43 48 SOC PROJECT SUPPORT
44 49 T151
45 50 SECURE ELEMENT
46 51 T139 SUPPORT
47 52 I2C CONNECTIONS 1
48 53 I2C CONNECTIONS 2
49 54 POWER SENSORS HIGH SIDE
50 55 POWER SENSORS LOAD SIDE
51 56 POWER SENSORS EXTENDED
52 57 POWER SENSORS EXTENDED 2
53 58 THERMAL SENSORS
54 59 POWER SENSORS EXTENDED 3
A 55 60 FANS/SMC/AMUX SUPPORT A
DRAWING TITLE
56 62 AUDIO PLACEHOLDER SCHEM,MLB,X1782
57 63 AUDIO JACK CODEC DRAWING NUMBER SIZE

58 64 AUDIO LEFT AMPLIFIERS 051-05309 D

Apple Inc. REVISION

59 65 AUDIO RIGHT AMPLIFIERS 5.1.0

NOTICE OF PROPRIETARY PROPERTY: BRANCH
60 66 AUDIO FLEX CONNECTORS THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

LAST_MODIFICATION=Mon Dec 16 17:32:55 2019

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 98
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 8 7 6 5 4 3 2 1

D DESIGN DESCRIPTION SCHEMATIC BOARD MCO PANEL D

J223/MLB POR CFL MLB 051-05309 820-01987 056-09380 057-01595-D

J213/FLEX_AUDIOJACK AUDIO JACK, 051-04122 821-02091 056-07548-27 N/A

AMR, AND MESA

J680/FLEX_USBC LEFT SIDE USB 051-03140 821-01646 056-05483-A N/A

TONGUE FLEX
J130/FLEX_BMU_SIGNAL SIGNALS TO 051-01247 821-01726 056-05589-A N/A
BMU
J130/FLEX_BMU_PWR POWER TO/FROM 051-01195 821-00583
BMU 056-02919-A N/A
C
J130/FLEX_TCON_MLB_A DISPLAYPORT FROM 051-01897 821-00981 056-02852-A N/A
C
MLB TO TCON
J213/FLEX_TRACKPAD MLB TO 051-04335 821-02218 056-07655-08 N/A
TRACKPAD
J130/FLEX_KB KB FLEX FOR ALL 051-02011 821-01046 056-03725-B N/A
3 KB TYPES
J213/FLEX_3MIC MIC FLEX 051-04441 821-02265 056-07754-24 N/A

J79/GRAPE_FLEX DFR TOUCH FLEX 051-01338 821-00681 056-02220-A N/A

DFR DAUGHTER FLEX DFR DAUGHTER VENDOR VENDOR 099-14398 N/A

B FLEX B

A A
PAGE TITLE

SYSTEM PCB SUMMARY DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 2 OF 98
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 8 7 6 5 4 3 2 1

TOP SIDE STANDOFFS USB-C BOSS DFR WASHER POGO PINS BACKLIGHT MLB MTG HOLES 2.1X3.36 MM
OMIT_TABLE CRITICAL
CRITICAL Z0431 CRITICAL CRITICAL
Z0400 Z0420 4.75OD2.73ID-H0.2 PP0400 ZT0420
2.8OD1.2ID-1.49H-SM POGO-2.3OD-4.06H-SM TH-NSP
3.4OD1.75ID-1.12H-SM RING-TH
1
1
SM-1
1
998-19711
2
860-01216 1
860-00392 1
870-09670
SL-2.1X3.51-4.6X6.01
NEAR RIGHT SPKR CONNECTOR
EAST OF NAND ALIGNED WITH
CRITICAL CRITICAL
BOTTOM SIDE STANDOFF ZT0421
CRITICAL TH-NSP
OMIT_TABLE
Z0401 Z0421 860-01519 1
998-19711
2.8OD1.2ID-1.49H-SM
3.4OD1.75ID-1.12H-SM POGO PIN DISPLAY SL-2.1X3.51-4.6X6.01

D 1
1
860-00392 CRITICAL
NEAR TRACKPAD CONNECTOR D
2
860-01216 PP0420
POGO-2.3OD-4.0H-SM
NORTH OF NAND SM-1
CRITICAL
CRITICAL
OMIT_TABLE DFR BOSS 1
870-09667 ZT0422 998-19711
Z0402 CRITICAL WIFI WASHER 1
TH-NSP
2.8OD1.2ID-1.49H-SM
CRITICAL SL-2.1X3.51-4.6X6.01
1 Z0430 Z0432 NEAR LEFT SPKR CONNECTOR
2
860-01216 3.4OD1.75ID-1.5H-SM 4.75OD2.73ID-H0.2
RING-TH POGO PINS DRAM
CRITICAL
NORTH OF NAND
1
860-01484 1 CRITICAL
OMIT_TABLE PP0410
POGO-2.3OD-4.0H-SM
Z0404 SM-1
2.8OD1.2ID-1.49H-SM
1
TRACKPAD BOSS 860-01519 1
870-09667
2
860-01216 CPU THERM STAGE HOLES 3.15 MM
CRITICAL
FAR SIDE NEAR AJ CONN CRITICAL
CRITICAL Z0440 POGO PIN FAN CRITICAL ZT0400
3.5OD1.85ID-1.41H-SM 3P9R3P15
OMIT_TABLE
1
860-00381 CRITICAL PP0411
POGO-2.3OD-4.0H-SM
1 998-0845
Z0405 PP0430 SM-1 CORNER NEAREST KEYBOARD
2.8OD1.2ID-1.49H-SM POGO-2.3OD-4.0H-SM
1 CRITICAL
SM-1 1
870-09667
860-01216 Z0441
1
870-09667
C
2
SOUTH OF NAND
3.5OD1.85ID-1.41H-SM CPU THERM STAGE HOLES 3.6 MM C
CRITICAL 1
860-00381 CRITICAL
ZT0401
OMIT_TABLE SHIELD CAN ALIGMENT HOLES 4.0R3.6-NSP
1 998-03850
Z0406
2.8OD1.2ID-1.49H-SM
1
DISPLAY BOSS CRITICAL
ZT0441
860-01216 CRITICAL TH-NSP CRITICAL
2
NORTH OF NAND
Z0450
2.7X1.8R-1.4ID-0.91H-SM
1
SL-1.2X0.4-1.5X0.7
998-04440 ZT0402
4.0R3.6-NSP
CRITICAL 1 998-03850
1
860-00469 CRITICAL
ZT0442
TH-NSP

CRITICAL
1
998-04440 CRITICAL
BOTTOM SIDE TALL STANDOFF Z0451
SL-1.2X0.4-1.5X0.7 ZT0403
4.0R3.6-NSP
OMIT_TABLE 2.7X1.8R-1.4ID-0.91H-SM CRITICAL
ZT0443
1 998-03850
Z0460 1
860-00469 TH-NSP
2.8OD1.2ID-3.15H-SM 1
998-04440
1
860-01485 SL-1.2X0.4-1.5X0.7

2
EAST OF NAND ALIGNED WITH CRITICAL
ZT0444
FAN MTG HOLE 2.0X2.6 MM
TOP SIDE STANDOFF TH-NSP CRITICAL
AJ FLEX COWLING BOSS 1
SL-1.2X0.4-1.5X0.7
998-04440 ZT0430
TH-NSP

CRITICAL
1
SL-2.6X2.0-4.7X4.1
998-03974
Z0470 CRITICAL
B POGO PIN HEAT PIPE 3.5OD1.85ID-1.92H-SM ZT0445
TH-NSP
B
CRITICAL
1
860-00382 1
SL-1.2X0.4-1.5X0.7
998-04440
PP0499
POGO-2.3OD-4.0H-SM
SHIELD CAN ALIGNMENT SLOTS DRAM
SM-1 CRITICAL
ZT0446 CRITICAL
1 TH-NSP SL0490
TH-NSP
870-09667 1
SL-1.2X0.4-1.5X0.7
998-04440 1
998-04440
SL-1.2X0.4-1.5X0.7

CRITICAL
SL0491
TH-NSP

NOTE: REFER TO BOM TABLES. ONLY SOLDERED PARTS REMAIN IN RAMP/PVT SMT BOM. OTHERS MOVED TO POST-SMT ENCLOSURE BOM
1
SL-1.2X0.4-1.5X0.7
998-04440

USB-C SHIELD 2X PLATED SLOTS IN MEM AREA DUE TO

SPACE CONSTRAINTS <RDAR://44382678>
ALL OTHER SHIELD ALIGNMENT SLOTS ARE
NPTH + GND RING FOR BETTER TOLERANCE
806-19049 1 USBC_CAN CRITICAL
SHIELD CAN,HOLES,TITAN RIDGE,X1533 USBC_SHLD
LIQUID SPILL INDICATOR
870-08656 1 TAPE,NON COND,STIFFENER,TITAN RIDGE,CAN,X1533 USBC_CAN_TAPE CRITICAL USBC_TAPE
825-00493 4 LSI,BLACK,REEL,X1030 LSI1,LSI2,LSI3,LSI4 CRITICAL LSI

MEGA SHIELD CPU SLEDS

604-25986 1 MEGA CAN,INSULATED,X1533 MEGA_CAN CRITICAL MEGA_SHLD
806-14839 2 SLED,METAL,MATT NICKEL,X940 SLED1,SLED2 CRITICAL CPU_SLEDS
A SYNC_MASTER= SYNC_DATE= A
DRAM SHIELD TOP PAGE TITLE

PD PARTS
806-18560 1 FENCE,DRAM,UNIV,X1533 DRAM_TOP_FENCE CRITICAL DRAM_TOP_FENC DRAWING NUMBER SIZE

870-07840 1 DRAM_TOP_FENCE_TAPE CRITICAL DRAM_TOP_TAPE TOP SIDE STANDOFFS 051-05309 D

TAPE,COND,DRAM,UNIV,X1533 Apple Inc. REVISION

860-01216 6 BOSS,STANDOFF,MLB,X1533 Z0400-Z0402,Z0404-Z0406 CRITICAL STANDOFFS_TOP 5.1.0

DRAM SHIELD BOTTOM NOTICE OF PROPRIETARY PROPERTY: BRANCH

806-19048 1 SHIELD CAN,HOLES,DRAM,UNIV,X1533 DRAM_BOT_CAN CRITICAL DRAM_BOT_CAN BOTTOM SIDE STANDOFFS THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

870-08657 1 TAPE,NON COND,STIFFENER,DRAM,CAN DRAM_BOT_CAN_TAPE CRITICAL DRAM_BOT_TAPE 860-01485 1 BOSS,STANDOFF,MLB,TALL,X1533 Z0460 CRITICAL STANDOFFS_BOT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=MECHANICALS IV ALL RIGHTS RESERVED 3 OF 98
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 8 7 6 5 4 3 2 1

D D
U0500
CFL-U
4+3E
BGA
AL5 SYM 1 OF 20 AG4
25 OUT
DP_X_SNK0_ML_C_N<0> DDI1_TXN[0] OMIT_TABLE EDP_TXN[0] EDP_ML_N<0> OUT 76

25 DP_X_SNK0_ML_C_P<0> AL6 DDI1_TXP[0] EDP_TXP[0] AG3 EDP_ML_P<0> 76

OUT OUT
25 DP_X_SNK0_ML_C_N<1> AJ5 DDI1_TXN[1] EDP_TXN[1] AG2 EDP_ML_N<1> 76
OUT OUT
25 DP_X_SNK0_ML_C_P<1> AJ6 DDI1_TXP[1] EDP_TXP[1] AG1 EDP_ML_P<1> 76
OUT OUT
25 DP_X_SNK0_ML_C_N<2> AF6 DDI1_TXN[2] EDP_TXN[2] AJ4 EDP_ML_N<2> 76
OUT OUT
25 DP_X_SNK0_ML_C_P<2> AF5 DDI1_TXP[2] EDP_TXP[2] AJ3 EDP_ML_P<2> 76
OUT OUT
25 DP_X_SNK0_ML_C_N<3> AE5 DDI1_TXN[3] EDP_TXN[3] AJ2 EDP_ML_N<3> 76
OUT OUT
25 DP_X_SNK0_ML_C_P<3> AE6 DDI1_TXP[3] EDP_TXP[3] AJ1 EDP_ML_P<3> 76
OUT OUT

DDI

EDP
25 DP_X_SNK1_ML_C_N<0> AC4 DDI2_TXN[0] EDP_AUX_N AH4 EDP_AUXCH_N 76
OUT BI
25 DP_X_SNK1_ML_C_P<0> AC3 DDI2_TXP[0] EDP_AUX_P AH3 EDP_AUXCH_P 76
OUT BI
25 DP_X_SNK1_ML_C_N<1> AC1 DDI2_TXN[1]
OUT
25 DP_X_SNK1_ML_C_P<1> AC2 DDI2_TXP[1] DISP_UTILS AM7
OUT NC
25 DP_X_SNK1_ML_C_N<2> AE4 DDI2_TXN[2]
OUT
DDI1_AUX_N AC7 DP_X_SNK0_AUXCH_C_N 25
25 DP_X_SNK1_ML_C_P<2> AE3 DDI2_TXP[2]
BI
OUT
DDI1_AUX_P AC6 DP_X_SNK0_AUXCH_C_P 25
25 DP_X_SNK1_ML_C_N<3> AE1 DDI2_TXN[3]
BI
OUT
DDI2_AUX_N AD4 DP_X_SNK1_AUXCH_C_N 25
25 DP_X_SNK1_ML_C_P<3> AE2 DDI2_TXP[3]
BI
OUT
DDI2_AUX_P AD3 DP_X_SNK1_AUXCH_C_P 25
BI
DDI3_AUX_N AG7
NC
DISPLAY SIDEBANDS DDI3_AUX_P AG6
NC
27 4 UPC_XB_FAULT_L CK9 GPP_E12_USB2_OC3*
IN
GPP_E7/CPU_GP1 CN3 XDP_PCH_OBSDATA_A3 16
OUT

C 25 IN
DP_X_SNK0_HPD CN6 GPP_E13/DDPB_HPD0 GPP_E8/SATALED* CN7
CK6
XDP_PCH_OBSDATA_B0 OUT 16 C
87 83 73 9 7 PPVCCIO_S0_CPU CM6 GPP_E9/USB2_OC0* XDP_USB_EXTC_OC_L 4
PLACE_NEAR=U0500.AM6:15.24MM 25 DP_X_SNK1_HPD GPP_E14/DDPC_HPD1 CK5
1
IN
CP7 GPP_E10/USB2_OC1* XDP_USB_EXTD_OC_L 4
R0530 18 TEST_NOA_N_10 GPP_E15/DPPD_HPD2 CK8
GPP_E11/USB2_OC2* UPC_XA_FAULT_L IN 4 27
24.9 TEST_NOA_N_11 CP6
1% 18 GPP_E16/DPPE_HPD3 CK11
1/20W CM7 EDP_BKLTEN EDP_BKLT_EN 4 75 83
MF 43 4 XDP_DP_INT_HPD GPP_E17/EDP_HPD CH11
OUT

2 201
IN
EDP_BKLTCTL EDP_BKLT_PWM OUT 4 76 83

EDP_COMP AM6 DISP_RCOMP EDP_VDDEN CG11 EDP_PANEL_PWR_EN 4 76 83

OUT

U0500
CFL-U
4+3E
BGA
B NC
AL2 RSVD
SYM 20 OF 20
SPARE RSVD CR3
NC
B
AN2 RSVD OMIT_TABLE RSVD CR4
NC NC
AN4 RSVD RSVD CR35
NC NC
AT3 RSVD RSVD CP3
NC NC
AU3 RSVD RSVD G1
NC NC
H4 RSVD RSVD G2
NC NC
BV25 RSVD RSVD H3
NC NC
CG1 RSVD RSVD W3
NC NC
CG2 RSVD RSVD Y3
NC NC
AL1 RSVD RSVD BB24
NC NC
AL3 RSVD RSVD BC24
NC NC
AL4 RSVD RSVD BC28
NC NC
AM3 RSVD RSVD BK35
NC NC
AM4 RSVD RSVD BK36
NC NC
AN1 RSVD RSVD BT8
NC NC
AN3 RSVD RSVD BT9
NC NC
AY9 RSVD RSVD BV24
NC NC
BB9 RSVD RSVD BP8
NC NC
PP3V3_S5 5 7 11 12 13 14 18 42 43 47 69 RSVD BP9
71 73 74 83 89 NC

R0550 100K 1 2
5% 1/20W MF 201
UPC_XA_FAULT_L 4 27

R0551 100K 1 2
5% 1/20W MF 201
UPC_XB_FAULT_L 4 27

R0552 100K 1 2
5% 1/20W MF 201
XDP_USB_EXTC_OC_L 4

R0553 100K 1 2
5% 1/20W MF 201
XDP_USB_EXTD_OC_L 4

A R0557 100K 1 2
5% 1/20W MF 201
XDP_DP_INT_HPD 4 43
SYNC_MASTER= SYNC_DATE=
A
R0540 100K 1 2 EDP_BKLT_EN 4 75 83
PAGE TITLE

R0541 100K 1 2
5% 1/20W MF 201
EDP_BKLT_PWM 4 76 83
CPU GFX
5% 1/20W MF 201 DRAWING NUMBER SIZE
R0542 100K 1 2 EDP_PANEL_PWR_EN 4 76 83 051-05309 D
5% 1/20W MF 201 Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 4 OF 98
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 8 7 6 5 4 3 2 1
47 43 42 18 14 13 12 11 7 4 PP3V3_S5
89 83 74 73 71 69 DBGLED DBGLED
1
TP0600
1
R0690 R0691 1
A 750K 1K
1% 5%
TP-P5 1/20W 1/20W
PLACE_SIDE=BOTTOM MF MF
PLACE_NEAR=DS0601.A:13MM 2 201 201 2
CATERR_LED_G CATERR_LED_A
83 70 69 65 42 18 17 9 7 PP1V_S3
DBGLED A DS0601
83 71 16 9 7 PP1V_S0SW PLACE_NEAR=U0500.BJ1:25MM PLACE_NEAR=U7800.L6:13MM D 3 CRITICAL VALUE=GRN-90MCD-5MA-2.85V
PLACE_SIDE=BOTTOM
SILK_PART=CATERR
PLACE_NEAR=R0611:1MM R0612 1 1
R0614 Q0601 0402
1 1K 49.9 SSM6N15AFEAP
R0610 5% 1%
VER-1
SOT563
K DBGLED
1K 1/20W 1/20W U0500 CATERR_LED_K
5% MF MF CFL-U
D
1/20W
MF
201 2 PLACE_NEAR=U4750.4:13MM
201 2 2 201 4+3E
5 G S 4
D 6 DBGLED
CRITICAL
D
83 72 CPU_CATERR_L AA4 CATERR* BGA
42 CPU_PECI R0613 1 2 43 5% 1/20W MF 201 CPU_PECI_R
OUT
AR1 PECI
SYM 4 OF 20
OMIT_TABLE
Q0601
BI VER-1 SSM6N15AFEAP
42 BI
CPU_PROCHOT_L R0611 2 1 300 5% 1/20W MF 201 83 CPU_PROCHOT_R_L Y4 PROCHOT* SOT563
PLACE_NEAR=U0500.Y4:38MM 85 83 72 17 PM_THRMTRIP_L BJ1 THRMTRIP*
OUT
PROC_TCK T6 XDP_CPU_TCK 2 G
E1 IN 16 S 1
SKTOCC* U6
NC PROC_TDI XDP_CPU_TDI IN 16

84 XDP_BPM_L<0> U1 BPM[0]* PROC_TDO Y5 XDP_CPU_TDO 16

BI OUT
NC_XDP_BPM_L<1> U2 BPM[1]* PROC_TMS T5 XDP_CPU_TMS 16
IN

CPU MISC

JTAG
NC_XDP_BPM_L<2> U3 BPM[2]* PROC_TRST* AB6 XDP_CPU_TRST_L 16
IN
NC_XDP_BPM_L<3> U4 BPM[3]*
PCH_TCK W6 XDP_PCH_TCK 16
IN
PCH_TDI U5 XDP_PCH_TDI 16
IN
PCH_TDO W5 XDP_PCH_TDO 16
OUT
PCH_TMS P5 XDP_PCH_TMS 16
IN
PCH_TRST* Y6 XDP_PCH_TRST_L 16
IN
PCH_JTAGX P6 PCH_JTAGX 16
PROC_POPIRCOMP BP27 PROC_POPIRCOMP BI

PCH_OPIRCOMP BW25 PCH_OPIRCOMP

OPCE_RCOMP L5 OPCE_RCOMP
OPC_RCOMP N5 OPC_RCOMP

R0681 1 R0682 1 R0683 1 R0684 1

49.9 49.9 49.9 49.9
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
201 2 201 2 201 2 201 2

PLACE_NEAR=U0500.BP27:12.7MM
C PLACE_NEAR=U0500.BW25:12.7MM
PLACE_NEAR=U0500.L5:12.7MM
C
PLACE_NEAR=U0500.N5:12.7MM

U0500
CFL-U
4+3E
BGA
T4 SYM 19 OF 20 B35
16 BI
CPU_CFG<0> CFG[0] (IPU) RSVD_TP NC_CPU_B35
R4 RESERVED A34
16 BI
CPU_CFG<1> CFG[1] (IPU) RSVD_TP NC_CPU_A34
T3 OMIT_TABLE
CPU_CFG<2> CFG[2] (IPU)
BJ34
CFG<4> :EDP ENABLE/DISABLE: 1 = DISABLED 0 = ENABLED BI
R3 RSVD_TP TEST_CPU_BJ34 18
16 CPU_CFG<3> CFG[3] (IPU)
D34
BI
J4 RSVD_TP TEST_CPU_D34 18
16 BI
CPU_CFG<4> CFG[4] (IPU)

EDP_ENABLE 16 CPU_CFG<5> M4 CFG[5] (IPU)

BI
1 CPU_CFG<6> J3
R0634 16 BI
M3
CFG[6] (IPU)

1K 16 BI
CPU_CFG<7> CFG[7] (IPU)
5% R2
1/20W 16 BI
CPU_CFG<8> CFG[8] (IPU)
MF N2
201 2 16 BI
CPU_CFG<9> CFG[9] (IPU)

16 CPU_CFG<10> R1 CFG[10] (IPU)

BI
16 CPU_CFG<11> N1 CFG[11] (IPU)
BI
16 CPU_CFG<12> J2 CFG[12] (IPU)
BI
16 CPU_CFG<13> L2 CFG[13] (IPU)
BI
16 CPU_CFG<14> J1 CFG[14] (IPU)
BI
16 CPU_CFG<15> L1 CFG[15] (IPU)
BI

CPU_CFG<16> L3
B 16

16
BI
CPU_CFG<17> L4
CFG[16]
CFG[17]
(IPU)

(IPU)
B
BI

16 CPU_CFG<18> N3 CFG[18] (IPU)

BI
16 CPU_CFG<19> N4 CFG[19] (IPU)
BI

CPU_CFG_RCOMP AB5 CFG_RCOMP

PLACE_NEAR=U0500.AB5:13MM
W4
R0680 1 16 OUT
ITP_PMODE ITP_PMODE
49.9 TEST_CPU_A35 A35
1% 18 RSVD_TP BP36
1/20W TP NC_CPU_BP36
MF
201 2
TP BP35 NC_CPU_BP35
TP BR18 NC_CPU_BR18

TP1 BP34 NC_CPU_BP34

TP BK34 NC_CPU_BK34

ZVM* AH26 CPU_ZVM_L 69 CONNECT TO OPC VRS

OUT

RSVD_TP F34 TEST_CPU_F34 18

RSVD_TP CN36 TEST_CPU_CN36 18

MSM* AJ27 NC_CPU_MSM_L CONNECT TO EOPIO VRS. Not used with combined VR for OPC/EOPIO

UFS_RESET* AR3
NC
18 TEST_CPU_F37 F37 RSVD_TP INPUT3VSEL BT27 CPU_INPUT3VSEL
IST_TRIG CP36 CPU_IST_TRIG
A 18 TEST_CPU_BJ36 BJ36 RSVD_TP TP0630 SYNC_MASTER= SYNC_DATE=
A
1 NOSTUFF PAGE TITLE
A
TP-P5
PLACE_SIDE=BOTTOM
1
R0632 1
R0631 CPU MISC/JTAG/CFG/RSVD
0 47K DRAWING NUMBER SIZE
5% 5%
For iFDIM test 1/20W 1/20W 051-05309 D
MF
2 0201
MF
2 201
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 5 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

U0500 U0500
D CFL-U
4+3E
CFL-U
4+3E
D
BGA BGA
A26 SYM 2 OF 20 V31 AN35 SYM 3 OF 20 AF29
20 BI
MEM_A_DQ<0> DDR0_DQ[0] DDR0_CKP[0] MEM_A_CLK_P<0> OUT 20 24 22 BI MEM_B_DQ<0> DDR1_DQ[0] DDR1_CKP[0] MEM_B_CLK_P<0> OUT 22 24

20 MEM_A_DQ<1> D26 DDR0_DQ[1] DDR0_CKN[0] V32 MEM_A_CLK_N<0> 20 24 22 MEM_B_DQ<1> AN34 DDR1_DQ[1] DDR1_CKN[0] AF28 MEM_B_CLK_N<0> 22 24
BI OUT BI OUT
20 MEM_A_DQ<2> D28 DDR0_DQ[2] DDR0_CKP[1] T31 MEM_A_CLK_P<1> 21 24 22 MEM_B_DQ<2> AR35 DDR1_DQ[2] DDR1_CKP[1] AE29 MEM_B_CLK_P<1> 23 24
BI OUT BI OUT
C28 T32 AR34 AE28

LPDDR3 NON-INTERLEAVED
MEM_A_DQ<3> MEM_A_CLK_N<1> MEM_B_DQ<3> MEM_B_CLK_N<1>

LPDDR3 NON-INTERLEAVED0
20 BI DDR0_DQ[3] DDR0_CKN[1] OUT 21 24 22 BI DDR1_DQ[3] DDR1_CKN[1] OUT 23 24

20 MEM_A_DQ<4> B26 DDR0_DQ[4] 22 MEM_B_DQ<4> AN37 DDR1_DQ[4]

BI BI
20 MEM_A_DQ<5> C26 DDR0_DQ[5] DDR0_CKE[0] U36 MEM_A_CKE<0> 20 24 22 MEM_B_DQ<5> AN36 DDR1_DQ[5] DDR1_CKE[0] T28 MEM_B_CKE<0> 22 24
BI OUT BI OUT
20 MEM_A_DQ<6> B28 DDR0_DQ[6] DDR0_CKE[1] U37 MEM_A_CKE<1> 20 24 22 MEM_B_DQ<6> AR36 DDR1_DQ[6] DDR1_CKE[1] T29 MEM_B_CKE<1> 22 24
BI OUT BI OUT
20 MEM_A_DQ<7> A28 DDR0_DQ[7] DDR0_CKE[2] U34 MEM_A_CKE<2> 21 24 22 MEM_B_DQ<7> AR37 DDR1_DQ[7] DDR1_CKE[2] V28 MEM_B_CKE<2> 23 24
BI OUT BI OUT
20 MEM_A_DQ<8> B30 DDR0_DQ[8] DDR0_CKE[3] U35 MEM_A_CKE<3> 21 24 22 MEM_B_DQ<8> AU35 DDR1_DQ[8] DDR1_CKE[3] V29 MEM_B_CKE<3> 23 24
BI OUT BI OUT
20 MEM_A_DQ<9> D30 DDR0_DQ[9] 22 MEM_B_DQ<9> AU34 DDR1_DQ[9]
BI BI
20 MEM_A_DQ<10> B33 DDR0_DQ[10] DDR0_CS*[0] AE32 MEM_A_CS_L<0> 20 21 24 22 MEM_B_DQ<10> AW35 DDR1_DQ[10] DDR1_CS*[0] AL37 MEM_B_CS_L<0> 22 23 24
BI OUT BI OUT
20 MEM_A_DQ<11> D32 DDR0_DQ[11] DDR0_CS*[1] AF32 MEM_A_CS_L<1> 20 21 24 22 MEM_B_DQ<11> AW34 DDR1_DQ[11] DDR1_CS*[1] AL35 MEM_B_CS_L<1> 22 23 24
BI OUT BI OUT
A30 AU37 OMIT_TABLE
20 BI MEM_A_DQ<12> DDR0_DQ[12] OMIT_TABLE 22 BI MEM_B_DQ<12> DDR1_DQ[12]
20 MEM_A_DQ<13> C30 DDR0_DQ[13] DDR0_ODT[0] AE31 MEM_A_ODT<0> 20 21 24 22 MEM_B_DQ<13> AU36 DDR1_DQ[13] DDR1_ODT[0] AL36 MEM_B_ODT<0> 22 23 24
BI OUT BI OUT
20 MEM_A_DQ<14> B32 DDR0_DQ[14] NC/DDR0_ODT[1] AF31 22 MEM_B_DQ<14> AW36 DDR1_DQ[14] NC/DDR1_ODT[1] AL34
BI NC BI NC
20 MEM_A_DQ<15> C32 DDR0_DQ[15] 22 MEM_B_DQ<15> AW37 DDR1_DQ[15]
BI BI
21 MEM_A_DQ<16> J22 DDR0_DQ[16] DDR0_CAA[0] AB35 MEM_A_CAA<0> 20 24 23 MEM_B_DQ<16> AJ29 DDR1_DQ[16] DDR1_CAA[0] AF35 MEM_B_CAA<0> 22 24
BI OUT BI OUT
21 MEM_A_DQ<17> H25 DDR0_DQ[17] DDR0_CAA[1] W36 MEM_A_CAA<1> 20 24 23 MEM_B_DQ<17> AJ30 DDR1_DQ[17] DDR1_CAA[1] AB29 MEM_B_CAA<1> 22 24
BI OUT BI OUT
21 MEM_A_DQ<18> G22 DDR0_DQ[18] DDR0_CAA[2] AA37 MEM_A_CAA<2> 20 24 23 MEM_B_DQ<18> AM32 DDR1_DQ[18] DDR1_CAA[2] AE37 MEM_B_CAA<2> 22 24
BI OUT BI OUT
21 MEM_A_DQ<19> H22 DDR0_DQ[19] DDR0_CAA[3] AB34 MEM_A_CAA<3> 20 24 23 MEM_B_DQ<19> AM31 DDR1_DQ[19] DDR1_CAA[3] AE36 MEM_B_CAA<3> 22 24
BI OUT BI OUT
21 MEM_A_DQ<20> F25 DDR0_DQ[20] DDR0_CAA[4] AA36 MEM_A_CAA<4> 20 24 23 MEM_B_DQ<20> AM30 DDR1_DQ[20] DDR1_CAA[4] AC29 MEM_B_CAA<4> 22 24
BI OUT BI OUT
21 MEM_A_DQ<21> J25 DDR0_DQ[21] DDR0_CAA[5] V34 MEM_A_CAA<5> 20 24 23 MEM_B_DQ<21> AM29 DDR1_DQ[21] DDR1_CAA[5] W29 MEM_B_CAA<5> 22 24
BI OUT BI OUT
21 MEM_A_DQ<22> G25 DDR0_DQ[22] DDR0_CAA[6] AA34 MEM_A_CAA<6> 20 24 23 MEM_B_DQ<22> AJ31 DDR1_DQ[22] DDR1_CAA[6] AB28 MEM_B_CAA<6> 22 24
BI OUT BI OUT
21 MEM_A_DQ<23> F22 DDR0_DQ[23] DDR0_CAA[7] W34 MEM_A_CAA<7> 20 24 23 MEM_B_DQ<23> AJ32 DDR1_DQ[23] DDR1_CAA[7] AC28 MEM_B_CAA<7> 22 24
BI OUT BI OUT

C 21 BI
MEM_A_DQ<24> D22
C22
DDR0_DQ[24] DDR0_CAA[8] V35
W35
MEM_A_CAA<8> OUT 20 24 23 BI MEM_B_DQ<24> AR31
AR32
DDR1_DQ[24] DDR1_CAA[8] W28
Y28
MEM_B_CAA<8> OUT 22 24 C
21 BI
MEM_A_DQ<25> DDR0_DQ[25] DDR0_CAA[9] MEM_A_CAA<9> OUT 20 24 23 BI MEM_B_DQ<25> DDR1_DQ[25] DDR1_CAA[9] MEM_B_CAA<9> OUT 22 24

21 MEM_A_DQ<26> C24 DDR0_DQ[26] 23 MEM_B_DQ<26> AV30 DDR1_DQ[26]

BI BI
21 MEM_A_DQ<27> D24 DDR0_DQ[27] DDR0_CAB[0] AC32 MEM_A_CAB<0> 21 24 23 MEM_B_DQ<27> AV29 DDR1_DQ[27] DDR1_CAB[0] AK35 MEM_B_CAB<0> 23 24
BI OUT BI OUT
21 MEM_A_DQ<28> A22 DDR0_DQ[28] DDR0_CAB[1] AB32 MEM_A_CAB<1> 21 24 23 MEM_B_DQ<28> AR30 DDR1_DQ[28] DDR1_CAB[1] AK34 MEM_B_CAB<1> 23 24
BI OUT BI OUT
21 MEM_A_DQ<29> B22 DDR0_DQ[29] DDR0_CAB[2] AC31 MEM_A_CAB<2> 21 24 23 MEM_B_DQ<29> AR29 DDR1_DQ[29] DDR1_CAB[2] AJ35 MEM_B_CAB<2> 23 24
BI OUT BI OUT
21 MEM_A_DQ<30> A24 DDR0_DQ[30] DDR0_CAB[3] Y32 MEM_A_CAB<3> 21 24 23 MEM_B_DQ<30> AV32 DDR1_DQ[30] DDR1_CAB[3] AJ34 MEM_B_CAB<3> 23 24
BI OUT BI OUT
21 MEM_A_DQ<31> B24 DDR0_DQ[31] DDR0_CAB[4] W32 MEM_A_CAB<4> 21 24 23 MEM_B_DQ<31> AV31 DDR1_DQ[31] DDR1_CAB[4] AJ37 MEM_B_CAB<4> 23 24
BI OUT BI OUT
20 MEM_A_DQ<32> H37 DDR0_DQ[32] DDR0_CAB[5] AC34 MEM_A_CAB<5> 21 24 22 MEM_B_DQ<32> BA35 DDR1_DQ[32] DDR1_CAB[5] AF34 MEM_B_CAB<5> 23 24
BI OUT BI OUT
20 MEM_A_DQ<33> H34 DDR0_DQ[33] DDR0_CAB[6] AB31 MEM_A_CAB<6> 21 24 22 MEM_B_DQ<33> BA34 DDR1_DQ[33] DDR1_CAB[6] AJ36 MEM_B_CAB<6> 23 24
BI OUT BI OUT
20 MEM_A_DQ<34> K34 DDR0_DQ[34] DDR0_CAB[7] Y31 MEM_A_CAB<7> 21 24 22 MEM_B_DQ<34> BC35 DDR1_DQ[34] DDR1_CAB[7] AG34 MEM_B_CAB<7> 23 24
BI OUT BI OUT
20 MEM_A_DQ<35> K35 DDR0_DQ[35] DDR0_CAB[8] AC36 MEM_A_CAB<8> 21 24 22 MEM_B_DQ<35> BC34 DDR1_DQ[35] DDR1_CAB[8] AG35 MEM_B_CAB<8> 23 24
BI OUT BI OUT
20 MEM_A_DQ<36> H36 DDR0_DQ[36] DDR0_CAB[9] AC37 MEM_A_CAB<9> 21 24 22 MEM_B_DQ<36> BA37 DDR1_DQ[36] DDR1_CAB[9] AG36 MEM_B_CAB<9> 23 24
BI OUT BI OUT
20 MEM_A_DQ<37> H35 DDR0_DQ[37] 22 MEM_B_DQ<37> BA36 DDR1_DQ[37]
BI
DDR0_DQSN[0] C27 MEM_A_DQS_N<0> 20
BI
DDR1_DQSN[0] AP35 MEM_B_DQS_N<0> 22
20 MEM_A_DQ<38> K36 DDR0_DQ[38]
BI
22 MEM_B_DQ<38> BC36 DDR1_DQ[38]
BI
BI
DDR0_DQSN[1] D31 MEM_A_DQS_N<1> 20
BI
DDR1_DQSN[1] AV34 MEM_B_DQS_N<1> 22
20 MEM_A_DQ<39> K37 DDR0_DQ[39]
BI
22 MEM_B_DQ<39> BC37 DDR1_DQ[39]
BI
BI
DDR0_DQSN[2] H24 MEM_A_DQS_N<2> 21
BI
DDR1_DQSN[2] AL31 MEM_B_DQS_N<2> 23
20 MEM_A_DQ<40> N36 DDR0_DQ[40]
BI
22 MEM_B_DQ<40> BE35 DDR1_DQ[40]
BI
BI
DDR0_DQSN[3] C23 MEM_A_DQS_N<3> 21
BI
DDR1_DQSN[3] AU31 MEM_B_DQS_N<3> 23
20 MEM_A_DQ<41> N34 DDR0_DQ[41]
BI
22 MEM_B_DQ<41> BE34 DDR1_DQ[41]
BI
BI
DDR0_DQSN[4] J35 MEM_A_DQS_N<4> 20
BI
DDR1_DQSN[4] BB35 MEM_B_DQS_N<4> 22
20 MEM_A_DQ<42> R37 DDR0_DQ[42]
BI
22 MEM_B_DQ<42> BG35 DDR1_DQ[42]
BI
BI
DDR0_DQSN[5] P34 MEM_A_DQS_N<5> 20
BI
DDR1_DQSN[5] BF34 MEM_B_DQS_N<5> 22
20 MEM_A_DQ<43> R34 DDR0_DQ[43]
BI
22 MEM_B_DQ<43> BG34 DDR1_DQ[43]
BI
BI
DDR0_DQSN[6] G30 MEM_A_DQS_N<6> 21
BI
DDR1_DQSN[6] BC31 MEM_B_DQS_N<6> 23
20 MEM_A_DQ<44> N37 DDR0_DQ[44]
BI
22 MEM_B_DQ<44> BE37 DDR1_DQ[44]
BI
BI
DDR0_DQSN[7] L30 MEM_A_DQS_N<7> 21
BI
DDR1_DQSN[7] BH31 MEM_B_DQS_N<7> 23
20 MEM_A_DQ<45> N35 DDR0_DQ[45]
BI
22 MEM_B_DQ<45> BE36 DDR1_DQ[45]
BI
BI BI
20 MEM_A_DQ<46> R36 DDR0_DQ[46] DDR0_DQSP[0] D27 MEM_A_DQS_P<0> 20 22 MEM_B_DQ<46> BG36 DDR1_DQ[46] DDR1_DQSP[0] AP34 MEM_B_DQS_P<0> 22
BI BI BI BI
20 MEM_A_DQ<47> R35 DDR0_DQ[47] DDR0_DQSP[1] C31 MEM_A_DQS_P<1> 20 22 MEM_B_DQ<47> BG37 DDR1_DQ[47] DDR1_DQSP[1] AV35 MEM_B_DQS_P<1> 22
BI BI BI BI
21 MEM_A_DQ<48> G31 DDR0_DQ[48] DDR0_DQSP[2] G24 MEM_A_DQS_P<2> 21 23 MEM_B_DQ<48> BA32 DDR1_DQ[48] DDR1_DQSP[2] AL30 MEM_B_DQS_P<2> 23
BI BI BI BI
21 MEM_A_DQ<49> G32 DDR0_DQ[49] DDR0_DQSP[3] D23 MEM_A_DQS_P<3> 21 23 MEM_B_DQ<49> BA31 DDR1_DQ[49] DDR1_DQSP[3] AU30 MEM_B_DQS_P<3> 23
BI BI BI BI
MEM_A_DQ<50> H29 J34 MEM_A_DQS_P<4> MEM_B_DQ<50> BD31 BB34 MEM_B_DQS_P<4>
B 21

21
BI
MEM_A_DQ<51> H28
DDR0_DQ[50]
DDR0_DQ[51]
DDR0_DQSP[4]
DDR0_DQSP[5] P35 MEM_A_DQS_P<5>
BI 20

20
23

23
BI
MEM_B_DQ<51> BD32
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQSP[4]
DDR1_DQSP[5] BF35 MEM_B_DQS_P<5>
BI 22

22
B
BI BI BI BI
21 MEM_A_DQ<52> G28 DDR0_DQ[52] DDR0_DQSP[6] H30 MEM_A_DQS_P<6> 21 23 MEM_B_DQ<52> BA30 DDR1_DQ[52] DDR1_DQSP[6] BC30 MEM_B_DQS_P<6> 23
BI BI BI BI
21 MEM_A_DQ<53> G29 DDR0_DQ[53] DDR0_DQSP[7] N30 MEM_A_DQS_P<7> 21 23 MEM_B_DQ<53> BA29 DDR1_DQ[53] DDR1_DQSP[7] BH30 MEM_B_DQS_P<7> 23
BI BI BI BI
21 MEM_A_DQ<54> H31 DDR0_DQ[54] 0 23 MEM_B_DQ<54> BD29 DDR1_DQ[54] PP1V2_S3_CPUDDR 7 9 50 83 88
BI
NC/DDR0_ALERT_L W37 CPU_DDDR0_ALERT_L 1 2 BI
NC/DDR1_ALERT_L Y29 CPU_DDDR1_ALERT_L 1 2
21 MEM_A_DQ<55> H32 DDR0_DQ[55] 23 MEM_B_DQ<55> BD30 DDR1_DQ[55]
BI W31 BI AE34 1
21 BI
MEM_A_DQ<56> L31 DDR0_DQ[56]
NC/DDR0_PAR NC R0703 5%
1/20W 23 BI
MEM_B_DQ<56> BG31 DDR1_DQ[56]
NC/DDR1_PAR NC R0704 5%
1/20W R0705
L32 AC35
MF BG32 MF 470
21 BI
MEM_A_DQ<57> DDR0_DQ[57] NC/DDR0_MA[3] NC
0201 23 BI
MEM_B_DQ<57> DDR1_DQ[57] NC/DDR1_MA[3] AG37 NC 0 0201 5%
N29 AA35 BK32 1/20W
21 BI
MEM_A_DQ<58> DDR0_DQ[58] NC/DDR0_MA[4] NC 23 BI
MEM_B_DQ<58> DDR1_DQ[58] NC/DDR1_MA[4] AE35 NC MF
21 MEM_A_DQ<59> N28 DDR0_DQ[59] 23 MEM_B_DQ<59> BK31 DDR1_DQ[59] 2 201
BI
DDR_VREF_CA F36 CPU_DIMM_VREFCA 19
BI
DRAM_RESET* BU31 CPU_DRAM_RESET_L
21 MEM_A_DQ<60> L28 DDR0_DQ[60]
OUT
23 MEM_B_DQ<60> BG29 DDR1_DQ[60]
BI BI
21 MEM_A_DQ<61> L29 DDR0_DQ[61] DDR0_VREF_DQ[0] D35 CPU_DIMMA_VREFDQ 19 23 MEM_B_DQ<61> BG30 DDR1_DQ[61] DDR_COMP[0] BN28 CPU_DDR_RCOMP<0>
BI OUT BI
21 MEM_A_DQ<62> N31 DDR0_DQ[62] DDR0_VREF_DQ[1] D37 23 MEM_B_DQ<62> BK30 DDR1_DQ[62] DDR_COMP[1] BN27 CPU_DDR_RCOMP<1>
BI NC BI
21 MEM_A_DQ<63> N32 DDR0_DQ[63] DDR1_VREF_DQ E36 CPU_DIMMB_VREFDQ 19 23 MEM_B_DQ<63> BK29 DDR1_DQ[63] DDR_COMP[2] BN29 CPU_DDR_RCOMP<2>
BI OUT BI

DDR_VTT_CNTL C35 PM_MEMVTT_EN 73

OUT

1 1 1
R0700 R0701 R0702
162 80.6 200
1% 1% 1%
1/20W 1/20W 1/20W
MF MF MF
2 201 2 201 2 201

PLACE_NEAR=U0500.BN29:6MM
PLACE_NEAR=U0500.BN27:6MM
PLACE_NEAR=U0500.BN28:6MM

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

CPU LPDDR3 INTERFACE

DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
7 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 6 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

U0500 PPVCCGT_S0_CPU
CFL-U 87 83 67 50 10

4+3E
BGA
PP1V2_S3_CPUDDR AD36 VDDQ
SYM 14 OF 20
VCCIO AK24 PPVCCIO_S0_CPU U0500
88 83 50 9 6
AH32 POWER 3 AK26
4 9 73 83 87
CFL-U
VDDQ VCCIO 4+3E
AH36 OMIT_TABLE AL24 BGA
VDDQ VCCIO
AM36 AL25 A11 SYM 13 OF 20 D20
VDDQ VCCIO VCCGT VCCGT
AN32 AL26 A12 POWER 2 D4
VDDQ VCCIO VCCGT VCCGT
AW32 AL27 A14 OMIT_TABLE D7
VDDQ VCCIO VCCGT VCCGT
AY36 VDDQ VCCIO AM25 A15 VCCGT VCCGT E4

D BE32 VDDQ VCCIO AM27 A17 VCCGT VCCGT F11 D

BH36 VDDQ VCCIO BH24 A18 VCCGT VCCGT F14
R32 VDDQ VCCIO BH25 A20 VCCGT VCCGT F17
Y36 VDDQ VCCIO BH26 A5 VCCGT VCCGT F20
VCCIO BH27 A6 VCCGT VCCGT F5
83 70 69 65 42 18 17 9 7 5 PP1V_S3 BP11 VCCST
VCCIO BJ24 A8 VCCGT VCCGT F6
BP2 VCCST
VCCIO BJ26 AA9 VCCGT VCCGT F7
83 71 16 9 5 PP1V_S0SW BG1 VCCSTG VCCIO BP16 AB10 VCCGT VCCGT F8
BG2 BP18 87 83 66 50 9 PPVCC_S0_CPU AB2 G11
VCCSTG VCCIO VCCGT VCCGT
BG3 VCCSTG AB8 VCCGT VCCGT G12
VCCSA BG10 PPVCCSA_S0_CPU 9 52 66 83 87
U0500 AB9 VCCGT VCCGT G14
PP1V2_S0SW BL27 VCCPLL_OC VCCSA BG8
83 74 9
BM26 BH9
CFL-U AC8 VCCGT VCCGT G15
VCCPLL_OC VCCSA 4+3E AD9 G17
BJ10 BGA VCCGT VCCGT
BR11 VCCSA AE10 G18
83 70 69 65 42 18 17 9 7 5 PP1V_S3 VCCPLL BJ8 AN10 SYM 12 OF 20 AW27 VCCGT VCCGT
BT11 VCCSA VCCCORE POWER 1 VCCCORE AE8 G20
VCCPLL BJ9 AN24 AW5 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AE9 H11
BK25 AN26 OMIT_TABLE AW6 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AF10 H12
BK27 AN27 AW7 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AF2 H14
BK8 AN9 AW8 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AF8 H15
BL10 AP2 AW9 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AG8 H17
BL24 AP24 AY24 VCCGT VCCGT
VCCSA VCCCORE VCCCORE AG9 H18
BL26 AP26 AY26 VCCGT VCCGT
VCCSA PLACE_NEAR=U0500::13MM PLACE_NEAR=U0500::13MM VCCCORE VCCCORE AH9 H20
BL8 1 1 AP9 BA25 VCCGT VCCGT
NO_XNET_CONNECTION=1
VCCSA R0804 R0801 VCCCORE VCCCORE AJ10 VCCGT VCCGT H5
R0850 0
PLACE_NEAR=R7819.2:5MM VCCSA BL9
5%
100
5%
100 AR10 VCCCORE VCCCORE BA27
AJ8 VCCGT VCCGT H6
1 2 PVPCORES5_FB_P 70 VCCSA BM24 1/20W 1/20W
AR25 VCCCORE VCCCORE BA5
0201 5% 1/20W MF
OUT
MF MF
AK2 VCCGT VCCGT H7
VCCSA BN25 AR27 VCCCORE VCCCORE BA7
NO_XNET_CONNECTION=1 2 201 2 201 AK9 VCCGT VCCGT H8
R0852 0
PLACE_NEAR=R7821.2:5MM
VCCIO_SENSE BP28 CPU_VCCIOSENSE_P
AR5 VCCCORE VCCCORE BA8
AL10 VCCGT VCCGT J11
C 2 1 PVPCORES5_FB_N
5% 1/20W MF 0201
OUT 70
VSSIO_SENSE BP29 CPU_VCCIOSENSE_N
OUT

OUT
73

73
AR6
AR7
VCCCORE VCCCORE BB2
BB26
AL8 VCCGT VCCGT J14 C
VCCCORE VCCCORE AL9 J17
BE7 PLACE_NEAR=U0500::13MM AR8 BC10 VCCGT VCCGT
PVCC_FB_N VSSSA_SENSE CPU_VCCSASENSE_N OUT 65
1 VCCCORE VCCCORE AM8 J20
54 PVCC_FB_P VCCSA_SENSE BG7 CPU_VCCSASENSE_P OUT 65
R0802 AT24 VCCCORE VCCCORE BC26
B11
VCCGT VCCGT
J7
100 AT26 BC27 VCCGT VCCGT
PLACE_NEAR=U0500::13MM 5% VCCCORE VCCCORE B14 J8
1 1/20W AT9 BC5 VCCGT VCCGT
NO_XNET_CONNECTION=1
PLACE_NEAR=U0500.BU15:30MM 2
NO_XNET_CONNECTION=1
2 PLACE_NEAR=XW0850::5mm R0803 MF
2 201 AU24
VCCCORE VCCCORE
BC6
B17 VCCGT VCCGT K11
100 VCCCORE VCCCORE B20 K2
XW0850 SM XW0852
SM
5%
1/20W
AU25 VCCCORE VCCCORE BC7
B3
VCCGT VCCGT
L10
MF AU26 BC9 VCCGT VCCGT
1 1
U0500 2 201 VCCCORE VCCCORE B4 VCCGT VCCGT L7
CFL-U AU27 VCCCORE VCCCORE BD10
B6
4+3E VCCGT VCCGT L8
AU5 VCCCORE VCCCORE BD25
BGA B8 VCCGT VCCGT M9
SYM 15 OF 20
AU6 VCCCORE VCCCORE BD27
86 83 70 54 11 PPVPCORE_S5 BU15 VCCPRIM_CORE VCCPRIM_1P05 BP20 PP1V_PRIM 7 11 16 54 70 73 83 86
C11 VCCGT VCCGT N10
POWER 4 AU7 VCCCORE VCCCORE BD5
BU22 VCCPRIM_CORE VCCPRIM_1P05 BP22 C12 VCCGT VCCGT N7
OMIT_TABLE 2 PLACE_NEAR=U0500.BP20:30MM AU8 VCCCORE VCCCORE BD8
BV15 VCCPRIM_CORE VCCPRIM_1P05 BR20 C14 VCCGT VCCGT N8
AU9 BE24
BV16 VCCPRIM_CORE VCCPRIM_1P05 BT18
SM
XW0853 PLACE_NEAR=R7820.2:5MM AV10
VCCCORE VCCCORE
BE25
C15 VCCGT VCCGT N9
BV18 BT19 VCCCORE VCCCORE C17 P2
BV19
VCCPRIM_CORE VCCPRIM_1P05
BT22 1 R0853 AV2 VCCCORE VCCCORE BE26
C18
VCCGT VCCGT
P8
VCCPRIM_CORE VCCPRIM_1P05
P1VPRIM_FB_R 1
0 2 P1VPRIM_FB AV27 BE27 VCCGT VCCGT
BV20 BU18 54
OUT 70 VCCCORE VCCCORE C2 R9
VCCPRIM_CORE VCCPRIM_1P05 AV5 BE9 VCCGT VCCGT
BV22 BU19 5% VCCCORE VCCCORE C20 T10
VCCPRIM_CORE VCCPRIM_1P05 1/20W VCCGT VCCGT
MF AV7 VCCCORE VCCCORE BF2
BW20 VCCPRIM_CORE VCCPRIM_1P05 BW16 0201 C3 VCCGT VCCGT T8
AW10 VCCCORE VCCCORE BF24
BW22 VCCPRIM_CORE VCCPRIM_1P05 BW18 C6 VCCGT VCCGT T9
AW24 VCCCORE VCCCORE BF26
CA12 VCCPRIM_CORE VCCPRIM_1P05 BW19 C7 VCCGT VCCGT U10
AW25 VCCCORE VCCCORE BF9
CA16 VCCPRIM_CORE VCCPRIM_1P05 BY16 C8 VCCGT VCCGT U8
AW26 VCCCORE VCCCORE BG27
CA18 VCCPRIM_CORE VCCPRIM_1P05 BY20 D11 VCCGT VCCGT V2
CA19 VCCPRIM_CORE VCCPRIM_1P05 CA14 32 18 17 16 15 14 13 12 11 7 PP1V8_S5 V24 VCC_OPC_1P8 VCCOPC K12 PLACE_NEAR=U0500::13MM D12 VCCGT VCCGT V9
83 74 73 72 70 69 65 53 47 42
CA20 W25 K14 D14 W8
VCCPRIM_CORE CC15 VCC_OPC_1P8 VCCOPC R0811 1 VCCGT VCCGT
B CB12 VCCPRIM_CORE
VCCPRIM_1P8
VCCPRIM_1P8 CC18 PP1V8_S5 7 11 12 13 14 15 16 17 18 32 42
47 53 65 69 70 72 73 74 83
Y24 VCC_OPC_1P8 VCCOPC K15 100
5%
D15 VCCGT VCCGT W9 B
CB14 VCCPRIM_CORE Y25 VCC_OPC_1P8 VCCOPC K17 1/20W
D17 VCCGT VCCGT Y10
VCCPRIM_1P8 CC19 MF
CB15 VCCPRIM_CORE VCCOPC K18 201 2
D18 VCCGT VCCGT Y8
VCCPRIM_1P8 CD15 86 83 69 9 PPVCCEDRAM_S0_CPU AA24 VCCEOPIO
VCCOPC K20
86 83 73 70 54 16 11 7 PP1V_PRIM BV12 VCCPRIM_MPHY_1P05 VCCPRIM_1P8 CD16 AA26 VCCEOPIO 65 CPU_VCCGTSENSE_P E3 VCCGT_SENSE
VCCOPC L25 OUT
BV14 VCCPRIM_MPHY_1P05 VCCPRIM_1P8 CD18 AB25 VCCEOPIO 65 CPU_VCCGTSENSE_N D2 VSSGT_SENSE
VCCOPC M24 OUT
BW12 VCCPRIM_MPHY_1P05 VCCPRIM_1P8 CD19 PLACE_NEAR=U0500::13MM AC24 VCCEOPIO PLACE_NEAR=U0500::13MM
VCCOPC M26
BW14 CP17 1 AC25
BY12
VCCPRIM_MPHY_1P05 VCCPRIM_1P8
CP23
R0823 AC26
VCCEOPIO
VCCOPC P24
1
PLACE_NEAR=U0500::13MM R0812 1
VCCPRIM_MPHY_1P05 VCCPRIM_1P8 100 VCCEOPIO R24 R0825 100
BY14 5% AD24 VCCOPC 5%
VCCPRIM_MPHY_1P05 BP23 PP3V3_S5 1/20W VCCEOPIO P26 100 1/20W
VCCPRIM_3P3 4 5 7 11 12 13 14 18 42 43 47 MF AD26 VCCOPC 5% MF
BV2 BW23 69 71 73 74 83 89 201 2 VCCEOPIO R25 1/20W 201 2
11 PP1V05_PRIMSW_PCH_VCCAMPHYPLL_F VCCAMPHYPLL_1P05 VCCPRIM_3P3 VCCOPC MF
VCCPRIM_3P3 CB16 69 CPU_VCCEOPIOSENSE_P V25 VCCEOPIO_SENSE VCCOPC R26 2 201
BR14 VCCAPLL_1P05
OUT
VCCPRIM_3P3 CB22 69 CPU_VCCEOPIOSENSE_N T25 VSSEOPIO_SENSE
11 PP1V05_PRIM_PCH_VCCAPLL_AUD_F BR15 VCCAPLL_1P05
OUT
VCC_SENSE AN6 CPU_VCCSENSE_P 65
VCCPRIM_3P3 CB23 PLACE_NEAR=U0500::13MM
OUT
BT12 VCCAPLL_1P05 VSS_SENSE AN5 CPU_VCCSENSE_N 65
CC22 OUT
BU14 VCCAPLL_1P05
VCCPRIM_3P3
CC23
R0824 1 AA3 PLACE_NEAR=U0500::13MM PP1V_S3 5 7 9 17 18 42 65 69 70 83
VCCPRIM_3P3 100 VIDALERT* CPU_VIDALERT_R_L 1
11 PP1V05_S5_PCH_VCCDSW BT24 VCCDSW_1P05 VCCPRIM_3P3 CD22 5%
1/20W VIDSCK AA1 CPU_VIDSCLK_R R0826 PLACE_NEAR=U0500::13MM
1 1
PLACE_NEAR=U0500::13MM
CD23 MF AA2 CPU_VIDSOUT_R 100 R0827 R0828
BR24 VCCPRIM_3P3 201 2 VIDSOUT 5%
47 43 42 18 14 13 12 11 7 5 4 PP3V3_S5 VCCDSW_3P3 CP29 1/20W 56 100
89 83 74 73 71 69
BT23 VCCPRIM_3P3 MF 1% 1%
VCCDSW_3P3 2 201 1/20W 1/20W
BR23 MF MF
BT20 VCCRTC PP3V_G3H_RTC 11 13 71 83 201 2 2 201
11 PP1V8_PRIM_PCH_VCCHDA_F VCCHDA
BP24 PPDCPRTC_PCH R0829 1
220 2
PLACE_NEAR=U0500.AA3:12.7MM
201 1% MF 1/20W CPU_VIDALERT_L
BV23 DCPRTC 11 IN 65
VCCSPI
R0830 1
0 2
PLACE_NEAR=U0500.AA1:12.7MM
0201 5% MF 1/20W CPU_VIDSCLK 65
1 C0824 PP1V24_S5_PCH_VCCDPHY BY23 VCCDPHY_1P24 GPP_B0/CORE_VID0 CB36 NC_PCH_CORE_VID0
0
OUT

20%
4.7UF BY24 VCCDPHY_1P24 GPP_B1/CORE_VID1 CB35 NC_PCH_CORE_VID1 R0831 1 2
PLACE_NEAR=U0500.AA2:12.7MM
0201 5% MF 1/20W CPU_VIDSOUT BI 65

2 6.3V
CA23 VCCDPHY_1P24
A X5R-CERM1
402 CA24 VCCDPHY_1P24 SYNC_MASTER= SYNC_DATE=
A
BYPASS=U0500.CP25::5MM PAGE TITLE
CP25 VCCDPHY_EC_1P24
XW0801 SHORT-L8-SM PLACE_NEAR=U0500.CC12:5MM CPU & PCH POWER
1 2 PP1V05_PRIM_PCH_VCCDUSB_XW CC12 VCCDUSB_1P05 DRAWING NUMBER SIZE
SHORT-L8-SM PLACE_NEAR=U0500.BR12:5MM
XW0802 1 2 PP1V05_PRIM_PCH_VCCA19P2_XW BR12 051-05309 D
SHORT-L8-SM PLACE_NEAR=U0500.BP14:5MM
VCCA_19P2_1P05 Apple Inc. REVISION
XW0803 1 2 PP1V05_PRIM_PCH_VCCABCLK_XW BP14 VCCA_BCLK_1P05 5.1.0
SHORT-L8-SM PLACE_NEAR=U0500.BU12:5MM
XW0804 1 2 PP1V05_PRIM_PCH_VCCASRC_XW BU12 VCCA_SRC_1P05
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

CP5 PROPRIETARY PROPERTY OF APPLE INC.
11 PP1V05_PRIM_PCH_VCCAXTAL_F VCCA_XTAL_1P05 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
8 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 7 OF 98

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U0500 U0500
U0500 CFL-U
CFL-U 4+3E
CFL-U 4+3E BGA
D
4+3E
BGA
BGA
SYM 17 OF 20
CF19 VSS
SYM 18 OF 20
VSS G27 D
A3 VSS SYM 16 OF 20 VSS AP36 BE10 VSS VSS BV3 GND 3
GND2
CF23 VSS VSS G33
A4 VSS GND1 VSS AR4 BE28 VSS VSS BV4 OMIT_TABLE
OMIT_TABLE CF28 VSS VSS G35
A32 VSS OMIT_TABLE VSS AR28 BE29 VSS VSS BV11
CG7 VSS VSS G36
A36 VSS VSS AT4 BE30 VSS VSS BV31
CG33 VSS VSS H9
AB3 VSS VSS AT33 BE31 VSS VSS BV33
CH31 VSS VSS H21
AB4 VSS VSS AT35 BF3 VSS VSS BW7
CJ2 VSS VSS H27
AB7 VSS VSS AT36 BF4 VSS VSS BW11
CJ3 VSS VSS J5
AB27 VSS VSS AU4 BF33 VSS VSS BW15
CJ4 VSS VSS J6
AB30 VSS VSS AU10 BF36 VSS VSS BW24
CJ11 VSS VSS J12
AB33 VSS VSS AU28 BG4 VSS VSS BY5
CJ14 VSS VSS J15
AB36 VSS VSS AU29 BG25 VSS VSS BY11
CJ19 VSS VSS J18
AC5 VSS VSS AU32 BG28 VSS VSS BY15
CJ23 VSS VSS J21
AC10 VSS VSS AV3 BH28 VSS VSS BY18
CJ28 VSS VSS J24
AC27 VSS VSS AV4 BH29 VSS VSS BY19
CJ33 VSS VSS J33
AC30 VSS VSS AV6 BH32 VSS VSS BY22
CJ35 VSS VSS J36
AD33 VSS VSS AV8 BH33 VSS VSS BY25
CJ36 VSS VSS K3
AD35 VSS VSS AV25 BH35 VSS VSS BY28
CK1 VSS VSS K4
AE7 VSS VSS AV28 BJ7 VSS VSS BY33
CK4 VSS VSS K9
AE24 VSS VSS AV33 BK2 VSS VSS BY35
CK7 VSS VSS K21
AE25 VSS VSS AV36 BK3 VSS VSS BY36
CK37 VSS VSS K22
AE26 VSS VSS AW1 BK4 VSS VSS C1
CL2 VSS VSS K24
AE27 VSS VSS AW3 BK7 VSS VSS C4
CM1 VSS VSS K25
AE30 VSS VSS AW4 BK10 VSS VSS C9
CM4 VSS VSS K27
AF3 VSS VSS AW28 BK28 VSS VSS C21
CM5 VSS VSS K28
AF4 VSS VSS AW29 BK33 VSS VSS C25
CM9 VSS VSS K29
AF7 VSS VSS AW30 BL7 VSS VSS C29
C AF25 VSS VSS AW31 BL25 VSS VSS C33
CM13
CM17
VSS VSS K30
K31
C
AF27 AY4 BL28 C34 VSS VSS
VSS VSS VSS VSS CM21 K32
AF30 AY33 BL29 C36 VSS VSS
VSS VSS VSS VSS CM25 L6
AF33 AY35 BL30 C37 VSS VSS
VSS VSS VSS VSS CM29 L27
AF36 B2 BL31 CA11 VSS VSS
VSS VSS VSS VSS CM31 L33
AG5 B5 BL32 CA15 VSS VSS
VSS VSS VSS VSS CM33 L35
AG10 B7 BM9 CA22 VSS VSS
VSS VSS VSS VSS CM37 L36
AG24 B9 BM33 CA25 VSS VSS
VSS VSS VSS VSS CN1 N6
AG26 B12 BM35 CB2 VSS VSS
VSS VSS VSS VSS CN2 N25
AH24 B15 BM36 CB3 VSS VSS
VSS VSS VSS VSS CN5 N27
AH25 B18 BN7 CB4 VSS VSS
VSS VSS VSS VSS CN9 P3
AH27 B21 BN30 CB7 VSS VSS
VSS VSS VSS VSS CN13 P4
AH28 B23 BP3 CB11 VSS VSS
VSS VSS VSS VSS CN17 P7
AH29 B25 BP4 CB18 VSS VSS
VSS VSS VSS VSS CN21 P10
AH30 B27 BP7 CB19 VSS VSS
VSS VSS VSS VSS CN25 P33
AH31 B29 BP12 CB20 VSS VSS
VSS VSS VSS VSS CN29 P36
AH33 B31 BP15 CB24 VSS VSS
VSS VSS VSS VSS CN37 R27
AH35 B34 BP19 CB25 VSS VSS
VSS VSS VSS VSS CP1 R28
AJ7 B36 BP25 CB33 VSS VSS
VSS VSS VSS VSS CP2 R29
AJ25 B37 BP32 CC7 VSS VSS
VSS VSS VSS VSS CP9 R30
AJ28 BA3 BP33 CC11 VSS VSS
VSS VSS VSS VSS CP11 R31
AK3 BA4 CC14 VSS VSS
VSS VSS VSS CP13 T7
AK4 BA6 BR16 CC16 VSS VSS
VSS VSS VSS VSS CP15 T27
AK33 BA10 BR19 CC20 VSS VSS
VSS VSS VSS VSS CP19 T30
AK36 BA28 BR22 CC24 VSS VSS
VSS VSS VSS VSS CP21 T33
AL7 BB3 BR25 CC25 VSS VSS
VSS VSS VSS VSS CP27 T35
B AL28 VSS VSS BB4 BT5 VSS VSS CC28
CP35
VSS
VSS
VSS
VSS T36 B
AL29 VSS VSS BB33 BT14 VSS VSS CC31
CP37 VSS VSS U7
AL32 VSS VSS BB36 BT15 VSS VSS CD11
CR2 VSS VSS U24
AM5 VSS VSS BC4 BT16 VSS VSS CD12
CR6 VSS VSS U26
AM10 VSS VSS BC8 BT25 VSS VSS CD14
CR34 VSS VSS V3
AM28 VSS VSS BC25 BT28 VSS VSS CD20
CR36 VSS VSS V4
AM33 VSS VSS BC29 BT33 VSS VSS CD24
D1 VSS VSS V26
AM35 VSS VSS BC32 BT35 VSS VSS CD25
D5 VSS VSS V27
AN7 VSS VSS BD4 BT36 VSS VSS CE7
D6 VSS VSS V30
AN8 VSS VSS BD6 BU7 VSS VSS CE33
D8 VSS VSS V33
AN25 VSS VSS BD7 BU11 VSS VSS CE35
D9 VSS VSS V36
AN28 VSS VSS BD28 BU16 VSS VSS CE36
D21 VSS VSS W7
AN29 VSS VSS BD33 BU20 VSS VSS CF2
D25 VSS VSS W10
AN30 VSS VSS BD35 BU23 VSS VSS CF3
E9 VSS VSS W27
AN31 VSS VSS BD36 BU24 VSS VSS CF4
E23 VSS VSS W30
AP3 VSS VSS BE3 BU25 VSS VSS CF11
E27 VSS VSS Y7
AP4 VSS VSS BE4 VSS CF14
E29 VSS VSS Y26
AP33 VSS VSS BE8
E31 VSS VSS Y27
E33 VSS VSS Y30
E35 VSS VSS Y33
F2 VSS VSS Y35
F3 VSS
F4 VSS
F12 VSS
F15 VSS
F18
A F21
VSS
SYNC_MASTER= SYNC_DATE=
A
VSS PAGE TITLE
F24 VSS
F33 VSS
CPU & PCH Grounds
G3 DRAWING NUMBER SIZE
VSS
G4 051-05309 D
G9
VSS Apple Inc. REVISION
VSS
G21 5.1.0
VSS
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
9 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 8 OF 98

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88 83 50 7 6 PP1V2_S3_CPUDDR
1 C1070 1 C1071
20UF 1UF
20% 20%
2 2.5V
X6S-CERM 2 6.3V
X6S-CERM
0402-1 0201

Primary Backside
D D
1 C1050 1 C1051 1 C1064 1 C1065 1 C1066 1 C1060 1 C1061 1 C1062 1 C1063
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

PPVCC_S0_CPU
1 C1052 1 C1053 1 C1054 1 C1055
83 66 50 7
87 1UF 1UF 1UF 1UF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 20% 20% 20% 20%
1 1 1 1 1 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
C10G0 C10G1 C10H1 C10G3 C10G4 0201 0201 0201 0201
220UF 220UF 220UF 220UF 220UF
20% 20% 20% 20% 20%
2 2V 2 2V 2 2V 2 2V 2 2V
ELEC ELEC ELEC ELEC ELEC
SM SM SM SM SM

87 83 73 7 4 PPVCCIO_S0_CPU
1 C1010 1 C1011 1 C1012 1 C1013 1 C1014 1 C1015 1 C1016 1 C1017 1 C1018 1 C1019 1 C1080 1 C1081 1 C1087 1 C1082 1 C1083 1 C1084 1 C1085
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 3.0PF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% +/-0.1PF 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 25V
NP0-C0G 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402-1 0402-1 0201 0201 0201 0201 0201

NOSTUFF NOSTUFF NOSTUFF NOSTUFF

C 1 C1020
20UF
1 C1021
20UF
1 C1022
20UF
1 C1023
20UF
1 C1024
20UF
1 C1025
20UF
1 C1026
20UF
1 C1027
20UF
1 C1028
20UF
1 C1029
20UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
1 C1090 1 C1091 1 C1092 1 C1093 1 C1094 1 C1095
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
2.5V
2 X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
2.5V
2 X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20%
0402 0402 0402 0402 0402 0402 0402 0402 0402-1 0402-1 2 2.5V 2.5V
2 X6S-CERM 2 2.5V 2 2.5V 2 2.5V 2 2.5V
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF CRITICAL
1 C1030 1 C1031 1 C1032 1 C1033 1 C1034 1 C1035 1 C1036 1 C1037 1 C1038 1 C1039 1 C1040 1 C1041 1 C1042 1 C1043 1 C1044 1 C1045 1
C1086
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 220UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2V
ELEC
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 SM

1 C1000 1 C1001 1 C1002 1 C1003 1 C1004 1 C1005 1 C1006 1 C1007 1 C1008 1 C1009 1 C100A 1 C100B 1 C100C 1 C100D 1 C100E 1 C100F 1 C100G 1 C100H 87 83 66 52 7 PPVCCSA_S0_CPU
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF CRITICAL
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
1
C10H0
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 220UF
20%
2 2V
ELEC
SM

1 C100I 1 C100J 1 C100K 1 C100L 1 C100M 1 C100N 1 C100O 1 C100P 1 C100Q 1 C100R 1 C100S 1 C100T 1 C100U 1 C100V 1 C100W 1 C100X 1 C100Y
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM NOSTUFF NOSTUFF
B 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 1 C10B0 1 C10B1 1 C10B2 1 C10B3 B
20UF 20UF 20UF 20UF
20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
2.5V
2 X6S-CERM 2 2.5V
X6S-CERM
0402-1 0402-1 0402-1 0402-1

86 83 69 7 PPVCCEDRAM_S0_CPU
CRITICAL
1
C10H2
220UF
20%
2 2V
ELEC
SM
1 C10B6 1 C10B7
20UF 20UF
20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402-1 0402-1

1 C10D0 1 C10H3 1 C10E0 1 C10E1 1 C10E2 1 C10E3 1 C10E4 1 C10E5

20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
1 C10A0 1 C10A1 1 C10A2 1 C10A3 1 C10A4 1 C10A5 1 C10A6
1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
0201 0201 0201 0201 0201 0201 0201

1 C10D1 1 C10D2 1 C10D3 1 C10D4 1 C10D5 1 C10D6

1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X6S-CERM 2 6.3V
A X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201 0201
X6S-CERM
0201 SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

CPU Core Decoupling

DRAWING NUMBER SIZE

051-05309 D
83 70 69 65 42 18 17 9 7 5 PP1V_S3 83 74 7 PP1V2_S0SW 83 70 69 65 42 18 17 9 7 5 PP1V_S3 83 71 16 7 5 PP1V_S0SW Apple Inc. REVISION

1 C10F0 1 C10F1 1 C10F2 1 C10F3 5.1.0

1UF 1UF 1UF 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20% THE INFORMATION CONTAINED HEREIN IS THE
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM PROPRIETARY PROPERTY OF APPLE INC.
0201 0201 0201 0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 9 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

D D

87 83 67 50 7 PPVCCGT_S0_CPU

1 1 1 1 1
C1162 C1163 C1164 C1190 C1191
220UF 220UF 220UF 220UF 220UF
20% 20% 20% 20% 20%
2 2V 2 2V 2 2V 2 2V 2 2V
ELEC ELEC ELEC ELEC ELEC
SM SM SM SM SM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

NOSTUFF NOSTUFF NOSTUFF NOSTUFF

1 C1110 1 C1111 1 C1112 1 C1113 1 C1114 1 C1115 1 C1116 1 C1117 1 C1118 1 C1119 1 C1124 1 C1125 1 C1126 1 C1127 1 C1128 1 C1129
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
2.5V
2 X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
2.5V
2 X6S-CERM 2.5V
2 X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

C C
1 C1170 1 C1171 1 C1172 1 C1173 1 C1174 1 C1175 1 C1176 1 C1177 1 C1184 1 C1187
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2.5V
2 X6S-CERM 2 2.5V 2 2.5V 2 2.5V 2.5V
2 X6S-CERM 2 2.5V 2 2.5V 2.5V
2 X6S-CERM 2 2.5V 2 2.5V
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C1140 1 C1141 1 C1142 1 C1143 1 C1144 1 C1145 1 C1146 1 C1147 1 C1148 1 C1149
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF

1 C1150 1 C1151 1 C1152 1 C1153 1 C1154 1 C1155 1 C1156 1 C1157
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V
B X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402 B

1 C1100 1 C1101 1 C1102 1 C1103 1 C1104 1 C1105 1 C1106 1 C1107 1 C1108 1 C1109 1 C110A 1 C110B 1 C110C 1 C110D 1 C110E 1 C110F
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
6.3V
2 X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201

1 C110G 1 C110H 1 C110I 1 C110J 1 C110K 1 C110L 1 C110M 1 C110N 1 C110O 1 C110P 1 C110Q 1 C110R 1 C110S 1 C110T 1 C110U 1 C110V
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
6.3V
2 X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
6.3V
2 X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201

1 C110W 1 C110X
1UF 1UF
20% 20%
6.3V
2 X6S-CERM 2 6.3V
A 0201
X6S-CERM
0201 SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

CPU GT Decoupling
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 10 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

FILTERS
RAIL SIDE PCH SIDE

D D
L1260 MIN_LINE_WIDTH=0.2000
220-OHM-0.7A-0.28-OHM MIN_NECK_WIDTH=0.1000
86 83 70 54 7 PPVPCORE_S5 47 43 42 18 14 13 12 11 7 5 4 PP3V3_S5
89 83 74 73 71 69 32 18 17 16 15 14 13 12 11 7 PP1V8_S5 1 2 PP1V8_PRIM_PCH_VCCHDA_F 7
NOSTUFF NOSTUFF 83 74 73 72 70 69 65 53 47 42
0402-1
1 C1200 1 C1221 1 C1265 U0500.BT20::10mm 1 C1226 1 C1260
1UF 1UF
20% 20% 3.0PF 2.0PF 4.7UF
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
+/-0.1PF +/-0.1PF 20%
0201 0201 2 25V
NP0-C0G 2 25V
C0G-CERM 2 6.3V
X5R-CERM1
BYPASS=U0500.BV18::3MM BYPASS=U0500.BR24::3MM 0201 0201 402
BYPASS=U0500.BT20::10MM

BYPASS=U0500.BT20::10mm
86 83 73 70 54 16 11 7 PP1V_PRIM
7 PP1V05_S5_PCH_VCCDSW
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1 C1201 1 C1232
1UF
20%
6.3V
1UF
2 X6S-CERM 20%
0201 2 6.3V
X6S-CERM L1261 MIN_LINE_WIDTH=0.2000
BYPASS=U0500.BP20::3MM 0201 220-OHM-0.7A-0.28-OHM MIN_NECK_WIDTH=0.1000
BYPASS=U0500.BT24::3MM
86 83 73 70 54 16 11 7 PP1V_PRIM 1 2 PP1V05_PRIM_PCH_VCCAPLL_AUD_F 7
0402-1
U0500.BR15::3mm
PP1V_PRIM PP3V_G3H_RTC
1 C1267 1 C1262 1 C1261
86 83 73 70 54 16 11 7 83 71 13 7
3.0PF 2.0PF 4.7UF
+/-0.1PF +/-0.1PF 20%
CRITICAL 2 25V 2 25V 2 6.3V
1 C1203
1 C1227 1 C1228 NP0-C0G
0201
C0G-CERM
0201
X5R-CERM1
402
1UF 0.1UF BYPASS=U0500.BR15::3MM
20UF 20% 10%
20% 2 6.3V 2 10V
2 6.3V
CERM-X5R
X6S-CERM
0201
X5R-CERM
0201 BYPASS=U0500.BR15::3mm
C 0402
BYPASS=U0500.BV12::12MM
BYPASS=U0500.BR23::3MM C
BYPASS=U0500.BR23::3MM

32 18 17 16 15 14 13 12 11 7 PP1V8_S5
83 74 73 72 70 69 65 53 47 42 7 PPDCPRTC_PCH
NOSTUFF MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1 C1205 1 C1206 1 C1231
1UF 1UF
20% 20% 0.1UF
2 6.3V 2 6.3V
X6S-CERM
10%
X6S-CERM
0201 0201 2 10V
X5R-CERM
BYPASS=U0500.CP23::3MM 0201 R1250 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
BYPASS=U0500.BP24::3MM
PP1V_PRIM 1
0 2 PP1V05_PRIMSW_PCH_VCCAMPHYPLL_F
86 83 73 70 54 16 11 7 7
BYPASS=U0500.CP17::3MM
5%
1/16W
CRITICAL CRITICAL
PP3V3_S5
MF-LF
402
1 C1250 1 C1251 1 C1252
47 43 42 18 14 13 12 11 7 5 4
89 83 74 73 71 69 20UF 20UF 1UF
NOSTUFF 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
1 C1207 1 C1208 CERM-X5R
0402
CERM-X5R
0402
X6S-CERM
0201
3.0PF 0.1UF BYPASS=U0500.BV2::3MM
+/-0.1PF 10%
2 25V
NP0-C0G 2 10V
X5R-CERM
0201 0201 BYPASS=U0500.BV2::4MM
BYPASS=U0500.CP29::3MM BYPASS=U0500.BV2::5MM

BYPASS=U0500.CD23::7MM

R1253 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V_PRIM 1
0 2 PP1V05_PRIM_PCH_VCCAXTAL_F
86 83 73 70 54 16 11 7 7

5%
1/16W
CRITICAL CRITICAL
MF-LF
402
1 C1253 1 C1254 1 C1255
20UF 20UF 1UF
B 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
B
CERM-X5R CERM-X5R X6S-CERM
0402 0402 0201
BYPASS=U0500.CP5::3MM

BYPASS=U0500.CP5::3MM
BYPASS=U0500.CP5::3MM

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

PCH Decoupling
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
12 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 11 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

U0500 ALL GPP_F* PINS ARE 1.8V ONLY!

CFL-U
4+3E
AUDIO BGA SDIO/SDXC
BN34 SYM 7 OF 20 CP18
NC_PCH_I2S0_SYNC HDA_SYNC/I2S0_SFRM OMIT_TABLE GPP_F18/EMMC_DATA6 NC_PCH_GPP_F18
NC_PCH_I2S0_CLK BN37 HDA_BCLK/I2S0_SCLK GPP_F19/EMMC_DATA7 CM18 NC_PCH_GPP_F19
BN36 (1.8V) CM16
NC_HDA_SDOUT HDA_SDO/I2S0_TXD GPP_F20/EMMC_RCLK NC_PCH_GPP_F20
NC_PCH_I2S0_D2R BN35 HDA_SDI0/I2S0_RXD GPP_F21/EMMC_CLK CP16 NC_PCH_GPP_F21
D NC
BL36 HDA_SDI1/I2S1_RXD GPP_F22/EMMC_RESET* CN16 NC_PCH_GPP_F22 D
NC_PCH_I2S1_CLK BL35 HDA_RST*/I2S1_SCLK GPP_F23 CF17 NC_PCH_GPP_F23
NC_PCH_GPP_D17 CK25 GPP_D17/DMIC_CLK1 GPP_G0/SD_CMD CH36 TBT_X_CIO_PWR_EN 12 25 28 29
OUT
BL37 I2S1_SFRM GPP_G1/SD3_DATA0 CL35 TBT_X_USB_PWR_EN 12 25 28 29
NC OUT
BL34 I2S1_TXD
NC GPP_A17/SD_VDD1_PWR_EN*/ISH_GP7 BW36 NC_PCH_GPP_A17
25 12 JTAG_TBT_X_TMS CC8 GPP_E18/DPPB_CTRLCLK GPP_A16/SD_1P8_SEL BY31 NC_PCH_GPP_A16
OUT
CC9 (STRAP)
12 PCH_DDPB_CTRLDATA GPP_E19/DPPB_CTRLDATA
12 JTAG_TBT_T_TMS CH4 GPP_E20/DPPC_CTRLCLK SD_1P8_RCOMP CK33 SD_RCOMP
12 PCH_DDPC_CTRLDATA CH3 GPP_E21/DPPC_CTRLDATA SD_3P3_RCOMP CM34 PLACE_NEAR=U0500.CK33:12.7MM
CM24
(STRAP)
CR18
R1370 1
MLB_RAMCFG0 GPP_D13/ISH_UART0_RXD/ NC_PCH_GPP_F17 200
MEMORY CONFIGURATION STRAPS: 12

12 MLB_RAMCFG1 CN23
SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/
(1.8V) GPP_F17/EMMC_DATA5
1%
1/20W
SML0BCLK/I2C4B_SCL MF
CM22 (BSSB_CLK) 201 2
(PCH INTERNAL PULL-UPS ARE TO 1.8V) NC_PCH_GPP_D11 GPP_D11
12 PCH_STRP_JTAGODTDIS CP22 GPP_D12
(BSSB_DATA_IN)
NC_PCH_STRP_TOPBLK_SWP_L CF35 GPP_B14/SPKR (STRAP)

12 MLB_RAMCFG0
12 MLB_RAMCFG1 NC_PCH_GPP_F0 CP20 GPP_F0/CNV_PA_BLANKING GPP_H12/M2_SKT2/CFG[0] CR28 JTAG_ISP_TCK 12 25
OUT
12 MLB_RAMCFG2 NC_PCH_GPP_F1 CK19 GPP_F1 GPP_H13/M2_SKT2/CFG[1] CP28 JTAG_ISP_TDI 12 25
OUT
12 MLB_RAMCFG3 NC_PCH_GPP_F2 CG17 GPP_F2 GPP_H14/M2_SKT2/CFG[2] CN28 JTAG_ISP_TDO 12 25
IN
12 MLB_RAMCFG4 NC_PCH_GPP_F3 CN20 GPP_F3 GPP_H15/M2_SKT2/CFG[3] CM28 TBT_POC_RESET 12 28 29
OUT
RAMCFG4_L RAMCFG3_L RAMCFG2_L RAMCFG1_L RAMCFG0_L NC_PCH_I2C_UPC_SDA CF27 CR26 NC_PCH_GPP_H16
1 1 1 1 1 GPP_H4/I2C2_SDA GPP_H16/DDPF_CTRLCLK
R1334 R1333 R1332 R1331 R1330 NC_PCH_I2C_UPC_SCL CF29 GPP_H5/I2C2_SCL GPP_H17/DDPF_CTRLDATA CP26 NC_PCH_DDPF_CTRLDATA
1K 1K 1K 1K 1K NC_PCH_GPP_H6 CH27 CN27 CPU_C10_GATE_L
5% 5% 5% 5% 5% GPP_H6/I2C3_SDA GPP_H18/CPU_C10_GATE* OUT 12 71 73 74 83
1/20W 1/20W 1/20W 1/20W 1/20W CH28 CM27
MF MF MF MF MF NC_PCH_GPP_H7 GPP_H7/I2C3_SCL GPP_H19/TIMESYNC[0] PCH_WLAN_AUDIO_SYNC IN 12 18
2 201 2 201 2 201 2 201 2 201 NC_PCH_GPP_H8 CJ30 GPP_H8/I2C4_SDA GPP_H20/IMGCLKOUT[1] CH25 NC_PCH_GPP_H20
NC_PCH_GPP_H9 CJ31 GPP_H9/I2C4_SCL GPP_H21 CF25 PCH_STRP_XTAL_24MHZ
C NC_PCH_GPP_H10 CJ27 GPP_H10/I2C5_SDA/ISH_I2C2_SDA GPP_H22 CN26 NC_PCH_GPP_H22
12
C
NC_PCH_GPP_H11 CJ29 GPP_H11/I2C5_SCL/ISH_I2C2_SCL GPP_H23 CM26 PCH_STRP_SPIROM_SAF 12

U0500
CFL-U
4+3E
BGA
TP_SPI_PCHROM_CLK CH37 SPI0_CLK SYM 5 OF 20 GPP_C0/SMBCLK CK14 SMBUS_PCH_CLK 47
OUT
NC_SPI_PCHROM_MISO CF37 OMIT_TABLE CH15 SMBUS_PCH_DATA
SPI0_MISO GPP_C1/SMBDATA BI 47
CF36 IO1 CJ15
12 SPI_PCHROM_MOSI SPI0_MOSI GPP_C2/SMBALERT* NC_PCH_STRP_TLSCONF
CF34 IO0 (STRAP)
PP3V3_S5 4 5 7 11 13 14 18 42 43 47 69 16 12 SPI_PCHROM_IO<2> SPI0_IO2 CH14

SMBUS,SMLINK
GPP_C3/SML0CLK SML_PCH_0_CLK

SPI-FLASH
71 73 74 83 89 47
12 SPI_PCHROM_IO<3> CG34 SPI0_IO3
OUT
GPP_C4/SML0DATA CF15 SML_PCH_0_DATA 47
NOSTUFF TP_SPI_PCHROM_CS_L CG36 SPI0_CS0*
BI
R1399 1K 1 2
5% 1/20W MF 201
PCH_STRP_SPIROM_SAF 12
NC_SPI_CS1_L CG35 SPI0_CS1* (STRAP)
GPP_C5/SML0ALERT* CG15 PCH_STRP_ESPI 12

NC_SPI_CS2_L CH34 SPI0_CS2* GPP_C6/SML1CLK CN15 SML_PCH_1_CLK 12 47

OUT
R1346 100K 1 2
5% 1/20W MF 201
PCH_STRP_JTAGODTDIS 12
PCH_UART_DEBUG_D2R CR12 GPP_C20/UART2_RXD
GPP_C7/SML1DATA CM15 SML_PCH_1_DATA BI 12 47

R1355 10K 1 2
5% 1/20W MF 201
JTAG_TBT_X_TMS 12 25
83 27 12 IN
PCH_UART_DEBUG_R2D CP12 GPP_C21/UART2_TXD
GPP_B23/SML1ALERT*/PCHHOT* CC34 NC_PCH_STRP_BSSB_SEL_GPIO
R1356 10K JTAG_TBT_T_TMS 83 27 12

SPI-TOUCH
1 2 OUT
12 CN12 (STRAP)
5% 1/20W MF 201 NC_PCH_GPP_C22 GPP_C22/UART2_RTS*
R1359 10K 1 2 JTAG_ISP_TDO 12 25
PCH_UART2_CTS_L CM12 GPP_A1/LAD0/ESPI_IO0 CA29 ESPI_IO_PCH<0> R1320 20 1 2 ESPI_IO<0> BI 12 35

LPC
5% 1/20W MF 201 GPP_C23/UART2_CTS* 5% 1/20W MF 201
R1347 100K 1 2
5% 1/20W MF 201
CPU_C10_GATE_L 12 71 73 74 83
12

MLB_RAMCFG2 CM23 GPP_D15/ISH_UART0_RTS*

GPP_A2/LAD1/ESPI_IO1 BY29 ESPI_IO_PCH<1> R1321 20 1 2
5% 1/20W MF 201
ESPI_IO<1> BI 12 35
12

MLB_RAMCFG3 CR24 GPP_D16/ISH_UART0_CTS*

GPP_A3/LAD2/ESPI_IO2 BY27 ESPI_IO_PCH<2> R1322 20 1 2
5% 1/20W MF 201
ESPI_IO<2> BI 12 35

R1366 100K 1 2
5% 1/20W MF 201
SPI_PCHROM_MOSI 12
12

MLB_RAMCFG4 CG23 GPP_D21/SPI1_IO2

GPP_A4/LAD3/ESPI_IO3 BV27 ESPI_IO_PCH<3> R1323 20 1 2
5% 1/20W MF 201
ESPI_IO<3> BI 12 35

R1367 100K 1 2 SPI_PCHROM_IO<2> 12 16

12
GPP_A5/LFRAME*/ESPI_CS* CA28 ESPI_CS_PCH_L R1324 20 1 2 ESPI_CS_L OUT 12 35

B R1368 100K 1 2
5% 1/20W MF 201
SPI_PCHROM_IO<3> CH7 CA27 ESPI_RESET_L 5% 1/20W MF 201
B

C LINK
12
NC CL_CLK GPP_A14/SUS_STAT*/ESPI_RESET* OUT 12 35
5% 1/20W MF 201 CH8 CL_DATA
R1340 2.2K 1 2 PCH_DDPB_CTRLDATA ENABLE DPPB/C INTERFACES
12
NC
CH9 CL_RST*
GPP_A9/CLKOUT_LPC0/ESPI_CLK BV32 ESPI_CLK60M_R R1327 22 1 2
5% 1/20W MF 201
ESPI_CLK60M OUT 12 35
NC BV30 NC_PCH_GPP_A10
R1341 2.2K 1 2
5% 1/20W MF 201
PCH_DDPC_CTRLDATA 12 BV29
GPP_A10/CLKOUT_LPC1
BY30
5% 1/20W MF 201 18 12 PCH_BT_AUDIO_SYNC GPP_A0/RCIN* GPP_A8/CLKRUN* NC_PCH_GPP_A8
R1358 NOSTUFF
10K 1 2
5% 1/20W MF 201
PCH_GPP_A6 BV28 GPP_A6/SERIRQ

PP1V8_S5 7 11 13 14 15 16 17 18 32 42 47
53 65 69 70 72 73 74 83
ESPI ANALYZER CONNECTOR
NOSTUFF
R1344 100K 1 2
5% 1/20W MF 201
PCH_BT_AUDIO_SYNC 12 18 516S00115
R1345 1K 1 2
5% 1/20W MF 201
PCH_STRP_ESPI 12
505070-1222
R1352 47K 1 2
5% 1/20W MF 201
PCH_UART_DEBUG_D2R 12 27 83
J1301 ESPI_DBG
R1353 47K 1 2
5% 1/20W MF 201
PCH_UART_DEBUG_R2D 12 27 83 M-ST-SM
R1363 1K 1 2
5% 1/20W MF 201
PCH_STRP_SPIROM_SAF 12 13 14
R1365 1K 1 2
5% 1/20W MF 201
PCH_STRP_XTAL_24MHZ 12

R1348 100K 1 2 ESPI_IO<0> 12 35

35 12 ESPI_IO<0> R1380 43 1 2
1/20W 5% MF 201
ESPI_IO_DBG<0> 1 2 ESPI_RESET_L 12 35

R1349 100K 1 2
5% 1/20W MF 201
ESPI_IO<1> 12 35
35 12 ESPI_IO<1> R1381 43 1 2
1/20W 5% MF 201
ESPI_IO_DBG<1> 3 4
NC 43
R1350 100K 1 2
5% 1/20W MF 201
ESPI_IO<2> 12 35
35 12 ESPI_IO<2> R1382 43 1 2
1/20W 5% MF 201
ESPI_IO_DBG<2> 5 6 ESPI_CLK60M_DBG 1 2 ESPI_CLK60M 12 35

R1351 100K 1 2
5% 1/20W MF 201
ESPI_IO<3> 12 35
35 12 ESPI_IO<3> R1383 43 1 2
1/20W 5% MF 201
ESPI_IO_DBG<3> 7 8
NC 201 MF 1/20W 5%

R1357 100K 1 2
5% 1/20W MF 201
ESPI_CS_L 12 35
35 12 ESPI_CS_L R1384 43 1 2
1/20W 5% MF 201
ESPI_DBG_CS_L 9 10
NC R1385
5% 1/20W MF 201 11 12 ESPI_DBG
ESPI_DBG NC NC
R1369 100K 1 2 NOSTUFF
5% 1/20W MF 201
PCH_WLAN_AUDIO_SYNC 12 18
ESPI_DBG 15 16
R1375 2.2K 1 2 SML_PCH_1_CLK 12 47 ESPI_DBG
5% 1/20W MF 201
R1376 2.2K 1 2 SML_PCH_1_DATA ESPI_DBG
12 47
5% 1/20W MF 201 ESPI_DBG
A PM_SLP_S3_L 13 15 25 83 89
SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE
R1371 100K 1 2
5% 1/20W MF 201
TBT_X_CIO_PWR_EN 12 25 28 29
PCH AUDIO/LPC/SPI/SMBUS
R1372 100K 1 2
5% 1/20W MF 201
TBT_X_USB_PWR_EN 12 25 28 29
DRAWING NUMBER SIZE

051-05309 D
R1360 100K 1 2 JTAG_ISP_TCK 12 25
Apple Inc. REVISION
5% 1/20W MF 201
R1361 100K 1 2
5% 1/20W MF 201
JTAG_ISP_TDI 12 25 5.1.0
R1354 47K 1 2
5% 1/20W MF 201
PCH_UART2_CTS_L 12 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1362 100K 1 2
5% 1/20W MF 201
TBT_POC_RESET 12 28 29 THE INFORMATION CONTAINED HEREIN IS THE
R1364 100K 1 2
5% 1/20W MF 201
PCH_WLAN_AUDIO_SYNC 12 18
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

R1374 100K 1 2 PCH_BT_AUDIO_SYNC 12 18

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 500
5% 1/20W MF 201 BOM_COST_GROUP=CPU & CHIPSET III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

IV ALL RIGHTS RESERVED 12 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

D D

U0500
CFL-U
4+3E
BGA
SYM 11 OF 20
83 42 16 IN
SYSTEM POWER MANAGEMENT
PLACE_NEAR=U0500.CN10:5mm BJ37
C1400 1 OMIT_TABLE GPP_B12/SLP_S0* PM_SLP_S0_3V3_L OUT 13 18

100PF 83 18 17 15 13 PLT_RST_L BJ35 GPP_B13/PLTRST* GPD4/SLP_S3* BU36 PM_SLP_S3_L 12 13 15 25 83 89

OUT OUT
5% CN10 BU27
25V 2 PM_SYSRST_L SYS_RESET* GPD5/SLP_S4* PM_SLP_S4_L OUT 13 83 89
C0G BR36 BT29
0201 83 42 16 13 IN
PM_RSMRST_L RSMRST* GPD10/SLP_S5* PM_SLP_S5_L OUT 13 83 89
(1V ONLY)
R1406 TP_CPU_PWRGD AR2 PROCPWRGD SLP_SUS* BU29 PM_SLP_SUS_L 13

CPU_VCCST_PWRGD 1
60.41%2 CPU_VCCST_PWRGD_R BJ2 BT31
18 IN VCCST_PWRGOOD SLP_LAN* NC
VCCST_PWRGD 1V TOLERANT 201 MF 1/20W GPD9/SLP_WLAN* BT30 NC_PCH_SLP_WLAN_L
PLACE_NEAR=U0500.BJ2:38mm 83 42 PM_PCH_SYS_PWROK CR10 SYS_PWROK
IN
GPD6/SLP_A* BU37 NC_PCH_SLP_A_L
83 42 PM_PCH_PWROK BP31 PCH_PWROK PP3V_G3H_RTC 7 11 71 83
IN
83 42 16 13 PM_RSMRST_L BP30 DSW_PWROK GPD3/PWRBTN* BU28 PCH_PWRBTN_L 13 16 72 83
IN IN 1
BV34 GPD1/ACPRESENT BU35 SPIROM_USE_MLB 13
R1401
NC_PCH_GPP_A13 GPP_A13/SUSWARN*/SUSPWRDACK BV36 1M
BY32 GPD0/BATLOW* PCH_BATLOW_L 13 5%
NC_PCH_GPP_A15 GPP_A15/SUSACK* 1/20W
CA32 MF
BU30 GPP_A11/PME* NC_PCH_GPP_A11 2 201
13 PCIE_WAKE_L WAKE* BR35
BU32 INTRUDER* PCH_INTRUDER_L
13 PCH_LAN_WAKE_L GPD2/LAN_WAKE*
NC_PCH_LANPHYPC BU34 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE* CC37 PCH_HSIO_PWR_EN 13

13 PCH_STRP_GPD7 BV35 GPD7 GPP_B2/VRALERT* CC36 NC_PCH_GPP_B2

C C

U0500
CFL-U
4+3E
BGA
CR30 SYM 9 OF 20 CN31
NC CNV_WR_D0N CNV_WR_CLKN NC
B NC
CP30 CNV_WR_D0P
OMIT_TABLE
CNV
CNV_WR_CLKP CP31
NC
B
CM30 CNV_WR_D1N
NC CNV_WT_CLKN CP34
CN30 CNV_WR_D1P NC
NC CNV_WT_CLKP CN34
NC
CN32 CNV_WT_D0N
NC CNV_WT_RCOMP[0] CP32 CSI2_COMP
CM32 CNV_WT_D0P PLACE_NEAR=U0500.CP32:12.7MM
NC CNV_WT_RCOMP[1] CR32
CP33 1
NC
CN33
CNV_WT_D1N R1480
NC CNV_WT_D1P 100
1%
1/20W
CG20 MF
GPP_D0/SPI1_CS0*/BK0/SBK0 2 201
PP1V8_S5 7 11 12 14 15 16 17 18 32 42 47
53 65 69 70 72 73 74 83
NC

R1461 1K 1 2
5% 1/20W MF 201
PCH_STRP_CNV_DISABLE 13 changed EMMC
R1446 100K 1 2
5% 1/20W MF 201
PCH_SWD_SOC_CLK 13 GPP_F7/CNV_RGI_RSP CH19 NC_PCH_GPP_F7
ALL GPP_F* PINS ARE 1.8V ONLY!
R1445 100K 1 2
5% 1/20W MF 201
PCH_SWD_SOC_IO 13
(1.8V)
GPP_F8/CNV_MFUART2_RXD CJ17 NC_PCH_GPP_F8
GPP_F9/CNV_MFUART2_TXD CH17 NC_PCH_GPP_F9
GPP_F10 CK17 NC_PCH_GPP_F10 changed
PP3V3_S5 4 5 7 11 12 14 18 42 43 47 69 CR16
71 73 74 83 89 GPP_F11/EMMC_CMD PCH_BT_ROM_BOOT_L OUT 32

R1440 100K 1 2
5% 1/20W MF 201
SPIROM_USE_MLB 13 GPP_F12/EMMC_DATA0 CR20 PCH_SWD_SOC_CLK 13 CKPLUS_WAIVE=CLK_DATA_CON
R1441 100K 1 2
5% 1/20W MF 201
PCH_STRP_GPD7 13 GPP_F13/EMMC_DATA1 CM20 PCH_SWD_SOC_IO 13

R1451 100K 1 2
5% 1/20W MF 201
PCH_BATLOW_L 13 GPP_F14/EMMC_DATA2 CN19 SOC_SWD_MUX_SEL_PCH 13 83 changed
R1452 10K 1 2
5% 1/20W MF 201
PCIE_WAKE_L 13
GPP_F15/EMMC_DATA3 CM19 DP_INT_HPD_MASK
R1453 100K 1 2
5% 1/20W MF 201
PCH_LAN_WAKE_L 13
GPP_F16/EMMC_DATA4 CN18 NC_PCH_GPP_F16
IN 35 43

R1459 100K 1 2
5% 1/20W MF 201
PCH_HSIO_PWR_EN 13
GPP_F6/CNV_RGI_DT CG19 PCH_STRP_CNV_DISABLE changed
R1463 10K 1 2
5% 1/20W MF 201
PCH_PWRBTN_L 13 16 72 83
13

EMMC_RCOMP CK15 EMMC_RCOMP

PLACE_NEAR=U0500.CK15:12.7MM
R1460 100K 1 2 PLT_RST_L 13 15 17 18 83
1
A R1444 100K 5% 1/20W MF 201
SOC_SWD_MUX_SEL_PCH R1481
R1454 100K
1
1
2
2
5% 1/20W MF 201
PM_SLP_S5_L
13 83

13 83 89 1%
200 SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE
5% 1/20W MF 201 1/20W
R1455 100K 1 2
5% 1/20W MF 201
PM_SLP_S4_L 13 83 89 MF
PCH POWER MANAGEMENT
R1456 100K 1 2 PM_SLP_S3_L 12 13 15 25 83 89
2 201
5% 1/20W MF 201
R1457 100K 1 2
5% 1/20W MF 201
PM_SLP_S0_3V3_L 13 18
DRAWING NUMBER

051-05309
SIZE

D
R1458 100K 1 2
5% 1/20W MF 201
PM_SLP_SUS_L 13 Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

NOTE: =PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED. THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE. THE POSESSOR AGREES TO THE FOLLOWING: PAGE

THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
14 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 13 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

U0500
CFL-U
4+3E
BGA
CB5 SYM 8 OF 20 BK6
27 IN USB3_BSSB_D2R_N PCIE1_RXN/USB31_1_RXN PCIE13_RXN PCIE_SOC_D2R_N<0> IN 37
CB6 OMIT_TABLE BK5
27 IN USB3_BSSB_D2R_P PCIE1_RXP/USB31_1_RXP PCIE13_RXP PCIE_SOC_D2R_P<0> IN 37
CA4 BM4 SOC LANE 0
EXT A (SS,DCI) 27 OUT USB3_BSSB_R2D_C_N PCIE1_TXN/USB31_1_TXN PCIE13_TXN PCIE_SOC_R2D_C_N<0> OUT 43

27 USB3_BSSB_R2D_C_P CA3 PCIE1_TXP/USB31_1_TXP PCIE13_TXP BM3 PCIE_SOC_R2D_C_P<0> 43

OUT OUT

83 TP_USB3_EXTC_D2R_N BY8 PCIE2_RXN/USB31_2_RXN PCIE14_RXN BJ6 PCIE_SOC_D2R_N<1> 37

IN IN
83 TP_USB3_EXTC_D2R_P BY9 PCIE2_RXP/USB31_2_RXP PCIE14_RXP BJ5 PCIE_SOC_D2R_P<1> 37
IN IN
FIXTURE USB-A CA2 BL2
83 OUT TP_USB3_EXTC_R2D_C_N PCIE2_TXN/USB31_2_TXN PCIE14_TXN PCIE_SOC_R2D_C_N<1> OUT 43 SOC LANE 1

D 83 OUT TP_USB3_EXTC_R2D_C_P CA1 PCIE2_TXP/USB31_2_TXP PCIE14_TXP BL1 PCIE_SOC_R2D_C_P<1> OUT 43 D

32 PCH_PCIE_WLAN_D2R_N BY7 PCIE3_RXN/USB31_3_RXN PCIE15_RXN/SATA1B_RXN BG5 PCIE_SOC_D2R_N<2> 37
IN IN
32 PCH_PCIE_WLAN_D2R_P BY6 PCIE3_RXP/USB31_3_RXP PCIE15_RXP/SATA1B_RXP BG6 PCIE_SOC_D2R_P<2> 37
IN IN
AIRPORT BY4 BL4 SOC LANE 2
32 OUT PCH_PCIE_WLAN_R2D_C_N PCIE3_TXN/USB31_3_TXN PCIE15_TXN/SATA1B_TXN PCIE_SOC_R2D_C_N<2> OUT 43

32 PCH_PCIE_WLAN_R2D_C_P BY3 PCIE3_TXP/USB31_3_TXP PCIE15_TXP/SATA1B_TXP BL3 PCIE_SOC_R2D_C_P<2> 43

OUT OUT

83 USB3_EXTD_D2R_N BW6 PCIE4_RXN/USB31_4_RXN PCIE16_RXN/SATA2_RXN BE5 PCIE_SOC_D2R_N<3> 37

IN IN
83 USB3_EXTD_D2R_P BW5 PCIE4_RXP/USB31_4_RXP PCIE16_RXP/SATA2_RXP BE6 PCIE_SOC_D2R_P<3> 37
IN IN
BW2 BJ4 SOC LANE 3
EXT USB-A 83 OUT USB3_EXTD_R2D_C_N PCIE4_TXN/USB31_4_TXN PCIE16_TXN/SATA2_TXN PCIE_SOC_R2D_C_N<3> OUT 43

83 USB3_EXTD_R2D_C_P BW1 PCIE4_TXP/USB31_4_TXP PCIE16_TXP/SATA2_TXP BJ3 PCIE_SOC_R2D_C_P<3> 43

OUT OUT

27 PCIE_TBT_X_D2R_N<0> BW9 PCIE5_RXN/USB31_5_RXN

IN
USB2_1N CE3 USB_EXTA_N
27 PCIE_TBT_X_D2R_P<0> BW8 PCIE5_RXP/USB31_5_RXP BI
IN
USB2_1P CE4 USB_EXTA_P TO TP
THUNDERBOLT X LANE 0 27 PCIE_TBT_X_R2D_C_N<0> BW4 PCIE5_TXN/USB31_5_TXN BI
OUT
27 PCIE_TBT_X_R2D_C_P<0> BW3 PCIE5_TXP/USB31_5_TXP USB2_2N CE1 NC_USB_EXTBN
OUT
USB2_2P CE2 NC_USB_EXTBP NOT USED
27 PCIE_TBT_X_D2R_N<1> BU6 PCIE6_RXN/USB31_6_RXN
IN
27 PCIE_TBT_X_D2R_P<1> BU5 PCIE6_RXP/USB31_6_RXP USB2_3N CG3 NC_USB_EXTCN
IN
THUNDERBOLT X LANE 1 BU4 CG4
27 OUT PCIE_TBT_X_R2D_C_N<1> PCIE6_TXN/USB31_6_TXN USB2_3P NC_USB_EXTCP NOT USED
27 PCIE_TBT_X_R2D_C_P<1> BU3 PCIE6_TXP/USB31_6_TXP
OUT
USB2_4N CD3 TP_USB_FIXT2_N 83
BI
27 PCIE_TBT_X_D2R_N<2> BT7 PCIE7_RXN USB2_4P CD4 TP_USB_FIXT2_P 83 TP FOR FIXTURE
IN BI
27 PCIE_TBT_X_D2R_P<2> BT6 PCIE7_RXP
THUNDERBOLT X LANE 2
IN
USB2_5N CG5 NC_USB_EXTDN
27 PCIE_TBT_X_R2D_C_N<2> BU2 PCIE7_TXN NOT USED
OUT
USB2_5P CG6 NC_USB_EXTDP
27 PCIE_TBT_X_R2D_C_P<2> BU1 PCIE7_TXP
OUT
CC1 USB2_UPC_PCH_XA_N

PCIE/USB3/SATA
BU9 USB2_6N 28
27 PCIE_TBT_X_D2R_N<3> PCIE8_RXN CC2
BI
IN
BU8 USB2_6P USB2_UPC_PCH_XA_P 28 XA RP

USB2
THUNDERBOLT X LANE 3 27 IN PCIE_TBT_X_D2R_P<3> PCIE8_RXP BI

PCIE_TBT_X_R2D_C_N<3> BT4 PCIE8_TXN USB2_7N CG8 NC_TP_USB_UPC_PCH_TA_N

C 27

27
OUT

OUT PCIE_TBT_X_R2D_C_P<3> BT3 PCIE8_TXP USB2_7P CG9 NC_TP_USB_UPC_PCH_TA_P NOT USED

C
BP5 PCIE9_RXN USB2_8N CB8 USB2_UPC_PCH_XB_N 29
NC BI
BP6 PCIE9_RXP USB2_8P CB9 USB2_UPC_PCH_XB_P 29 XB RP
NC BI
BR2 PCIE9_TXN
NC USB2_9N CH5 NC_TP_USB_UPC_PCH_TB_N
BR1 PCIE9_TXP
NC USB2_9P CH6 NC_TP_USB_UPC_PCH_TB_P NOT USED
BN6 PCIE10_RXN
NC USB2_10N CC3 TP_USB_FIXT1_N 83
BN5 PCIE10_RXP BI
NC USB2_10P CC4 TP_USB_FIXT1_P 83 TP FOR FIXTURE
BR4 PCIE10_TXN BI
NC
PLACE_NEAR=U0500.CE6:12.7mm BR3 PCIE10_TXP USB2_COMP CC5 PCH_USB2_COMP
NC
1 CE8
R1504 PCH_PCIE_RCOMP_N CE6 PCIE_RCOMP_N
USB2_ID
CC6
(GROUNDED PER CFL EDS) 1
R1501
100 CE5 USB2_VBUSSENSE PCH_USB2_VBUSSENSE
1% PCH_PCIE_RCOMP_P PCIE_RCOMP_P 113
1/20W CE9 1 1%
MF W1 GPP_E3/CPU_GP0 XDP_PCH_OBSFN_C1 16 R1503 1/20W
201 2 16 XDP_CPU_PRDY_L PROC_PRDY* CP8
IN
MF
OUT
W2 GPP_E4/DEVSLP0 XDP_PCH_OBSDATA_A0 16 1K 2 201
16 XDP_CPU_PREQ_L PROC_PREQ* CR8
IN
5%
IN
GPP_E5/DEVSLP1 XDP_PCH_OBSDATA_A1 IN 16 1/20W
CC32 CM8 MF
14 PCH_GPP_A7 GPP_A7/PIRQA* GPP_E6/DEVSLP2 XDP_PCH_OBSDATA_A2 IN 16
2 201
BN10 CH23 PLACE_NEAR=U0500.CC5:12.7MM
NC PCIE11_RXN/SATA0_RXN GPP_D22/SPI1_IO3 NC_SDCONN_OC_L
BN8 PCIE11_RXP/SATA0_RXP GPP_D23/I2S_MCLK CK23 NC_PCH_ENET_LOW_PWR
NC PLACE_NEAR=U0500.CC6:12.7MM
BN4 PCIE11_TXN/SATA0_TXN
NC GPP_D18/DMIC_DATA1 CJ25 NC_PCH_GPP_D18
BN3 PCIE11_TXP/SATA0_TXP
NC GPP_D19/DMIC_CLK0 CP24 NC_PCH_GPP_D19
BL6 PCIE12_RXN/SATA1A_RXN
NC GPP_D20/DMIC_DATA0 CN24 NC_PCH_GPP_D20
BL5 PCIE12_RXP/SATA1A_RXP
NC
BN2 PCIE12_TXN/SATA1A_TXN GPP_E0/SATAXPCIE0/SATAGP0 CN8 XDP_PCH_OBSDATA_D1 16
NC IN
BN1 PCIE12_TXP/SATA1A_TXP GPP_E1/SATAXPCIE1/SATAGP1 CM10 XDP_PCH_OBSDATA_D2 16
NC IN
GPP_E2/SATAXPCIE2/SATAGP2 CP10 XDP_PCH_OBSDATA_D3 16
IN
B B

U0500
CFL-U
4+3E
BGA
SYM 10 OF 20
ANY CLKREQ CAN MAP TO ANY CLK. CLOCK SIGNALS
ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT. AW2 OMIT_TABLE
NC_PCIE_CLK100M0N CLKOUT_PCIE_N0
UNUSED CLKREQS AND CLKS SHOULD BE DISABLED. AY3
NC_PCIE_CLK100M0P CLKOUT_PCIE_P0
PER SKYLAKE PDG, SKYLAKE PCH EDS. CF32
NC_DEBUG_CLKREQ0_L GPP_B5/SRCCLKREQ0*

84 37 PCIE_CLK100M_SOC_N BC1 CLKOUT_PCIE_N1

OUT
84 37 PCIE_CLK100M_SOC_P BC2 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N AU1 NC_ITPXDP_CLK100MN
PP3V3_S5 4 5 7 11 12 13 18 42 43 47 69
OUT
CE32 AU2
71 73 74 83 89 37 14 IN SOC_CLKREQ_L GPP_B6/SRCCLKREQ1* CLKOUT_ITPXDP_P NC_ITPXDP_CLK100MP
PCIE_CLK100M_TBT_X_N BD3 CLKOUT_PCIE_N2 GPD8/SUSCLK BT32 NC_PCH_CLK32K_SUS
R1531 47K 1 2
5% 1/20W MF 201
TBT_X_CLKREQ_L 14 25
84 25

84 25
OUT
PCIE_CLK100M_TBT_X_P BC3 CLKOUT_PCIE_P2
OUT CK3 PCH_CLK24M_XTALIN
R1532 10K 1 2 PCH_GPP_A7 14 25 14 TBT_X_CLKREQ_L CF30 GPP_B7/SRCCLKREQ2*
XTAL_IN
CK2
IN 17

NOSTUFF 5% 1/20W MF 201 IN

XTAL_OUT PCH_CLK24M_XTALOUT OUT 17

NC_PCIE_CLK100M3N BH3 CLKOUT_PCIE_N3

CLKIN_XTAL CM3 PCH_CLKIN_XTAL 14
NC_PCIE_CLK100M3P BH4 CLKOUT_PCIE_P3 CJ1 PCH_DIFFCLK_BIASREF
NC_DEBUG_CLKREQ3_L CE31 GPP_B8/SRCCLKREQ3*
CLK_BIASREF 14
R1573
PP1V8_S5 7 11 12 13 15 16 17 18 32 42 47 BN31 100K
53 65 69 70 72 73 74 83
BA1 RTCX1 PMU_CLK32K_PCH_1V0 1 2 PMU_CLK32K_PCH 72
32 PCH_PCIE_CLK100M_WLAN_N CLKOUT_PCIE_N4 BN32
IN
OUT
RTCX2 NC_TP_PCH_RTCX2_OUT 1%
R1533 47K 1 2
5% 1/20W MF 201
SOC_CLKREQ_L 14 37 32 OUT PCH_PCIE_CLK100M_WLAN_P BA2 CLKOUT_PCIE_P4 R1572 1 1/20W
MF
R1534 47K 1 2 PCH_WLAN_CLKREQ_L 14 32 32 14 PCH_WLAN_CLKREQ_L CE30 GPP_B9/SRCCLKREQ4* SRTCRST* BR37 PCH_RTC_RESET_L 72 83 127K 201
A 5% 1/20W MF 201
IN

NC_PCIE_CLK100M5N BE1 RTCRST* BR34

IN
1%
1/20W SYNC_MASTER= SYNC_DATE=
A
CLKOUT_PCIE_N5 MF PAGE TITLE
BE2 201 2 PLACE_NEAR=U0500.BN31:5MM
NC_PCIE_CLK100M5P
NC_DEBUG_CLKREQ5_L CF31
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5*
PLACE_NEAR=U0500.BN31:5MM
PCH PCIE/USB/CLKS
DRAWING NUMBER SIZE

051-05309 D
R1521 0 1 2 PCH_CLKIN_XTAL 14
Apple Inc. REVISION
5% 1/20W MF 0201
PLACE_NEAR=U0500.CM3:25.4mm
5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1520 60.4 1 2 PCH_DIFFCLK_BIASREF 14 THE INFORMATION CONTAINED HEREIN IS THE
1% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE_NEAR=U0500.CJ1:25.4mm I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 14 OF 98
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 8 7 6 5 4 3 2 1

D D
ALL GPP_F* PINS ARE 1.8V ONLY!
83 18 17 13 IN
PLT_RST_L

R1675 1 1
R1676 U0500
100K 100K CFL-U
5% 5%
1/20W 1/20W 4+3E
MF MF BGA
201 2 2 201 LPSS ISH
CC27 SYM 6 OF 20 CK22
34 15 OUT
PCH_SOC_SYNC GPP_B15/GSPI0_CS0* GPP_D5/ISH_I2C0_SDA NC_PCH_GPP_D5
SOC_PERST_L CE28 OMIT_TABLE CH20 NC_PCH_GPP_D6
85 35 OUT GPP_B16/GSPI0_CLK GPP_D6/ISH_I2C0_SCL
NC_PCH_ENETSD_RESET_L CE27 GPP_B17/GSPI0_MISO GPP_D7/ISH_I2C1_SDA CH22 NC_PCH_GPP_D7
15 PCH_STRP_NO_REBOOT CE29 GPP_B18/GSPI0_MOSI GPP_D8/ISH_I2C1_SCL CJ22 NC_PCH_UPC_I2C_INT_L
(STRAP)
NC_PCH_GPP_B19 CA31 GPP_B19/GSPI1_CS0* GPP_D1/SPI1_CLK CF20 NC_PCH_GPP_D1
NC_PCH_GPP_B20 CC29 GPP_B20/GSPI1_CLK GPP_D2/SPI1_MISO_IO1 CG22 NC_PCH_GPP_D2
NC_PCH_GPP_B21 CC30 GPP_B21/GSPI1_MISO
GPP_D3/SPI1_MOSI_IO0 CF22 NC_PCH_GPP_D3
NC_PCH_STRP_BOOT_SPI_L CA30 GPP_B22/GSPI1_MOSI PM_SLP_S3_L 12 13 25 83 89
(STRAP) GPP_D4/IMGCLKOUT0 CG25 NC_PCH_GPP_D4
CR14
IN
NC_PCH_BT_UART_D2R
CP14
GPP_C8/UART0_RXD
GPP_F4/CNV_BRI_DT CJ20 NC_PCH_GPP_F4 R1671 1 1
R1670
NC_PCH_BT_UART_R2D GPP_C9/UART0_TXD (1.8V) CK20 100K 100K
OUT
CN14 GPP_F5/CNV_BRI_RSP NC_PCH_GPP_F5 5% 5%
OUT
NC_PCH_BT_UART_RTS_L GPP_C10/UART0_RTS* (1.8V) 1/20W 1/20W
CM14 CK36 MF MF
IN
NC_PCH_BT_UART_CTS_L GPP_C11/UART0_CTS* GPP_G6/SD_CLK NC_TBT_X_DPMUX_SEL 201 2 2 201
GPP_D9 CN22 TBT_X_PLUG_EVENT_L 25
NC_PCH_GPP_C16 CM11 GPP_C16/I2C0_SDA
IN
GPP_D10 CR22 TBT_T_PLUG_EVENT_L
NC_PCH_GPP_C17 CN11 GPP_C17/I2C0_SCL
GPP_G7/SD_WP CK34 NC_TBT_T_DPMUX_SEL
NC_PCH_GPP_C18 CK12 GPP_C18/I2C1_SDA
NC_PCH_GPP_C19 CJ12 GPP_C19/I2C1_SCL GPP_G2/SD3_DATA1 CL36 NC_TBT_T_CIO_PWR_EN
GPP_G3/SD3_DATA2 CM35 NC_TBT_T_USB_PWR_EN
NC_PCH_GPP_C12 CG12 GPP_C12/UART1_RXD/ISH_UART1_RXD
C NC_PCH_GPP_C13 CH12 GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_G4/SD_DATA3 CN35
CH35
TBT_X_PCI_RESET_L OUT 18 25 C
GPP_G5/SD_CD* NC_TBT_T_PCI_RESET_L
NC_PCH_GPP_C14 CF12 GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_A18/ISH_GP0 BW35 NC_PCH_GPP_A18
NC_PCH_GPP_C15 CG14 GPP_C15/UART1_CTS*/ISH_UART1_CTS*
GPP_A19/ISH_GP1 BW34 NC_PCH_GPP_A19
NC_MEM_OK CP4 GPP_E22/DPPD_CTRLCLK GPP_A20/ISH_GP2 CA37 NC_PCH_GPP_A20
NC_PCH_DDPD_CTRLDATA CN4 GPP_E23/DPPD_CTRLDATA GPP_A21/ISH_GP3 CA36 NC_PCH_GPP_A21
GPP_A22/ISH_GP4 CA35 NC_BTI2SMUX_SEL_PCH
NC_PCH_I2S_BT_CLK CH32 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
GPP_A23/ISH_GP5 CA34 NC_PCH_BT_DEV_WAKE
NC_PCH_I2S_BT_SYNC CJ32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK
GPP_A12/ISH_GP6/BM_BUSY*/ BW37 NC_PCH_GPP_A12
CH29 (1.8V)
NC_PCH_I2S_BT_R2D GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI SX_EXIT_HOLDOFF*

NC_PCH_I2S_BT_D2R CH30 GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

32 PCH_WLAN_PERST_L CB34 GPP_B3/CPU_GP2

OUT
15 PCH_WLAN_DEV_WAKE CC35 GPP_B4/CPU_GP3

B B

PP1V8_S5 7 11 12 13 14 16 17 18 32 42 47
53 65 69 70 72 73 74 83

R1656 1K 1 2
5% 1/20W MF 201
PCH_STRP_NO_REBOOT 15

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

PCH SPI/UART/GPIO
DRAWING NUMBER SIZE

051-05309 D
R1677 100K 1 2 PCH_WLAN_DEV_WAKE 15
Apple Inc. REVISION
5% 1/20W MF 201
R1674 100K 1 2
5% 1/20W MF 201
PCH_SOC_SYNC 15 34 5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 15 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
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 8 7 6 5 4 3 2 1

Primary / Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

86 83 73 70 54 11 7 PP1V_PRIM

XDP_CONN:YES
D J1800 83 71 9 7 5 PP1V_S0SW D
DF40RC-60DP-0.4V
M-ST-SM1
62 61 XDP:YES
16 5 XDP_PCH_TDO R1890 100 2
PLACE_NEAR=U0500.W5:28MM
1
5% 1/20W MF 201

XDP_PRESENT_CPU 2 1 XDP:YES
XDP_PIN_1
14 XDP_CPU_PREQ_L OBSFN_A0 4 3 OBSFN_C0 CPU_CFG<17> 5
16 5 XDP_PCH_TDI R1891 51
PLACE_NEAR=U0500.U5:28MM
2 1
5% 1/20W MF 201
BI IN
XDP:YES 14 XDP_CPU_PRDY_L OBSFN_A1 6 5 OBSFN_C1 CPU_CFG<16> 5 XDP:YES
IN IN
NO_XNET_CONNECTION R1801 1 8 7 16 5 XDP_PCH_TMS R1892 51
PLACE_NEAR=U0500.P5:28MM
2 1
5% 1/20W MF 201
1K 5 CPU_CFG<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<8> 5
IN IN
5%
CPU_CFG<1> 12 11 CPU_CFG<9> XDP:YES
1/20W OBSDATA_A1 OBSDATA_C1
PULLS CFG<3> LOW MF
201 2
5 IN
14 13
IN 5
16 5 XDP_CPU_TDO R1810 100 2
PLACE_NEAR=U0500.Y5:28MM
1
5% 1/20W MF 201
WHEN XDP PRESENT CPU_CFG<2> 16 15 CPU_CFG<10>
5 IN OBSDATA_A2 OBSDATA_C2 IN 5

CPU_CFG<3> 18 17 CPU_CFG<11> XDP:YES

OBSDATA_A3 OBSDATA_C3
5 IN
20 19
IN 5
16 5 XDP_CPU_TCK R1813 51
PLACE_NEAR=U0500.T6:28MM
2 1
5% 1/20W MF 201
OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<19> 5 NOSTUFF
NC IN

NC OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<18> IN 5 16 5 XDP_PCH_TCK R1897 51

PLACE_NEAR=U0500.W6:28MM
2 1
5% 1/20W MF 201
26 25
5 CPU_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<12> 5
IN IN
5 CPU_CFG<5> OBSDATA_B1 30 29 OBSDATA_D1 CPU_CFG<13> 5 PLACE_NEAR=J1800.45:32MM
IN IN
32 31 1
34 33
R1830
5 IN
CPU_CFG<6> OBSDATA_B2 OBSDATA_D2 CPU_CFG<14> IN 5 1K
36 35 5%
PLACE_NEAR=U0500.BR36:18MM 5 IN
CPU_CFG<7> OBSDATA_B3 OBSDATA_D3 CPU_CFG<15> IN 5 1/20W
38 37 MF
XDP:YES 2 201
83 42 13 IN
PM_RSMRST_L R1800 1K 1 2
5% 1/20W MF 201
XDP_PM_RSMRST_L HOOK0 40 39 ITPCLK/HOOK4 NC
HOOK1 42 41 ITPCLK#/HOOK5
83 72 13 PCH_PWRBTN_L R1802 10 1 2 XDP_CPU_PWRBTN_L NC
C
C OUT
5% 1/20W MF 201 VCC_OBS_AB 44 43 VCC_OBS_CD
XDP:YES
XDP:YES
C1804 1
NC HOOK2 46 45 RESET#/HOOK6 ITP_PMODE IN 5

PLACE_NEAR=U0500.BU28:8MM 0.1UF
10% NC HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L R1806 0 1 2 PM_SYSRST_L BI 13 42 83
PLACE_NEAR=J1800.42:28MM 10V 50 49
X5R-CERM 2 XDP:YES 5%
0201 SDA 52 51 TDO
1 C1806 XDP:YES 1/20W
MF
NC 0.1UF PLACE_NEAR=J1800.47:28MM 0201
SCL 54 53 TRSTn 10%
NC
56 55 2 10V
X5R-CERM
16 5 OUT
XDP_PCH_TCK TCK1 TDI 0201 ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
16 5 XDP_CPU_TCK TCK0 58 57 TMS
OUT
XDP:YES 60 59 XDP_PRESENT#
5 PCH_JTAGX R1835 0 1 2 XDP:YES XDP:YES
R1821 0 1 2
5% 1/20W
XDP_CPU_TDO
MF 0201 IN 5 16
OUT
5% 1/20W MF 0201 XDP:YES
PLACE_NEAR=J1800.58:28MM
C1800 1
64 63
1 C1801 R1822 0 1 2 XDP_CPU_TRST_L
0.1UF 0.1UF 5% 1/20W MF 0201 OUT 5

PLACE_NEAR=J1800.44:28MM 10% 10%

10V
X5R-CERM 2 2 10V
0201 518S0847 X5R-CERM
0201 R1823 0 1 2
5% 1/20W
XDP_CPU_TDI
MF 0201
OUT 5

PLACE_NEAR=J1800.43:28MM XDP:YES
R1824 0 1 2
5% 1/20W
XDP_CPU_TMS
MF 0201
OUT 5

XDP:YES XDP_PCH_TDO IN 5 16

PLACE NEARS FOR R1801, R1821, R1822, R1823, R1824 XDP_PCH_TRST_L OUT 5

REQUIRE UPDATE FOR P1 PER <RDAR://42934724> XDP_PCH_TDI OUT 5 16

XDP_PCH_TMS OUT 5 16

XDP_PRESENT_L OUT 35

B PCH XDP Signals B

These signals do not connect to the Primary (Merged) XDP connector in this architecture.
42 32 18 17 15 14 13 12 11 7 PP1V8_S5
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. 83 74 73 72 70 69 65 53 47 XDP:YES
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere. XDP:YES
XDP:YES
1 C1830
0.1UF

6
1
R1850 VCC
10%
PCH/XDP Signals Non-XDP Signals 100K 2 10V
X5R-CERM
5%
1/20W
U1830 0201 XDP:YES
14 XDP_PCH_OBSDATA_A0 1 TP MF 74AUP1G07GF R1831
BI
TP-P6
TP1868 201 2 SOT891
1.5K
14 XDP_PCH_OBSDATA_A1 1 TP 2 A Y 4 SPI_IO2_STRAP_L 1 2 SPI_PCHROM_IO<2> 12
BI
TP-P6
TP1869 (OD)
5%
OUT

14 XDP_PCH_OBSDATA_A2 1 TP 1 NC NC 5 1/20W
BI
TP-P6
TP1870 NC NC MF
201 (STRAP TO PCH)
4 XDP_PCH_OBSDATA_A3 1 TP GND
BI
TP1871 PLACE_NEAR=U0500.CF34:10MM

3
TP-P6
4 XDP_PCH_OBSDATA_B0 1 TP NO_XNET_CONNECTION=1
BI
TP-P6
TP1872
14 XDP_PCH_OBSDATA_D1 1 TP PULL STRAP LOW WHEN XDP IS PLUGGED IN.
BI
TP-P6
TP1878 (UNDOCUMENTED STRAP FUNCTION)
14 XDP_PCH_OBSDATA_D2 1 TP
BI
TP-P6
TP1879
14 XDP_PCH_OBSDATA_D3 1 TP
BI
TP-P6
TP1880
14 XDP_PCH_OBSFN_C1 1 TP
BI
TP-P6
TP1881

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE
Unused GPIOs have TPs.
CPU/PCH Merged XDP
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DEBUG IV ALL RIGHTS RESERVED 16 OF 98
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QQ微信：181806465
 8 7 6 5 4 3 2 1

24MHz CLOCK

CRITICAL
C1907 R1900
9.5PF 0
1 2 PCH_CLK24M_XTALOUT_R 1 2 PCH_CLK24M_XTALOUT
D 5%
IN

OUT
14

14
D
+/-0.1PF 1/20W
50V MF
CER-C0G 0201
0201

CRITICAL

3
Y1900 1
R1901

2 4
24MHZ-10PPM-8PF-40OHM 200K
1%

1
2.5X2.0MM-SM 1/20W
MF
2 201
PLACE_NEAR=U0500.CK2:25.4mm
CRITICAL
C1908
9.5PF
1 2 PCH_CLK24M_XTALIN
+/-0.1PF NOTE: 30 PPM or better required for SKL PCH
50V
CER-C0G
0201

THRMTRIP# ISOLATION & LEVEL-SHIFT TO 1V8

C 83 70 69 65 42 18 9 7 5 PP1V_S3 PP1V8_S5 7 11 12 13 14 15 16 18 32 42 47
53 65 69 70 72 73 74 83
C
C1900 1 1 C1901
0.1UF 0.1UF
10% 10%
10V 2 10V
X5R-CERM 2 X5R-CERM
0201 0201

U1900
74AXP1T57
1

SOT833

85 83 72 5 IN
PM_THRMTRIP_L 3
6 CPU_SMC_THRMTRIP_L 35
OUT
83 18 15 13 IN
PLT_RST_L 7 NOSTUFF
1
R1902
100K
2

4
5

5%
1/20W
MF
2 201

B B

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

Chipset Support 1
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 17 OF 98
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QQ微信：181806465
 8 7 6 5 4 3 2 1

PLATFORM RESET LEVEL-SHIFTER TO 3V3

69 47 43 42 14 13 12 11 7 5 4
89 83 74 73 71
PP3V3_S5
1 C2006
0.1UF
10%
2 16V
X5R-CERM
0201
U2002 BT AUDIO SYNC BUFFER
74AUP1T97

5
SOT891
PLT_RST_L PLT_RST_3V3_L
D
83 18 17 15 13 IN
1 4
D
R2000

6
1 100K PP1V8_G3S
R2003 58 57 55 51 48 47 45 44 43 18

3
2 1 TBT_X_PCI_RESET_L 15 25 83 76 74 68 62 61 60 59

2
OUT
100K 5% 1/20W MF 201
5%
1/20W
C2021 1

MF 0.1UF
201 2 10%
16V
X5R-CERM 2
0201

6
VCC
U2021
SN74LVC1G126DRYR-M
LLP
PLT_RST_L 1 OE
SLP_S0# LEVEL SHIFTER TO 1V8 83 18 17 15 13 IN

32 IN
BT_AUDIO_SYNC 2 A Y 4 PCH_BT_AUDIO_SYNC OUT 12

32 18 17 16 15 14 13 12 11 7 PP1V8_S5 1
R2023
83 74 73 72 70 69 65 53 47 42 GND NC
10K
1 C2010

5
5%
0.1UF 1/20W
10% MF
2 16V 2 201 NC
X5R-CERM
0201 U2010
74AUP1G34GX
5

SOT1226
PM_SLP_S0_3V3_L 2 4 PM_SLP_S0_L NOSTUFF
13 IN OUT 35 72 83 89
R2022
NC

1 0
R2001
3

1 2
1

100K 5%
5%
1/20W 1/20W
NC MF MF
0201
2 201
C C

ALL_SYS_PWRGD QUALIFIER & VCCST_PWRGD LEVEL SHIFTER TO 1V

32 18 17 16 15 14 13 12 11 7 PP1V8_S5
83 74 73 72 70 69 65 53 47 42 83 70 69 65 42 17 9 7 5 PP1V_S3
C2009 1 C2007 1
1 WLAN AUDIO SYNC BUFFER
0.1UF
10%
0.1UF
10%
R2094
1K
6

16V 16V
X5R-CERM 2
0201
U2009 X5R-CERM 2
0201 VCC
5%
1/20W 58 57 55 51 48 47 45 44 43 18 PP1V8_G3S
74LVC1G08FZ4 MF 83 76 74 68 62 61 60 59
DFN1410-COMBO U2003 2 201 C2020 1
6 74AUP1G07GF 0.1UF
42 35 IN
SMC_RSMRST_L 2
B
SOT891
10%
4 2 A Y 4 CPU_VCCST_PWRGD 16V
X5R-CERM 2

6
Y OUT 13

83 72 IN
ALL_SYS_PWRGD 1
A 1 1 NC VCC 0201
NC
5 3
R2004 NC NC 5 NC
U2020
1M GND SN74LVC1G126DRYR-M
5%
1/20W LLP
3

MF
NC
2 201 83 18 17 15 13 IN
PLT_RST_L 1 OE

NOSTUFF
34 32 IN
WLAN_AUDIO_SYNC 2 A Y 4 PCH_WLAN_AUDIO_SYNC OUT 12
R2007
0 ALL_SYS_PWRGD_R OUT 65 69
1
R2020
B 1 2
100K
GND NC
B

5
5% 5%
1/20W 1/20W
MF MF
0201
2 201 NC

NOSTUFF
R2021
1
0 2
5%
1/20W
MF
0201
TPs for Chipset Debug Pins
P2MM
SM
5 IN
TEST_CPU_D34 1
PP
PP2001
P2MM
SM
5 IN
TEST_CPU_BJ34 1
PP
PP2002
P2MM
SM
5 IN
TEST_CPU_A35 1
PP
PP2003
P2MM
SM
5 IN
TEST_CPU_F37 1
PP
PP2004
P2MM
SM
5 IN
TEST_CPU_BJ36 1
PP
PP2005
P2MM
SM
A 5 IN
TEST_CPU_F34 1
PP
PP2006 SYNC_MASTER= SYNC_DATE=
A
P2MM PAGE TITLE
SM
5 IN
TEST_CPU_CN36 1
PP
PP2007 CHIPSET SUPPORT 2
DRAWING NUMBER SIZE
P2MM
TEST_NOA_N_10 1
SM 051-05309 D
4 IN PP
PP2008 Apple Inc. REVISION
P2MM
SM
5.1.0
4 IN
TEST_NOA_N_11 1
PP NOTICE OF PROPRIETARY PROPERTY: BRANCH
PP2009
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 18 OF 98
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 8 7 6 5 4 3 2 1

D D

CPU-Based Margining

PP1V2_S3
VRef Dividers 20 21 22 23 50 73 74 83 88

1
R2221
8.2K
1%
1/20W
MF
R2223 2 201
CPU_DIMMA_VREFDQ 1
10 2 PP0V6_S3_MEM_VREFDQ_A
6 IN 20 21

1% PLACE_NEAR=R2221.2:1mm
1/20W
1
MF
201 R2222
8.2K
1%
1/20W
1 C2220 MF
201 2
0.022UF
10%
C 2 6.3V
X5R-CERM
0201 R2220
C
24.9 1
MEM_VREFDQ_A_RC 1 2 R2241
1%
8.2K
1%
1/20W 1/20W
MF MF
201
R2243 2 201
CPU_DIMMB_VREFDQ 1
10 2 PP0V6_S3_MEM_VREFDQ_B
6 IN 22 23

1% PLACE_NEAR=R2241.2:1mm
1/20W
1
MF
201 R2242
8.2K
1%
1/20W
1 C2240 MF
201 2
0.022UF
10%
2 6.3V
X5R-CERM
0201 R2240 1
MEM_VREFDQ_B_RC 1
24.9 2 R2261
1%
8.2K
1%
1/20W 1/20W
MF MF
201
R2263 2 201
CPU_DIMM_VREFCA 1
5.1 2 PP0V6_S3_MEM_VREFCA_A
6 IN 20 21 22 23

1% PLACE_NEAR=R2261.2:1mm
1/20W
1
NOTE: CPU has single output for VREFCA.
MF
0201 R2262
8.2K
VREFCA. Connected to 4 DRAMs. 1%
1/20W
1 C2260 MF
201 2
0.022UF
10%
2 6.3V
X5R-CERM
0201 R2260
B MEM_VREFCA_RC 1
24.9 2
B
1%
1/20W
MF
201

A SYNC_MASTER= SYNC_DATE= A
PAGE TITLE

LPDDR3 VREF MARGINING

DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
22 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 19 OF 98

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D
LPDDR3 CHANNEL A (0-31) D

U2300 U2300
LPDDR3-1600-32GB LPDDR3-1600-32GB
EDFB232A1MA EDFB232A1MA
24 6 MEM_A_CAA<0> R2 CA0 FBGA DQ0 P9 MEM_A_DQ<15> 6 88 83 51 23 22 21 20 PP1V8_S3_MEM A3 FBGA B2
IN BI
SYM 1 OF 2 SYM 2 OF 2
24 6 IN
MEM_A_CAA<1> P2 CA1 DQ1 N9 MEM_A_DQ<14> BI 6
A4 B5
24 6 IN
MEM_A_CAA<2> N2 CA2 DQ2 N10 MEM_A_DQ<9> BI 6
A5 C5
24 6 IN
MEM_A_CAA<3> N3 CA3 DQ3 N11 MEM_A_DQ<12> BI 6
A6 E4
24 6 IN
MEM_A_CAA<4> M3 CA4 DQ4 M8 MEM_A_DQ<11> BI 6
A10
VDD1
E5
24 6 IN
MEM_A_CAA<5> F3 CA5 DQ5 M9 MEM_A_DQ<10> BI 6
U3 F5
24 6 IN
MEM_A_CAA<6> E3 CA6 DQ6 M10 MEM_A_DQ<13> BI 6
U4 J12
24 6 IN
MEM_A_CAA<7> E2 CA7 DQ7 M11 MEM_A_DQ<8> BI 6
U5 K2
24 6 IN
MEM_A_CAA<8> D2 CA8 DQ8 F11 MEM_A_DQ<32> BI 6
U6 L6
24 6 IN
MEM_A_CAA<9> C2 CA9 DQ9 F10 MEM_A_DQ<37> BI 6
U10
VSS
M5
DQ10 F9 MEM_A_DQ<34> BI 6 N4
24 6 IN
MEM_A_CKE<0> K3 CKE0 OMIT_TABLE DQ11 F8 MEM_A_DQ<33> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A8 OMIT_TABLE N5
24 6 IN
MEM_A_CKE<1> K4 CKE1 CRITICAL DQ12 E11 MEM_A_DQ<36> BI 6
A9 CRITICAL R4
DQ13 E10 MEM_A_DQ<35> BI 6
D4 R5
24 6 IN
MEM_A_CLK_P<0> J3 CK_T DQ14 E9 MEM_A_DQ<38> BI 6
D5 T2
MEM_A_CLK_N<0> J2 CK_C DQ15 D9 MEM_A_DQ<39> D6 T3
C 24 6 IN
DQ16 T8 MEM_A_DQ<4>
BI

BI
6

6
G5 T4 C
24 21 6 IN
MEM_A_CS_L<0> L3 CS0* DQ17 T9 MEM_A_DQ<5> BI 6
H5 T5
24 21 6 IN
MEM_A_CS_L<1> L4 CS1* DQ18 T10 MEM_A_DQ<7> BI 6
H6 H2
DQ19 T11 MEM_A_DQ<3> 6 H12 VDD2
BI
L8 DM0 DQ20 R8 MEM_A_DQ<0> BI 6 J5 C3
G8 DM1 DQ21 R9 MEM_A_DQ<1> BI 6 J6 D3
P8 DM2 DQ22 R10 MEM_A_DQ<6> BI 6 K5 F4
D8 DM3 DQ23 R11 MEM_A_DQ<2> BI 6 K6 G3
DQ24 C11 MEM_A_DQ<40> 6 K12 VSSCA G4
BI
24 21 6 IN
MEM_A_ODT<0> J8 ODT DQ25 C10 MEM_A_DQ<41> BI 6 L5 P3
DQ26 C9 MEM_A_DQ<47> BI 6 P4 M4
MEM_A_ZQ<0> B3 ZQ0 DQ27 C8 MEM_A_DQ<42> BI 6 P5 J4
MEM_A_ZQ<1> B4 ZQ1 DQ28 B11 MEM_A_DQ<44> BI 6 P6
DQ29 B10 MEM_A_DQ<45> BI 6 U8 B6
R2300 1 R2301 1 23 22 21 19 PP0V6_S3_MEM_VREFCA_A H4 VREFCA DQ30 B9 MEM_A_DQ<43> BI 6 U9 B12
243 243 PP0V6_S3_MEM_VREFDQ_A J11 B8 MEM_A_DQ<46> C6
1% 1% 21 19 VREFDQ DQ31 BI 6
1/20W 1/20W
MF MF 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 F2 D12
201 2 201 2 A1 DQS0_C L11 MEM_A_DQS_N<1> 6 G2 E6
C2340 1 1 C2341 NC
A2 DQS1_C G11 MEM_A_DQS_N<4>
BI
H3 F6
0.047UF 0.047UF NC BI 6
VDDCA
10%
6.3V 2
10% A12 DQS2_C P11 MEM_A_DQS_N<0> 6 L2 F12
2 6.3V NC BI
X5R X5R A13 DQS3_C D11 MEM_A_DQS_N<5> 6 M2 G6
201 201 NC BI
B1 G9
NC VSSQ
NC
B13 DQS0_T L10 MEM_A_DQS_P<1> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A11 H10

NC
T1
NU DQS1_T G10 MEM_A_DQS_P<4> BI 6 C12 K10

NC
T13 DQS2_T P10 MEM_A_DQS_P<0> BI 6 E8 L9

NC
U1 DQS3_T D10 MEM_A_DQS_P<5> BI 6 E12 M6
B NC
U2 G12 M12 B
U12 C4 H8 N6
NC NC
U13 K9 H9 P12
NC NC NC
R3 H11 R6
NC
J9 VDDQ T6
J10 T12
88 83 74 73 50 23 22 21 20 19 PP1V2_S3 K8
K11
1 C2300 1 C2301 1 C2302 1 C2303 1 C2304 1 C2305 1 C2306 1 C2307 L12
0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF 10UF N8
10% 10% 20% 20% 20% 20% 20% 20%
2 16V
X5R-CERM 2 16V
X5R-CERM 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
N12
0201 0201 0201 0201 0201 0201 0402-7 0402-7 R12
U11

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
1 C2320 1 C2321 1 C2322 1 C2323 1 C2324
1UF 1UF 1UF 10UF 10UF
20% 20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0201 0201 0402-7 0402-7

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
PLACEMENT_NOTE:
1 C2310 1 C2311 1 C2312
1UF 1UF 10UF
A 20%
2 10V
X5R
20%
2 10V
X5R
20%
2 10V
X5R-CERM
10uF caps are shared between DRAM.
SYNC_MASTER= SYNC_DATE= A
0201 0201 0402-7 Distribute evenly. PAGE TITLE

LPDDR3 DRAM Channel A (00-31)

DRAWING NUMBER SIZE

88 83 51 23 22 21 20 PP1V8_S3_MEM 051-05309 D
Apple Inc. REVISION
1 C2330 1 C2331 1 C2332 1 C2333 5.1.0
1UF 1UF 10UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
0201 0201 0402-7 0402-7 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
23 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM IV ALL RIGHTS RESERVED 20 OF 98

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 8 7 6 5 4 3 2 1

D
LPDDR3 CHANNEL A (32-63) D

U2400 U2400
LPDDR3-1600-32GB LPDDR3-1600-32GB
EDFB232A1MA EDFB232A1MA
24 6 MEM_A_CAB<0> R2 CA0 FBGA DQ0 P9 MEM_A_DQ<48> 6 88 83 51 23 22 21 20 PP1V8_S3_MEM A3 FBGA B2
IN BI
SYM 1 OF 2 SYM 2 OF 2
24 6 IN
MEM_A_CAB<1> P2 CA1 DQ1 N9 MEM_A_DQ<51> BI 6
A4 B5
24 6 IN
MEM_A_CAB<2> N2 CA2 DQ2 N10 MEM_A_DQ<50> BI 6
A5 C5
24 6 IN
MEM_A_CAB<3> N3 CA3 DQ3 N11 MEM_A_DQ<55> BI 6
A6 E4
24 6 IN
MEM_A_CAB<4> M3 CA4 DQ4 M8 MEM_A_DQ<52> BI 6
A10
VDD1
E5
24 6 IN
MEM_A_CAB<5> F3 CA5 DQ5 M9 MEM_A_DQ<53> BI 6
U3 F5
24 6 IN
MEM_A_CAB<6> E3 CA6 DQ6 M10 MEM_A_DQ<54> BI 6
U4 J12
24 6 IN
MEM_A_CAB<7> E2 CA7 DQ7 M11 MEM_A_DQ<49> BI 6
U5 K2
24 6 IN
MEM_A_CAB<8> D2 CA8 DQ8 F11 MEM_A_DQ<22> BI 6
U6 L6
24 6 IN
MEM_A_CAB<9> C2 CA9 DQ9 F10 MEM_A_DQ<18> BI 6
U10
VSS
M5
DQ10 F9 MEM_A_DQ<21> BI 6 N4
24 6 IN
MEM_A_CKE<2> K3 CKE0 OMIT_TABLE DQ11 F8 MEM_A_DQ<17> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A8 OMIT_TABLE N5
24 6 IN
MEM_A_CKE<3> K4 CKE1 CRITICAL DQ12 E11 MEM_A_DQ<20> BI 6
A9 CRITICAL R4
DQ13 E10 MEM_A_DQ<23> BI 6
D4 R5
24 6 IN
MEM_A_CLK_P<1> J3 CK_T DQ14 E9 MEM_A_DQ<19> BI 6
D5 T2
MEM_A_CLK_N<1> J2 CK_C DQ15 D9 MEM_A_DQ<16> D6 T3
C 24 6 IN
DQ16 T8 MEM_A_DQ<59>
BI

BI
6

6
G5 T4 C
24 20 6 IN
MEM_A_CS_L<0> L3 CS0* DQ17 T9 MEM_A_DQ<63> BI 6 H5 T5
24 20 6 IN
MEM_A_CS_L<1> L4 CS1* DQ18 T10 MEM_A_DQ<57> BI 6 H6 H2
DQ19 T11 MEM_A_DQ<56> 6 H12 VDD2
BI
L8 DM0 DQ20 R8 MEM_A_DQ<58> BI 6 J5 C3
G8 DM1 DQ21 R9 MEM_A_DQ<62> BI 6 J6 D3
P8 DM2 DQ22 R10 MEM_A_DQ<61> BI 6 K5 F4
D8 DM3 DQ23 R11 MEM_A_DQ<60> BI 6 K6 G3
DQ24 C11 MEM_A_DQ<27> 6 K12 VSSCA G4
BI
24 20 6 IN
MEM_A_ODT<0> J8 ODT DQ25 C10 MEM_A_DQ<31> BI 6 L5 P3
DQ26 C9 MEM_A_DQ<29> BI 6 P4 M4
MEM_A_ZQ<2> B3 ZQ0 DQ27 C8 MEM_A_DQ<25> BI 6 P5 J4
MEM_A_ZQ<3> B4 ZQ1 DQ28 B11 MEM_A_DQ<30> BI 6 P6
DQ29 B10 MEM_A_DQ<26> BI 6 U8 B6
R2400 1 R2401 1 23 22 20 19 PP0V6_S3_MEM_VREFCA_A H4 VREFCA DQ30 B9 MEM_A_DQ<28> BI 6 U9 B12
243 243 PP0V6_S3_MEM_VREFDQ_A J11 B8 MEM_A_DQ<24> C6
1% 1% 20 19 VREFDQ DQ31 BI 6
1/20W 1/20W
MF MF 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 F2 D12
201 2 201 2 A1 DQS0_C L11 MEM_A_DQS_N<6> 6 G2 E6
C2440 1 1 C2441 NC
A2 DQS1_C G11 MEM_A_DQS_N<2>
BI
H3 F6
0.047UF 0.047UF NC BI 6
VDDCA
10% 10% A12 DQS2_C P11 MEM_A_DQS_N<7> 6 L2 F12
6.3V 2 2 6.3V NC BI
X5R X5R A13 DQS3_C D11 MEM_A_DQS_N<3> 6 M2 G6
201 201 NC BI
B1 G9
NC VSSQ
NC
B13 DQS0_T L10 MEM_A_DQS_P<6> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A11 H10

NC
T1
NU DQS1_T G10 MEM_A_DQS_P<2> BI 6 C12 K10

NC
T13 DQS2_T P10 MEM_A_DQS_P<7> BI 6 E8 L9

NC
U1 DQS3_T D10 MEM_A_DQS_P<3> BI 6 E12 M6
B NC
U2 G12 M12 B
U12 C4 H8 N6
NC NC
U13 K9 H9 P12
NC NC NC
R3 H11 R6
NC
J9 VDDQ T6
J10 T12
88 83 74 73 50 23 22 21 20 19 PP1V2_S3 K8
K11
1 C2400 1 C2401 1 C2402 1 C2403 1 C2404 1 C2405 1 C2406 1 C2407 L12
0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF 10UF N8
10% 10% 20% 20% 20% 20% 20% 20%
2 16V
X5R-CERM 2 16V
X5R-CERM 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
N12
0201 0201 0201 0201 0201 0201 0402-7 0402-7 R12
U11

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
1 C2420 1 C2421 1 C2422 1 C2423 1 C2424
1UF 1UF 1UF 10UF 10UF
20% 20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0201 0201 0402-7 0402-7

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
PLACEMENT_NOTE:
1 C2410 1 C2411 1 C2412
1UF 1UF 10UF
A 20%
2 10V
X5R
20%
2 10V
X5R
20%
2 10V
X5R-CERM
10uF caps are shared between DRAM.
SYNC_MASTER= SYNC_DATE= A
0201 0201 0402-7 Distribute evenly. PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

DRAWING NUMBER SIZE

88 83 51 23 22 21 20 PP1V8_S3_MEM 051-05309 D
Apple Inc. REVISION
1 C2430 1 C2431 1 C2432 1 C2433 5.1.0
1UF 1UF 10UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
0201 0201 0402-7 0402-7 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
24 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM IV ALL RIGHTS RESERVED 21 OF 98

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 8 7 6 5 4 3 2 1

D
LPDDR3 CHANNEL B (0-31) D

U2500 U2500
LPDDR3-1600-32GB LPDDR3-1600-32GB
EDFB232A1MA EDFB232A1MA
24 6 MEM_B_CAA<0> R2 CA0 FBGA DQ0 P9 MEM_B_DQ<7> 6 88 83 51 23 22 21 20 PP1V8_S3_MEM A3 FBGA B2
IN BI
SYM 1 OF 2 SYM 2 OF 2
24 6 IN
MEM_B_CAA<1> P2 CA1 DQ1 N9 MEM_B_DQ<2> BI 6
A4 B5
24 6 IN
MEM_B_CAA<2> N2 CA2 DQ2 N10 MEM_B_DQ<6> BI 6
A5 C5
24 6 IN
MEM_B_CAA<3> N3 CA3 DQ3 N11 MEM_B_DQ<3> BI 6
A6 E4
24 6 IN
MEM_B_CAA<4> M3 CA4 DQ4 M8 MEM_B_DQ<4> BI 6
A10
VDD1
E5
24 6 IN
MEM_B_CAA<5> F3 CA5 DQ5 M9 MEM_B_DQ<5> BI 6
U3 F5
24 6 IN
MEM_B_CAA<6> E3 CA6 DQ6 M10 MEM_B_DQ<0> BI 6
U4 J12
24 6 IN
MEM_B_CAA<7> E2 CA7 DQ7 M11 MEM_B_DQ<1> BI 6
U5 K2
24 6 IN
MEM_B_CAA<8> D2 CA8 DQ8 F11 MEM_B_DQ<39> BI 6
U6 L6
24 6 IN
MEM_B_CAA<9> C2 CA9 DQ9 F10 MEM_B_DQ<33> BI 6
U10
VSS
M5
DQ10 F9 MEM_B_DQ<32> BI 6 N4
24 6 IN
MEM_B_CKE<0> K3 CKE0 OMIT_TABLE DQ11 F8 MEM_B_DQ<36> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A8 OMIT_TABLE N5
24 6 IN
MEM_B_CKE<1> K4 CKE1 CRITICAL DQ12 E11 MEM_B_DQ<34> BI 6
A9 CRITICAL R4
DQ13 E10 MEM_B_DQ<35> BI 6
D4 R5
24 6 IN
MEM_B_CLK_P<0> J3 CK_T DQ14 E9 MEM_B_DQ<38> BI 6
D5 T2
MEM_B_CLK_N<0> J2 CK_C DQ15 D9 MEM_B_DQ<37> D6 T3
C 24 6 IN
DQ16 T8 MEM_B_DQ<8>
BI

BI
6

6
G5 T4 C
24 23 6 IN
MEM_B_CS_L<0> L3 CS0* DQ17 T9 MEM_B_DQ<13> BI 6 H5 T5
24 23 6 IN
MEM_B_CS_L<1> L4 CS1* DQ18 T10 MEM_B_DQ<15> BI 6 H6 H2
DQ19 T11 MEM_B_DQ<10> 6 H12 VDD2
BI
L8 DM0 DQ20 R8 MEM_B_DQ<9> BI 6 J5 C3
G8 DM1 DQ21 R9 MEM_B_DQ<12> BI 6 J6 D3
P8 DM2 DQ22 R10 MEM_B_DQ<14> BI 6 K5 F4
D8 DM3 DQ23 R11 MEM_B_DQ<11> BI 6 K6 G3
DQ24 C11 MEM_B_DQ<40> 6 K12 VSSCA G4
BI
24 23 6 IN
MEM_B_ODT<0> J8 ODT DQ25 C10 MEM_B_DQ<44> BI 6 L5 P3
DQ26 C9 MEM_B_DQ<42> BI 6 P4 M4
MEM_B_ZQ<0> B3 ZQ0 DQ27 C8 MEM_B_DQ<43> BI 6 P5 J4
MEM_B_ZQ<1> B4 ZQ1 DQ28 B11 MEM_B_DQ<45> BI 6 P6
DQ29 B10 MEM_B_DQ<47> BI 6 U8 B6
R2500 1 R2501 1 23 21 20 19 PP0V6_S3_MEM_VREFCA_A H4 VREFCA DQ30 B9 MEM_B_DQ<46> BI 6 U9 B12
243 243 PP0V6_S3_MEM_VREFDQ_B J11 B8 MEM_B_DQ<41> C6
1% 1% 23 19 VREFDQ DQ31 BI 6
1/20W 1/20W
MF MF 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 F2 D12
201 2 201 2 A1 DQS0_C L11 MEM_B_DQS_N<0> 6 G2 E6
C2540 1 1 C2541 NC
A2 DQS1_C G11 MEM_B_DQS_N<4>
BI
H3 F6
0.047UF 0.047UF NC BI 6
VDDCA
10%
6.3V 2
10% A12 DQS2_C P11 MEM_B_DQS_N<1> 6 L2 F12
2 6.3V NC BI
X5R X5R A13 DQS3_C D11 MEM_B_DQS_N<5> 6 M2 G6
201 201 NC BI
B1 G9
NC VSSQ
NC
B13 DQS0_T L10 MEM_B_DQS_P<0> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A11 H10

NC
T1
NU DQS1_T G10 MEM_B_DQS_P<4> BI 6 C12 K10

NC
T13 DQS2_T P10 MEM_B_DQS_P<1> BI 6 E8 L9

NC
U1 DQS3_T D10 MEM_B_DQS_P<5> BI 6 E12 M6
B NC
U2 G12 M12 B
U12 C4 H8 N6
NC NC
U13 K9 H9 P12
NC NC NC
R3 H11 R6
NC
J9 VDDQ T6
J10 T12
88 83 74 73 50 23 22 21 20 19 PP1V2_S3 K8
K11
1 C2500 1 C2501 1 C2502 1 C2503 1 C2504 1 C2505 1 C2506 1 C2507 L12
0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF 10UF N8
10% 10% 20% 20% 20% 20% 20% 20%
2 16V
X5R-CERM 2 16V
X5R-CERM 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
N12
0201 0201 0201 0201 0201 0201 0402-7 0402-7 R12
U11

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
1 C2520 1 C2521 1 C2522 1 C2523 1 C2524
1UF 1UF 1UF 10UF 10UF
20% 20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0201 0201 0402-7 0402-7

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
PLACEMENT_NOTE:
1 C2510 1 C2511 1 C2512
1UF 1UF 10UF
A 20%
2 10V
X5R
20%
2 10V
X5R
20%
2 10V
X5R-CERM
10uF caps are shared between DRAM.
SYNC_MASTER= SYNC_DATE= A
0201 0201 0402-7 Distribute evenly. PAGE TITLE

LPDDR3 DRAM Channel B (00-31)

DRAWING NUMBER SIZE

88 83 51 23 22 21 20 PP1V8_S3_MEM 051-05309 D
Apple Inc. REVISION
1 C2530 1 C2531 1 C2532 1 C2533 5.1.0
1UF 1UF 10UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
0201 0201 0402-7 0402-7 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
25 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM IV ALL RIGHTS RESERVED 22 OF 98

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QQ微信：181806465
 8 7 6 5 4 3 2 1

D
LPDDR3 CHANNEL B (32-63) D

U2600 U2600
LPDDR3-1600-32GB LPDDR3-1600-32GB
EDFB232A1MA EDFB232A1MA
24 6 MEM_B_CAB<0> R2 CA0 FBGA DQ0 P9 MEM_B_DQ<48> 6 88 83 51 23 22 21 20 PP1V8_S3_MEM A3 FBGA B2
IN BI
SYM 1 OF 2 SYM 2 OF 2
24 6 IN
MEM_B_CAB<1> P2 CA1 DQ1 N9 MEM_B_DQ<49> BI 6
A4 B5
24 6 IN
MEM_B_CAB<2> N2 CA2 DQ2 N10 MEM_B_DQ<50> BI 6
A5 C5
24 6 IN
MEM_B_CAB<3> N3 CA3 DQ3 N11 MEM_B_DQ<54> BI 6
A6 E4
24 6 IN
MEM_B_CAB<4> M3 CA4 DQ4 M8 MEM_B_DQ<52> BI 6
A10
VDD1
E5
24 6 IN
MEM_B_CAB<5> F3 CA5 DQ5 M9 MEM_B_DQ<53> BI 6
U3 F5
24 6 IN
MEM_B_CAB<6> E3 CA6 DQ6 M10 MEM_B_DQ<51> BI 6
U4 J12
24 6 IN
MEM_B_CAB<7> E2 CA7 DQ7 M11 MEM_B_DQ<55> BI 6
U5 K2
24 6 IN
MEM_B_CAB<8> D2 CA8 DQ8 F11 MEM_B_DQ<16> BI 6
U6 L6
24 6 IN
MEM_B_CAB<9> C2 CA9 DQ9 F10 MEM_B_DQ<17> BI 6
U10
VSS
M5
DQ10 F9 MEM_B_DQ<22> BI 6 N4
24 6 IN
MEM_B_CKE<2> K3 CKE0 OMIT_TABLE DQ11 F8 MEM_B_DQ<23> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A8 OMIT_TABLE N5
24 6 IN
MEM_B_CKE<3> K4 CKE1 CRITICAL DQ12 E11 MEM_B_DQ<19> BI 6
A9 CRITICAL R4
DQ13 E10 MEM_B_DQ<20> BI 6
D4 R5
24 6 IN
MEM_B_CLK_P<1> J3 CK_T DQ14 E9 MEM_B_DQ<21> BI 6
D5 T2
MEM_B_CLK_N<1> J2 CK_C DQ15 D9 MEM_B_DQ<18> D6 T3
C 24 6 IN
DQ16 T8 MEM_B_DQ<63>
BI

BI
6

6
G5 T4 C
24 22 6 IN
MEM_B_CS_L<0> L3 CS0* DQ17 T9 MEM_B_DQ<62> BI 6 H5 T5
24 22 6 IN
MEM_B_CS_L<1> L4 CS1* DQ18 T10 MEM_B_DQ<59> BI 6 H6 H2
DQ19 T11 MEM_B_DQ<60> 6 H12 VDD2
BI
L8 DM0 DQ20 R8 MEM_B_DQ<58> BI 6 J5 C3
G8 DM1 DQ21 R9 MEM_B_DQ<61> BI 6 J6 D3
P8 DM2 DQ22 R10 MEM_B_DQ<57> BI 6 K5 F4
D8 DM3 DQ23 R11 MEM_B_DQ<56> BI 6 K6 G3
DQ24 C11 MEM_B_DQ<27> 6 K12 VSSCA G4
BI
24 22 6 IN
MEM_B_ODT<0> J8 ODT DQ25 C10 MEM_B_DQ<31> BI 6 L5 P3
DQ26 C9 MEM_B_DQ<28> BI 6 P4 M4
MEM_B_ZQ<2> B3 ZQ0 DQ27 C8 MEM_B_DQ<25> BI 6 P5 J4
MEM_B_ZQ<3> B4 ZQ1 DQ28 B11 MEM_B_DQ<26> BI 6 P6
DQ29 B10 MEM_B_DQ<30> BI 6 U8 B6
R2600 1 R2601 1 22 21 20 19 PP0V6_S3_MEM_VREFCA_A H4 VREFCA DQ30 B9 MEM_B_DQ<29> BI 6 U9 B12
243 243 PP0V6_S3_MEM_VREFDQ_B J11 B8 MEM_B_DQ<24> C6
1% 1% 22 19 VREFDQ DQ31 BI 6
1/20W 1/20W
MF MF 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 F2 D12
201 2 201 2 A1 DQS0_C L11 MEM_B_DQS_N<6> 6 G2 E6
C2640 1 1 C2641 NC
A2 DQS1_C G11 MEM_B_DQS_N<2>
BI
H3 F6
0.047UF 0.047UF NC BI 6
VDDCA
10%
6.3V 2
10% A12 DQS2_C P11 MEM_B_DQS_N<7> 6 L2 F12
2 6.3V NC BI
X5R X5R A13 DQS3_C D11 MEM_B_DQS_N<3> 6 M2 G6
201 201 NC BI
B1 G9
NC VSSQ
NC
B13 DQS0_T L10 MEM_B_DQS_P<6> BI 6 88 83 74 73 50 23 22 21 20 19 PP1V2_S3 A11 H10

NC
T1
NU DQS1_T G10 MEM_B_DQS_P<2> BI 6 C12 K10

NC
T13 DQS2_T P10 MEM_B_DQS_P<7> BI 6 E8 L9

NC
U1 DQS3_T D10 MEM_B_DQS_P<3> BI 6 E12 M6
B NC
U2 G12 M12 B
U12 C4 H8 N6
NC NC
U13 K9 H9 P12
NC NC NC
R3 H11 R6
NC
J9 VDDQ T6
J10 T12
88 83 74 73 50 23 22 21 20 19 PP1V2_S3 K8
K11
1 C2600 1 C2601 1 C2602 1 C2603 1 C2604 1 C2605 1 C2606 1 C2607 L12
0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF 10UF N8
10% 10% 20% 20% 20% 20% 20% 20%
2 16V
X5R-CERM 2 16V
X5R-CERM 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
N12
0201 0201 0201 0201 0201 0201 0402-7 0402-7 R12
U11

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
1 C2620 1 C2621 1 C2622 1 C2623 1 C2624
1UF 1UF 1UF 10UF 10UF
20% 20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0201 0201 0402-7 0402-7

88 83 74 73 50 23 22 21 20 19 PP1V2_S3
PLACEMENT_NOTE:
1 C2610 1 C2611 1 C2612
1UF 1UF 10UF
A 20%
2 10V
X5R
20%
2 10V
X5R
20%
2 10V
X5R-CERM
10uF caps are shared between DRAM.
SYNC_MASTER= SYNC_DATE= A
0201 0201 0402-7 Distribute evenly. PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

88 83 51 23 22 21 20 PP1V8_S3_MEM 051-05309 D
Apple Inc. REVISION
1 C2630 1 C2631 1 C2632 1 C2633 5.1.0
1UF 1UF 10UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R-CERM 2 10V
X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
0201 0201 0402-7 0402-7 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
26 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM IV ALL RIGHTS RESERVED 23 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK D
D 88 83 73 24 PP0V6_S0_DDRVTT 88 83 73 24 PP0V6_S0_DDRVTT

20 6 MEM_A_CAA<9> R2700 68 1 2 22 6 MEM_B_CAA<9> R2740 68 1 2

IN
MEM_A_CAA<8> R2701 68 1 2
1% 1/20W 201 MF 1 C2700 IN
MEM_B_CAA<8> R2741 68 1 2
1% 1/20W 201 MF 1 C2710
20 6 IN
1% 1/20W 201 MF 0.47UF 22 6 IN
1% 1/20W 201 MF 0.47UF
20 6 MEM_A_CAA<6> R2702 68 1 2 20% 22 6 MEM_B_CAA<7> R2742 68 1 2 20%
IN
1% 1/20W 201 MF 2 4V IN
1% 1/20W 201 MF 2 4V
20 6 IN
MEM_A_CAA<7> R2703 68 1 2 CERM-X5R-1
201 22 6 IN MEM_B_CAA<6> R2743 68 1 2 CERM-X5R-1
201
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<5> R2704 68 1 2 22 6 IN MEM_B_CAA<5> R2744 68 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CLK_P<0> R2705 39 1 2 22 6 IN MEM_B_CLK_P<0> R2745 39 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CLK_N<0> R2706 39 1 2 1 C2701 1 C2702 22 6 IN MEM_B_CLK_N<0> R2746 39 1 2 1 C2711 1 C2712
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CKE<1> R2707 82 1 2 0.47UF
20%
0.47UF
20% 22 6 IN MEM_B_CKE<1> R2747 82 1 2 0.47UF
20%
0.47UF
20%
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CKE<0> R2708 82 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1 22 6 IN MEM_B_CKE<0> R2748 82 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<4> R2709 68 1 2 201 201 22 6 IN MEM_B_CAA<4> R2749 68 1 2 201 201
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<3> R2710 68 1 2 22 6 IN MEM_B_CAA<2> R2750 68 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<2> R2711 68 1 2 22 6 IN MEM_B_CAA<3> R2751 68 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<1> R2712 68 1 2 1 C2703 1 C2704 22 6 IN MEM_B_CAA<1> R2752 68 1 2 1 C2713 1 C2714
1% 1/20W 201 MF 1% 1/20W 201 MF
20 6 IN
MEM_A_CAA<0> R2713 68 1 2 0.47UF
20%
0.47UF
20% 22 6 IN MEM_B_CAA<0> R2753 68 1 2 0.47UF
20%
0.47UF
20%
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<9> R2714 68 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1 23 6 IN MEM_B_CAB<9> R2754 68 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<8> R2715 68 1 2 201 201 23 6 IN MEM_B_CAB<8> R2755 68 1 2 201 201
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<6> R2716 68 1 2 23 6 IN MEM_B_CAB<7> R2756 68 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<7> R2717 68 1 2 23 6 IN MEM_B_CAB<6> R2757 68 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<5> R2718 68 1 2 1 C2705 1 C2706 23 6 IN MEM_B_CAB<5> R2758 68 1 2 1 C2715 1 C2716
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CLK_P<1> R2719 39 1 2 0.47UF
20%
0.47UF
20% 23 6 IN MEM_B_CLK_N<1> R2759 39 1 2 0.47UF
20%
0.47UF
20%
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CLK_N<1> R2720 39 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1 23 6 IN MEM_B_CLK_P<1> R2760 39 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CKE<2> R2721 82 1 2 201 201 23 6 IN MEM_B_CKE<2> R2761 82 1 2 201 201
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CKE<3> R2722 82 1 2 23 6 IN MEM_B_CKE<3> R2762 82 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
MEM_A_CAB<4> R2723 68 1 2 MEM_B_CAB<4> R2763 68 1 2
C 21 6

21 6
IN

IN
MEM_A_CAB<2> R2724 68 1 2
1% 1/20W 201 MF 1 C2707 1 C2708
23 6

23 6
IN

IN MEM_B_CAB<2> R2764 68 1 2
1% 1/20W 201 MF 1 C2717 1 C2718 C
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<3> R2725 68 1 2 0.47UF
20%
0.47UF
20% 23 6 IN MEM_B_CAB<3> R2765 68 1 2 0.47UF
20%
0.47UF
20%
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<1> R2726 68 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1 23 6 IN MEM_B_CAB<1> R2766 68 1 2 2 4V
CERM-X5R-1 2 4V
CERM-X5R-1
1% 1/20W 201 MF 1% 1/20W 201 MF
21 6 IN
MEM_A_CAB<0> R2727 68 1 2 201 201 23 6 IN MEM_B_CAB<0> R2767 68 1 2 201 201
1% 1/20W 201 MF 1% 1/20W 201 MF
21 20 6 IN
MEM_A_CS_L<0> R2728 82 1 2 23 22 6 IN MEM_B_CS_L<0> R2768 82 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
21 20 6 IN
MEM_A_CS_L<1> R2729 82 1 2 23 22 6 IN MEM_B_CS_L<1> R2769 82 1 2
1% 1/20W 201 MF 1% 1/20W 201 MF
21 20 6 IN
MEM_A_ODT<0> R2730 82 1 2 1 C2709 23 22 6 IN MEM_B_ODT<0> R2770 82 1 2 1 C2719
1% 1/20W 201 MF 0.47UF 1% 1/20W 201 MF 0.47UF
20% 20%
2 4V
CERM-X5R-1 2 4V
CERM-X5R-1
201 201

CRITICAL CRITICAL
1 C2720 1 C2740
20UF 20UF
20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402 0402

B B

A SYNC_MASTER= SYNC_DATE= A
PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
27 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM IV ALL RIGHTS RESERVED 24 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PP3V3_UPC_XB_LDO 25 27 29

1 C2890
R2891 1 1
R2893 R2892 1 1UF
3.3K 3.3K 3.3K 10% 27 PCIE_TBT_X_R2D_P<0> Y23 PCIE_RX0_P U2800 PCIE_TX0_P V23 PCIE_TBT_X_D2R_C_P<0> 27
1
R2890 5% 5% 5% 2 6.3V
CERM
IN OUT
1/20W 1/20W 1/20W 402 27 IN PCIE_TBT_X_R2D_N<0> Y22 PCIE_RX0_N TITAN-RIDGE-DP PCIE_TX0_N V22 PCIE_TBT_X_D2R_C_N<0> OUT 27
3.3K MF MF MF
CSP

8
5% 201 2 2 201 201 2
1/20W
MF VCC SYM 1 OF 2
2 201 27
PCIE_TBT_X_R2D_P<1> T23 PCIE_RX1_P PCIE_TX1_P P23 PCIE_TBT_X_D2R_C_P<1> 27
U2890 IN
PCIE_TBT_X_R2D_N<1> T22 PCIE_RX1_N OMIT_TABLE PCIE_TX1_N P22 PCIE_TBT_X_D2R_C_N<1>
OUT

8MBIT-3.0V 27 IN OUT 27

W25Q80DVUXIE
CRITICAL D
TBT_X_SPI_CLK 6 DI(IO0) 5 TBT_X_SPI_MOSI
D 27 CLK USON
DO(IO1) 2 TBT_X_SPI_MISO
27

27 27 PCIE_TBT_X_R2D_P<2> M23 PCIE_RX2_P PCIE_TX2_P K23 PCIE_TBT_X_D2R_C_P<2> 27

27 TBT_X_SPI_CS_L 1 CS* IN
PCIE_TBT_X_R2D_N<2>
OUT

OMIT_TABLE 27 IN
M22 PCIE_RX2_N PCIE_TX2_N K22 PCIE_TBT_X_D2R_C_N<2> OUT 27

TBT_X_ROM_WP_L 3 WP*(IO2)

PCIE GEN3
25
CRITICAL
TBT_X_ROM_HOLD_L 7 HOLD*(IO3) PCIE_TBT_X_R2D_P<3>
27 IN
H23 PCIE_RX3_P PCIE_TX3_P F23 PCIE_TBT_X_D2R_C_P<3> OUT 27

GND EPAD 27 IN
PCIE_TBT_X_R2D_N<3> H22 PCIE_RX3_N PCIE_TX3_N F22 PCIE_TBT_X_D2R_C_N<3> OUT 27

9
PLACE_NEAR=U2800.N16:2MM
84 14 PCIE_CLK100M_TBT_X_P V19 PCIE_REFCLK_100_IN_P
R2828 IN
PERST* T4 TBT_X_PCI_RESET_L 15 18
R2851
84 14 IN
PCIE_CLK100M_TBT_X_N T19 PCIE_REFCLK_100_IN_N
IN
1K TBT_X_PCIE_BIAS 3.01K 2
SNK0 AC Coupling 14 OUT
TBT_X_CLKREQ_L 1 2 TBT_X_CLKREQ_R_L Y6 PCIE_CLKREQ* PCIE_RBIAS N16 1
5% 1%
1/20W 1/20W
4 IN
DP_X_SNK0_ML_C_P<0> C2820 1 2
20%
DP_X_SNK0_ML_P<0>
6.3V 0201
25 MF
201 25 DP_X_SNK0_ML_P<0> AC7 DPSNK1_ML0_P
DPSRC_ML0_P AB21 NC_DP_X_SRC_ML_P<0> MF
201
0.22UF X5R DPSRC_ML0_N AC21 NC_DP_X_SRC_ML_N<0>
DP_X_SNK0_ML_N<0> AB7 DPSNK1_ML0_N
4 IN
DP_X_SNK0_ML_C_N<0> C2821 1 2
20%
DP_X_SNK0_ML_N<0>
6.3V 0201
25
25

DPSRC_ML1_P AC19 NC_DP_X_SRC_ML_P<1>

0.22UF X5R 25 DP_X_SNK0_ML_P<1> AB9 DPSNK1_ML1_P
DPSRC_ML1_N AB19 NC_DP_X_SRC_ML_N<1>
DP_X_SNK0_ML_N<1> AC9 DPSNK1_ML1_N
DP_X_SNK0_ML_C_P<1> C2822 1 2 DP_X_SNK0_ML_P<1> 25

SINK PORT 1
4 25
IN
20% 6.3V 0201 DPSRC_ML2_P AB17 NC_DP_X_SRC_ML_P<2>

SOURCE PORT
0.22UF X5R 25 DP_X_SNK0_ML_P<2> AC11 DPSNK1_ML2_P
DPSRC_ML2_N AC17 NC_DP_X_SRC_ML_N<2>
4 IN
DP_X_SNK0_ML_C_N<1> C2823 1 2
20%
DP_X_SNK0_ML_N<1>
6.3V 0201
25 25 DP_X_SNK0_ML_N<2> AB11 DPSNK1_ML2_N
0.22UF X5R DPSRC_ML3_P AC15 NC_DP_X_SRC_ML_P<3>
25 DP_X_SNK0_ML_P<3> AB13 DPSNK1_ML3_P
DPSRC_ML3_N AB15 NC_DP_X_SRC_ML_N<3>
4 IN
DP_X_SNK0_ML_C_P<2> C2824 1 2
20%
DP_X_SNK0_ML_P<2>
6.3V 0201
25 25 DP_X_SNK0_ML_N<3> AC13 DPSNK1_ML3_N
0.22UF X5R DPSRC_AUX_P N4 NC_DP_X_SRC_AUX_P
DP_X_SNK0_AUXCH_P N1 DPSNK1_AUX_P
4 IN
DP_X_SNK0_ML_C_N<2> C2825 1 2
20%
DP_X_SNK0_ML_N<2>
6.3V 0201
25
25

25 DP_X_SNK0_AUXCH_N N2 DPSNK1_AUX_N
DPSRC_AUX_N N5 NC_DP_X_SRC_AUX_N PP3V3_UPC_XB_LDO 25 27 29

0.22UF X5R
C 4 OUT DP_X_SNK0_HPD AA2 SNK1_HPD DPSRC_HPD R5 DP_X_SRC_HPD 27 C
4 DP_X_SNK0_ML_C_P<3> C2826 1 2 DP_X_SNK0_ML_P<3> 25 25 DP_X_SNK1_ML_P<0> A5 DPSNK2_ML0_P W1
IN
0.22UF 20%
X5R
6.3V 0201 R2830 1 25 DP_X_SNK1_ML_N<0> B5 DPSNK2_ML0_N
GPIO_0
W2
TBT_X_HDMI_DDC_DATA OUT 27
PP3V3_TBT_X_SX 25 26 28 29 74
100K GPIO_1 TBT_X_HDMI_DDC_CLK
4 IN
DP_X_SNK0_ML_C_N<3> C2827 1 2
20%
DP_X_SNK0_ML_N<3>
6.3V 0201
25 5%
1/20W 25 DP_X_SNK1_ML_P<1> B3 DPSNK2_ML1_P EE_WP* W4 TBT_X_ROM_WP_L
OUT
25
27

0.22UF

LC GPIO
X5R MF
TBT_X_TMU_CLK_OUT 1 1
DP_X_SNK1_ML_N<1> A3 Y1 1

SINK PORT 2
201 2 25 DPSNK2_ML1_N TMU_CLKOUT 25 R2834 R2835 R2810
WAKE* Y2 TBT_WAKE_3V3_L 2.2K 2.2K 100K
4 BI
DP_X_SNK0_AUXCH_C_P C2828 1 2
20%
DP_X_SNK0_AUXCH_P
6.3V 0201
25 25 DP_X_SNK1_ML_P<2> C2 DPSNK2_ML2_P
CIO_PLUG_EVENT* AA1 TBT_X_PLUG_EVENT_L
OUT 27

15
5%
1/20W
5%
1/20W
5%
1/20W
0.22UF X5R 25 DP_X_SNK1_ML_N<2> C1 DPSNK2_ML2_N W6 TBT_X_TMU_CLK_IN
OUT
MF MF MF
TMU_CLKIN 2 201 2 201 2 201
4 BI
DP_X_SNK0_AUXCH_C_N C2829 1 2
20%
DP_X_SNK0_AUXCH_N
6.3V 0201
25
25 DP_X_SNK1_ML_P<3> E2 DPSNK2_ML3_P
25

0.22UF X5R I2C_SCL V2 I2C_TBT_X_SCL 27 28

25 DP_X_SNK1_ML_N<3> E1 DPSNK2_ML3_N V1
BI 29
I2C_SDA I2C_TBT_X_SDA 27 28 29
SNK1 AC Coupling 25 DP_X_SNK1_AUXCH_P P1 DPSNK2_AUX_P USB_FORCE_PWR V5 TBT_X_USB_PWR_EN 12 28 29
BI

POC GPIO
IN
V4 PU at PCH
DP_X_SNK1_AUXCH_N P2 DPSNK2_AUX_N FORCE_PWR TBT_X_CIO_PWR_EN
4 IN
DP_X_SNK1_ML_C_P<0> C2830 1 2
20%
DP_X_SNK1_ML_P<0>
6.3V 0201
25
4
25
DP_X_SNK1_HPD Y4 SNK2_HPD BATLOW* U2 TBT_X_BATLOW_L 25
IN 12 28 29

0.22UF X5R
OUT
U1
SLP_S3* PM_SLP_S3_L
4 IN
DP_X_SNK1_ML_C_N<0> C2831 1 2
20%
DP_X_SNK1_ML_N<0>
6.3V 0201
25 R2831 1 NC
AC5 U0_SSTXP1
RTD3_PWR_EN T5 TBT_X_RTD3_PWR_EN
IN 12 13 15 83 89

0.22UF X5R 100K AB5 U0_SSTXN1

USBSS
5% NC
1/20W AC3 U0_SSRXP1 RESET* E5 USBC_X_RESET_L
4 IN
DP_X_SNK1_ML_C_P<1> C2832 1 2
20%
DP_X_SNK1_ML_P<1>
6.3V 0201
25 MF
201 2
NC
AB3 U0_SSRXN1
IN 29

0.22UF X5R NC XTAL_25_IN D22 TBT_X_XTAL25M_IN IN 27

4 IN
DP_X_SNK1_ML_C_N<1> C2833 1 2
20%
DP_X_SNK1_ML_N<1>
6.3V 0201
25 12 IN
JTAG_ISP_TDI W20 TDI XTAL_25_OUT D23 TBT_X_XTAL25M_OUT OUT 27

0.22UF X5R 12 JTAG_TBT_X_TMS Y20 TMS

IN
EE_DI Y18 UPC_X_SPI_MOSI 27
JTAG_ISP_TCK W19 TCK
DP_X_SNK1_ML_C_P<2> C2834 1 2 DP_X_SNK1_ML_P<2> 12 IN
EE_DO W16 UPC_X_SPI_MISO

FLASH
4 25 27

JTAG
IN
20% 6.3V 0201 12 JTAG_ISP_TDO Y19 TDO
0.22UF X5R
OUT
EE_CS* W18 UPC_X_SPI_CS_L 27 To SPI Flash
4 IN
DP_X_SNK1_ML_C_N<2> C2835 1 2
20%
DP_X_SNK1_ML_N<2>
6.3V 0201
25 TBT_X_TEST_EN R4 TEST_EN EE_CLK Y16 UPC_X_SPI_CLK 27

0.22UF X5R TBT_X_TEST_PWR_GOOD W5 TEST_PWR_GOOD

1
R2825
B 4 IN
DP_X_SNK1_ML_C_P<3> C2836 1 2
20%
DP_X_SNK1_ML_P<3>
6.3V 0201
25
5%
100 1
R2829 IN
USBC_XA_D2R_P<2> A15 ASSRXP2 BSSRXp2 B7 USBC_XB_D2R_P<2> IN 30
B
0.22UF X5R 1/20W 100 30 IN
USBC_XA_D2R_N<2> B15 ASSRXN2 BSSRXn2 A7 USBC_XB_D2R_N<2> IN 30
MF 5%
4 IN
DP_X_SNK1_ML_C_N<3> C2837 1 2
20%
DP_X_SNK1_ML_N<3>
6.3V 0201
25
2 201 1/20W
MF 30 USBC_XA_R2D_CR_P<2> A17 ASSTXP2 BSSTXp2 A9 USBC_XB_R2D_CR_P<2> 30
0.22UF X5R 2 201
OUT
B17 B9
OUT
30 OUT USBC_XA_R2D_CR_N<2> ASSTXN2 BSSTXn2 USBC_XB_R2D_CR_N<2> OUT 30

4 BI
DP_X_SNK1_AUXCH_C_P C2838 1 2
20%
DP_X_SNK1_AUXCH_P
6.3V 0201
25 30 OUT
USBC_XA_R2D_CR_P<1> A19 ASSTXP1 BSSTXp1 A11 USBC_XB_R2D_CR_P<1> OUT 30

0.22UF X5R 30 OUT

USBC_XA_R2D_CR_N<1> B19 ASSTXN1 BSSTXn1 B11 USBC_XB_R2D_CR_N<1> OUT 30

DP_X_SNK1_AUXCH_C_N C2839 1 2 DP_X_SNK1_AUXCH_N

TBT PORT A

TBT PORT B
4 BI
20% 6.3V 0201
25
30 USBC_XA_D2R_P<1> B21 ASSRXP1 BSSRXp1 A13 USBC_XB_D2R_P<1> 30
0.22UF X5R
IN
USBC_XA_D2R_N<1> A21 B13
IN
30 IN ASSRXN1 BSSRXn1 USBC_XB_D2R_N<1> IN 30

84 28 USBC_XA_AUXLSX1 H4 ASBU1 BSBU1 L4 USBC_XB_AUXLSX1 29 84 PP3V3_TBT_X_SX 25 26 28 29 74

74 29 28 26 25 PP3V3_TBT_X_SX BI
USBC_XA_AUXLSX2 J4 L5 USBC_XB_AUXLSX2
BI
NOSTUFF
NOSTUFF 84 28 BI ASBU2 BSBU2 BI 29 84
1
R2836 1
E20 E19
R2837
NC PA_USB2_D_P PB_USB2_D_P NC 2.2K
2.2K D20 D19 5%
5% NC PA_USB2_D_N PB_USB2_D_N NC 1/20W
1/20W MF
MF T2 T1 2 201
PP3V3_TBT_X_SX 201 2 28 25 IN
DP_XA_HPD PA_HPD PB_HPD DP_XB_HPD IN 25 29
25 26 28 29 74
28 27 IN
I2C_TBT_XA_INT_L M4 PA_I2C_INT PB_I2C_INT M5 I2C_TBT_XB_INT_L IN 27 29

25 TBT_XA_USB2_MXCTL R2 PA_USB2_MXCTL PB_USB2_MXCTL R1 TBT_XB_USB2_MXCTL 25

TBT_XA_USB2_RBIAS H19 PA_USB2_RBIAS PB_USB2_RBIAS F19 TBT_XB_USB2_RBIAS

100K R2864 PLACE_NEAR=U2800.H19:2MM PLACE_NEAR=U2800.F19:2MM
1 2
5% 1/20W MF 201
TBT_X_BATLOW_L 25 R2854 1 1
R2853
200
1% 200
1
10K 2 R2839 1/20W
TBT_X_RBIAS J6 B23 1%
MF RBIAS USB2_ATEST NC 1/20W
5% 1/20W MF 201 201 2 J5 MF
NOSTUFF PU for NVM 1 2 TBT_X_RSENSE RSENSE AB23 2 201
PCIE_ATEST NC
TF 1/20W 4.75K A23
0.5% PA_MONDC D5
1
100K 2 R2863 TBT_X_TMU_CLK_IN R2855 0201 MONDC_SVR
25
A 100K
5% 1/20W MF 201 PLACE_NEAR=U2800.J5:2MM
PLACE_NEAR=U2800.J6:2MM
A1 PB_MONDC
VGA_RES H5
NC SYNC_MASTER= SYNC_DATE=
A
1 2 R2873 TBT_X_TMU_CLK_OUT 25 AC23 PC_MONDC DEBUG
J9
PAGE TITLE

100K
5% 1/20W

R2862
MF 201
AC1 USB_MONDC
ATEST_P
ATEST_N J11
NC USB-C HIGH SPEED 1
1 2 DP_XA_HPD 25 28
NC DRAWING NUMBER SIZE
5% 1/20W MF 201
100K
D4 TEST_EDM THERMDA V8 TBTTHMSNS_D1_P OUT 53 051-05309 D
1 2 R2872 DP_XB_HPD 25 29 L8 USE NEAREST GND BALL Apple Inc. REVISION
5% 1/20W MF 201 FUSE_VQPS_64
100K
(V9) FOR THERM_D_N 5.1.0
1 2 R2860 TBT_XA_USB2_MXCTL 25 NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% 1/20W MF 201
THE INFORMATION CONTAINED HEREIN IS THE
1
100K 2 R2861 TBT_XB_USB2_MXCTL PROPRIETARY PROPERTY OF APPLE INC.
25 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
28 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TBT IV ALL RIGHTS RESERVED 25 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
SOURCED BY INTERNAL SWITCH SOURCED BY
88 26 PP0V9_TBT_X_SVR H11 VCC3P3_LC V6 PP3V3_TBT_X_LC INTERNAL SWITCH
H9 U2800 25 28 29 74
1 C2980 MIN_LINE_WIDTH=0.2000
TITAN-RIDGE-DP
F18 PP3V3_TBT_X_SX 1.0UF MIN_NECK_WIDTH=0.1000
1 C2930 1 C2931 1 C2932 1 C2934 1 C2936 1 C2935 1 C2933 H12
VCC0P9_SVR_PAB_ANA CSP
VCC3P3_SX R6 FROM USB-C PORT
CONTROLLER (UPC) 20% VOLTAGE=3.3V
4UF 4UF 4UF 4UF 4UF 2.2UF 2.2UF H13 2 6.3V
X5R
20% 20% 20% 20% 20% 20% 20% SYM 2 OF 2
2 6.3V 2 6.3V 6.3V
2 CER-X5R 2 6.3V 2 6.3V 2 6.3V 2 6.3V H15 VCC3P3_S0 L6 0201-1
CER-X5R
0201
CER-X5R
0201 0201
CER-X5R
0201
CER-X5R
0201
CER-X5R
0201
CER-X5R
0201 H16 OMIT_TABLE
VOLTAGE=3.449
MIN_LINE_WIDTH=0.2000
1 C2981 1 C2983
VCC3P3A E6 MIN_NECK_WIDTH=0.1000 1.0UF 1.0UF
CRITICAL 20% 20%
T12
G1 1 C2991 C2990 1 C2994 1 C2995 1 2 6.3V
X5R 2 6.3V
X5R
T13 VCC0P9_SVR_PC_ANA 1.0UF 47UF 47UF 0201-1 0201-1
G2 1.0UF 20%
6.3V 2
20% 20%
T15 VCC VCC3P3_SVR 20% 6.3V 6.3V
H2 2 6.3V X5R CER-X5R 2 CER-X5R 2
X5R 0201-1 0603 0603
N6 VCC0P9_SVR_DPAUX_ANA 0201-1
R8
T11 R11
D T9 VCC0P9_SVR_USB_ANA L11
PP3V3_TBT_X_S0 27 51 88 D
E8 VCC0P9_SVR_BRD_SENSE
M8 1 C2975 1 C2976 1 C2977 1 C2978
SOURCED BY INTERNAL SWITCH M13 10UF 10UF 10UF 10UF
20% 20% 20% 20%
PP0V9_TBT_X_PCIE J18 VCC0P9_PCIE R16 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
MIN_LINE_WIDTH=0.2000 R13 0402-4 0402-4 0402-4 0402-4
MIN_NECK_WIDTH=0.1000 L19 BYPASS=U2800.G1:J1:10MM
1 C2968 1 C2964 1 C2965 1 C2966 1 C2967 VOLTAGE=0.9V
M19 VCC0P9_ANA_PCIE_1
J13
10UF 1.0UF 1.0UF 1.0UF 1.0UF VCC0P9_SVR L13
20% 20% 20% 20% 20% PP0V9_TBT_X_SVR 26 88
2 6.3V
CERM-X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
L18 N8 MIN_LINE_WIDTH=0.2000
0402-4 0201-1 0201-1 0201-1 0201-1 M18 N11 MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 M16
VCC0P9_ANA_PCIE_2
N13
1 C2917 1 C2910 1 C2911 1 C2912 1 C2913 1 C2914 1 C2915 1 C2916
VOLTAGE=3.3V 12PF 4UF 4UF 4UF 4UF 4UF 4UF 4UF
SOURCED BY INTERNAL SWITCH T8 5% 20% 20% 20% 20% 20% 20% 20%
PP3V3_TBT_X_ANA E16 VCC3P3_ANA T16 2 25V
NP0-C0G 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R
SOURCED BY INTERNAL SWITCH CRITICAL 0201 0201 0201 0201 0201 0201 0201
PP3V3_TBT_X_ANA_PCIE L16 VCC3P3_ANA_PCIE 0201
PP3V3_TBT_X_ANA_USB2 H18
M11 L2950
1 C2984 1 C2985 MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
VCC3P3_ANA_USB2
L1
0.68UH-20%-6.1A-0.020OHM
1.0UF 1.0UF MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 W11 VR0V9_IND_TBT_X 1 2
20% 20% VOLTAGE=3.3V VOLTAGE=3.3V VSS_ANA L2
2 6.3V
X5R 2 6.3V
X5R Y11 VSS_ANA SWITCH_NODE=TRUE 1210
0201-1 0201-1 1 C2921 Y5 VSS_ANA
SVR_IND K1 DIDT=TRUE 1 C2950 1 C2951 1 C2952
1 C2920 K2 10UF 47UF 47UF INTERNAL SWITCHING VR OUTPUT
1.0UF W12 VSS_ANA 20% 20% 20%
1.0UF 20% 2 25V 2 6.3V 2 6.3V
20% 2 6.3V
X5R
Y12 VSS_ANA J1 X5R-CERM CER-X5R CER-X5R
2 6.3V
X5R 0201-1 Y8 J2
0603 0603 0603
0201-1 VSS_ANA SVR_VSS
SOURCED BY AB4 VSS_ANA H1
INTERNAL SWITCH AC4 VSS_ANA
C23 VCC0P9_LC J8 PP0V9_TBT_X_LC
VSS_ANA H8 MIN_LINE_WIDTH=0.2000
VCC0P9_LVR MIN_NECK_WIDTH=0.1000
C22 VSS_ANA
VCC0P9_LVR_SENSE H6 PP0V9_TBT_X_LVR SOURCED BY INTERNAL SWITCH VOLTAGE=0.945 1 C2982
W13 VSS_ANA 1.0UF
MIN_LINE_WIDTH=0.2000 20%
AB2 VSS_ANA VSS_ANA D13 MIN_NECK_WIDTH=0.1000 2 6.3V
VOLTAGE=0.9V X5R
C D6
W15
VSS_ANA VSS_ANA D15
D16 C2992 1 C2993 1 C2954 1 C2955 1
0201-1
C
VSS_ANA VSS_ANA 1.0UF 1.0UF 10UF 10UF
Y15 VSS_ANA VSS_ANA D18 20% 20% 20% 20%
6.3V 2 6.3V 2 6.3V 6.3V
A4 VSS_ANA VSS_ANA E9 X5R X5R CERM-X5R 2 CERM-X5R 2
0201-1 0201-1 0402-4 0402-4
B4 VSS_ANA VSS_ANA E11
F2 VSS_ANA VSS_ANA E15 2x 10uF outside BGA area
D2 VSS_ANA VSS_ANA A12
F1 VSS_ANA VSS_ANA E22
D1 VSS_ANA VSS_ANA E23
B1 VSS_ANA VSS_ANA F9
B2 VSS_ANA VSS_ANA F20
E18 VSS F16
VSS_ANA VSS_ANA
V11 VSS_ANA VSS_ANA G22
V12 VSS_ANA VSS_ANA G23
V13 VSS_ANA VSS_ANA A14
M6 VSS_ANA VSS_ANA H20
N19 VSS_ANA VSS_ANA J19
N18 VSS_ANA VSS_ANA J20
E12 VSS_ANA VSS_ANA J22
E13 VSS_ANA VSS_ANA A16
F11 VSS_ANA VSS_ANA J23
F12 VSS_ANA VSS_ANA L20 Add XW or alias on ISOLATE GND OF SVR_IND CAPS
F13 VSS_ANA VSS_ANA L22 support page AND GND OF VCC3P3_SVR CAPS
F15 VSS_ANA VSS_ANA L23 FROM SYSTEM GND IN LAYOUT
J16 VSS_ANA VSS_ANA A18 (SEE INTEL LAYOUT GUIDELINES)
A2 VSS_ANA VSS_ANA M20 XW 27 P0V9_TBT_X_SVR_AGND
F8 N20 MIN_LINE_WIDTH=0.0910
B A6
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA N22
MIN_NECK_WIDTH=0.0910
VOLTAGE=0V B
A8 VSS_ANA VSS_ANA N23
B8 VSS_ANA VSS_ANA R18
AB8 VSS_ANA VSS_ANA A20
AB10 VSS_ANA VSS_ANA R19
AB12 VSS_ANA VSS_ANA R20
AB14 VSS_ANA VSS_ANA R22 XW2900
SM
AB16 VSS_ANA VSS_ANA R23
AB18 T20
1 2 TBTTHMSNS_D1_N OUT 53
VSS_ANA VSS_ANA
AB20 VSS_ANA VSS_ANA U23 PLACE_NEAR=U2800.V9:6MM
AB22 VSS_ANA VSS_ANA U22 NO_XNET_CONNECTION=1
AC6 VSS_ANA VSS_ANA A22
AC8 VSS_ANA VSS_ANA V9
B10 VSS_ANA VSS_ANA V15
AC10 VSS_ANA VSS_ANA V20
AC12 VSS_ANA VSS_ANA W8
AC14 VSS_ANA VSS_ANA B6
AC16 VSS_ANA VSS_ANA W9
AC18 VSS_ANA VSS_ANA W22
AC20 VSS_ANA VSS_ANA W23
AC22 VSS_ANA VSS_ANA Y9
B12 VSS_ANA VSS_ANA Y13
B14 VSS_ANA VSS_ANA AA22
B16 VSS_ANA VSS_ANA AA23
B18 VSS_ANA VSS_ANA AB6

A B20
B22
VSS_ANA VSS_ANA E4
J15 SYNC_MASTER= SYNC_DATE=
A
VSS_ANA VSS_ANA PAGE TITLE
D8 AB1
D9
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA AC2 USB-C HIGH SPEED 2
A10 DRAWING NUMBER SIZE
VSS_ANA VSS_ANA F5
D11 F6 051-05309 D
D12
VSS_ANA VSS_ANA
J12
Apple Inc. REVISION
VSS_ANA VSS_ANA
5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
N15
L15
V18
F4
R9
R12
L12
M15
L9
M9
R15
M1
M2
V16
M12
N9
N12
T6
T18

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
29 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TBT IV ALL RIGHTS RESERVED 26 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
USB VBUS Detect USBC_ARKANOID
DEBUG PATHS RIDGE PULL UP/DOWN 100
ARKANOID
R3094 1 2
5%
TBT_X_SPI_ARK_CLK
1/20W MF 201
27

R3081
PP1V8_AWAKE 0
70 62 43 42 40 37
83 72
1 2
PCH USB3 (DCI) XB UPC DBG [3:0] USBC_AARDVARKANOID
15 AARDVARKANOID
5% MF 1/20W 0201
0
PP3V3_TBT_X_S0 26 51 88 R3086 1 2 TBT_X_SPI_DBG_CLK 27

14 USB3_BSSB_D2R_P R3012 1 2 USB3_BSSB_D2R_R_P 29 83 15 5% 1/20W MF 201 USBC_AARDVARKANOID

R3080 OUT
5% 1/20W MF 0201 IN
R3043 1
100K 2 TBT_X_HDMI_DDC_CLK 25
R3087 1 2
5%
TBT_X_SPI_DBG_CS_L
1/20W MF 201 USBC_AARDVARKANOID
27

30K SOC_USB_VBUS R3013 0 5% 1/20W MF 201 15

87 83 30 28 PP20V_USBC_XA_VBUS 1 2 34 83 14 OUT
USB3_BSSB_D2R_N 1 2
5% 1/20W
USB3_BSSB_D2R_R_N
MF 0201 IN 29 83 R3088 1 2
5%
TBT_X_SPI_DBG_MOSI
1/20W MF 201 USBC_AARDVARKANOID
27

<rdar://25149752> NOSTUFF 1/20W

5% I1023 R3044 100K 15
K
D3001 0.1UF
1 2 TBT_X_HDMI_DDC_DATA 25 R3089 1 2 TBT_X_SPI_DBG_MISO 27
MF
USB3_BSSB_R2D_C_P C3010 1 2 USB3_BSSB_R2D_P
5% 1/20W MF 201 5% 1/20W MF 201

D
201
BZT52C3V0LP-COMBO
DFN1006
14 IN
10% 16V X5R-CERM 0201
OUT 29 83
D
A
NOSTUFF 14 USB3_BSSB_R2D_C_N C3011 1 2 0.1UF USB3_BSSB_R2D_N 29 83
ROM 15 XB ACE
IN
10% 16V X5R-CERM 0201
OUT
25 OUT
TBT_X_SPI_CLK R3095 1 2
5%
UPC_XB_SPI_CLK
1/20W MF 201
IN 29

15
25 OUT
TBT_X_SPI_CS_L R3096 1 2
5%
UPC_XB_SPI_CS_L
1/20W MF 201
IN 29

15
Ridge 0.9V SVR XW H9M PLACE_NEAR=U3100.G16:5MM XB UPC DBG [5:4] 25 OUT
TBT_X_SPI_MOSI R3097 1 2
5%
UPC_XB_SPI_MOSI
1/20W MF 201
IN 29

SWD_SOC_DEBUG_SWCLK R3014 1
0 2 SWD_SOC_SWCLK_XB X ACE-SMC I2C SERIES R'S TBT_X_SPI_MISO R3098 1
15 2 UPC_XB_SPI_MISO
XW3001
SHORT-L6-SM
89 28 OUT
5% 1/20W MF 0201 IN 29 83 25 IN
5% 1/20W MF 201
OUT 29

P0V9_TBT_X_SVR_AGND SWD_SOC_DEBUG_SWDIO R3015 1

0 2 SWD_SOC_SWDIO_XB PLACE_NEAR=U3200.B7:7MM
26 1 2 89 28 29 83 CKPLUS_WAIVE=I2C_PULLUP
NO_XNET_CONNECTION=1
BI
PLACE_NEAR=U3100.F15:5MM
5% 1/20W MF 0201 BI
83 47 35 29 I2C_UPC_SDA R3045 1
0 2 I2C_UPC_X_SDA2 27 28 15 TR
5% 1/20W MF 0201
CKPLUS_WAIVE=I2C_PULLUP
R3090 1 2
5%
UPC_X_SPI_CLK
1/20W MF 201
IN 25

R3046 0 15
83 47 35 29 I2C_UPC_SCL 1 2 I2C_UPC_X_SCL2
5% 1/20W MF 0201
27 28 R3091 1 2
5%
UPC_X_SPI_CS_L
1/20W MF 201
IN 25

PLACE_NEAR=U3200.A6:7MM 15
PCH UART 2 PLACE_NEAR=U3100.D15:5MM XA UPC DBG [7:6] R3092 1 2
5%
UPC_X_SPI_MOSI
1/20W MF 201
IN 25

15
DP SRC OPTIONS 83 12 PCH_UART_DEBUG_R2D R3016 1
0 2 PCH_UART_DEBUG_R_R2D 28 FOR LAYOUT PURPOSES: DIRECTLY CONNECT TO XB
R3093 1 2
5%
UPC_X_SPI_MISO
1/20W MF 201
OUT 25
IN OUT
5% 1/20W MF 0201
THEN BRANCH OFF TO XA AND ARKANOID CONNECTOR
PCH_UART_DEBUG_D2R R3017 1
0 2 PCH_UART_DEBUG_R_D2R
R3040 83 12 OUT
5% 1/20W MF 0201 IN 28

DP_X_SRC_HPD 1
100K 2
25
PLACE_NEAR=U3100.D19:5MM
5%
1/20W
MF
USB2 OC
201
R3047
UPC_XA_FAULT_L 1
0 2 UPC_XA_FAULT_L_R
4 28
5% 1/20W MF 0201
TR XTAL
ACE2 PULL DOWNS Ridge PCIE Caps
C R3048
C
25 IN
TBT_X_XTAL25M_OUT
UPC_XB_FAULT_L 1
0 2 UPC_XB_FAULT_L_R
4 29
1 C3002 R3039 1
100K 2 PD_UPC_XA_GPIO4
5% 1/20W MF 0201

CRITICAL 5%
20PF
100K
5% 1/20W MF 201 28
D2R
3

2 25V R3038 1 2 PD_UPC_XB_GPIO1

2 4

5% 1/20W MF 201 29
Y3000 C0G
0201 100K PCIE_TBT_X_D2R_C_P<0> 2 1 C3050 PCIE_TBT_X_D2R_P<0>
25MHZ-25PPM-20PF-50OHM 0201
R3037 1 2 5% 1/20W MF 201 PD_UPC_XB_GPIO4 29
25 IN
0201 X5R 6.3V 20%
OUT 14

0.22UF
1

2.00X1.60-SM 2 C0G R3036 100K

25V
5%
1 2 5% 1/20W MF 201 PD_UPC_XB_GPIO9 29
2 1 C3051
25 PCIE_TBT_X_D2R_C_N<0> PCIE_TBT_X_D2R_N<0> 14
20PF R3035 100K IN OUT

1 C3003 1 2 5% 1/20W MF 201 PD_UPC_XB_GPIO10 29

0201 X5R 6.3V 20% 0.22UF
25 TBT_X_XTAL25M_IN R3034 100K C3052
OUT 1 2 5% 1/20W MF 201 PD_UPC_X_5V_EN 28 29 25 IN
PCIE_TBT_X_D2R_C_P<1> 2 1 PCIE_TBT_X_D2R_P<1> OUT 14

100K 0201 X5R 6.3V 20% 0.22UF

R3033 1 2 5% 1/20W MF 201 SPARE_UPC_XA_USB3_RN 28
86 89
R3032 100K 25 PCIE_TBT_X_D2R_C_N<1> 2 1 C3053 PCIE_TBT_X_D2R_N<1> 14
74 72 71 70
42 40 34 29
64
28 PP1V8_SLPS2R PP3V3_G3H_RTC 63
28
71
29
72
50 1 2 5% 1/20W MF 201 SPARE_UPC_XA_USB3_RP 28
IN
0201 X5R 6.3V 20%
OUT
63 60 47 44
89 86 83
43
81
54
74
57
76
61
83
100K 0.22UF
R3031 1 2 5% 1/20W MF 201 SPARE_UPC_XB_USB3_RN 29
C3054
R3065 PCIE_TBT_X_D2R_C_P<2> 2 1 PCIE_TBT_X_D2R_P<2>
1

25 IN OUT 14
100K R3030 1
100K 2 SPARE_UPC_XB_USB3_RP 0201 X5R 6.3V 20%
5% 1/20W MF 201 29 0.22UF
201 MF
G

1/20W R3029 1
100K 2 5% 1/20W MF 201 SPARE_UPC_XB_USB2_RN PCIE_TBT_X_D2R_C_N<2> 2 1 C3055 PCIE_TBT_X_D2R_N<2>
5% 29 25 IN OUT 14
1

100K 0201 X5R 6.3V 20% 0.22UF

2 3
R3028 1 2 5% 1/20W MF 201 SPARE_UPC_XB_USB2_RP 29
35 TBT_WAKE_L TBT_WAKE_3V3_L 25
C3056
OUT IN
R3027 100K 25 PCIE_TBT_X_D2R_C_P<3> 2 1 PCIE_TBT_X_D2R_P<3> 14
S

SMC HAS IPU 1 2 5% 1/20W MF 201 SPARE_UPC_XA_DBG0_R 28

IN
0201 X5R 6.3V 20%
OUT

100K 0.22UF
R3026 1 2 5% 1/20W MF 201 SPARE_UPC_XA_DBG1_R 28
C3057
Q3001 100K 25 IN
PCIE_TBT_X_D2R_C_N<3> 2 1 PCIE_TBT_X_D2R_N<3> OUT 14

DMN2250UFB R3025 1 2 5% 1/20W MF 201 SPARE_UPC_XA_DBG2_R 28

0201 X5R 6.3V 20% 0.22UF
DFN1006-3 100K
R3024 1 2 5% 1/20W MF 201 SPARE_UPC_XA_DBG3_R 28 R2D
B R3023 1
0 2
NOSTUFF UPC_XA_VDDIO_CFG
B
5% 1/20W MF 0201 28
14 IN
PCIE_TBT_X_R2D_C_P<0> 2 1 C3040 PCIE_TBT_X_R2D_P<0> OUT 25
0 NOSTUFF
RIDGE TBT X ARKANOID CONN R3022 1 2 5% 1/20W MF 0201 UPC_XB_VDDIO_CFG 29
0201 X5R 6.3V 20% 0.22UF
R3021 1
0 2 5% 1/20W MF 0201 UPC_XA_RESET PCIE_TBT_X_R2D_C_N<0> 2 1 C3041 PCIE_TBT_X_R2D_N<0>
28 14 25
NOTE:J3001 IS DELETED DUE 0
IN
0201 X5R 6.3V 20% 0.22UF
OUT

R3020 1 2 5% 1/20W MF 0201 UPC_XB_RESET 29

TO SPACE LIMITATION. 14 IN
PCIE_TBT_X_R2D_C_P<1> 2 1 C3042 PCIE_TBT_X_R2D_P<1> OUT 25
0201 X5R 6.3V 20% 0.22UF
SIGNALS CAN BE CONNECTED AT ICT TP 14 PCIE_TBT_X_R2D_C_N<1> 2 1 C3043 PCIE_TBT_X_R2D_N<1> 25
IN OUT
0201 X5R 6.3V 20% 0.22UF
14 IN
PCIE_TBT_X_R2D_C_P<2> 2 1 C3044 PCIE_TBT_X_R2D_P<2> OUT 25
0201 X5R 6.3V 20% 0.22UF
14 IN
PCIE_TBT_X_R2D_C_N<2> 2 1 C3045 PCIE_TBT_X_R2D_N<2> OUT 25
0201 X5R 6.3V 20% 0.22UF
14 IN
PCIE_TBT_X_R2D_C_P<3> 2 1 C3046 PCIE_TBT_X_R2D_P<3> OUT 25
0201 X5R 6.3V 20% 0.22UF
FUSES FOR UPC
PCIE_TBT_X_R2D_C_N<3> 2 1 C3047 PCIE_TBT_X_R2D_N<3>
AARDVARKANOID CONN F3000
14 IN
0201 X5R 6.3V 20% 0.22UF
OUT 25

6A-32V
ACE2 ARKANOID DEBUG CONN NO 3D BODY PART USED PER <RDAR://48050692>
PPDCIN_G3H 1 2 PPDCIN_XA_G3H_F 28 87

PLACE_NEAR=U3100:5MM
USBC_ARKANOID OMIT_TABLE
C3020 1
0603-1
CRITICAL
0.1UF
10%
J3000 J3002 35V
CER-X5R 2
505070-1222 505070-1222
A 13
M-ST-SM
14 13
SM
14
0201
SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

29 25 I2C_TBT_XB_INT_L 1 2 I2C_TBT_XA_INT_L 25 28 29 25 PP3V3_UPC_XB_LDO 1 2 TBT_X_SPI_DBG_CS_L 27 F3001 USB-C SUPPORT

3 4 740S00053 DRAWING NUMBER SIZE
28 27 I2C_UPC_X_SCL2 I2C_TBT_X_SDA 25 27 28 29 29 UPC_XB_SWD_DATA 3 4 TBT_X_SPI_DBG_CLK 27 6A-32V
I2C_UPC_X_SDA2 5 6 I2C_TBT_X_SCL UPC_XB_SWD_CLK 5 6 TBT_X_SPI_DBG_MOSI 1 2 PPDCIN_XB_G3H_F 051-05309 D
28 27
7 8
25 27 28 29 29 27 29 87 Apple Inc. REVISION
47 35 29 28 UPC_I2C_INT_L UPC_XA_SER_DBG 28 84 27 TBT_X_SPI_DBG_MISO 7 8 UPC_XA_SWD_CLK 28 PLACE_NEAR=U3200:5MM
TBT_X_SPI_ARK_CLK 9 10 UPC_XB_SER_DBG I2C_TBT_X_SDA 9 10 UPC_XA_SWD_DATA C3021 1 0603-1
CRITICAL 5.1.0
27 29 84 29 28 27 25 28
0.1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 28 UPC_XA_UART_TX 11 12 UPC_XA_UART_RX 28 29 29 28 27 25 I2C_TBT_X_SCL 11 12 PP3V3_UPC_XA_LDO 28
10%
35V
CER-X5R 2 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
15 16 15 16
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TBT IV ALL RIGHTS RESERVED 27 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PRIMARY USB-C PORT CONTROLLER (UPC) [FRONT LEFT]

PP20V_USBC_XA_VBUS 27 28 30 83 87

C3101 1
1UF
10%
35V 2
X5R
0402
<CVBUS>
D D
87 28 27 PPDCIN_XA_G3H_F PP3V3_G3H_RTC 27 29 50 54 57 61 63 71 72 74
76 83 86 89
MAX 100UF TOTAL ON RAIL
C3100 1
10UF
20%
6.3V
CERM-X5R 2
0402-1
83 75 68 55 54 52 51 50 46 29
86
PP5V_G3S <CVIN_3V3>
NOSTUFF

L10

N10
K11
L12
M11
N12

N14
M13
K9

M9

G2
G4
H1
H3
J2
J4
K1
K3
L2
L4
M1
M3
N2
N4

G6
G8
H5
H7
J6
J8
K5
K7
L6
L8
M5
M7
N6
N8
1 C3111 PP1V8_SLPS2R 27 29 34 40 42 43 44 47 60 63
64 70 71 72 74 81 83 86 89
2.2UF
20%
2 25V C3102

PP_5V0

PP_CABLE

PP_HV

VBUS
1
X6S-CERM
0402 1.0UF
CRITICAL 20%
6.3V 2
<CPP_5V0> X5R
0201-1
OMIT_TABLE <CVDDIO>

27 UPC_XA_RESET B13 HRESET (LDO_CORE)

U3100 VIN_3V3 C20
IN
TBT_POC_RESET A14 CD3217
29 12 IN MRESET (LDO_3V3)
A12
FCBGA VDDIO
NC_USBC_XA_RESET_L B17 RESET* (LDO_3V3)
VER-2 VDDIO_CFG D11 UPC_XA_VDDIO_CFG 27

84 27 UPC_XA_SER_DBG A2 CRITICAL
OUT
B1 GPIO0 (T.B.D.) C22 PP3V3_UPC_XA_LDO 27 28
LDO_3V3 D21
PMU_ACTIVE_READY D1 GPIO1 (VDDIO)
1 C3108
89 83 72 34 IN
VIN_LV L20 10UF
29 25 12 TBT_X_CIO_PWR_EN F1 GPIO2 (LDO_3V3) 20%
IN
VOUT_LV L18 PP3V3_TBT_X_SX 25 26 29 74 2 6.3V
CERM-X5R
29 27 OUT
PD_UPC_X_5V_EN C2 GPIO3 (LDO_3V3) 0402-1
27 BI
PD_UPC_XA_GPIO4 E2 GPIO4 (LDO_3V3) VRET C16 <CLDO_3V3>
27 UPC_XA_FAULT_L_R B3 GPIO5 (LDO_3V3)
OUT
SS L22 UPC_XA_SS
C 29 25 12 IN
TBT_X_USB_PWR_EN C4 GPIO6 (LDO_3V3) POWER C
83 35 29 OUT
SOC_DOCK_CONNECT D3 GPIO7 (VDDIO, PMOS O/D)
LDO_CORE E22 PP1V5_UPC_XA_LDO_CORE
1 C3109
85 83 72 63 29 OUT
UPC_PMU_RESET E4 GPIO8 (VDDIO) 0.68UF
5%
83 34 IN
SOC_DFU_STATUS F3 GPIO9 (VDDIO) 1 C3105 2 6.3V
X6S
89 83 72 34 SOC_FORCE_DFU F7 GPIO10 (VDDIO) 10UF 0402
OUT 20% <CSS>
2 6.3V
CERM-X5R
28 27 IN
PP3V3_UPC_XA_LDO A18 BUSPOWER (LDO_3V3) 0402-1
M19 <CLDO_CORE>
GND I2C_ADDR I2C_ADDR (LDO_3V3)
M15
PRIMARY ONLY
UPC_XA_R_OSC M21 TYPE-C USBC_XA_CC1 BI 28 30 83
R_OSC (LDO_CORE) C_CC1 N16

R31031 28 I2C_UPC_XA_DBG_CTL_SDA A16 I2CM_SDA_CNFG (LDO_3V3, 4K IPU)

M17 USBC_XA_CC2 28 30 83
15K 28 I2C_UPC_XA_DBG_CTL_SCL B15 I2CM_SCL_CNFG (LDO_3V3, 4K IPU) C_CC2 N18
BI
0.1%
1/20W
TF-LF 29 27 25 BI
I2C_TBT_X_SDA B5 I2C_SDA1 (LDO_3V3)
L14 USBC_XA_CC1
0201 2 RPD_G1 28 30 83
29 27 25 BI
I2C_TBT_X_SCL A4 I2C_SCL1 (LDO_3V3)
RPD_G2 L16 USBC_XA_CC2
BI 1 C3114 1 C3113
27 25 OUT
I2C_TBT_XA_INT_L D7 I2C_IRQ1* (N/A, NMOS O/D)
BI 28 30 83
220PF 220PF
10% 10%
C_USB_TP K19 USBC_XA_USB_TOP_P 30 2 16V 16V
2 CER-X7R
27 I2C_UPC_X_SDA2 B7 I2C_SDA2 (VDDIO)
BI CER-X7R
0201 0201
BI
C_USB_TN K21 USBC_XA_USB_TOP_N 30
TO SMC 27 BI
I2C_UPC_X_SCL2 A6 I2C_SCL2 (VDDIO)
BI

47 35 29 27 OUT
UPC_I2C_INT_L C8 I2C_IRQ2* (N/A, NMOS O/D) C_USB_BP J20 USBC_XA_USB_BOT_P BI 30

B9 C_USB_BN J22 USBC_XA_USB_BOT_N BI 30

SPI_CLK
REAR PORT: B11 SPI_MOSI C_SBU1 J16 USBC_XA_SBU1 BI 30 83
CONNECT UPC SPI TO ROM A10 H15 USBC_XA_SBU2
FRONT PORT: SPI_MISO C_SBU2 BI 30 83
GROUND UPC SPI A8 SPI_SSZ DIGITAL CORE I/O & CONTROL

27 BI
UPC_XA_SWD_DATA E20 SWD_DATA (LDO_3V3)
L3100
90-OHM-0.1A
27 BI
UPC_XA_SWD_CLK E16 SWD_CLK (LDO_3V3)

B EXCX4CE
SYM_VER-1
29 28 27 IN
UPC_XA_UART_RX B19 UART_RX (LDO_3V3) B
14 BI
USB2_UPC_PCH_XA_P 1 4 29 27 OUT
UPC_XA_UART_TX A20 UART_TX (LDO_3V3)
DNU E18
USB2_UPC_PCH_XA_F_P H19 USB_RP1_P C18
DNU
14 USB2_UPC_PCH_XA_N 2 3 USB2_UPC_PCH_XA_F_N H21 USB_RP1_N
BI
DNU F5 PPDCIN_XA_G3H_F 27 28 87
PLACE_NEAR=U3100:5MM 89 83 USB_SOC_TYPEC_P G20 USB_RP2_P
BI
PORT_MUX GND DNU D5 PP20V_USBC_XA_VBUS 27 28 30 83 87
89 83 BI
USB_SOC_TYPEC_N G22 USB_RP2_N D17
DNU
27 BI
SPARE_UPC_XA_USB3_RP F19 USB_RP3_P G18
DNU
27 BI
SPARE_UPC_XA_USB3_RN F21 USB_RP3_N

84 25 BI
USBC_XA_AUXLSX1 J12 AUX_P
84 25 BI
USBC_XA_AUXLSX2 H11 AUX_N

25 OUT
DP_XA_HPD C12 HPD

27 BI
SPARE_UPC_XA_DBG0_R G12 DEBUG0 (T.B.D.)
27 BI
SPARE_UPC_XA_DBG1_R F11 DEBUG1 (T.B.D.)
27 BI
SPARE_UPC_XA_DBG2_R E8 DEBUG2 (T.B.D.)
27 BI
SPARE_UPC_XA_DBG3_R E12 DEBUG3 (T.B.D.)
89 27 OUT
SWD_SOC_DEBUG_SWCLK G16 DEBUG4 (T.B.D.)
89 27 BI
SWD_SOC_DEBUG_SWDIO F15 DEBUG5 (T.B.D.)
27 IN
PCH_UART_DEBUG_R_R2D D15 DEBUG6 (T.B.D.)
27 OUT
PCH_UART_DEBUG_R_D2R D19 DEBUG7 (T.B.D.) GND
PP3V3_UPC_XA_LDO 27 28

A22
H9
N20
B21
K15
N22
A 1
1M 2 R3109 I2C_UPC_XA_DBG_CTL_SCL SYNC_MASTER= SYNC_DATE=
A
28
PAGE TITLE
5% 1/20W MF 201
1
1M 2 R3108 I2C_UPC_XA_DBG_CTL_SDA 28
USB-C PORT CONTROLLER A
5% 1/20W MF 201 DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

1M PROPRIETARY PROPERTY OF APPLE INC.
1 2 R3105 UPC_XA_UART_RX 27 28 29 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
31 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=USB-C IV ALL RIGHTS RESERVED 28 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

SECONDARY USB-C PORT CONTROLLER (UPC) [REAR LEFT]

PP20V_USBC_XB_VBUS 29 30 83 87

C3201 1
1UF
10%
35V 2
X5R
0402
<CVBUS>
D D
87 29 27 PPDCIN_XB_G3H_F PP3V3_G3H_RTC 27 28 50 54 57 61 63 71 72 74
76 83 86 89
MAX 100UF TOTAL ON RAIL
C3200 1
10UF
20%
6.3V
CERM-X5R 2
0402-1
83 75 68 55 54 52 51 50 46 28
86
PP5V_G3S <CVIN_3V3>
NOSTUFF

L10

N10
K11
L12
M11
N12

N14
M13
K9

M9

G2
G4
H1
H3
J2
J4
K1
K3
L2
L4
M1
M3
N2
N4

G6
G8
H5
H7
J6
J8
K5
K7
L6
L8
M5
M7
N6
N8
1 C3211 PP1V8_SLPS2R 27 28 34 40 42 43 44 47 60 63
64 70 71 72 74 81 83 86 89
2.2UF
20%
2 25V C3202

PP_5V0

PP_CABLE

PP_HV

VBUS
1
X6S-CERM
0402 1.0UF
CRITICAL 20%
6.3V 2
<CPP_5V0> X5R
0201-1
OMIT_TABLE <CVDDIO>

27 UPC_XB_RESET B13 HRESET (LDO_CORE)

U3200 VIN_3V3 C20
IN
TBT_POC_RESET A14 CD3217
28 12 IN MRESET (LDO_3V3)
A12
FCBGA VDDIO
25 USBC_X_RESET_L B17 RESET* (LDO_3V3)
OUT
VER-2 VDDIO_CFG D11 UPC_XB_VDDIO_CFG 27

84 27 UPC_XB_SER_DBG A2 CRITICAL
OUT
B1 GPIO0 (T.B.D.) C22 PP3V3_UPC_XB_LDO 25 27 29
LDO_3V3 D21
PD_UPC_XB_GPIO1 D1 GPIO1 (VDDIO)
1 C3208
27 BI
VIN_LV L20 10UF
28 25 12 TBT_X_CIO_PWR_EN F1 GPIO2 (LDO_3V3) 20%
IN
VOUT_LV L18 PP3V3_TBT_X_SX 25 26 28 74 2 6.3V
CERM-X5R
28 27 OUT
PD_UPC_X_5V_EN C2 GPIO3 (LDO_3V3) 0402-1
27 BI
PD_UPC_XB_GPIO4 E2 GPIO4 (LDO_3V3) VRET C16 <CLDO_3V3>
27 UPC_XB_FAULT_L_R B3 GPIO5 (LDO_3V3)
OUT
SS L22 UPC_XB_SS
C 28 25 12 IN
TBT_X_USB_PWR_EN C4 GPIO6 (LDO_3V3) POWER C
83 35 28 OUT
SOC_DOCK_CONNECT D3 GPIO7 (VDDIO, PMOS O/D)
LDO_CORE E22 PP1V5_UPC_XB_LDO_CORE
1 C3209
85 83 72 63 28 OUT
UPC_PMU_RESET E4 GPIO8 (VDDIO) 0.68UF
5%
27 BI
PD_UPC_XB_GPIO9 F3 GPIO9 (VDDIO) 1 C3205 2 6.3V
X6S
27 PD_UPC_XB_GPIO10 F7 GPIO10 (VDDIO) 10UF 0402
BI 20% <CSS>
2 6.3V
CERM-X5R
29 27 25 IN
PP3V3_UPC_XB_LDO A18 BUSPOWER (LDO_3V3) 0402-1
<CLDO_CORE>
NC_UPC_XB_I2C_ADDR M19 I2C_ADDR (LDO_3V3) M15
UPC_XB_R_OSC M21 TYPE-C USBC_XB_CC1 BI 29 30 83
R_OSC (LDO_CORE) C_CC1 N16
CRITICAL
R32031 29 I2C_UPC_XB_DBG_CTL_SDA A16 I2CM_SDA_CNFG (LDO_3V3, 4K IPU) M17 USBC_XB_CC2 29 30 83
15K 29 I2C_UPC_XB_DBG_CTL_SCL B15 I2CM_SCL_CNFG (LDO_3V3, 4K IPU) C_CC2 N18
BI
0.1%
1/20W
TF-LF 28 27 25 BI
I2C_TBT_X_SDA B5 I2C_SDA1 (LDO_3V3)
L14 USBC_XB_CC1
0201 2 RPD_G1 29 30 83
28 27 25 BI
I2C_TBT_X_SCL A4 I2C_SCL1 (LDO_3V3)
RPD_G2 L16 USBC_XB_CC2
BI 1 C3214 1 C3213
27 25 OUT
I2C_TBT_XB_INT_L D7 I2C_IRQ1* (N/A, NMOS O/D)
BI 29 30 83
220PF 220PF
10% 10%
C_USB_TP K19 USBC_XB_USB_TOP_P 30 2 16V 2 16V
83 47 35 27 I2C_UPC_SDA B7 I2C_SDA2 (VDDIO)
BI CER-X7R
0201
CER-X7R
0201
BI
C_USB_TN K21 USBC_XB_USB_TOP_N 30
83 47 35 27 BI
I2C_UPC_SCL A6 I2C_SCL2 (VDDIO)
BI

47 35 28 27 OUT
UPC_I2C_INT_L C8 I2C_IRQ2* (N/A, NMOS O/D) C_USB_BP J20 USBC_XB_USB_BOT_P BI 30

C_USB_BN J22 USBC_XB_USB_BOT_N 30

27 OUT
UPC_XB_SPI_CLK B9 SPI_CLK
BI

REAR PORT: 27 OUT

UPC_XB_SPI_MOSI B11 SPI_MOSI C_SBU1 J16 USBC_XB_SBU1 BI 30 83
CONNECT UPC SPI TO ROM USBC_XB_SBU2
FRONT PORT: 27 IN
UPC_XB_SPI_MISO A10 SPI_MISO C_SBU2 H15
BI 30 83
GROUND UPC SPI
27 OUT
UPC_XB_SPI_CS_L A8 SPI_SSZ DIGITAL CORE I/O & CONTROL

27 BI
UPC_XB_SWD_DATA E20 SWD_DATA (VDDIO, IPU)
L3200
90-OHM-0.1A
27 BI
UPC_XB_SWD_CLK E16 SWD_CLK (VDDIO, IPU)

B EXCX4CE
SYM_VER-1
29 28 27 IN
UPC_XA_UART_TX B19 UART_RX (LDO_3V3) B
14 BI
USB2_UPC_PCH_XB_P 1 4 28 27 OUT UPC_XA_UART_RX A20 UART_TX (LDO_3V3)
DNU E18
USB2_UPC_PCH_XB_F_P H19 USB_RP1_P C18
DNU
14 USB2_UPC_PCH_XB_N 2 3 USB2_UPC_PCH_XB_F_N H21 USB_RP1_N
BI
DNU F5 PPDCIN_XB_G3H_F 27 29 87
PLACE_NEAR=U3100:5MM 27 SPARE_UPC_XB_USB2_RP G20 USB_RP2_P
BI
PORT_MUX GND DNU D5 PP20V_USBC_XB_VBUS 29 30 83 87
27 BI
SPARE_UPC_XB_USB2_RN G22 USB_RP2_N D17
DNU
27 BI
SPARE_UPC_XB_USB3_RP F19 USB_RP3_P G18
DNU
27 BI
SPARE_UPC_XB_USB3_RN F21 USB_RP3_N

84 25 BI
USBC_XB_AUXLSX1 J12 AUX_P
84 25 BI
USBC_XB_AUXLSX2 H11 AUX_N

25 OUT
DP_XB_HPD C12 HPD

83 27 OUT
USB3_BSSB_D2R_R_P G12 DEBUG0 (T.B.D.)
83 27 OUT
USB3_BSSB_D2R_R_N F11 DEBUG1 (T.B.D.)
83 27 IN
USB3_BSSB_R2D_P E8 DEBUG2 (T.B.D.)
83 27 IN
USB3_BSSB_R2D_N E12 DEBUG3 (T.B.D.)
83 27 OUT
SWD_SOC_SWCLK_XB G16 DEBUG4 (T.B.D.)
83 27 BI
SWD_SOC_SWDIO_XB F15 DEBUG5 (T.B.D.)
89 IN
SMC_DEBUGPRT_R_TX D15 DEBUG6 (T.B.D.)
89 OUT
SMC_DEBUGPRT_R_RX D19 DEBUG7 (T.B.D.) GND
PP3V3_UPC_XB_LDO 25 27 29

A22
H9
N20
B21
K15
N22
A 1
1M 2 R3209 I2C_UPC_XB_DBG_CTL_SCL SYNC_MASTER= SYNC_DATE=
A
29
PAGE TITLE
5% 1/20W MF 201
1
1M 2 R3208 I2C_UPC_XB_DBG_CTL_SDA 29
USB-C PORT CONTROLLER B
5% 1/20W MF 201 DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

1M PROPRIETARY PROPERTY OF APPLE INC.
1 2 R3205 UPC_XA_UART_TX 27 28 29 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
32 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=USB-C IV ALL RIGHTS RESERVED 29 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

87 83 29 PP20V_USBC_XB_VBUS
<RDAR://52485973>
K <RDAR://48380003>
CRITICAL K
1610-COMBO
D3370 ESDA25P35-1U1M-COMBO D3398
DSN2
D3302 TVS2200
NSR20F40NX_G A
WSON
A NOSTUFF 4 IN
5 IN
6 IN

7 EPAD
1 GND
2 GND
3 GND
D D

83 29 BI
USBC_XB_CC1
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
25 USBC_XB_R2D_CR_N<1> R3371 1 2 2 USBC_XB_R2D_C_N<1> C3391 1 2 0.22UF USBC_XB_R2D_N<1>
IN
5% 1/20W MF 201 10% 25V X5R 0201
CC1
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
25 USBC_XB_R2D_CR_P<1> R3370 1 2 2 USBC_XB_R2D_C_P<1> C3390 1 2 0.22UF USBC_XB_R2D_P<1>
IN
5% 1/20W MF 201 10% 25V X5R 0201
TBT_R2D0 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
25 USBC_XB_D2R_N<1> R3352 1 2 2 USBC_XB_D2R_R_N<1> C3381 1 2 0.33UF USBC_XB_D2R_CR_N<1>
OUT
5% 1/20W MF 201 10% 25V CER-X5R 0201
TBT_D2R0 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
25 USBC_XB_D2R_P<1> R3353 1 2 2 USBC_XB_D2R_R_P<1> C3380 1 2 0.33UF USBC_XB_D2R_CR_P<1>
OUT
5% 1/20W MF 201 10% 25V CER-X5R 0201
SBU2 83 29 BI
USBC_XB_SBU2
29 BI
USBC_XB_USB_BOT_N
USB2 BOT USBC_XB_USB_BOT_P
29 BI
TP_USBC_PP20V_XB OUT 83
GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
USBC_XB_CC2

X3DFN2

X3DFN2
GND_VOID=TRUE GND_VOID=TRUE 29 83

ESDL20-1BF4
BI
J3300 CC2

ESDL20-1BF4
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

2
201

201

201

201
SESDL2011

SESDL2011

SESDL2011

SESDL2011

20875-056E-01 1 2 USBC_XB_R2D_CR_N<2>

DZ3352
2
2

2 2 C3392 R3376 1 2

2
USBC_XB_R2D_N<2> 0.22UF USBC_XB_R2D_C_N<2>
ESD-SLP-COMBO

ESD-SLP-COMBO
D3354

D3349
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

2 2 IN 25

DZ3350
D3386

D3371

D3372

D3373

0201
F-ST-SM 25V 10% X5R 0201 1/20W 5% MF 201

R3351

R3350

R3349

R3348
2 2

0201
GND_VOID=TRUE GND_VOID=TRUE

MF

MF

MF

MF
57 PWR 58 1 2 USBC_XB_R2D_CR_P<2> TBT_R2D1
USBC_XB_R2D_P<2> C3393 0.22UF USBC_XB_R2D_C_P<2> R3377 1 2 2 IN 25
25V 10% X5R 0201 GND_VOID=TRUE 1/20W 5% MF 201 GND_VOID=TRUE

1
C USBC_XB_USB_TOP_P C

1/20W

1/20W

1/20W

1/20W
1

1
1 1 1 1 BI 29
1 1 SIGNAL USBC_XB_USB_TOP_N USB2 TOP

220K

220K

220K

220K
GND_VOID=TRUE GND_VOID=TRUE 29
1 2 GND_VOID=TRUE GND_VOID=TRUE
BI
USBC_XB_D2R_CR_N<2> C3386 1 2 0.33UF USBC_XB_D2R_R_N<2> R3359 1 2 2 USBC_XB_D2R_N<2> 25
3 4 OUT

5%

5%

5%

5%
25V 10% CER-X5R 0201 1/20W 5% MF 201
5 6 1 2 GND_VOID=TRUE
USBC_XB_D2R_P<2> TBT_D2R1
USBC_XB_D2R_CR_P<2> C3387 0.33UF USBC_XB_D2R_R_P<2> R3357 1 2 2 OUT 25
7 8 25V 10% CER-X5R 0201 GND_VOID=TRUE 1/20W 5% MF 201
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
PLACE_NEAR=J3300.3:5mm 9 10 USBC_XB_SBU1 29 83 SBU1
28 BI
USBC_XA_USB_BOT_N GND_VOID=TRUE GND_VOID=TRUE
BI
USB2 BOT USBC_XA_USB_BOT_P 11 12 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

X3DFN2
28 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

ESDL20-1BF4

ESDL20-1BF4
BI

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL
SESDL2011

SESDL2011

SESDL2011

SESDL2011
2

2
USBC_XA_SBU1 13 14

2
X3DFN2
201

201

201

201

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
83 28 BI GND_VOID=TRUE

DZ3353

DZ3351

D3382

D3383

D3384

D3385
SBU1 2 2

ESD-SLP-COMBO

ESD-SLP-COMBO
D3358

D3360
R3373 GND_VOID=TRUE C3373 GND_VOID=TRUE
15 16

GND_VOID=TRUE
0201
GND_VOID=TRUE

R3354

R3358
R3356

R3355
25 USBC_XA_R2D_CR_P<2> GND_VOID=TRUE 1 2 2 USBC_XA_R2D_C_P<2>
GND_VOID=TRUE
1 2 0.22UF USBC_XA_R2D_P<2> 2 2 2 2
IN 17 18

MF

MF

MF

MF
5% 1/20W MF 201 25V 10% X5R 0201

TBT_R2D1 R3372 GND_VOID=TRUE C3372 GND_VOID=TRUE

19 20

1
0201
GND_VOID=TRUE GND_VOID=TRUE
USBC_XA_R2D_CR_N<2> 21 22

1/20W

1/20W

1/20W

1/20W
25 1 2 2 USBC_XA_R2D_C_N<2> 1 2 0.22UF USBC_XA_R2D_N<2> GND_VOID=TRUE 1 1
IN
5% 1/20W MF 201 25V 10% X5R 0201 23 24 1 1
R3326 C3383 1 1

220K

220K
220K

220K
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
25 USBC_XA_D2R_P<2> 1 2 2 USBC_XA_D2R_R_P<2> 1 2 0.33UF USBC_XA_D2R_CR_P<2> 25 26
OUT

5%

5%

5%

5%
5% 1/20W MF 201 10% 25V CER-X5R 0201 27 28
TBT_D2R1 R3327 GND_VOID=TRUE GND_VOID=TRUE C3382 29 30 PLACE_NEAR=J3300.6:5mm
USBC_XA_SBU2
GND_VOID=TRUE GND_VOID=TRUE 28 83
25 OUT
USBC_XA_D2R_N<2> 1 2 2 USBC_XA_D2R_R_N<2> 1 2 0.33UF USBC_XA_D2R_CR_N<2> 31 32
BI
5% 1/20W MF 201 10% 25V CER-X5R 0201 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
CC2 83 28 USBC_XA_CC2 33 34 GND_VOID=TRUE SBU2
BI
C3370 1 2 0.22UF USBC_XA_R2D_C_P<1> R3374 1 2 2 USBC_XA_R2D_CR_P<1>
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE USBC_XA_R2D_P<1> IN 25
GND_VOID=TRUE

35 36 25V 10% X5R 0201 1/20W 5% MF 201

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE USBC_XA_R2D_N<1> GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
37 38 C3371 1 2 0.22UF USBC_XA_R2D_C_N<1> R3375 1 2 2 USBC_XA_R2D_CR_N<1> TBT_R2D0
X3DFN2
D3312

201

201

201

201
25
ESDL20-1BF4

IN
X3DFN2
D3328

25V 10% X5R 0201 1/20W 5% MF 201

ESDL20-1BF4

39 40
DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

2
DZ3303
SESDL2011

SESDL2011

SESDL2011

SESDL2011

R3325

R3324

R3329

22 22 R3328 USBC_XA_USB_TOP_P
2

2 2
2
DZ3301

28
41 42 BI
MF

MF

MF

MF
D3374

D3375

D3376

D3377

GND_VOID=TRUE
USBC_XA_USB_TOP_N USB2 BOT
0201

28
GND_VOID=TRUE 43 44 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
BI
GND_VOID=TRUE
45 46 C3384 1 2 2 USBC_XA_D2R_P<1>
1/20W

1/20W

1/20W

1/20W

GND_VOID=TRUE USBC_XA_D2R_CR_P<1> 0.33UF USBC_XA_D2R_R_P<1> R3323 1 2 OUT 25

ESD-SLP-COMBO

ESD-SLP-COMBO

11 11 47 48 25V 10% CER-X5R 0201 1/20W 5% MF 201

TBT_D2R0
1

1 1 USBC_XA_D2R_CR_N<1>
0201

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

220K

220K

220K

220K

GND_VOID=TRUE
GND_VOID=TRUE 49 50 C3385 1 2 0.33UF USBC_XA_D2R_R_N<1> R3322 1 2 2 USBC_XA_D2R_N<1> 25
OUT
5%

5%

5%

5%

B 51 52 25V 10% CER-X5R 0201 1/20W 5% MF 201

USBC_XA_CC1 BI 28 83 CC1 B
53 54

GND_VOID=TRUE

GND_VOID=TRUE
PLACE_NEAR=J3300.53:5mm

GND_VOID=TRUE
55 56

GND_VOID=TRUE

GND_VOID=TRUE
TP_USBC_PP20V_XA 83

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PLACE VBUS CAP NEAR EACH VBUS PIN PWR

X3DFN2

X3DFN2
PP20V_USBC_XA_VBUS 59 60

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL

DSN2-THICKSTNCL
SESDL2011

SESDL2011

SESDL2011

SESDL2011
87 83 30 28 27

ESDL20-1BF4

ESDL20-1BF4

2
201

201

201

201

D3378

D3379

D3380

D3381
2 2

2
D3304
ESD-SLP-COMBO

D3329
ESD-SLP-COMBO
DZ3300

DZ3302
<RDAR://52485973> 22 22
<RDAR://48380003>

R3319

R3318
R3321

R3320
CRITICAL K K GND

0201

0201
61 62

MF

MF

MF

MF
1610-COMBO
D3300 ESDA25P35-1U1M-COMBO D3399 63 64
DSN2
D3301 TVS2200

1
65 66

1/20W

1/20W

1/20W

1/20W
NSR20F40NX_G

1
WSON 11 11 1 1
A A 4 IN 67 68
NOSTUFF

220K

220K
220K

220K
5 IN 69 70

5%

5%

5%

5%
6 IN 71 72
73 74 PLACE_NEAR=J3300.52:5mm
7 EPAD
1 GND
2 GND
3 GND

75 76
77 78
79 80 PP20V_USBC_XA_VBUS 27 28 30 83 87
81 82
83 84
85 86

LAST CHANGE: Wed Apr 1 22:57:37 2015

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

USB-C CONNECTOR A
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=USB-C IV ALL RIGHTS RESERVED 30 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER=J223_METE SYNC_DATE=05/14/2019
A
PAGE TITLE

WIFI/BT SUPPORT
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=WIRELESS IV ALL RIGHTS RESERVED 31 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

83 50 32 PP3V3_G3S_WLANBT
0.1UF SHUNT CAPACITORS FOR FEM BIAS PINS ARE INSIDE THE MODULE
PLACE_NEAR=U3701.64:5MM

1 C3724 1
PLACE_NEAR=U3701.65:5MM

C3725 1 C3721 1 C3722 PP3719

P5MM-SP SM-SP
10UF 10UF 10UF 10UF 32 BT_SPI2_MISO 1
PP
20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R PP3718
P5MM-SP SM-SP
0402-4 0402-4 0402-4 0402-4 32 BT_SPI2_MOSI 1
PP

PP1V8_G3S_WLANBT 32 51 83
PP3717
P5MM-SP SM-SP
32 BT_SPI2_CLK 1
PP
PLACE_NEAR=U3701.71:1MM
1 C3723 1 C3700 1 C3704 PP3716 D

137
138
139

144
D P5MM-SP SM-SP

64
65
66

16
17

28
29
76
77

71
0.1UF 12PF 3.0PF BT_SPI2_CSN 1

6
7
32
10% 5% +/-0.1PF PP
2 6.3V 2 25V 2 25V
CERM-X5R NP0-C0G NP0-C0G PP3715

VBAT
VBAT
VBAT
VBAT
VBAT
VBAT

VBAT_2P4GHZ_BTPA
VBAT_2P4GHZ_BTPA
VBAT_2P4GHZ_C0C1
VBAT_2P4GHZ_C0C1

VBAT_5GHZ_C0
VBAT_5GHZ_C0
VBAT_5GHZ_C1
VBAT_5GHZ_C1

VDDIO_1P8V
VDDIO_1P8V
0201 0201 0201 P5MM-SP SM-SP
32 BT_GPIO_5 1
PP

83 50 32 PP3V3_G3S_WLANBT PP3714
P5MM-SP SM-SP
PLACE_NEAR=U3701.16:2MM 32 BT_GPIO_4 1
PP
PLACE_NEAR=U3701.16:2MM PLACE_NEAR=U3701.6:2.5MM PLACE_NEAR=U3701.28:2MM PLACE_NEAR=U3701.76:2MM

1 C3713 1 C3714 1 C3715 1

PLACE_NEAR=U3701.6:2MM

C3716 1 C3717 1
PLACE_NEAR=U3701.28:2MM

C3718 1 C3719 1
PLACE_NEAR=U3701.76:2MM

C3720 PP3713
P5MM-SP SM-SP
12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 32 PCIE_PME_L 1
PP
5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF
2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G TP3712
0201 0201 0201 0201 0201 0201 0201 0201 32 TP_WLAN_JTAG_TRST_L 1
A
TP-P5
33 50_ANT_C0 24 ANT_C0
U3701 PCIE_REFCLK_N 128 PCH_PCIE_CLK100M_WLAN_N 14 32 TP3711
BI
LBEE5XV1SA-255 IN
36 33 32 WLAN_THROTTLE 1
A
33 BI
50_ANT_C1 80 ANT_C1 LGA PCIE_REFCLK_P 53 PCH_PCIE_CLK100M_WLAN_P IN 14 32
TP-P5
(TP_WLAN_JTAG_TMS)
PCIE_RXD_N 126 PCH_PCIE_WLAN_R2D_N 32
TP3710
SYM 1 OF 4
PCIE_RXD_P 51 PCH_PCIE_WLAN_R2D_P 32 32 TP_WLAN_JTAG_TCK 1
A
83 51 32 PP1V8_G3S_WLANBT SAPPORO PCIE_TXD_N 124 PCH_PCIE_WLAN_D2R_C_N 32 TP-P5
CRITICAL 49 PCH_PCIE_WLAN_D2R_C_P TP3709
1 1 PCIE_TXD_P 32
R3715 R3714 32 TP_WLAN_JTAG_SEL 1
A
WLAN_SROM_CLK 141 SPROM_CLK GPIO13
100K 100K PCI_PME* 135 PCIE_PME_L 32 TP-P5
5% 5% 32 WLAN_SROM_CS_R 142 SPROM_CS GPIO15 TP3708
1/20W 1/20W PCIE_CLKREQ* 58 PCH_WLAN_CLKREQ_R_L 32
MF MF 32 WLAN_SROM_DIN 68 SPROM_MI GPIO18 33 32 TP_WLAN_JTAG_TDO 1
A
2 201 2 201 PCIE_PERST* 134 PCH_WLAN_PERST_L 15
32 WLAN_SROM_DOUT 69 SPROM_MO GPIO19 IN
(TP_WLAN_JTAG_TDO) TP-P5

UART_WLAN_R2D_RTS_L 46 TP_WLAN_JTAG_TDI
TP3707
1
36 IN WL_FAST_UART_CTS GPIO10 (HI-Z) 33 32 A
43 36 UART_WLAN_D2R_CTS_L 43 WL_FAST_UART_RTS GPIO11 (HI-Z) (TP_WLAN_JTAG_TDI) TP-P5
OUT
PD 50K BT_SF_CLK 114 BT_SPI2_CLK 32
36 UART_WLAN_R2D 44 WL_FAST_UART_RX GPIO8 (HI-Z)
IN
PD 50K BT_SF_CS* 113 BT_SPI2_CSN 32
UART_WLAN_D2R 45 WL_FAST_UART_TX GPIO9 (HI-Z) PP1V8_S5 TP3706
C 43 36 OUT
PD 50K BT_SF_MISO 115 BT_SPI2_MISO 32
42 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47
32 WLAN_SROM_CLK 1
A
C
34 18 OUT
WLAN_AUDIO_SYNC 121 WLAN_TIME_SYNC GPIO12 (HI-Z) PD 50K BT_SF_MOSI 37 BT_SPI2_MOSI 32
1 TP-P5
BT_SFLASH_STRAP
33 32 TP_WLAN_JTAG_TDI 57 CXT_A/JTAG_TD1 GPIO4 (HI-Z) PU 50K BT_UART_CTS* 117 HIGH: SFLASH
R3704
10K TP3705
IN NC LOW: NO SFLASH 5% 32 WLAN_SROM_CS 1
A
33 32 IN
TP_WLAN_JTAG_TDO 59 CXT_B/JTAG_TDO GPIO5 (HI-Z) PU 50K BT_UART_RTS* 40
NC 1/20W
TP-P5
MF
32 TP_WLAN_JTAG_SEL 70 JTAG_SEL PU 50K BT_UART_RX 39
NC NOSTUFF 201 2 TP3704
NC
143 JTAG_SEL_BS DO NOT CONNECT PU 50K BT_UART_TX 119
NC R3720 32 WLAN_SROM_DIN 1
A
32 TP_WLAN_JTAG_TCK 132 JTAG_TCK GPIO2 (HI-Z) 0 TP-P5
PD 50K BT_GPIO_2 36 BT_GPIO_2 1 2 PCH_BT_ROM_BOOT_L 13
TP3703
36 33 32 WLAN_THROTTLE 133 JTAG_TMS GPIO3 (HI-Z) IN
IN
PU 50K BT_GPIO_3 112 BT_AUDIO_SYNC 18 5% 32 WLAN_SROM_DOUT 1
A
32 TP_WLAN_JTAG_TRST_L 131 JTAG_TRST* GPIO6 (HI-Z) OUT
1/20W
PU 50K BT_GPIO_4 38 BT_GPIO_4 32 MF TP-P5
__ 0201
| 32 BT_INTERFACE_SEL 136 GPIO_14 (HI-Z) PU 50K BT_GPIO_5 116 BT_GPIO_5 32
|
STRAP PINS | WLAN_SROM_STRAP 60 GPIO_17 (HI-Z)
|
32

WLAN_SROM_SIZE 61 PD 50K BT_I2S_CLK 34 UART_BT_LH_D2R OUT 36 TP3701

P2MM
R3711 | __ 32 GPIO_20 (HI-Z, WEAK PU <1SEC )
PD 50K BT_I2S_DI 35 NC_I2S_BT_R2D SM
1K 32 14 PCH_PCIE_CLK100M_WLAN_N 1
32 PCH_WLAN_CLKREQ_R_L PCH_WLAN_CLKREQ_L BI 14
NC
120 LHL_GPIO2 PD 50K BT_I2S_DO 32 NC_I2S_BT_D2R PP
1 2 PLACE TP3701 AND TP3702
5% PD 50K BT_I2S_WS 33 UART_BT_LH_R2D ON THE BOTTOM SIDE
1/20W
MF
83 72 IN
PMU_CLK32K_WLANBT 109 LPO_IN
IN 36
FOR PCIE PROBE ACCESS TP3702
P2MM
201 PD 50K BT_DEV_WAKE 118 SM
35 33 OUT
WLBT_HOST_WAKE 56 WL_HOST_WAKE GPIO0 (HI-Z) NC 32 14 PCH_PCIE_CLK100M_WLAN_P 1
PP
WLBT_HOST_WAKE TOGGLES FOR BOTH BT AND WLAN WAKE BT_DEV_WAKE NOT TOGGLED WHEN BT OVER PCIE ENABLED
72 IN
WLAN_PWR_EN 110 WL_REG_ON PD 50K 42
PD 50K BT_HOST_WAKE NC
BT_HOST_WAKE IS NOT USED
WLBT_HOST_WAKE TOGGLES FOR BOTH BT AND WLAN WAKE

PD 50K BT_REG_ON 111

NC
DO NOT TOGGLE WHEN BT OVER PCIE ENABLED
BOOT_STRAPS SCHEMATIC LAYOUT SYMBOL IS 339S00586

PLACE C3706 AND C3707 ON THE BOTTOM SIDE FOR PCIE PROBE ACCESS
83 51 32 PP1V8_G3S_WLANBT
U3701.124:8MM
B 1
R3702 R37131 32 PCH_PCIE_WLAN_D2R_C_N C3706 2 1 0.1UF PCH_PCIE_WLAN_D2R_N 14
B
OUT
1K 10K 10% 6.3V CERM-X5R 0201
0.5% NOSTUFF 5%
1/20W 1/20W
MF MF U3701.49:8MM
2 0201 201 2
32 PCH_PCIE_WLAN_D2R_C_P C3707 2 1 0.1UF PCH_PCIE_WLAN_D2R_P 14
32 WLAN_SROM_STRAP 32 BT_INTERFACE_SEL 10% 6.3V CERM-X5R 0201
OUT

WLAN_SROM_STRAP: BT_INTERFACE_SEL
LOW: OTP LOW: (DEFAULT): PCIE
HIGH: SROM HIGH: UART

PLACE C3708 AND C3709 ON THE BOTTOM SIDE FOR PCIE PROBE ACCESS
32 TP_WLAN_JTAG_SEL U3701.126:8MM
R37001 32 PCH_PCIE_WLAN_R2D_N C3708 2 1 0.1UF PCH_PCIE_WLAN_R2D_C_N IN 14
10K 10% 6.3V CERM-X5R 0201
5%
1/20W
MF U3701.51:8MM
201 2
32 PCH_PCIE_WLAN_R2D_P C3709 2 1 0.1UF PCH_PCIE_WLAN_R2D_C_P 14
IN
10% 6.3V CERM-X5R 0201

WLAN_JTAG_SEL:
LOW: Some JTAG are GPIOs 83 51 32 PP1V8_G3S_WLANBT PLACE_NEAR=U3710.8:2MM BLUETOOTH SERIAL FLASH
HIGH: JTAG Enabled 83 51 32 PP1V8_G3S_WLANBT
1 C3711 PLACE_NEAR=U3750.8:2.8MM
0.1UF PLACE_NEAR=U3750.8:4MM
10%
R3712 1 1 C3710 1 C3712

8
2 6.3V R37511 R37521 R3753 1
8

CERM-X5R
0201 10K VCC
0.1UF 10UF
5% 100K 100K 10K 10% 20%
VCC
1/20W 5% 5% 5% U3750 2 6.3V 2 6.3V
32 WLAN_SROM_SIZE U3710 MF 1/20W 1/20W 1/20W 4MBIT-1.8V
CERM-X5R
0201
CERM-X5R
0402-4
CAS93C86B 201 2 MF MF MF
A 1
R3705 R3718 3 DI UDFN8
201 2 201 2 201 2 MX25U4035FZUI A
WLAN_SROM_DOUT DO 4 WLAN_SROM_DIN USON SYNC_MASTER=J223_METE SYNC_DATE=05/14/2019

32 32
1K 1K 1 CS 32 BT_SPI2_CLK 6 SCLK SI/SIO0 5 BT_SPI2_MOSI 32
PAGE TITLE
WLAN_SROM_CS_R WLAN_SROM_CS
0.5%
1/20W
MF
32 2
0.5%
1 32

32 WLAN_SROM_CLK 2 SK ORG 6 WLAN_SROM_ORG R3754 OMIT_TABLE WIFI/BT MODULE 1

2 0201
1/20W
BT_SPI2_CSN 1
1K 2 BT_SFLASH_CS_L 1 DRAWING NUMBER SIZE
MF
0201
NC
7 PE
OMIT_TABLE
32

5% 3
CS*
WP*/SIO2
SO/SIO1 2 BT_SPI2_MISO 32
Apple Inc.
051-05309 D
1/20W REVISION
7
WLAN_SROM_SIZE: R3717 1 GND EPAD MF
201
HOLD*/SIO3
THRM 5.1.0
10K
5

LOW: 16 KBIT 5% GND PAD NOTICE OF PROPRIETARY PROPERTY: BRANCH

1/20W BT_SFLASH_WP_L
HIGH: 4 KBIT WLAN SERIAL EEPROM

9
MF THE INFORMATION CONTAINED HEREIN IS THE
201 2 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
BT_SFLASH_HOLD_L
NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=WIRELESS IV ALL RIGHTS RESERVED 32 OF 98
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 8 7 6 5 4 3 2 1

U3701 U3701 U3701 RF CONNECTORS

LBEE5XV1SA-255 LBEE5XV1SA-255 LBEE5XV1SA-255
LGA LGA
1 SYM 2 OF 4 160 250 SYM 3 OF 4 340 SYM 4 OF 4
GND GND GND GND 430 GND GND 443
2 OMIT_TABLE 161 251 OMIT_TABLE 341 431 OMIT_TABLE 444
GND GND GND GND GND GND
3 CRITICAL 162 252 CRITICAL 342 432 CRITICAL 445
GND GND GND GND GND GND CRITICAL
4 GND GND 163 253 GND GND 343 433 GND GND 446 J3810
5 GND GND 164 254 GND GND 344 434 GND GND 447 20449-001E-03
F-ST-SM
8 165 255 345 435 448
D 9
GND
GND
GND
GND 166 256
GND
GND
GND
GND 346 436
GND
GND
GND
GND 449
1 50_ANT_C0 BI 32 D
10 GND GND 167 257 GND GND 347 437 GND GND 450

2
3
4
11 GND GND 168 258 GND GND 348 438 GND GND 451
12 GND GND 169 259 GND GND 349 439 GND
13 GND GND 170 260 GND GND 350 440 GND
14 GND GND 171 261 GND GND 351 441 GND
15 GND GND 172 262 GND GND 352 442 GND
18 GND GND 173 263 GND GND 353
19 GND GND 174 264 GND GND 354
20 175 265 355 CRITICAL
GND GND GND GND
21 GND GND 176 266 GND GND 356
J3820
20449-001E-03
22 GND GND 177 267 GND GND 357 F-ST-SM
23 GND GND 178 268 GND GND 358 1 50_ANT_C1 BI 32
25 GND GND 179 269 GND GND 359
26 180 270 360

2
3
4
GND GND GND GND
27
30
GND
GND
GND
GND
181
182
271
272
GND
GND
GND
GND
361
362
WIRELESS MODULE GND PINS
31 GND GND 183 273 GND GND 363
41 GND GND 184 274 GND GND 364
47 GND GND 185 275 GND GND 365
48 GND GND 186 276 GND GND 366
50 GND GND 187 277 GND GND 367
52 GND GND 188 278 GND GND 368
54 GND GND 189 279 GND GND 369
55 GND GND 190 280 GND GND 370
62 GND GND 191 281 GND GND 371

C 63
67
GND GND 192
193
282
283
GND GND 372
373
C
GND GND GND GND
72 GND GND 194 284 GND GND 374
73 GND GND 195 285 GND GND 375
74 GND GND 196 286 GND GND 376
75 GND GND 197 287 GND GND 377
78 GND GND 198 288 GND GND 378
79 GND GND 199 289 GND GND 379
81 GND GND 200 290 GND GND 380
82 GND GND 201 291 GND GND 381
83 GND GND 202 292 GND GND 382
84 GND GND 203 293 GND GND 383
85 GND GND 204 294 GND GND 384
86 GND GND 205 295 GND GND 385
87 GND GND 206 296 GND GND 386
88 GND GND 207 297 GND GND 387
89 GND GND 208 298 GND GND 388
90 GND GND 209 299 GND GND 389
91 GND GND 210 300 GND GND 390
92 GND GND 211 301 GND GND 391
93 GND GND 212 302 GND GND 392
94 GND GND 213 303 GND GND 393
95 GND GND 214 304 GND GND 394
96 GND GND 215 305 GND GND 395
97 GND GND 216 306 GND GND 396
98 GND GND 217 307 GND GND 397
99 218 308 398
B 100
GND
GND
GND
GND 219 309
GND
GND
GND
GND 399
B
101 GND GND 220 310 GND GND 400
102 GND GND 221 311 GND GND 401
103 GND GND 222 312 GND GND 402
104 GND GND 223 313 GND GND 403
105 GND GND 224 314 GND GND 404
106 GND GND 225 315 GND GND 405
107 GND GND 226 316 GND GND 406
108 GND GND 227 317 GND GND 407
122 GND GND 228 318 GND GND 408
123 GND GND 229 319 GND GND 409
125 GND GND 230 320 GND GND 410
127 GND GND 231 321 GND GND 411
129 GND GND 232 322 GND GND 412
130 GND GND 233 323 GND GND 413
140 GND GND 234 324 GND GND 414
145 GND GND 235 325 GND GND 415
146 GND GND 236 326 GND GND 416
147 GND GND 237 327 GND GND 417
148 238 328 418
149
GND GND
239 329
GND GND
419
R3805 1
201
2 100K WLAN_THROTTLE 32 36
GND GND GND GND
1/20W MF 5%
150 GND GND 240 330 GND GND 420
151 GND GND 241 331 GND GND 421 R3804 1
201
2 100K TP_WLAN_JTAG_TDI 32
152 GND GND 242 332 GND GND 422 1/20W MF 5%
153 243 333 423
GND GND GND GND R3803 1
201
2 100K TP_WLAN_JTAG_TDO 32
A 154
155
GND GND 244
245
334
335
GND GND 424
425
1/20W MF 5% SYNC_MASTER=J223_METE SYNC_DATE=05/14/2019
A
GND GND GND GND PAGE TITLE
156 336
157
GND
GND
GND
GND
246
247 337
GND
GND
GND
GND
426
427 WIFI/BT MODULE 2
DRAWING NUMBER SIZE
158 248 338 428
159
GND
GND
GND
GND 249 339
GND
GND
GND
GND 429
R3801 1
201
2 100K WLBT_HOST_WAKE 32 35
Apple Inc.
051-05309 D
1/20W MF 5% NOSTUFF REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=WIRELESS IV ALL RIGHTS RESERVED 33 OF 98
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 8 7 6 5 4 3 2 1
Note IPU/IPD represents SW configured state, not HW default

D D
OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP
43 NC_PLCAM_TX_THROTTLE A13 GPIO0 TMIB21B0-B7 TMR32_PWM0 F33 WLAN_AUDIO_SYNC 18 32
IN
43 NC_GNSS_HOST_TIME A12 GPIO1 SYM 3 OF 17 TMR32_PWM1 J29 DFR_PWR_EN 46 83
OUT
43 NC_GNSS_DEV_WAKE B12 GPIO2 GPIO/TEST/MISC TMR32_PWM2 G28 SOC_KBD_BKLT_PWM_R 75 83

57 CODEC_INT_L AC33 GPIO3

IN
L32 CFSB H28 PMU_ACTIVE_READY 28 72 83 89
45 OUT
SE_CTLR_FW_DWLD GPIO4 IN

15 IN
PCH_SOC_SYNC P32 GPIO5 (IPD) FORCE_DFU U28 SOC_FORCE_DFU IN 28 72 83 89

44 IN
MESA_INT R33 GPIO6 (IPD) DFU_STATUS N33 SOC_DFU_STATUS OUT 28 83

44 MESA_PWR_EN N30 GPIO7

OUT
M32 HOLD_RESET F28 SOC_HOLD_RESET 34
43 NC_SOC_WLAN_DEV_WAKE GPIO8
42 IN
BOARD_REV0 P33 GPIO9 ANALOGMUX_OUT AH33 TP_SOC_AMUXOUT 43

59 58 SPKRAMP_INT_L M30 GPIO10 (IPU) TST_CLKOUT L28 TP_SOC_TST_CLKOUT 43

IN
59 58 SPKRAMP_RESET_L M33 GPIO11 (IPD) TESTMODE C12 SOC_TESTMODE 34
OUT
42 BOARD_REV1 T28 GPIO12
IN
P29 DROOP F29 PMU_DROOP_L 72
62 TPAD_SPI_EN GPIO13 IN
OUT
H29 SOCHOT G30 SOC_SOCHOT_L 83
34
R3941
82 80 79 78 77 OUT
SSD_BFH GPIO14 OUT 72

SE_DEV_WAKE G33 SOC_XTAL24M_OUT

85
0 SOC_XTAL24M_OUT_R
45 OUT GPIO15 XO0 AP20 1 2
42 BOOT_CONFIG0 E28 GPIO16 XI0 AP21 SOC_XTAL24M_IN 5%
IN
1/20W
BOOT_CONFIG1 N28 1
42 IN
J28
GPIO17 R3940 MF
0201
42 IN
BOOT_CONFIG2 GPIO18 511K
1%
SSD_PMU_RESET_L E33 GPIO19 1/20W Y3940
C 83 81 43

83 46
OUT

IN
DFR_DISP_INT T30 GPIO20 (IPD)
MF
2 201
1.60X1.20MM-SM C
24MHZ-30PPM-9.5PF-60OHM
1 3
NC GND

4
2
C3940 1 1 C3941
12PF 12PF
5% 5%
25V 2 25V
CERM 2 CERM
0201 0201

PP1V1_SLPDDR 39 40 71 83

OMIT_TABLE
CRITICAL R39701 R39711 R39721 R39731 R39741 R39751
240 240 240 240 240 240
1% 1% 1% 1% 1% 1%
U3900 1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
POP-1GB-20NM-M-SCK B
B FCCSP
201 2 201 2 201 2 201 2 201 2 201 2

42 BI
I2C_SEP_SDA AP4 SEP_I2C0_SDA TMIB21B0-B7 DDR0_RREF H2 SOC_DDR0_RREF
42 OUT
I2C_SEP_SCL AN4 SEP_I2C0_SCL SYM 7 OF 18 DDR1_RREF E32 SOC_DDR1_RREF
AP5 SEP/USB/DDR DDR2_RREF AH2 SOC_DDR2_RREF
60 SEP_CAM_DISABLE_L SEP_SPI0_MISO
OUT
DDR3_RREF AH32 SOC_DDR3_RREF
60 OUT
SEP_DMIC_DISABLE_L AN5 SEP_SPI0_MOSI
60 OUT
SEP_DISABLE_STROBE AM5 SEP_SPI0_SCLK DDR0_ZQ N4 SOC_DDR0_ZQ
DDR3_ZQ AC30 SOC_DDR3_ZQ
89 83 USB_SOC_P B20 USB_DP
BI
DDR0_RET* H4 AON_SLEEP1_RESET_L 35
89 83 BI
USB_SOC_N A20 USB_DM E30
IN
DDR1_RET*
43 NC_SOC_USB_ID D20 USB_ID DDR2_RET* AH4
83 27 SOC_USB_VBUS E20 USB_VBUS (IPD) DDR3_RET* AH30
IN
SOC_USB_REXT F22 USB_REXT
DDR0_SYS_ALIVE G2 PMU_SYS_ALIVE IN 35 72 81 82 83 85

DDR1_SYS_ALIVE D31
1
R3960 DDR2_SYS_ALIVE AJ2
200 AJ32
1% DDR3_SYS_ALIVE
1/20W
MF
2 201

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

PP1V8_SLPS2R 27 28 29 40 42 43 44 47 60 63
64 70 71 72 74 81 83 86 89
SOC GPIO/SEP/USB/DDR/TEST
DRAWING NUMBER SIZE

051-05309 D
R3939 47K 1 2 SOC_SOCHOT_L 34 72 83 85
Apple Inc. REVISION
5% 1/20W MF 201
5.1.0
R3934 10K 1 2
5% 1/20W MF 201
SOC_HOLD_RESET 34 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R3937 10K 1 2
5% 1/20W MF 201
SOC_TESTMODE 34 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
39 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 34 OF 98
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QQ微信：181806465
 8 7 6 5 4 3 2 1
OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP
43 NC_WLAN_CONTEXT_A B5 AOP_FUNC[0] TMIB21B0-B7 AOP_PDM_CLK0 N6 PDM_DMIC_CLK0_R 43
OUT
43 NC_WLAN_CONTEXT_B D4 AOP_FUNC[1] SYM 6 OF 17 AOP_PDM_CLK1 J6 PDM_DMIC_CLK1_R 43
OUT
AOP
84 43 IN
ACCEL_INT1 G1 AOP_FUNC[2] (IPD) (IPU) AOP_PDM_CLK2 F5 TP_SMC_FIXTURE_MODE_L 83

43 ACCEL_INT2 C5 AOP_FUNC[3] (IPD) AOP_PDM_CLK3 F2 NC_PLCAM_PROX_INT_L 43

IN
45 SE_HOST_WAKE_R D1 AOP_FUNC[4] AOP_PDM_CLK4 J4 NC_PLCAM_ROMEO_B2B_DETECT 43

85 15 SOC_PERST_L E4 AOP_FUNC[5]
IN
(IPD) AOP_PDM_DATA0 F1 PDM_DMIC_DATA0 60
NC_ALTIMETER_INT C4 IN

D 84 43 OUT
43

SPI_ACCEL_CS_L F4
AOP_FUNC[6]
AOP_FUNC[7]
(IPD) AOP_PDM_DATA1 J1 PDM_DMIC_DATA1 IN 60 D
43 NC_SPI_ALTIMETER_CS_L E1 AOP_FUNC[8] AOP_SPI_MOSI A5 SPI_AOP_SENSOR_MOSI_R OUT 43

AOP_SPI_SCLK E5 SPI_AOP_SENSOR_CLK_R 43
43 NC_I2C_AOP_SCL H6 AOP_I2C0_SCL OUT
AOP_SPI_MISO C2 SPI_AOP_SENSOR_MISO 43 84
43 NC_I2C_AOP_SDA G6 AOP_I2C0_SDA IN

OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP
83 46 IN
DFR_TOUCH_INT_L AG6 AON_GPIO0 TMIB21B0-B7 (IPU) JTAG_TCK AF6 SWD_SOC_SWCLK IN 89

17 IN
CPU_SMC_THRMTRIP_L AB6 AON_GPIO1 (IPU) SYM 5 OF 17 (IPU) JTAG_TMS AH1 SWD_SOC_SWDIO BI 89
AON
43 NC_SMC_GFX_SELF_THROTTLE AL1 AON_GPIO2 (IPU) JTAG_TDI AE6 DEBUG_JTAG_SOC_TDI IN 83

43 NC_SMC_TOPBLK_SWP_L AH5 AON_GPIO3 JTAG_TDO AK1 DEBUG_JTAG_SOC_TDO OUT 83

16 IN
XDP_PRESENT_L AG1 AON_GPIO4 (IPD) JTAG_TRST* AH6 TP_JTAG_SOC_TRST_L 83

57 OUT
CODEC_RESET_L AL4 AON_GPIO5 JTAG_SEL Y8 SOC_JTAG_SEL 35
AK4 (DAP=0, TAP=1)
NC_BT_DEV_WAKE AON_GPIO6
OUT
AD6 DOCK_CONNECT AJ5 SOC_DOCK_CONNECT 28 29 35 83
43 NC_PCIEDN_WAKE_L AON_GPIO7 IN

43 NC_ENET_LOW_PWR AM1 AON_GPIO8 AON_SWD0_TMS AF2 NC_SOC_WLAN_JTAG_TMS 43

62 IN
TPAD_SPI_INT_L AJ6 AON_GPIO9 AON_SWD1_TMS AE4 NC_MESA_MENUKEY_L 43

43 NC_SDCONN_STATE_CHANGE_L AK5 AON_GPIO10 AON_SWD01_TCK AE5 NC_SOC_WLAN_JTAG_TCK 43

43 NC_ENET_MEDIA_SENSE AJ1 AON_GPIO11

AL6 WDOG AF5 SOC_WDOG 72 83 85
PLACE_NEAR=U3900.AA6:5MM PMU_INT_L AON_GPIO12 (IPU) OUT

C 72 IN
AON_SLEEP1_RESET* AC6 AON_SLEEP1_RESET_L C
72 OUT
SPMI_CLK R4036 20 1 2
5% 1/20W MF 201
SPMI_CLK_R AA6 AON_SPMI_SCLK OUT 34

72 BI
SPMI_DATA R4037 20 1 2
5% 1/20W MF 201
SPMI_DATA_R AK2 AON_SPMI_SDATA
PLACE_NEAR=U7800.M7:5MM
83 72 IN
PMU_CLK32K_SOC AK6 RT_CLK32768
R4039
5% 1/20W
1 2
MF
4.7K
201
83 SOC_COLD_RESET_L AG4 COLD_RESET*
85 83 72 60 IN
PMU_COLD_RESET_L AF4 CFSB_AON

COLD_RESET and CFSB_AON requires isolation per <rdar://30222445>

OMIT_TABLE
CRITICAL

PLACE_NEAR=U3900.R4:5MM
PLACE_NEAR=U3900.R1:5MM
U3900
PLACE_NEAR=U3900.T5:5MM POP-1GB-20NM-M-SCK
PLACE_NEAR=U3900.T6:5MM FCCSP
12 BI
ESPI_IO<0> R4050 20 1 2
5% 1/20W MF 201
ESPI_IO_R<0> R4 SMC_ESPI_IO0 TMIB21B0-B7 SMC_GPIO0 V4 CODEC_WAKE_L IN 57

12 BI
ESPI_IO<1> R4051 20 1 2 ESPI_IO_R<1> R1 SMC_ESPI_IO1 SYM 9 OF 17 (IPD) SMC_GPIO1 V8 NC_BT_HOST_WAKE IN
12 BI
ESPI_IO<2> R4052 20 1 2 5% 1/20W MF 201
ESPI_IO_R<2> T5 SMC_ESPI_IO2 SMC (IPD) SMC_GPIO2 V6 WLBT_HOST_WAKE IN 32 33
5% 1/20W MF 201
12 BI
ESPI_IO<3> R4053 20 1 2
5% 1/20W MF 201
ESPI_IO_R<3> T6 SMC_ESPI_IO3 SMC_GPIO3 U4 DP_INT_HPD_MASK OUT 13 43

12 ESPI_CLK60M P2 SMC_ESPI_CLK (IPD) SMC_GPIO4 V7 SMC_LID_RIGHT 43 83

IN IN
12 ESPI_CS_L T4 SMC_ESPI_CS* SMC_GPIO5 U6 NC_PCC_EVENT 43
IN
12 ESPI_RESET_L T2 SMC_ESPI_RESET* (IPD) SMC_GPIO6 V1 NC_TPAD_VIBE_L 43
IN
SMC_GPIO7 W5 TPAD_KBD_WAKE_L 62 83
42 SMC_PECI_RX M6 SMC_PECI_IN (IPD) AC1
IN
IN
R6 SMC_GPIO8 SMC_LID_LEFT 43 83
42 SMC_PECI_TX SMC_PECI_OUT AB2
IN
OUT
SMC_GPIO9 NC_SPI_DESCRIPTOR_OVERRIDE_L 43

42 SMC_PCH_PWROK U7 PCH_PWROK SMC_GPIO10 AB1 NC_DISP_GCON_INT_L 43

OUT
B 42 OUT
SMC_PCH_SYS_PWROK U8 SYS_PWROK SMC_GPIO11 AA4 NC_PCH_GCON_INT_L 43 B
SMC_GPIO12 W8 TPAD_ACTUATOR_DISABLE_L 62
42 18 SMC_RSMRST_L U1 RSMRST* BI
OUT
(IPU) SMC_GPIO13 AA1 TBT_WAKE_L 27
83 42 SMC_SYSRST_L U5 SYS_RESET* AC2
IN
OUT
(IPU) SMC_GPIO14 UPC_I2C_INT_L IN 27 28 29 47

89 83 72 18 PM_SLP_S0_L W1 SLP_S0B (IPU) SMC_GPIO_15 K2 DP_INT_HPD_L 43

IN IN
65 43 42 SMC_PROCHOT_L P6 PROCHOT*
BI
SMC_ADC0 AE1 SMC_CPU_HS_ISENSE 49
IN
85 83 82 81 72 34 PMU_SYS_ALIVE W6 SYS_ALIVE SMC_ADC1 Y5 SMC_PBUS_VSENSE 49
IN IN
SMC_ADC2 AE2 SMC_BMON_ISENSE 49
83 47 29 27 I2C_UPC_SCL K4 SMC_I2C0_SCL IN
OUT
SMC_ADC3 AB5 SMC_DCIN_ISENSE 49
83 47 29 27 I2C_UPC_SDA H1 SMC_I2C0_SDA Y7
IN
BI
SMC_ADC4 SMC_DCIN_VSENSE IN 49

47 I2C_SNS0_S0_SCL L4 SMC_I2C1_SCL SMC_ADC5 AD4 SMC_PP3V3_WLANBT_ISENSE 50

OUT IN
47 I2C_SNS0_S0_SDA L5 SMC_I2C1_SDA SMC_ADC6 AF1 SMC_PP1V8_WLANBT_ISENSE 51
BI IN
SMC_ADC7 Y6 SMC_CALPE_ISENSE 52
47 I2C_THMSNS_SCL M4 SMC_I2C2_SCL IN
OUT
47 BI
I2C_THMSNS_SDA K1 SMC_I2C2_SDA REFP_ADC AC5 PP1V25_SLPS2R_SMC_AVREF 42

REFM_ADC AC4 GND_SMC_AVSS 42 49 50 51 52

47 OUT
I2C_DISP_SCL L2 SMC_I2C3_SCL
47 BI
I2C_DISP_SDA P5 SMC_I2C3_SDA SMC_PWM0 E2 SMC_FAN_0_PWM OUT 55 1 PLACE_NEAR=U3900.AC4:4MM
SMC_TACH0 K6 SMC_FAN_0_TACH 55 60
83 72 47 OUT
I2C_PWR_SCL L1 SMC_I2C4_SCL IN
XW4089
83 72 47 BI
I2C_PWR_SDA M1 SMC_I2C4_SDA SMC_PWM1 N5 NC_SMC_FAN_1_PWM 43 SM
2
SMC_TACH1 L6 NC_SMC_FAN_1_TACH 43
47 OUT
I2C_SENSE_SCL N1 SMC_I2C5_SCL
47 BI
I2C_SENSE_SDA N2 SMC_I2C5_SDA SMC_PWM2 K5 NC_SMC_LED_ONEWIRE 43

81 47 OUT
I2C_SSD_SCL P1 SMC_I2C6_SCL (IPU) SMC_UART0_RXD U2 SMC_DEBUGPRT_RX IN 83 89

81 47 BI
I2C_SSD_SDA P4 SMC_I2C6_SDA SMC_UART0_TXD T1 SMC_DEBUGPRT_TX OUT 83 89

A SWD_OUT0_TCK AB4 SSD0_SWCLK OUT 77 78 79 80 82

A
SWD_OUT0_TMS Y1 SSD0_SWDIO SYNC_MASTER= SYNC_DATE=

BI 77 78 79 80 82
PAGE TITLE

SWD_OUT1_TCK AD1 NC_SSD1_SWCLK_UART_R2D 43 SOC AOP/AON/SMC

R4046 10K 1 2
5% 1/20W MF 201
SOC_JTAG_SEL 35 SWD_OUT1_TMS W7 NC_SSD1_SWDIO_UART_D2R 43 DRAWING NUMBER SIZE
R4047 100K 1 2 SOC_DOCK_CONNECT 28 29 35 83 051-05309 D
5% 1/20W MF 201 Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 35 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP
84 76 IN
MIPI_FTCAM_DATA_P<0> B24 MIPI0C_DATA0_P TMIB21B0-B7 ISP_I2C0_SDA AC28 I2C_FTCAM_SDA BI 48

84 76 IN
MIPI_FTCAM_DATA_N<0> A24 MIPI0C_DATA0_N SYM 4 OF 17 ISP_I2C0_SCL AD33 I2C_FTCAM_SCL OUT 48
B22 ISP
MIPI0C_DATA1_P
A22 ISP_I2C1_SDA AA29 NC_I2C_PLCAM_SDA 43
MIPI0C_DATA1_N
ISP_I2C1_SCL AD30 NC_I2C_PLCAM_SCL
D 84 76 MIPI_FTCAM_CLK_P B23 MIPI0C_CLK_P
43
D
IN
SENSOR0_CLK AF32 NC_FTCAM_CLK12M_R 43
84 76 MIPI_FTCAM_CLK_N A23 MIPI0C_CLK_N
IN
SENSOR0_RST AF30 NC_FTCAM_RESET_L 43

B25 SENSOR0_ISTRB AC29 DFR_TOUCH_RESET_L OUT 46 83

MIPI1C_DATA0_P
A25 MIPI1C_DATA0_N SENSOR1_CLK AA28 NC_PLCAM_RX_CLK12M_R 43
B27 MIPI1C_DATA1_P SENSOR1_RST AB30 NC_PLCAM_RX_RESET_L 43
A27 MIPI1C_DATA1_N SENSOR1_ISTRB AA30 DFR_DISP_RESET_L OUT 46 83

B26 MIPI1C_CLK_P SENSOR2_CLK AB28 NC_PLCAM_TX_CLK12M_R 43

A26 MIPI1C_CLK_N SENSOR2_RST AD28 NC_PLCAM_TX_RESET_L 43

SENSOR_INT W28 NC_PLCAM_TX_INT 43

46 MIPI_DFR_DATA_P B30 MIPID_DATA0_P

OUT
46 MIPI_DFR_DATA_N A30 MIPID_DATA0_N
OUT
(IPD) DISP_TE D33 DFR_DISP_TE IN 46 83

46 MIPI_DFR_CLK_P B29 MIPID_CLK_P

OUT
A29 DISP_VSYNC L30 BOARD_REV2 42
46 OUT
MIPI_DFR_CLK_N MIPID_CLK_N IN

CLK32K_OUT AF29 DFR_TOUCH_CLK32K_RESET_L OUT 46 83

SOC_MIPI0C_REXT F23 MIPI0C_REXT

SOC_MIPI1C_REXT F25 MIPI1C_REXT
SOC_MIPID_REXT F26 MIPID_REXT

1 1 1
R4100 R4101 R4102
4.02K 4.02K 4.02K
1% 1% 1%
1/20W 1/20W 1/20W
MF MF MF
2 201 2 201 2 201

PLACE_NEAR=U3900.F23:5MM PLACE_NEAR=U3900.F26:5MM
C PLACE_NEAR=U3900.F25:5MM
C
OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP PLACE_NEAR=U3900.AM4:5MM
58 48 I2C_SPKRAMP_L_SDA W33 I2C0_SDA TMIB21B0-B7 SPI0_MISO AN6 SPI_SOCROM_MISO 42 PLACE_NEAR=U3900.AN3:5MM
BI IN
58 48 OUT
I2C_SPKRAMP_L_SCL U30 I2C0_SCL SYM 2 OF 17
I2C/UART/SPI/I2S
SPI0_MOSI AM4 SPI_SOCROM_MOSI_R R4171 20 1 2 SPI_SOCROM_MOSI OUT 42

SPI0_SCLK AN3 SPI_SOCROM_CLK_R R4172 20 1 2 5% 1/20W MF 201

SPI_SOCROM_CLK 42
59 48 I2C_SPKRAMP_R_SDA AB32 I2C1_SDA 5% 1/20W MF 201
OUT
BI
SPI0_SSIN AP6 SPI_SOCROM_CS_L 42
59 48 I2C_SPKRAMP_R_SCL V30 I2C1_SCL OUT
OUT
(IPU) SPI1_MISO K30 SPI_TPAD_MISO 42 43
57 48 I2C_CODEC_SDA H30 I2C2_SDA IN
BI
SPI1_MOSI J30 SPI_TPAD_MOSI_R 43
57 48 I2C_CODEC_SCL P28 I2C2_SCL OUT
OUT
SPI1_SCLK K33 SPI_TPAD_CLK_R 43
OUT
48 I2C_ALS_SDA V28 I2C3_SDA SPI1_SSIN R28 SPI_TPAD_CS_L 62
BI OUT
48 I2C_ALS_SCL AB33 I2C3_SCL
OUT
SPI2_MISO B17 SPI_MESA_MISO 44
IN
48 I2C_DFR_SDA L33 I2C4_SDA SPI2_MOSI C17 SPI_MESA_MOSI_R 43
BI OUT
48 I2C_DFR_SCL R29 I2C4_SCL SPI2_SCLK D16 SPI_MESA_CLK_R 43
OUT OUT
SPI2_SSIN A17 WLAN_THROTTLE 32 33
43 NC_I2C_SOC_5_SDA M29 I2C5_SDA OUT

43 NC_I2C_SOC_5_SCL R30 I2C5_SCL SPI3_MISO C14 SPI_DFR_MISO 43

IN
SPI3_MOSI D15 SPI_DFR_MOSI_R 43
83 59 SPKR_ID1 J33 I2C6_SDA (IPU) OUT
IN
SPI3_SCLK C16 SPI_DFR_CLK_R 43
83 58 SPKR_ID0 L29 I2C6_SCL (IPU)
OUT
IN
SPI3_SSIN A16 SPI_DFR_CS_L 46 83
OUT

B 83 SOC_DEBUGPRT_RX V32 UART0_RXD (IPU)

(IPD) I2S0_DIN Y28 I2S_SPKRAMP_L_D2R 58 59
B
83 SOC_DEBUGPRT_TX U32 UART0_TXD IN
I2S0_DOUT AC32 I2S_SPKRAMP_L_R2D_R 43
OUT
45 UART_SE_D2R B15 UART1_RXD I2S0_BCLK Y29 I2S_SPKRAMP_L_BCLK_R 43
IN OUT
45 UART_SE_R2D A15 UART1_TXD I2S0_LRCK AE32 I2S_SPKRAMP_L_LRCLK 43
OUT OUT
45 UART_SE_D2R_CTS_L D13 UART1_CTS* I2S0_MCK AM33 NC_DFR_TOUCH_RSVD 43
IN
45 UART_SE_R2D_RTS_L E12 UART1_RTS*
OUT
I2S1_DIN C18 I2S_SPKRAMP_R_D2R 43
IN
43 NC_UART_BT_D2R F32 UART2_RXD I2S1_DOUT E17 I2S_SPKRAMP_R_R2D_R 43
OUT
43 NC_UART_BT_R2D F30 UART2_TXD I2S1_BCLK D17 I2S_SPKRAMP_R_BCLK_R 43
OUT
43 NC_UART_BT_D2R_CTS_L M28 UART2_CTS* I2S1_LRCK B18 I2S_SPKRAMP_R_LRCLK 43
OUT
43 NC_UART_BT_R2D_RTS_L K28 UART2_RTS* I2S1_MCK D18 NC_PCHROM_SW_EN 43

32 UART_BT_LH_D2R H32 UART3_RXD (IPD) I2S2_DIN Y33 I2S_CODEC_D2R 57

IN IN
32 UART_BT_LH_R2D J32 UART3_TXD I2S2_DOUT AA33 I2S_CODEC_R2D_R 43
OUT OUT
43 NC_UART_GNSS_D2R_CTS_L H33 UART3_CTS* I2S2_BCLK AE33 I2S_CODEC_BCLK_R 43
OUT
43 NC_UART_GNSS_R2D_RTS_L P30 UART3_RTS* I2S2_LRCK V29 I2S_CODEC_LRCLK 43
OUT
I2S2_MCK AL30 NC_I2S_CODEC_MCLK 43
43 32 UART_WLAN_D2R B14 UART4_RXD
IN
32 UART_WLAN_R2D A14 UART4_TXD I2S3_DIN R32 NC_I2S_HAWKING_D2R 43
OUT
43 32 UART_WLAN_D2R_CTS_L C13 UART4_CTS* I2S3_DOUT U33 NC_I2S_CODEC1_R2D_R 43
IN
32 UART_WLAN_R2D_RTS_L D12 UART4_RTS* I2S3_BCLK T33 NC_I2S_HAWKING_BCLK_R 43
OUT
I2S3_LRCK U29 NC_I2S_HAWKING_LRCLK 43

I2S3_MCK V33 NC_I2S_CODEC1_MCLK 43

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

SOC ISP/I2C/UART/SPI/I2S
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 36 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
14 PCIE_SOC_D2R_P<0>
C4210 1 2
20% 6.3V X5R 0201 PCIE_SOC_D2R_C_P<0> B10 PCIE_UP_TX0_P
FCCSP
TMIB21B0-B7 PCIE_DN_TX0_P AP28 NC_PCIE_WLAN_R2D_C_P 43
OUT
0.22UF C10
PCIE_SOC_D2R_N<0> PCIE_SOC_D2R_C_N<0> PCIE_UP_TX0_N SYM 1 OF 17 PCIE_DN_TX0_N AN28 NC_PCIE_WLAN_R2D_C_N
14 OUT
C4211 1 2
20% 6.3V X5R 0201 43 PCIE_SOC_R2D_P<0> E10 PCIE_UP_RX0_P
PCIE UP/DN
PCIE_DN_RX0_P AL28 NC_PCIE_WLAN_D2R_P
43

43
0.22UF IN
F10 AK28
43 IN
PCIE_SOC_R2D_N<0> PCIE_UP_RX0_N PCIE_DN_RX0_N NC_PCIE_WLAN_D2R_N 43

14 PCIE_SOC_D2R_P<1>
C4212 1 2
20% 6.3V X5R 0201 PCIE_SOC_D2R_C_P<1> A9 PCIE_UP_TX1_P PCIE_DN_TX1_P AN27 NC_PCIE_ENET_R2D_C_P 43
OUT
0.22UF
D 14 OUT
PCIE_SOC_D2R_N<1>
C4213 1 2 PCIE_SOC_D2R_C_N<1> B9 PCIE_UP_TX1_N PCIE_DN_TX1_N AM27 NC_PCIE_ENET_R2D_C_N 43 D
20% 6.3V X5R 0201 43 PCIE_SOC_R2D_P<1> D9 PCIE_UP_RX1_P PCIE_DN_RX1_P AK27 NC_PCIE_ENET_D2R_P 43
0.22UF IN
E9 AJ27
43 IN
PCIE_SOC_R2D_N<1> PCIE_UP_RX1_N PCIE_DN_RX1_N NC_PCIE_ENET_D2R_N 43

14 PCIE_SOC_D2R_P<2>
C4214 1 2
20% 6.3V X5R 0201 PCIE_SOC_D2R_C_P<2> B8 PCIE_UP_TX2_P PCIE_DN_TX2_P AP26 NC_PCIE_DN2_R2D_C_P 43
OUT
0.22UF C8
PCIE_SOC_D2R_N<2> PCIE_SOC_D2R_C_N<2> PCIE_UP_TX2_N PCIE_DN_TX2_N AN26 NC_PCIE_DN2_R2D_C_N
14 OUT
C4215 1 2
20% 6.3V X5R 0201 43 PCIE_SOC_R2D_P<2> E8 PCIE_UP_RX2_P PCIE_DN_RX2_P AL26 NC_PCIE_DN2_D2R_P
43

43
0.22UF IN
F8 AK26
43 IN
PCIE_SOC_R2D_N<2> PCIE_UP_RX2_N PCIE_DN_RX2_N NC_PCIE_DN2_D2R_N 43

14 PCIE_SOC_D2R_P<3>
C4216 1 2
20% 6.3V X5R 0201 PCIE_SOC_D2R_C_P<3> A7 PCIE_UP_TX3_P PCIE_DN_TX3_P AN25 NC_PCIE_DN3_R2D_C_P 43
OUT
0.22UF B7
PCIE_SOC_D2R_N<3> PCIE_SOC_D2R_C_N<3> PCIE_UP_TX3_N PCIE_DN_TX3_N AM25 NC_PCIE_DN3_R2D_C_N
14 OUT
C4217 1 2
20% 6.3V X5R 0201 43 PCIE_SOC_R2D_P<3> D7 PCIE_UP_RX3_P PCIE_DN_RX3_P AK25 NC_PCIE_DN3_D2R_P
43

43
0.22UF IN
E7 AJ25
43 IN
PCIE_SOC_R2D_N<3> PCIE_UP_RX3_N PCIE_DN_RX3_N NC_PCIE_DN3_D2R_N 43

14 OUT
SOC_CLKREQ_L R4218 1 2
5% 1/20W MF 201
SOC_CLKREQ_R_L A18 PCIE_UP_CLKREQ* PCIE_DN_REFCLK0_P AK23 NC_PCIE_CLK100M_WLAN_P 43
1K G12 PCIE_DN_REFCLK0_N AL23 NC_PCIE_CLK100M_WLAN_N 43
84 14 PCIE_CLK100M_SOC_P PCIE_UP_EXT_REFCLK_P AG29
IN
G11 PCIE_DN_CLKREQ0* NC_WLAN_CLKREQ_L 43
84 14 PCIE_CLK100M_SOC_N PCIE_UP_EXT_REFCLK_N AJ33
IN
PCIE_DN_PERST0* NC_WLAN_PERST_L 43

SOC_PCIE_UP_REXT G10 PCIE_UP_REXT

PCIE_DN_REFCLK1_P AJ22 NC_PCIE_CLK100M_ENET_P 43
PLACE_NEAR=U3900.G10:5MM AK22
1 PCIE_DN_REFCLK1_N NC_PCIE_CLK100M_ENET_N 43
R4200 PCIE_DN_CLKREQ1* AG30 ENET_CLKREQ_L 37 (UID_MODE strap on A00)
3.01K AG33 NC_ENET_RESET_L
1% PCIE_DN_PERST1* 43
1/20W
MF AN23
2 201 PCIE_DN_REFCLK2_P NC_PCIE_CLK100M_DN2_P 43

PCIE_DN_REFCLK2_N AP23 NC_PCIE_CLK100M_DN2_N 43

PCIE_DN_CLKREQ2* AD29 NC_PCIEDN2_CLKREQ_L 43

PCIE_DN_PERST2* AH29 NC_PCIEDN2_RESET_L 43

PCIE_DN_REFCLK3_P AM22 NC_PCIE_CLK100M_DN3_P

C PCIE_DN_REFCLK3_N AN22 NC_PCIE_CLK100M_DN3_N
43

43
C
PCIE_DN_CLKREQ3* AF33 NC_PCIEDN3_CLKREQ_L 43

PCIE_DN_PERST3* AE30 NC_PCIEDN3_RESET_L 43

PCIE_DN_EXT_REFCLK_P AH25
PCIE_DN_EXT_REFCLK_N AH24

PCIE_DN_REXT AH23 SOC_PCIE_DN_REXT

PLACE_NEAR=U3900.AH23:5MM
R42011
3.01K
1%
1/20W
MF
201 2

OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
FCCSP
77 PCIE_SSD0_R2D_C_P<0> AN8 PCIE_STG0_TX0_P TMIB21B0-B7 PCIE_STG1_TX0_P AN13 NC_PCIE_SSD1_R2D_C_P<0> 43
OUT
77 PCIE_SSD0_R2D_C_N<0> AM8 PCIE_STG0_TX0_N SYM 8 OF 17 PCIE_STG1_TX0_N AM13 NC_PCIE_SSD1_R2D_C_N<0> 43
OUT
PCIE STG 0/1 AK13
84 77 IN
PCIE_SSD0_D2R_P<0> AK8 PCIE_STG0_RX0_P PCIE_STG1_RX0_P NC_PCIE_SSD1_D2R_P<0> 43

84 77 PCIE_SSD0_D2R_N<0> AJ8 PCIE_STG0_RX0_N PCIE_STG1_RX0_N AJ13 NC_PCIE_SSD1_D2R_N<0> 43

IN

78 PCIE_SSD0_R2D_C_P<1> AP9 PCIE_STG0_TX1_P PCIE_STG1_TX1_P AP14 NC_PCIE_SSD1_R2D_C_P<1> 43

OUT
78 PCIE_SSD0_R2D_C_N<1> AN9 PCIE_STG0_TX1_N PCIE_STG1_TX1_N AN14 NC_PCIE_SSD1_R2D_C_N<1> 43
OUT
B 78 IN
PCIE_SSD0_D2R_P<1> AL9 PCIE_STG0_RX1_P PCIE_STG1_RX1_P AL14 NC_PCIE_SSD1_D2R_P<1> 43 B
78 PCIE_SSD0_D2R_N<1> AK9 PCIE_STG0_RX1_N PCIE_STG1_RX1_N AK14 NC_PCIE_SSD1_D2R_N<1> 43
IN

79 PCIE_SSD0_R2D_C_P<2> AN10 PCIE_STG0_TX2_P PCIE_STG1_TX2_P AN15 NC_PCIE_SSD1_R2D_C_P<2> 43

OUT
79 PCIE_SSD0_R2D_C_N<2> AM10 PCIE_STG0_TX2_N PCIE_STG1_TX2_N AM15 NC_PCIE_SSD1_R2D_C_N<2> 43
OUT
79 PCIE_SSD0_D2R_P<2> AK10 PCIE_STG0_RX2_P PCIE_STG1_RX2_P AK15 NC_PCIE_SSD1_D2R_P<2> 43
IN
79 PCIE_SSD0_D2R_N<2> AJ10 PCIE_STG0_RX2_N PCIE_STG1_RX2_N AJ15 NC_PCIE_SSD1_D2R_N<2> 43
IN

80 PCIE_SSD0_R2D_C_P<3> AP11 PCIE_STG0_TX3_P PCIE_STG1_TX3_P AP16 NC_PCIE_SSD1_R2D_C_P<3> 43

OUT
80 PCIE_SSD0_R2D_C_N<3> AN11 PCIE_STG0_TX3_N PCIE_STG1_TX3_N AN16 NC_PCIE_SSD1_R2D_C_N<3> 43
OUT
80 PCIE_SSD0_D2R_P<3> AL11 PCIE_STG0_RX3_P PCIE_STG1_RX3_P AL16 NC_PCIE_SSD1_D2R_P<3> 43
IN
80 PCIE_SSD0_D2R_N<3> AK11 PCIE_STG0_RX3_N PCIE_STG1_RX3_N AK16 NC_PCIE_SSD1_D2R_N<3> 43
IN

84 78 77 OUT
PCIE_CLK100M_SSD0_01_P AK18 PCIE_STG0_REFCLK01_P PCIE_STG1_REFCLK01_P AN18 NC_PCIE_CLK100M_SSD1_01_P 43

84 78 77 OUT
PCIE_CLK100M_SSD0_01_N AL18 PCIE_STG0_REFCLK01_N PCIE_STG1_REFCLK01_N AP18 NC_PCIE_CLK100M_SSD1_01_N 43

77 43 IN
SSD0_CLKREQ0_L AM30 PCIE_STG0_CLKREQ0* PCIE_STG1_CLKREQ0* C15 NC_SSD1_CLKREQ0_L 43

78 43 IN
SSD0_CLKREQ1_L AK30 PCIE_STG0_CLKREQ1* PCIE_STG1_CLKREQ1* E15 NC_SSD1_CLKREQ1_L 43

84 80 79 OUT
PCIE_CLK100M_SSD0_23_P AJ19 PCIE_STG0_REFCLK23_P PCIE_STG1_REFCLK23_P AM19 NC_PCIE_CLK100M_SSD1_23_P 43

84 80 79 OUT
PCIE_CLK100M_SSD0_23_N AK19 PCIE_STG0_REFCLK23_N PCIE_STG1_REFCLK23_N AN19 NC_PCIE_CLK100M_SSD1_23_N 43

79 43 IN
SSD0_CLKREQ2_L AL33 PCIE_STG0_CLKREQ2* PCIE_STG1_CLKREQ2* E14 NC_SSD1_CLKREQ2_L 43

80 43 IN
SSD0_CLKREQ3_L AK33 PCIE_STG0_CLKREQ3* PCIE_STG1_CLKREQ3* D14 NC_SSD1_CLKREQ3_L 43

80 79 78 77 43 OUT
SSD0_PCIE_RESET_L AM32 PCIE_STG0_PERST* PCIE_STG1_PERST* AK32 NC_SSD1_PCIE_RESET_L 43

43 OUT
SSD0_CLK24M_R AM6 PCIE_STG0_NANDCLK PCIE_STG1_NANDCLK AM2 NC_SSD1_CLK24M_R 43

A AH12 PCIE_STG0_EXT_REFCLK_P PCIE_STG1_EXT_REFCLK_P AH17 SYNC_MASTER= SYNC_DATE=

A
AH13 PCIE_STG0_EXT_REFCLK_N PCIE_STG1_EXT_REFCLK_N AH18 PAGE TITLE

SOC PCIE
SOC_PCIE_STG0_REXT AH14 PCIE_STG0_REXT PCIE_STG1_REXT AH19 SOC_PCIE_STG1_REXT DRAWING NUMBER SIZE

PLACE_NEAR=U3900.AH14:5MM PLACE_NEAR=U3900.AH19:5MM 051-05309 D

1
R4250 R4251 1 Apple Inc. REVISION
3.01K
1%
3.01K
1%
5.1.0
1/20W 1/20W NOTICE OF PROPRIETARY PROPERTY: BRANCH
PP1V8_AWAKE 27 40 42 43 62 70 72 83 MF MF
2 201 201 2 THE INFORMATION CONTAINED HEREIN IS THE
R4232 47K 1 2
5% 1/20W MF 201
ENET_CLKREQ_L 37
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 37 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3 OMIT_TABLE
CRITICAL

U3900
POP-1GB-20NM-M-SCK
86 83 70 43 PPVDDCPU_AWAKE FCCSP PPVDDCPUSRAM_AWAKE 70 83 86

0.625V - 1.06V AA12 TMIB21B0-B7 AA10 0.8V - 1.06V

11.6A Max AA14 SYM 10 OF 17 N10 0.9A Max
AA16 R16
C4300 C4301 C4302 C4303 C4304 AB11 T11
C4350 C4351 C4352 C4353 C4354 C4357
9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF
20% 20% 20% 20% 20% AB13 T13 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
CERM CERM CERM CERM CERM AB15 VDD_CPU_SRAM T15 CERM CERM CERM CERM CERM CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
1 3 1 3 1 3 1 3 1 3 N12 U10 1 3 1 3 1 3 1 3 1 3 1 3
D N14 V11 D
2 4 2 4 2 4 2 4 2 4 N16 V13 2 4 2 4 2 4 2 4 2 4 2 4
P11 V15
P13 W16
P15
R10 VDD_CPU
C4305 C4306 C4307 C4308 C4309 R12
C4355 C4356 C4360
9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF 9.1UF
20% 20% 20% 20% 20% R14 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
CERM CERM CERM CERM CERM U12 CERM CERM CERM
0402 0402 0402 0402 0402 0402 0402 0402
1 3 1 3 1 3 1 3 1 3 U14 1 3 1 3 1 3
U16
2 4 2 4 2 4 2 4 2 4 W10 2 4 2 4 2 4
W12 VDD_CPU_SENSE M17 SOC_VDDCPU_SENSE 72 84
OUT
W14
Y11 VSS_CPU_SENSE M16 NC_SOC_VSSCPU_SENSE
Y13
C4320 C4321 C4322 C4323 C4324 Y15
9.1UF 9.1UF 9.1UF 9.1UF 9.1UF
20% 20% 20% 20% 20%
4V 4V 4V 4V 4V
CERM CERM CERM CERM CERM
0402 0402 0402 0402 0402
1 3 1 3 1 3 1 3 1 3

2 4 2 4 2 4 2 4 2 4

C4330 C4331 C4332 C4333 C4334

C 9.1UF
20%
9.1UF
20%
9.1UF
20%
9.1UF
20%
9.1UF
20%
C
4V 4V 4V 4V 4V
CERM CERM CERM CERM CERM
0402 0402 0402 0402 0402
1 3 1 3 1 3 1 3 1 3

2 4 2 4 2 4 2 4 2 4

OMIT_TABLE
CRITICAL

U3900
PP0V82_SLPDDR POP-1GB-20NM-M-SCK
86 83 70 43
FCCSP
5.6A Max AC10 TMIB21B0-B7 R18
AC12 SYM 11 OF 17 R20
AC14 R22
C4370 C4371 C4372 C4373 AC16 R24
9.1UF 9.1UF 9.1UF 9.1UF
20% 20% 20% 20% AC18 T19
4V 4V 4V 4V
CERM CERM CERM CERM AC20 T21
0402 0402 0402 0402
1 3 1 3 1 3 1 3 AC22 T23
AC24 T25
2 4 2 4 2 4 2 4 AD11 VDD_SOC W18
B AD13 W20 B
AD15 W22
AD17 W24
AD19 Y17
C4380 C4381 AD21 Y19
9.1UF 9.1UF
20% 20% AD23 VDD_SOC Y21
4V 4V
CERM CERM AD25 Y23
0402 0402
1 3 1 3 L10
L12
2 4 2 4 L14
L16
L18
L20
L22
C4385 C4386 L24 VDD_SOC_SENSE Y25 NC_SOC_VDDSOC_SENSE
9.1UF 9.1UF
20% 20% M11
4V 4V VSS_SENSE Y26 NC_SOC_VSSSOC_SENSE
CERM CERM M13
0402 0402
1 3 1 3 M15
M19
2 4 2 4 M21
M23
M25

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

SOC POWER 1
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 38 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3 R4460
1
5.1 2
1% 1/20W MF 0201
OMIT_TABLE
CRITICAL FL4400
120-OHM-25%-0.48A-0.21DCR
U3900 83 71 40 39 34 PP1V1_SLPDDR 1 2
POP-1GB-20NM-M-SCK 8mA Max 0201
83 71 40 39 34 PP1V1_SLPDDR FCCSP
0.86A Max C3 TMIB21B0-B7 VDDIO11_PLL_DDR0 H9 PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F
E3 13 OF 17 G26 MIN_LINE_WIDTH=0.2000
VDDIO11_PLL_DDR1 MIN_NECK_WIDTH=0.1000
VOLTAGE=1.1V
C4450 1 C4451 1 C4452 1 C4453 1 G3 VDDIO11_PLL_DDR2 AG8 1 C4460 1 C4461 1 C4462 1 C4463
2.2UF 2.2UF 2.2UF 2.2UF H8 AF26 0.22UF 0.22UF 0.22UF 0.22UF
D 20%
4V
20%
4V
20%
4V
20%
4V J9
VDDIO11_PLL_DDR3 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
D
X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 VDDIO11_DDR0 X6S-CERM X6S-CERM X6S-CERM X6S-CERM
0201 0201 0201 0201 K8 0201 0201 0201 0201
L9
P3
R3
C4454 1 C4455 1 C4456 1 C4457 1 U3
2.2UF 2.2UF 2.2UF 2.2UF VDDIO11_RET_DDR0 G4 PP1V1_SLPS2R 40 70 71 83 86
20% 20% 20% 20%
4V 4V 4V 4V VDDIO11_RET_DDR1 D30 Current included in VDD2
X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2
0201 0201 0201 0201
C33 VDDIO11_RET_DDR2 AJ4 1 C4470 1 C4471 1 C4472 1 C4473
VDDIO11_RET_DDR3 AJ30 2.2UF 2.2UF 2.2UF 2.2UF
E31 20% 20% 20% 20%
G31 2 4V
X6S-CERM 2 4V
X6S-CERM 2 4V
X6S-CERM 2 4V
X6S-CERM
0201 0201 0201 0201
H27
J26
K27 VDDIO11_DDR1
L26
P31
R31
U31

PP0V9_SLPDDR OMIT_TABLE
86 83 70 43 39
CRITICAL
1.9A Max
AB3
AC9
C4400 C4401 C4402 U3900 AD3
9.1UF 9.1UF 9.1UF
20% 20% 20% POP-1GB-20NM-M-SCK AD8
4V 4V 4V FCCSP
CERM CERM CERM AA18 K21 AE3
0402 0402 0402 TMIB21B0-B7 VDDIO11_DDR2
C 1 3 1 3 1 3 AA20
AA22
SYM 12 OF 17 K23
K25
AE9
AF8
C
2 4 2 4 2 4 AA24 N18 AK3
AB17 N20 AM3
AB19 N22
AB21 N24
AB23 P17
C4405 C4406 AB25 P19
9.1UF 9.1UF AA27
20% 20% AE10 P21
4V 4V AB26
CERM CERM AE12 P23
0402 0402 AB31
1 3 1 3 AE14 VDD_FIXED P25
AC27
AE16 U18
2 4 2 4 AD26
AE18 U20
AD31 VDDIO11_DDR3
AE20 U22
AE27
AE22 VDD_FIXED U24
AE31
AE24 V19
AK31
AE26 V21
C4410 C4411 AG9 V23
AM31
9.1UF 9.1UF
20% 20% J10 V25
4V 4V
CERM CERM J12
0402 0402
1 3 1 3 J14
J16
2 4 2 4 J18
J20
J22 PP0V9_SLPDDR 39 43 70 83 86
J24 330mA Max
K11
B K13
C4430 C4431 B
4.3UF 4.3UF
K15 20% 20%
4V 4V
K17 CERM CERM
0402 0402
K19 1 3 1 3

9mA Max 2 4 2 4
86 83 70 43 39 PP0V9_SLPDDR U17 VDD_FIXED_CPU AG11
VDD_FIXED_STG0_PCIE_ANA AG12 PP0V9_SLPDDR 39 43 70 83 86
86 83 70 43 39 PP0V9_SLPDDR G19 VDD_FIXED_USB AG14 330mA Max
5mA Max
AF11 C4435 C4436
86 83 70 43 39 PP0V9_SLPDDR AF13 4.3UF 4.3UF
H20 VDD_FIXED_STG0_PCIE_CLK 20% 20%
25mA Max AF15 4V
CERM
4V
CERM
H22
C4420 H24
VDD_FIXED_MIPI
AG16 1
0402
3 1
0402
3
4.3UF
20% AG18
4V VDD_FIXED_STG1_PCIE_ANA
CERM AG20 2 4 2 4
0402
1 3
AF17 PP0V9_SLPDDR 39 43 70 83 86

2 4 VDD_FIXED_STG1_PCIE_CLK AF19 330mA Max

AG15
M9 C4440 C4441
P9 AG23 4.3UF 4.3UF
20% 20%
T9 AG24 4V 4V
VDD_LOW VDD_FIXED_DN_PCIE_ANA CERM CERM
83 71 PP0V8_SLPS2R V9 AG26 0402 0402
102mA Max 1 3 1 3
Y9
C4423 1 AF23
2 4 2 4
2.2UF VDD_FIXED_DN_PCIE_CLK AF24
20%
A 4V
X6S-CERM 2
0201
H10
H12
AF25
SYNC_MASTER= SYNC_DATE=
A
H14
VDD_FIXED_UP_PCIE_ANA AE13 R4445 PP0V9_SLPDDR 39 43 70 83 86
PAGE TITLE
0
86 83 70 43 39 PP0V9_SLPDDR
H13
AE19
AE23
PP0V9_SLPDDR_SOC_PCIEREFBUF
MIN_LINE_WIDTH=0.2000
2 1 45mA Max SOC POWER 2
330mA Max VDD_FIXED_PCIE_REFBUF C4445 MIN_NECK_WIDTH=0.1000 5%
1/20W
DRAWING NUMBER SIZE
VOLTAGE=0.9V
C4425 C4426 J11 VDD_FIXED_UP_PCIE_CLK AF21 4.3UF MF 051-05309 D
4.3UF 4.3UF J13 AG22 20%
4V
0201
Apple Inc. REVISION
20% 20% CERM
4V
CERM
4V
CERM
0402 5.1.0
0402 0402 1 3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 3 1 3 THE INFORMATION CONTAINED HEREIN IS THE
2 4 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 4 2 4 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
44 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 39 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

D D

OMIT_TABLE
CRITICAL

U3900
89
PP1V8_SLPS2R POP-1GB-20NM-M-SCK PP1V2_AWAKE
60 47 44 43 42 40 34 29 28 27
86 83 81 74 72 71 70 64 63
A4
FCCSP 40 71 83
R4555 PP1V2_AWAKE 40 71 83
134mA Max TMIB21B0-B7 VDD12_CPU_UVD V17 10mA Max 0
AP3
1 2 13mA Max
SYM 14 OF 17
5%
C4500 1 C4501 1 C4502 1 C4503 1 AP30 1 C4550 C4555 1
1/20W
MF
2.2UF 2.2UF 2.2UF 2.2UF B32 2.2UF 0201
20% 20% 20% 20% VDD1 20% 0.1UF
4V 4V 4V 4V W2 2 4V 10%
X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 6.3V 2
0201 0201 0201 0201 W32 0201 X6S
0201
89
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R Y2
86 83 81 74 72 71 70 64 63
Y32 VOLTAGE=1.2V
20mA Max MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VDD12_PLL_CPU T17 PP1V2_AWAKE_SOC_PLLCPU_F R4560
C4510 1
C4511 C4512 C4513 1 M8
0
PP1V2_AWAKE 40 71 83
2.2UF 9.1UF 9.1UF 0.1UF N9 AF22 PP1V2_AWAKE_SOC_PCIEREFBUF_F 1 2 80mA Max
20% 20% 20% 10% VDD12_PCIE_REFBUF VOLTAGE=1.2V
4V 4V 4V 6.3V 2 P8 AH21 MIN_LINE_WIDTH=0.2000 5%
X6S-CERM 2 CERM CERM X6S VDDIO18_AOP1 MIN_NECK_WIDTH=0.1000 1/20W
0201 0402 0402 0201 R9 C4560 1 MF
0201
1 C4561 1 C4562
C 1 3 1 3 U9
W9
0.1UF
10%
6.3V 2
0.1UF
10% 20%
2.2UF C
R4515 2 6.3V 2 4V
89
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R 2 4 2 4 X6S
0201
X6S
0201
X6S-CERM
0201
86 83 81 74 72 71 70 64 63 49.9 AA9
1mA Max 1 2
1% AB8 VDDIO18_AOP2
1/20W VOLTAGE=1.89
MF MIN_LINE_WIDTH=0.2000
201 MIN_NECK_WIDTH=0.1000 VDD12_DN_PCIE AJ24
R4519 PP1V8_SLPS2R_SOC_LPADC_RC AA8 VDD18_LPADC VDD12_UP_PCIE G13 R4565 PP1V2_AWAKE 40 71 83
89
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R 0
86 83 81 74 72 71 70 64 63 49.9 Y10 PP1V2_AWAKE_SOC_PCIEPLL_F 1 2 60mA Max
1mA Max 1 2 PP1V8_SLPS2R_SOC_LPOSC_RC VDD18_LPOSC VDD12_STG0_PCIE AH11 VOLTAGE=1.2V
VOLTAGE=1.89 MIN_LINE_WIDTH=0.2000 5%
1% MIN_LINE_WIDTH=0.2000 VDD12_STG1_PCIE AH16 MIN_NECK_WIDTH=0.1000 1/20W
1/20W
MF
MIN_NECK_WIDTH=0.1000
C4519 1 C4515 1 M27 C4565 1 C4566 1 C4567 1 C4568 1 MF
0201
201 2.2UF 2.2UF 2.2UF 2.2UF
2.2UF 20UF N26 20%
4V
20%
4V
20%
4V
20%
4V
20% 20%
4V 2.5V 2 P27 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2
X6S-CERM 2 X6S-CERM 0201 0201 0201 0201
0201 0402 R26
T27 VDDIO18_GRP1
U26 R4570 PP1V2_AWAKE 40 71 83
83 72 70 62 43 42 40 37 27 PP1V8_AWAKE V27 AA21 0
PP1V2_AWAKE_SOC_PLLSOC_F 1 2 31mA Max
40mA Max W26 AB20 VOLTAGE=1.2V
5%
VDD12_PLL_SOC MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 1/20W
C4521 1 C4522 1 C4523 1
Y20 C4570 1 C4571 1 MF 1 C4572
2.2UF 2.2UF 2.2UF
C4524 C4525 C4526 C4527 0.1UF
10%
0.1UF
10%
0201
20%
2.2UF
9.1UF 9.1UF 9.1UF 9.1UF AG3 6.3V 2 6.3V 2
20%
4V
20%
4V
20%
4V 20% 20% 20% 20% G15 X6S X6S 2 4V
X6S-CERM
X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 4V 4V 4V 4V AG31 0201 0201 0201
0201 0201 0201 CERM CERM CERM CERM G17
0402 0402 0402 0402 AJ3
1 3 1 3 1 3 1 3 H16 VDDIO18_GRP2
AJ31
H18
2 4 2 4 2 4 2 4 AN2
AN30 PP1V1_SLPS2R 39 70 71 83 86

AN31 1.74A Max

B AE28 B3
1 C4580 1 C4581 1 C4582 1 C4583 B
83 72 70 62 43 42 40 37 27 PP1V8_AWAKE R4530 AG28 VDDIO18_GRP3 B4
2.2UF 2.2UF 2.2UF 2.2UF
0 PP1V8_AWAKE_SOC_TSADC_RC C31 20% 20% 20% 20%
2MA MAX 1 2
AH9
VOLTAGE=1.8V D32 2 4V
X6S-CERM
4V
2 X6S-CERM 2 4V
X6S-CERM 2 4V
X6S-CERM
5% MIN_LINE_WIDTH=0.2000 VDD2
1/20W MIN_NECK_WIDTH=0.1000 AH10 VDDIO18_GRP4 0201 0201 0201 0201
MF
0201
C4530 1 J3
1UF J31
20% W17
6.3V K3
X6S-CERM 2 N15
0201 K31
AA15
VDD18_TSADC M3
AC17
M31
H25
83 72 70 62 43 42 40 37 27 PP1V8_AWAKE W3
7mA Max G20 W31
PP1V8_AWAKE G22 Y3
83 72 70 62 43 42 40 37 27
VDD18_MIPI R4590
20mA Max C4535 1 C4536 1 G24 Y31
1
5.1 2
2.2UF 0.1UF 1% 1/20W MF 0201
20% 10%
C4540 1 4V
X6S-CERM 2
6.3V 2
X6S L4590
0.1UF 0201 0201
FERR-240OHM-25%-350MA
10%
6.3V 2 PP1V1_SLPDDR 34 39 71 83
X6S
0201 VDD11_XTAL AJ20 PP1V1_SLPDDR_SOC_XTAL_F 1 2 4mA Max
VOLTAGE=1.1V 0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
H19 VDD18_USB C4590 1 1 C4591
PP3V3_AWAKE 0.1UF 2.2UF
83 72 70 62 43 42 40 37 27 PP1V8_AWAKE R4545 PP1V8_AWAKE_SOC_FMON_RC AC11 VDD18_FMON
71 83
10% 20%
49.9 VOLTAGE=1.8V VDD33_USB F21 12mA Max 6.3V 2
X6S 2 4V
X6S-CERM
1mA Max 1 2 MIN_LINE_WIDTH=0.2000 AH28 0201 0201
MIN_NECK_WIDTH=0.1000 VDD18_EFUSE1
1%
1/20W
MF C4545 1
AF10 VDD18_EFUSE2 1 C4595
201 0.1UF
1UF 10%
A 20%
6.3V
X6S-CERM 2
2 6.3V
X6S
0201 SYNC_MASTER= SYNC_DATE=
A
0201 PAGE TITLE

SOC POWER 3
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
45 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 40 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

U3900 U3900 U3900

POP-1GB-20NM-M-SCK POP-1GB-20NM-M-SCK POP-1GB-20NM-M-SCK
FCCSP FCCSP FCCSP
A1 TMIB21B0-B7 AG13 AP10 TMIB21B0-B7 F18 N23 TMIB21B0-B7 T32
A2 SYM 15 OF 17 AG17 AP12 SYM 16 OF 17 F19 N25 SYM 17 OF 17 U11
A3 AG19 AP13 OMIT_TABLE F20 N27 OMIT_TABLE U13
OMIT_TABLE
A6 AG21 AP15 CRITICAL F24 N29 CRITICAL U15
CRITICAL
A8 AG25 AP17 F27 N31 U19
A10 AG27 AP19 F31 N32 U21
A11 AG32 AP22 G5 P7 U23

D A19 AH3 AP24 G7 P10 U25 D

A21 AH7 AP25 G8 P12 U27
A28 AH8 AP27 G9 P14 V2
A31 AH15 AP29 G14 P16 V3
A32 AH20 AP31 G16 P18 V5
A33 AH22 AP32 G18 P20 V10
AA2 AH26 AP33 G21 P22 V12
AA3 AH27 B1 G23 P24 V14
AA5 AH31 B2 G25 P26 V16
AA7 AJ7 B6 G27 R2 V18
AA11 AJ9 B11 G29 R5 V20
AA13 AJ11 B13 G32 R7 V22
AA17 AJ12 B16 H3 R8 V24
AA19 AJ14 B19 H5 R11 VSS VSS V26
AA23 AJ16 B21 H7 R13 V31
AA25 AJ17 B28 H11 R15 W4
AA26 AJ18 B31 H15 R17 W11
AA31 AJ21 B33 H17 R19 W13
AA32 AJ23 C1 H21 R21 W15
AB7 AJ26 C6 H23 R23 W19
AB9 AJ28 C7 H26 R25 W21
AB10 AJ29 C9 H31 R27 W23
AB12 AK7 C11 J2 T3 W25
AB14 AK12 C19 J5 T7 W27
AB16 AK17 C20 J7 T8 W29
AB18 AK20 C21 J8 T10 W30
AB22 AK21 C22 J15 T12 Y4
C AB24 AK24 C23 J17 T14 Y12 C
AB27 AK29 C24 J19 T16 Y14
AB29 AL2 C25 J21 T18 Y16
AC3 AL3 C26 J23 T20 Y18
AC7 AL5 C27 J25 T22 Y22
AC8 AL7 C28 J27 T24 Y24
AC13 AL8 C29 VSS K7 T26 Y27
AC15 AL10 C30 VSS K9 T29 Y30
AC19 VSS AL12 C32 K10 T31
VSS
AC21 AL13 D2 K12
AC23 AL15 D3 K14
AC25 AL17 D5 K16
AC26 AL19 D6 K18
AC31 AL20 D8 K20
AD2 AL21 D10 K22
AD5 AL22 D11 K24
AD7 AL24 D19 K26
AD9 AL25 D21 K29
AD10 AL27 D22 K32
AD12 AL29 D23 L3
AD14 AL31 D24 L7
AD16 AL32 D25 L8
AD18 AM7 D26 L11
AD20 AM9 D27 L13
AD22 AM11 D28 L15
AD24 AM12 D29 L17
B AD27 AM14 E6 L19 B
AD32 AM16 E11 L21
AE7 AM17 E13 L23
AE8 AM18 E16 L25
AE11 AM20 E18 L27
AE15 AM21 E19 L31
AE17 AM23 E21 M2
AE21 AM24 E22 M5
AE25 AM26 E23 M7
AE29 AM28 E24 M10
AF3 AM29 E25 M12
AF7 AN1 E26 M14
AF9 AN7 E27 M18
AF12 AN12 E29 M20
AF14 AN17 F3 M22
AF16 AN20 F6 M24
AF18 AN21 F7 M26
AF20 AN24 F9 N3
AF27 AN29 F11 N7
AF28 AN32 F12 N8
AF31 AN33 F13 N11
AG2 AP1 F14 N13
AG5 AP2 F15 N17
AG7 AP7 F16 N19
AG10 AP8 F17 N21

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

SOC GROUND
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 41 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PCH PM Level Shifting

Boot Config BOOTCFG0 Test Mode
89
60 47 44 43 42 40 34 29 28 27
86 83 81 74 72 71 70 64 63
PP1V8_SLPS2R
BYPASS=U4760.3::5MM BYPASS=U4760.2::5MM
PP3V3_S5 4 5 7 11 12 13 14 18 43 47 69
71 73 74 83 89

PP1V8_AWAKE 27 37 40 42 43 62 70
72 83
C4760 1 1 C4765 1
R4767 1
R4768
0.1UF 0.1UF 100K 100K

2
0 Disabled 10% 10%
10V 5% 5%
BOOTCFG0 BOOTCFG1 BOOTCFG2 1 Enabled X5R-CERM 2 VCCA VCCB 2 10V
X5R-CERM 1/20W 1/20W
0201 0201 MF MF
1
R4700 1
R4701 1
R4702 U4760 2 201 2 201 R4769
1K 1K 1K PQFP 2.2K
5% 5% 5%
1/20W 1/20W 1/20W BOOTCFG2 BOOTCFG1 Frequency 83 35 IN
SMC_SYSRST_L 6 1A1 1B1 15 PM_SYSRST_R_L 1 2 PM_SYSRST_L OUT 13 16 83
MF MF MF 5% 1/20W MF 201
2 201 2 201 2 201 35 IN
SMC_PCH_SYS_PWROK 8 2A1 2B1 13 PM_PCH_SYS_PWROK OUT 13 83
0 0 40 MHz SN74AVC4T245RSV D
D 34 OUT
BOOT_CONFIG0 0 1 6 MHz 4 1DIR
34 OUT
BOOT_CONFIG1 1 0 24 MHz 1 1OE*
34 BOOT_CONFIG2 1 1 Invalid
OUT
35 IN
SMC_PCH_PWROK 7 1A2 1B2 14 PM_PCH_PWROK OUT 13 83

35 18 IN
SMC_RSMRST_L 9 2A2 2B2 12 PM_RSMRST_L OUT 13 16 83

5 2DIR

Board ID R47602
100K
5%
R47612
100K
5%
R47621
100K
5%
R47631
100K
5%
16 2OE*
CRITICAL
1

5%
R4765
100K
1

5%
R4766
100K
PP1V8_AWAKE 70 72 83
27 37 40
42 43 62
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF GND MF MF
201 1 201 1 201 2 201 2 2 201 2 201
BOARDID0 BOARDID1 BOARDID2 BOARDID3 BOARDID4 BOARDID5

10

11
1 1 1 1 1 1
R4710 R4711 R4712 R4713 R4714 R4715
3.0K 3.0K 3.0K 3.0K 3.0K 3.0K
5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF

42 36 SPI_SOCROM_CLK
2 201 2 201 2 201 2 201 2 201 2 201 PECI Level Shifting
OUT
42 36 OUT
SPI_SOCROM_MOSI PP1V_S3 5 7 9 17 18 65 69 70 83

42 36 OUT
SPI_SOCROM_MISO
62 43 OUT
SPI_TPAD_MOSI U4750
SPI_TPAD_MISO

5
43 36 OUT SN74AUC1G126
62 43 OUT
SPI_TPAD_CLK BOARD_ID[5:0] = 111011 SC70
<RDAR://PROBLEM/51341193> H9M BOARD IDS FOR J223 2 A
4
Y
BYPASS=U4750::5MM OE

C4750 1 CRITICAL

1
Board Revision 0.1UF

3
10%
BOARDREV 10V
PP1V8_AWAKE X5R-CERM 2
C 27 37 40 42 43 62 70 72 83
BUILD <2> <1> <0>
PLACE_NEAR=U3900.R6:5MM
0201
C
BOARDREV0 BOARDREV1 BOARDREV2 PROTO 0 0 0 0 R4750
1 1 1 PROTO 0 0 0 1 0
R4720 R4721 R4722 35 IN
SMC_PECI_TX 1 2 SMC_PECI_TX_R
1K 1K 1K PROTO 1A 0 1 0 5% 1/20W MF 0201
5% 5% 5%
1/20W 1/20W 1/20W PROTO 1B 0 1 1 PP1V8_S5
MF MF MF 32 18 17 16 15 14 13 12 11 7
2 201 2 201 2 201 EVT 1 0 0 83 74 73 72 70 69 65 53 47 42
BYPASS=U4755::5MM BYPASS=U4755::5MM
PVT 1 0 1
34 OUT
BOARD_REV0 C4755 1 1 C4756
34 OUT
BOARD_REV1 0.1UF 0.1UF
10% 10%

6
36 OUT
BOARD_REV2 10V
X5R-CERM 2 VCCA VCCB 2 10V
X5R-CERM
0=NO_STUFF, 1=STUFF 0201 0201
U4755
74AVC1T45
35 OUT
SMC_PECI_RX 3 A SOT886 B 4 CPU_PECI BI 5

5 DIR NC
R47551
CRITICAL 330
5%
SEP EEPROM GND 1/20W
MF

2
201 2
(Write: 0xA2, Read 0xA3)

62 43 42 40 37 27
83 72 70
PP1V8_AWAKE
BYPASS=U4730::6MM
8 1 C4730
0.1UF

R47301 U4730
VCC

M24128
10%
2 10V
X5R-CERM
0201
1
R4731
PROCHOT# Level
rdar://problem/34583713
Shifting
2.2K EEPROM 2.2K B
B 5%
1/20W
3 E2 MLP 5%
1/20W
MF 2 E1 MF 32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42
PP1V8_S5
201 2 1 2 201
E0 BYPASS=U4790::3MM
SEP_WP 7 WC* R47901 1 C4790
10K 0.1UF
5%
34 I2C_SEP_SCL 6 SCL SDA 5 I2C_SEP_SDA 34 1/20W 10%

6
2 10V
IN BI
MF X5R-CERM
VSS THM_P 201 2 VCC 0201
R4732 1 Also available in
U4790
10K 4 9 CSP package 335S0946 74LVC1G07FW5
5%
1/20W DFN1010 R4791
MF
SMC_PROCHOT_L 2 A Y 4 CPU_PROCHOT_OUT_L 1
75 2 CPU_PROCHOT_L
201 2 65 43 35 IN OUT 5

1%
1 NC NC 5 1/20W
NC NC MF
201
GND

3
SoC ROM CRITICAL

62 43 42 40 37 27
83 72 70
PP1V8_AWAKE
BYPASS=U4770::5MM
R4770 1
R4771 1 CRITICAL 1 C4770
8

100K
5%
1/20W
10K
5%
1/20W
VCC 0.1UF
10%
2 10V
SMC AVREF Supply
MF MF U4770 X5R-CERM
0201 Footprint supports 353S01042 alternate
201 2 201 2
4MX8-1.8V
USON U4780
42 36 IN
SPI_SOCROM_CLK 6 SCLK SI/SIO0 5 SPI_SOCROM_MOSI IN 36 42 REF3312AIRSE
MX25U3235F UQFN-COMBO
VER 2 R4773
89
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R PP1V25_SLPS2R_SMC_AVREF 35
86 83 81 74 72 71 70 64 63 MIN_LINE_WIDTH=0.2000
A 36 IN
SPI_SOCROM_CS_L
SPI_SOCROM_WP_L
1 CS*
3 WP*/SIO2 SO/SIO1 2 SPI_SOCROM_MISO_R 1
20 2 SPI_SOCROM_MISO OUT 36 42
5 IN OUT 8 MIN_NECK_WIDTH=0.1000
A
CRITICAL
SYNC_MASTER= SYNC_DATE=

5% MF 1/20W 201 PAGE TITLE

7 RESET*/SIO3 1
PLACE_NEAR=U4770.2:5MM BYPASS=U4780::3MM NC0 BYPASS=U4780::3MM
SOC SHARED SUPPORT
10 EPAD
EPAD

NC
GND

C4780 1 NC1 2
NC
1 C4781
1.0UF NC2 3 1.0UF DRAWING NUMBER SIZE
20% NC 20% 051-05309 D
4

6.3V 2 6 2 6.3V
X5R
0201-1
NC3
7
NC X5R
0201-1
Apple Inc. REVISION
NC4
5.1.0

4 GND
NC
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
GND_SMC_AVSS 35 49 50 51 52 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 42 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PCIe Up R2D AC Caps Triaxial acceleration sensor Lid Detect Sensors

C4820 1 2 NOSTUFF U4870 etc. per <rdar://46140415>
14 IN
PCIE_SOC_R2D_C_P<0>
0.22UF 20% 6.3V X5R 0201 PCIE_SOC_R2D_P<0> OUT 37 L4870 VOLTAGE=1.8
MIN_LINE_WIDTH=0.2000
SMC_LID_LEFT OUT 35 83

PCIE_SOC_R2D_C_N<0> PCIE_SOC_R2D_N<0> FERR-240OHM-25%-350MA MIN_NECK_WIDTH=0.1000

14 IN
C4821 1 2
20% 6.3V X5R 0201
OUT 37

58 57 55 51 48 47 45 44 43 18 PP1V8_G3S 1 2 PP1V8_ACCEL_FILT Clamshell Closed/Open = Low/High PP1V8_SLPS2R 27 28 29 34 40 42 43 44 47 60

0.22UF 83 76 74 68 62 61 60 59 63 64 70 71 72 74 81 83 86 89
0201 NOSTUFF NOSTUFF SMC and U6650 isolated per <rdar://45820207>
C4822 NOSTUFF
PCIE_SOC_R2D_C_P<1>
1 2
PCIE_SOC_R2D_P<1> PLACE_NEAR=U4870.7:2MM 1 C4870 1 C4871 BYPASS=U4802::5MM
20% 6.3V X5R 0201 0.22UF 0.22UF J4800

7
14 37
IN
PCIE_SOC_R2D_C_N<1>
0.22UF
PCIE_SOC_R2D_N<1>
OUT
20% 20% INTERPOSER-AMR-MLB
C4802 1
14 IN
C4823 1 2
20% 6.3V X5R 0201
OUT 37 VDD VDDIO
2 10V
0201 2 10V
0201 SMT-PAD
0.1UF
10%
0.22UF U4870 PLACE_NEAR=U4870.7:2MM 8 1 OUT 60
R4804 6.3V 2
CERM-X5R
6
U4802
BMA282 PLACE_NEAR=U4870.8:2MM 10K 0201 74LVC1G32
PCIE_SOC_R2D_C_P<2>
C4824 1 2
PCIE_SOC_R2D_P<2> LGA
7 2 LID_OPEN_LEFT 1 2 2 SOT891
D
D 14 IN
PCIE_SOC_R2D_C_N<2>
0.22UF 20% 6.3V X5R 0201
PCIE_SOC_R2D_N<2>
OUT 37

SPI_ACCEL_CS_L 4 CS* NOSTUFF SCX 1 SPI_AOP_SENSOR_CLK

6 3 PP1V8_SLPS2R 27 28 29 34 40 42 43 44 47 60
63 64 70 71 72 74 81 83 86 89
5%
1/20W
4 IPD_LID_OPEN OUT 46 62 83
14 IN
C4825 1 2
20% 6.3V X5R 0201
OUT 37 84 43 35 IN
SDX 2 SPI_AOP_SENSOR_MOSI
43

43
5 4 MF
201
1
NC
0.22UF
SDO 3 SPI_AOP_SENSOR_MISO_R 43
5 3
C4826 1 2 OMIT_TABLE
14 PCIE_SOC_R2D_C_P<3> 20% 6.3V X5R 0201 PCIE_SOC_R2D_P<3> 37 NC
IN
0.22UF OUT
PCIE_SOC_R2D_C_N<3> PCIE_SOC_R2D_N<3>
14 IN
C4827 1 2 OUT 37
84 35 OUT
ACCEL_INT1 6 INT1 PS 13
0.22UF 20% 6.3V X5R 0201
35 OUT
ACCEL_INT2 5 INT2 R4805
LID_OPEN_RIGHT 1
10K 2 SMC_LID_RIGHT
60 IN OUT 35 83
GND GNDIO 5%
GPIO Source Termination 1/20W

9
11
12
14

10
MF
201

36 I2S_SPKRAMP_L_R2D_R R4843 20 1 2 I2S_SPKRAMP_L_R2D 58

Unused SOC Signals
IN
PLACE_NEAR=U3900.AC32:5MM 5% 1/20W MF 201
OUT
34 BI
NC_PLCAM_TX_THROTTLE NO_TEST=1 37 BI NC_PCIE_WLAN_R2D_C_P NO_TEST=1
36 IN
I2S_SPKRAMP_L_BCLK_R R4844 20
PLACE_NEAR=U3900.Y29:5MM
1 2
5%
I2S_SPKRAMP_L_BCLK
1/20W MF 201
OUT 58 34 BI
NC_GNSS_HOST_TIME NO_TEST=1 37 BI NC_PCIE_WLAN_R2D_C_N NO_TEST=1
NC_GNSS_DEV_WAKE NO_TEST=1 NC_PCIE_WLAN_D2R_P NO_TEST=1
58 OUT
I2S_SPKRAMP_L_LRCLK_R R4863 20
PLACE_NEAR=U3900.AE32:5MM
1 2
5%
I2S_SPKRAMP_L_LRCLK
1/20W MF 201
IN 36
Project Specific Pull-Ups
34

34
BI
NC_SOC_WLAN_DEV_WAKE NO_TEST=1
37

37
BI
NC_PCIE_WLAN_D2R_N NO_TEST=1
BI BI
36 IN
I2S_SPKRAMP_R_R2D_R R4845 20
PLACE_NEAR=U3900.E17:5MM
1 2
5%
I2S_SPKRAMP_R_R2D
1/20W MF 201
OUT 59 37 BI NC_PCIE_ENET_R2D_C_P NO_TEST=1
NC_SOC_USB_ID NO_TEST=1 NC_PCIE_ENET_R2D_C_N NO_TEST=1
36 IN
I2S_SPKRAMP_R_BCLK_R R4846 20
PLACE_NEAR=U3900.D17:5MM
1 2
5%
I2S_SPKRAMP_R_BCLK
1/20W MF 201
OUT 59 PP1V8_SLPS2R 27 28 29 34 40 42 43 44 47 60
63 64 70 71 72 74 81 83 86 89
34 BI 37

37
BI
NC_PCIE_ENET_D2R_P NO_TEST=1
BI
59 OUT
I2S_SPKRAMP_R_LRCLK_R R4864 20
PLACE_NEAR=U3900.B18:5MM
1 2
5%
I2S_SPKRAMP_R_LRCLK
1/20W MF 201
IN 36 R4895 100K 1 2
5% 1/20W MF 201
SSD_PMU_RESET_L 34 81 83 35 BI
NC_ALTIMETER_INT NO_TEST=1 37 BI NC_PCIE_ENET_D2R_N NO_TEST=1
NC_SPI_ALTIMETER_CS_L NO_TEST=1 NC_PCIE_DN2_R2D_C_P NO_TEST=1
36 IN
I2S_CODEC_R2D_R R4847 20
PLACE_NEAR=U3900.AA33:5MM
1 2
5%
I2S_CODEC_R2D
1/20W MF 201
OUT 57
PP1V8_AWAKE 27 37 40 42 62 70 72 83
35

35
BI
NC_I2C_AOP_SCL NO_TEST=1
37

37
BI
NC_PCIE_DN2_R2D_C_N NO_TEST=1
BI BI
36 IN
I2S_CODEC_BCLK_R R4848 20
PLACE_NEAR=U3900.AE33:5MM
1 2
5%
I2S_CODEC_BCLK
1/20W MF 201
OUT 57
R4883 47K 1 2 SSD0_CLKREQ0_L 37 77
35 BI
NC_I2C_AOP_SDA NO_TEST=1 37 BI NC_PCIE_DN2_D2R_P NO_TEST=1
5% 1/20W MF 201 NC_UART_BT_D2R NO_TEST=1 NC_PCIE_DN2_D2R_N NO_TEST=1
57 OUT
I2S_CODEC_LRCLK_R R4865 20
PLACE_NEAR=U3900.V29:5MM
1 2
5%
I2S_CODEC_LRCLK
1/20W MF 201
IN 36 R4884 47K 1 2
5% 1/20W MF 201
SSD0_CLKREQ1_L 37 78
36 BI
NC_UART_BT_R2D NO_TEST=1
37 BI
NC_PCIE_DN3_R2D_C_P NO_TEST=1
SPI_TPAD_MOSI_R R4851 20 1 2 SPI_TPAD_MOSI
R4887 47K 1 2
5% 1/20W MF 201
SSD0_CLKREQ2_L 37 79
36 BI
NC_UART_BT_D2R_CTS_L NO_TEST=1
37 BI
NC_PCIE_DN3_R2D_C_N NO_TEST=1
C 36 IN
PLACE_NEAR=U3900.J30:5MM 5% 1/20W MF 201
OUT 42 62
R4888 47K 1 2
5% 1/20W MF 201
SSD0_CLKREQ3_L 37 80
36 BI
NC_UART_BT_R2D_RTS_L NO_TEST=1
37 BI
NC_PCIE_DN3_D2R_P NO_TEST=1
C
36 IN
SPI_TPAD_CLK_R R4852 20
PLACE_NEAR=U3900.K33:5MM
1 2
5%
SPI_TPAD_CLK
1/20W MF 201
OUT 42 62
36

36
BI
NC_UART_GNSS_D2R_CTS_L NO_TEST=1
37

37
BI
NC_PCIE_DN3_D2R_N NO_TEST=1
PP1V8_G3S BI BI
62 IN
SPI_TPAD_MISO_R R4867 20 1 2 SPI_TPAD_MISO OUT 36 42
18 43 44 45 47 48 51 55 57 58
59 60 61 62 68 74 76 83 36 BI
NC_UART_GNSS_R2D_RTS_L NO_TEST=1 37 BI NC_PCIE_CLK100M_WLAN_P NO_TEST=1
PLACE_NEAR=U6860.4:2MM 5% 1/20W MF 201 R4871 100K 2 1 SPI_ACCEL_CS_L NC_PLCAM_PROX_INT_L NO_TEST=1 NC_PCIE_CLK100M_WLAN_N NO_TEST=1
36 IN
SPI_MESA_MOSI_R R4853 20
PLACE_NEAR=U3900.A20:5MM
1 2
5%
SPI_MESA_MOSI
1/20W MF 201
OUT 44
R4872 100K 2 1
5% 1/20W MF 201
SPI_AOP_SENSOR_CLK
35 43 84

43
35

35
BI
NC_PLCAM_ROMEO_B2B_DETECT NO_TEST=1
37

37
BI
NC_WLAN_CLKREQ_L NO_TEST=1
BI BI
36 IN SPI_MESA_CLK_R R4854 20 1 2 SPI_MESA_CLK OUT 44
R4873 100K 2 1
5% 1/20W MF 201
SPI_AOP_SENSOR_MOSI 43 35 BI
NC_SMC_GFX_SELF_THROTTLE NO_TEST=1 37 BI NC_WLAN_PERST_L NO_TEST=1
PLACE_NEAR=U3900.D16:5MM 5% 1/20W MF 201 R4874 100K 2 1
5% 1/20W MF 201
SPI_AOP_SENSOR_MISO NC_SMC_TOPBLK_SWP_L NO_TEST=1 NC_PCIE_CLK100M_ENET_P NO_TEST=1
83 46 IN SPI_DFR_MISO_R R4866 20
PLACE_NEAR=J5100.7:7MM
1 2
5%
SPI_DFR_MISO
1/20W MF 201
OUT 36
R4875 100K 2 1
5% 1/20W MF 201
UART_WLAN_D2R
35 43 84

32 36
35

35
BI
NC_PCIEDN_WAKE_L NO_TEST=1
37

37
BI
NC_PCIE_CLK100M_ENET_N NO_TEST=1
BI BI
36 IN SPI_DFR_MOSI_R R4855 20 1 2 SPI_DFR_MOSI OUT 46 83
R4876 100K 2 1
5% 1/20W MF 201
UART_WLAN_D2R_CTS_L 32 36 35 BI
NC_ENET_LOW_PWR NO_TEST=1 37 BI NC_ENET_RESET_L NO_TEST=1
PLACE_NEAR=U3900.C17:5MM 5% 1/20W MF 201 5% 1/20W MF 201
NC_SDCONN_STATE_CHANGE_L NO_TEST=1 NC_PCIE_CLK100M_DN2_P NO_TEST=1
36 IN SPI_DFR_CLK_R R4856 20
PLACE_NEAR=U3900.C16:5MM
1 2
5%
SPI_DFR_CLK
1/20W MF 201
OUT 46 83
35

35
BI
NC_ENET_MEDIA_SENSE NO_TEST=1
37

37
BI
NC_PCIE_CLK100M_DN2_N NO_TEST=1
BI BI
37 IN SSD0_CLK24M_R R4857 0
PLACE_NEAR=U3900.AM6:7MM
1 2
5%
SSD0_CLK24M
1/20W MF 0201
OUT 43 77 79
R4885 100K 1 2 SSD0_PCIE_RESET_L 37 77 78 79 80
35 BI
NC_SOC_WLAN_JTAG_TMS NO_TEST=1 37 BI NC_PCIEDN2_CLKREQ_L NO_TEST=1
5% 1/20W MF 201 NC_MESA_MENUKEY_L NO_TEST=1 NC_PCIEDN2_RESET_L NO_TEST=1
35 IN
PDM_DMIC_CLK0_R R4859 20
PLACE_NEAR=U3900.N6:5MM
1 2
5%
PDM_DMIC_CLK0
1/20W MF 201
OUT 60 83 R4886 47K 1 2
5% 1/20W MF 201
SSD0_CLK24M
PLACE_NEAR=R4857.1:1MM
43 77 79
35

35
BI
NC_SOC_WLAN_JTAG_TCK NO_TEST=1
37

37
BI
NC_PCIE_CLK100M_DN3_P NO_TEST=1
BI BI
35 IN PDM_DMIC_CLK1_R R4860 20
PLACE_NEAR=U3900.J6:5MM
1 2
5%
PDM_DMIC_CLK1
1/20W MF 201
OUT 60 83 R4870 47K 1 2
5% 1/20W MF 201
I2S_SPKRAMP_R_D2R 36 35 BI
NC_PCC_EVENT NO_TEST=1 37 BI NC_PCIE_CLK100M_DN3_N NO_TEST=1
NC_TPAD_VIBE_L NO_TEST=1 NC_PCIEDN3_CLKREQ_L NO_TEST=1
35 IN
SPI_AOP_SENSOR_MOSI_R R4861 20
PLACE_NEAR=U3900.A5:5MM
1 2
5%
SPI_AOP_SENSOR_MOSI
1/20W MF 201
43
35

35
BI
NC_SPI_DESCRIPTOR_OVERRIDE_L NO_TEST=1
37

37
BI
NC_PCIEDN3_RESET_L NO_TEST=1
BI BI
35 IN
SPI_AOP_SENSOR_CLK_R R4862 20
PLACE_NEAR=U3900.E5:5MM
1 2
5%
SPI_AOP_SENSOR_CLK
1/20W MF 201
43
SoC Test Points 35 BI
NC_DISP_GCON_INT_L NO_TEST=1
NC_PCH_GCON_INT_L NO_TEST=1 NC_PCIE_SSD1_R2D_C_P<0> NO_TEST=1
43 SPI_AOP_SENSOR_MISO_R R4869 20
PLACE_NEAR=U4870.3:5MM
1 2
5%
SPI_AOP_SENSOR_MISO
1/20W MF 201
OUT 35 43 84
PP4801
35

35
BI
NC_SMC_FAN_1_PWM NO_TEST=1
37

37
BI
NC_PCIE_SSD1_R2D_C_N<0> NO_TEST=1
BI BI
34 TP_SOC_AMUXOUT 1
PP 35 BI
NC_SMC_FAN_1_TACH NO_TEST=1 37 BI NC_PCIE_SSD1_D2R_P<0> NO_TEST=1
SM-SP 35 BI
NC_SMC_LED_ONEWIRE NO_TEST=1 37 BI
NC_PCIE_SSD1_D2R_N<0> NO_TEST=1
35 BI
NC_SSD1_SWCLK_UART_R2D NO_TEST=1 37 BI
NC_PCIE_SSD1_R2D_C_P<1> NO_TEST=1
PP4802 35 BI
NC_SSD1_SWDIO_UART_D2R NO_TEST=1 37 BI
NC_PCIE_SSD1_R2D_C_N<1> NO_TEST=1
Remote Feedback Sense (Buck 0, 2 & 5) 34 TP_SOC_TST_CLKOUT 1
PP 36 BI
NC_I2C_SOC_5_SDA NO_TEST=1 37 BI
NC_PCIE_SSD1_D2R_P<1> NO_TEST=1
SM-SP NC_I2C_SOC_5_SCL NO_TEST=1 NC_PCIE_SSD1_D2R_N<1> NO_TEST=1
B PLACE_NEAR=U3900.AA12:5MM
XW4820
SM NOSTUFF PLACE_NEAR=R7806.1:1MM
36

36
BI
NC_DFR_TOUCH_RSVD NO_TEST=1
37

37
BI
NC_PCIE_SSD1_R2D_C_P<2> NO_TEST=1 B
BI BI
86 83 70 38 PPVDDCPU_AWAKE 1 2 PVDDCPUAWAKE_FB_R R4820
0201 5%
1 2 0
MF 1/20W
PVDDCPUAWAKE_FB OUT 70 36 BI
NC_PCHROM_SW_EN NO_TEST=1 37 BI
NC_PCIE_SSD1_R2D_C_N<2> NO_TEST=1
NC_I2S_CODEC_MCLK NO_TEST=1 NC_PCIE_SSD1_D2R_P<2> NO_TEST=1
PLACE_NEAR=U3900.M25:5MM
XW4821
SM PLACE_NEAR=R7812.1:1MM
36

36
BI
NC_I2S_HAWKING_D2R NO_TEST=1
37

37
BI
NC_PCIE_SSD1_D2R_N<2> NO_TEST=1
BI BI
86 83 70 38 PP0V82_SLPDDR 1 2 P0V8SLPDDR_FB_R R4821
0201 5%
1 2 0
MF 1/20W
P0V8SLPDDR_FB OUT 70 36 BI
NC_I2S_CODEC1_R2D_R NO_TEST=1 37 BI
NC_PCIE_SSD1_R2D_C_P<3> NO_TEST=1
NC_I2S_HAWKING_BCLK_R NO_TEST=1 NC_PCIE_SSD1_R2D_C_N<3> NO_TEST=1
PLACE_NEAR=U3900.AE22:5MM
XW4822
SM PLACE_NEAR=R7816.1:1MM
36

36
BI
NC_I2S_HAWKING_LRCLK NO_TEST=1
37

37
BI
NC_PCIE_SSD1_D2R_P<3> NO_TEST=1
BI BI
86 83 70 39 PP0V9_SLPDDR 1 2 P0V9SLPDDR_FB_R R4822
0201 5%
1 2 0
MF 1/20W
P0V9SLPDDR_FB OUT 70 36 BI
NC_I2S_CODEC1_MCLK NO_TEST=1 37 BI
NC_PCIE_SSD1_D2R_N<3> NO_TEST=1
36 BI
NC_I2C_PLCAM_SDA NO_TEST=1 37 BI
NC_PCIE_CLK100M_SSD1_01_P NO_TEST=1
36 BI
NC_I2C_PLCAM_SCL NO_TEST=1 37 BI
NC_PCIE_CLK100M_SSD1_01_N NO_TEST=1
36 BI
NC_FTCAM_CLK12M_R NO_TEST=1 37 BI
NC_SSD1_CLKREQ0_L NO_TEST=1
36 BI
NC_FTCAM_RESET_L NO_TEST=1 37 BI
NC_SSD1_CLKREQ1_L NO_TEST=1
36 BI
NC_PLCAM_RX_CLK12M_R NO_TEST=1 37 BI
NC_PCIE_CLK100M_SSD1_23_P NO_TEST=1
36 BI
NC_PLCAM_RX_RESET_L NO_TEST=1 37 BI
NC_PCIE_CLK100M_SSD1_23_N NO_TEST=1
Droop Circuit 36 BI
NC_PLCAM_TX_CLK12M_R NO_TEST=1 37 BI
NC_SSD1_CLKREQ2_L NO_TEST=1
36 BI
NC_PLCAM_TX_RESET_L NO_TEST=1 37 BI
NC_SSD1_CLKREQ3_L NO_TEST=1
36 BI
NC_PLCAM_TX_INT NO_TEST=1 37 BI
NC_SSD1_PCIE_RESET_L NO_TEST=1
47 43 42 18 14 13 12 11 7 5 4 PP3V3_S5 47 43 42 18 14 13 12 11 7 5 4 PP3V3_S5 37 BI
NC_SSD1_CLK24M_R NO_TEST=1
89 83 74 73 71 69 89 83 74 73 71 69
BYPASS=U4801::5MM BYPASS=U4800::5MM
NC_WLAN_CONTEXT_A
C4804
0.1UF
1
R4806 1 C4803
0.1UF
1 HPD KSF Comp Circuit 35

35
BI
NC_WLAN_CONTEXT_B
NO_TEST=1
NO_TEST=1
73
65
69
49 PPBUS_HS_CPU 10% 100K 10% R4830 needs to be characterized and adjusted if necessary BI
1

67 66 5%
87 85 6.3V 6.3V
CERM-X5R 2 1/20W CERM-X5R 2
0201 MF
201 2
VDD 0201 R4830
4.7K XDP_DP_INT_HPD
1 U4800 83 76 IN DP_INT_HPD 1 2 OUT 4
R4802 CRITICAL SLG4AP41473 5%
665K STQFN
1/20W

A 0.1% 5 U4801 DP_INT_HPD_L

MF
1/20W
TK
0201 2
43 PBUS_DIVIDER_REF 3 LMV331 72 OUT
UVP_DIS_L 2 ENABLE
CRITICAL
DUMMY_OUTPU_COMP 3
NC
35 OUT
201
SYNC_MASTER= SYNC_DATE=
A
VCC+ SC70-5 PAGE TITLE
4 PBUS_DIVIDER_OUT 9 10 PBUS_DIVIDER_REF
1 GND
COMP_INPUT VREF_1V2 43

6 D 3 D
SOC PROJECT SUPPORT
PBUS_DIVIDER NC
5 CPU_THROTTLE* 12 SMC_PROCHOT_L OUT 35 42 65 CRITICAL CRITICAL DRAWING NUMBER SIZE

NOSTUFF 2 NC
8 NC 6 Q4830 Q4830 051-05309 D
BYPASS=U4801::5MM NC
11 GPU_THROTTLE* NC SSM6N15AFEAP VER-1 SSM6N15AFEAP VER-1 Apple Inc. REVISION
SOT563 SOT563
R4800 1 C4805 1 THROTTLE*_TEST_OUTPUT 4
NC 5.1.0
127K 0.1UF G 2 G 5 NOTICE OF PROPRIETARY PROPERTY:
1% 10% 1 S 4 S BRANCH
6.3V GND DP_INT_HPD_MASK
1/20W
MF CERM-X5R 2 IN 13 35 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
0201
7

201 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
48 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 43 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE T151 FLEX CONNECTOR ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE
ESD Filters ESD Filters
R4912 R4950
SPI_MESA_MISO 1 0 2 SPI_MESA_MISO_CONN
44 36 OUT 60 83
SPI_MESA_MOSI_CONN 2 0 1 SPI_MESA_MOSI
83 60 IN 43
5%
1/20W
MF
1 C4952 C4950 1 5%
1/20W
0201 56PF NOSTUFF MF
5% 56PF
D 2 25V
NP0-C0G
5%
25V 2
0201
D
0201 NP0-C0G
0201
NOSTUFF
R4953
34 MESA_INT 1 0 2 MESA_INT_CONN 60 83
R4951 54 44 PP3V3_G3H_RTC_MESA
OUT
5% SPI_MESA_CLK_CONN 2 0 1 SPI_MESA_CLK
83 60 43
1/20W
MF
1 C4953 5%
IN 1 C4956
0201 100PF C4951 1 1/20W 0.1UF
5% NOSTUFF 56PF MF 63 60 47 43 42 40 34 29 28 27 PP1V8_SLPS2R 10%
2 25V
C0G 5%
0201 89 86 83 81 74 72 71 70 64 2 10V
X5R-CERM
0201 25V 1 0201
NP0-C0G 2
0201
R4971
100K
NOSTUFF 5%
R4954 1/20W
MF U4901
0 R4911 2 201 74AUP1T97

5
44 MESA_BOOST_EN 1 2 MESA_BOOST_EN_CONN IN 60 83 SOT891
5% PMU_ONOFF_R_L_CONN 2 0 1 PMU_ONOFF_R_L 1 4 PMU_ONOFF_L
89 83 60 63 72
1/20W
MF
1 C4954 5%
OUT

100PF C4955

6
0201 1 1/20W

3
5% NOSTUFF MF
100PF

2
2 25V
C0G 5%
0201
0201 25V 2
C0G
0201

Output Voltage 16.0V +/- 2%

Mesa Power Sequencing Requirements
Iout (max avg) 6mA Power On: 1V8 -> 3V3 -> 16V0
OCP (min) 13 mA EMC Filter
C Active Discharge 15 mA sink
MOJAVE 16V BOOST MIN_LINE_WIDTH=0.2000
C
MIN_LINE_WIDTH=0.2000
Max Output Cap 0.5uF @ 16V Load Cap:6.6uF nom
MIN_NECK_WIDTH=0.1000 FL4900 MIN_NECK_WIDTH=0.1000
80-OHM-25%-500MA
EDP:13.75mA PP16V0_MESA 1 2
PP16V0_MESA_FILT_CONN
60 83
PLACE_NEAR=U4900:5MM MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
U4900 BYPASS=U4900.C3::4MM 0201
L4901 LM3638A0 1 C4924 1 C4925 1 C4926 BYPASS=U4900.C3::4MM
1.0UH-0.4A-0.636OHM DIDT=TRUE
BGA 2.2UF 2.2UF 56PF BYPASS=U4900.C3::5MM 1 C4927
1 2
PP3V3_G3H_MESA_SW B1
20% 20% 5% 100PF
SW 2 25V
X5R 2 25V
X5R 2 25V
NP0-C0G 5%
0402 0402-3 0402-3 0201 2 25V
C0G
54 44 PP3V3_G3H_RTC_MESA A2 VIN VOUT C3 0201

BYPASS=U4900.A2::3MM B2 EN_M
44 MESA_BOOST_EN A3 EN_S
C4910 1
PP17V0_MOJAVE_LDOIN
10UF C2 LDOIN PMID C1
20%
6.3V
CERM-X5R 2 PGND AGND 1 C4923
0402-9
2.2UF
A1

B3

20%
2 25V
X5R
0402-3

Output Voltage 3.0V +/- 2%

Iout (max avg) 250mA

Dropout Voltage 155mV

3.0V MESA EMC Filter
B OCP (min) 250 mA
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
B
Active Discharge 280 Ohm Typ
MIN_LINE_WIDTH=0.2000
U4910 Load Cap:14.3uF nom FL4910 MIN_NECK_WIDTH=0.1000
NCP160AMX300 EDP:100mA 80-OHM-25%-500MA VOLTAGE=3
4 XDFN-COMBO-THICKSTNCL
54 44 PP3V3_G3H_RTC_MESA IN PP3V0_MESA 1 2
PP3V0_MESA_FILT_CONN
OUT 1 60 83

44 PP1V8_MESA 3 EN BYPASS=U4910.1::3MM 0201

1 C4911 1 C4916
1UF GND EPAD 1 C4920 1 C4921 1 C4922 1 C4928 1 C4929
10% 1UF PP1V8_G3S
2 10V 10% 2.2UF 2.2UF 2.2UF 0.1UF 100PF 18 43 45 47 48 51 55 57 58 59
5

60 61 62 68 74 76 83
2

X5R-CERM 2 10V 20% 20% 20% 10% 5%

0402 X5R-CERM 2 6.3V 2 6.3V 2 6.3V 2 10V 2 25V
BYPASS=U4910.4::3MM 0402 X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
X6S-CERM
0201
C0G
0201 R4922 100K 1 2
5% 1/20W MF 201
MESA_PWR_EN 34 44

PP1V8_MESA 44

R4924 100K 1 2
5% 1/20W MF 201
SPI_MESA_MISO 36 44

Output Voltage 1.85V +/- 2%

Iout (max avg) 250mA

R4923 100K 1 2
5% 1/20W MF 201
MESA_BOOST_EN 44

Dropout Voltage 50mV Typ @ 100mA

OCP (min) 250 mA 1.85V MESA

Active Discharge 230 Ohm Typ
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
EMC Filter
Max Output Cap 10uF
Load Cap:3.4uF nom MIN_LINE_WIDTH=0.2000
U4920 EDP:0.5mA FL4920 MIN_NECK_WIDTH=0.1000
SCY99258
A PP3V3_G3H_RTC_MESA 4 XDFN-COMBO 44 PP1V8_MESA
80-OHM-25%-500MA
PP1V8_MESA_FILT_CONN SYNC_MASTER= SYNC_DATE=
A
54 44 IN 1 1 2 PAGE TITLE
OUT 60 83

1 C4912 44 34 IN
MESA_PWR_EN 3 EN BYPASS=U4920.1::3MM 0201 T151
1UF GND EPAD
1 C4914 1 C4918 DRAWING NUMBER SIZE
10% 1UF
2.2UF
1 C4917 051-05309 D
2 10V 10% 100PF Apple Inc.
5
2

X5R-CERM 2 10V 20% 5% REVISION

0402 X5R-CERM 2 6.3V
BYPASS=U4920.4::3MM 0402 X5R-CERM 2 25V
C0G 5.1.0
0201 0201
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=MESA IV ALL RIGHTS RESERVED 44 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

VENUS

D D
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S
BYPASS=U5000::3MM BYPASS=U5000::3MM BYPASS=U5000::3MM
C5023 1 C5032 1 C5033 1
1.0UF 0.1UF 0.1UF PPVDD_SE_VDDA MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0900
20% 10% 10%
6.3V 2
X5R
10V
X5R-CERM 2
10V
X5R-CERM 2
PP_VDD_SE_VDDC MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0900
0201-1 0201 0201 PP_VDD_SE_VDDNV MIN_NECK_WIDTH=0.0900 MIN_LINE_WIDTH=0.0900
PP_VDD_SE_VDDPLL MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0900
PP_VDD_SE_VHV MIN_NECK_WIDTH=0.0900 MIN_LINE_WIDTH=0.0900
83 76 75 74 62 57 51 50 PP3V3_G3S PP_VDD_SE_VREF MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0900
BYPASS=U5000::3MM BYPASS=U5000::3MM BYPASS=U5000::3MM BYPASS=U5000::3MM

NC
NC
NC

NC

NC

NC
1 C5021 1 C5022 1 C5031 1 C5036 1 C5037 1 C5038 1 C5039 1 C5040 1 C5024
2.2UF 2.2UF 1.0UF 0.1UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 10% 20% 20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 10V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V

PMUVCC1 B5
PMUVCC2 B6
PMUVCC3 B7

SIMVCC1 A6
SIMVCC2 A7
SIMVCC3 A8

VBAT E1
VBATPWR A3

VDDA H5

VDDBOOST B1

VDDC C2

VDDCIN C1

VDDIO C3

VDDIO_SE E5

VDDNV B3

VDDPA H2

VDDPLL H3

VHV F1

VREF D2
VUP G1
X5R-CERM X5R-CERM X5R X5R-CERM X5R X5R X5R X5R X5R
0201 0201 0201-1 0201 0201 0201 0201 0201 0201

H8 SE_GPIO0 F8 NC
NFC_CLK_REQ
NC SE_GPIO1 D4
45 34 SE_CTLR_FW_DWLD J8 NFC_DWL_REQ NC
IN
U5001 SE_I2C_SCL G8
E4 NFC_GPIO0 SN100VUK-B20147 NC
ALWAYS ON GPIOS NC
F3 WLCSP-1 SE_I2C_SDA F7 NC
NC NFC_GPIO1 OMIT_TABLE
R5032 47K MF 201 1
5%
2 1/20W NFC_GPIO2_AO G6 NFC_GPIO2_AO SE_ISO_CLK D6 NC
R5033 47K MF 201 1 2 NFC_GPIO3_AO G5 NFC_GPIO3_AO SE_ISO_IO D7 NC
5% 1/20W
C 45 36 IN
UART_SE_R2D_RTS_L F2 NFC_HSU_CTS
SE_ISO_RST D3 NC C
45 36 UART_SE_D2R_CTS_L F5 NFC_HSU_RTS SE_SPI_CLK E8
OUT NC
45 36 IN
UART_SE_R2D E3 NFC_HSU_RX DIG NFC DIS SE SE_SPI_CS E6
NC
45 36 OUT
UART_SE_D2R F4 NFC_HSU_TX SE_SPI_MISO E7
NC
D5
35 OUT
SE_HOST_WAKE_R R5036 1 2 SE_HOST_WAKE H7 NFC_IRQ
SE_SPI_MOSI NC
5% 1/20W MF
0201
A5 BOOST_LX A1 NC
NC NFC_SIM_SWIO1
PP1V8_G3S
0 B8
58 57 55 51 48 47 45 44 43 18
NC NFC_SIM_SWIO2
83 76 74 68 62 61 60 59
C8 NFC_SIM_SWIO3
1 NC
R5035 G7
22K 45 34 IN
SE_DEV_WAKE NFC_WKUP_REQ
5%
1/20W G3
MF NFC_CLK_32K
2 201
NFC_XTAL1 H6 NFC_XTAL1
B4 NFC_SIM_SWCTRL1
NC ANALOG SIGNAL
C6 NFC_SIM_SWCTRL2
NC
J7 NFC_XTAL2
Avoid false wakeup NC
R5030 10K 1 2 5% 201 SE_RX_P J5 RXP
MF 1/20W
R5031 10K 1 2 5% 201 SE_RX_N J4 RXN
MF 1/20W
J1 TX1
NC
J3 TX2
NC
G2 TXVCASC
NC
H1 TXVCM
NC
B SE_PWR_EN C4 B

VSS_DIG
VSS_DIG
VSS_DIG

VSS_NFC

VSS_PLL

VSS_PMU

VSS_PWR
VSS_PWR

VSS_REF

VSS_SUB
VSS_SUB
72 45 IN VEN

VSS_PA
J6 VTUNE
NC

C5
C7
D8

G4

J2

H4

D1

A2
B2

E2

A4
F6
PP1V8_G3S 18 43 44 45 47 48 51 55 57 58
A 59 60 61 62 68 74 76 83
SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE
R5021 100K 1 2
5% 1/20W MF 201
UART_SE_R2D 36 45
SECURE ELEMENT
R5022 100K 1 2
5% 1/20W MF 201
UART_SE_D2R 36 45

R5023 100K 1 2
5% 1/20W MF 201
UART_SE_R2D_RTS_L 36 45
DRAWING NUMBER

051-05309
SIZE

D
R5024 100K 1 2
5% 1/20W MF 201
UART_SE_D2R_CTS_L 36 45 Apple Inc. REVISION
R5020 100K 1 2
5% 1/20W MF 201
SE_CTLR_FW_DWLD 34 45 5.1.0
R5025 100K 1 2
5% 1/20W MF 201
SE_DEV_WAKE 34 45 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R5026 100K 1 2
5% 1/20W MF 201
SE_PWR_EN 45
72
EXTRA PULLDOWN ADDED
PER J152
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC IV ALL RIGHTS RESERVED 45 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PP1V8_DFR 46 48 83 87
T139 Support
2
S Q5100
R5102 DMP31D0UFB4
DFN1006H4-3
IPD_LID_OPEN 2
100K 1 IPD_LID_OPEN_R 1
83 62 43 IN

D 5%
1/20W
G D
MF
201 D
Touch Conn Disp Conn
3
J5100 J5110
AA07-S022VA1 DF40SG(1.5)-26DS-0.4V PLACE_NEAR=J5110:5MM
PLACE_NEAR=J5110:5MM
F-ST-SM F-ST-SM
24
23
28 27 L5110
3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM
2 GND 1 4 SYM_VER-2 1
83 46 DFR_TOUCH_LID_OPEN_L 2 1 TP_DFR_TOUCH_PANEL_DETECT 83

83 TP_DFR_TOUCH_GPIO2 4 3 83 DFR_DISP_VSYNC (Cumulus IPD) 4 3 83 MIPI_DFR_CLK_FILT_CONN_P MIPI_DFR_CLK_P 36

IN
6 5 83 36 DFR_DISP_TE 6 5 83 MIPI_DFR_CLK_FILT_CONN_N 3 2 MIPI_DFR_CLK_N 36
OUT IN
SPI_DFR_CS_L 8 7 SPI_DFR_MISO_R
83 36 IN OUT 43 46 83
8 GND 7 L5111
3.25-OHM-0.1A-2.4GHZ
83 43 SPI_DFR_MOSI 10 9 SPI_DFR_CLK 43 83
IN IN TAM0605-4SM
12 11 83 34 DFR_DISP_INT 10 9 83 MIPI_DFR_DATA_FILT_CONN_P 4 1 MIPI_DFR_DATA_P
SYM_VER-2
36
OUT IN
83 48 46 I2C_DFR_SCL_R 14 13 DFR_TOUCH_INT_L 35 46 83 83 46 36 DFR_DISP_RESET_L 12 11 83 MIPI_DFR_DATA_FILT_CONN_N MIPI_DFR_DATA_N 36
IN OUT IN IN
83 48 46 I2C_DFR_SDA_R 16 15 DFR_TOUCH_CLK32K_RESET_L 36 83
BI IN 14 13 3 2
L5100 83 46 36 IN
DFR_TOUCH_RESET_L 18 17 MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
GND
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1.2UH-20%-0.12A-1.17OHM 20 19 TP_DFR_TOUCH_ROM_WC 83 16 15
83 75 68 55 54 52 51 50 29 28 PP5V_G3S 1 2 83 PP5V_G3S_DFR_FILT 22 21 83 PP3V3_G3HSW_DFR 18 17
86 IN
0402 MIN_LINE_WIDTH=0.2000 NOSTUFF 20 19
MIN_NECK_WIDTH=0.1000 25 1 C5104 22 21 I2C_DFR_SCL_R
1 C5111
IN 46 48 83
1UF
26 0.1UF 24 23 I2C_DFR_SDA_R 46 48 83
10%
10% BI
2 10V
C5100 1 1 C5101 2 6.3V
X5R C5110 1
26 25
X5R-CERM
0402
0201 PP3V3_G3H_RTC_DFR 0.1UF GND
4.7UF 4.7UF BYPASS=J5100.21::10MM
50 46 IN 10%
6.3V 2
20% 20%
25V 2 2 25V X5R 30 29 BYPASS=J5110.17::3MM
BYPASS=J5100.22::10MM X5R X5R 0201
C BYPASS=J5100.22::10MM 0402 0402
C
U5100 Load Cap: 3.5uF nom U5111
SLG5AP1449V BYPASS=J5110.22::3MM
NCP160AMX180 EDP: 57mA R5110
4 XDFN-COMBO-THICKSTNCL STDFN
50 46 PP3V3_G3H_RTC_DFR IN 87 83 7.5K
IN
OUT 1 48 46 PP1V8_DFR 1 2 P1V8_DFR_R 1 ON D 2
C5102 1 3 EN 1%
1/20W S 3 EDP: 145mA
1UF GND EPAD
1 C5103 MF
10% 201 Load Cap: 22.2uF nom
10V
X5R-CERM 2
1UF GND
R5107 1 1 C5105 10%

5
2
0402 2 10V

4
BYPASS=U5100.4::3.6MM 100K 1UF X5R-CERM
0402
5% 20%
1/20W 2 16V
CER-X5R BYPASS=U5100.1::3MM
MF 0201
201 2
R5101
DFR_PWR_EN 2
1K 1 DFR_PWR_EN_R
83 34 IN Output Voltage 1.8V +/- 2%
Slew Rate 2.5V/ms
5%
1/20W Iout (max avg) 250mA
MF 40 mOhm Typ
201 RDS(on)
Dropout Voltage 250mV 55 mOhm Max

OCP (min) 250 mA Current 1A Max

Active Discharge 280 Ohm Typ Active

150 Ohm Typ
Discharge
87 83 48 46 PP1V8_DFR

R5103 1 R5104 1 R5105 1

4.7K 100K 100K
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 2 201 2 201 2
DFR_TOUCH_RESET_L
B 83 46 36

83 46 35 DFR_TOUCH_INT_L
B
83 46 43 SPI_DFR_MISO_R
83 46 36 DFR_DISP_RESET_L
83 46 DFR_TOUCH_LID_OPEN_L

R5106 1 R5111 1
100K 100K
5% 5%
1/20W 1/20W
MF MF
201 2 201 2

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

T139 SUPPORT
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
51 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DFR IV ALL RIGHTS RESERVED 46 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

CFL PCH S0 "SMBUS 0" CONNECTIONS SMC I2C "3" S0 Connections SMC I2C "4" G3H Connections
47 43 42 18 14 13 12 11 7 5 4 PP3V3_S5 32 18 17 16 15 14 13 12 11 7 PP1V8_S5 PP3V3_S0SW_LCD 76 83 88
89
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R
89 83 74 73 71 69 83 74 73 72 70 69 65 53 47 42 86 83 81 74 72 71 70 64 63
BYPASS=U5250.1::5MM BYPASS=U5250.8::5MM
1 C5250 C5251 1
R52801 1
R5281 Battery
R5200 1 1
R5201 R5250 1 1
R5251 R5252 1 0.1UF 0.1UF 4.7K 4.7K
CFL-LP PCH 10% 10% SMC 5% 5% J6951

8
2.2K 2.2K 2.2K 2.2K 100K 2 6.3V 6.3V 2 1 1
5% 5% 5% 5% 5% CERM-X5R CERM-X5R R5253 R5254 1/20W
MF
1/20W
MF (Write: 0x16 Read:0x17)
U0500 1/20W
MF
1/20W
MF SMC 1/20W
MF
1/20W
MF
1/20W
MF
0201 VL VCC
U5250
0201
5%
1.1K
5%
1.1K U3900 201 2 2 201
(MASTER) 201 2 2 201 201 2 2 201 201 2 NLSX4402 1/20W
MF
1/20W
MF
Internal DP (MASTER)
SMBUS_PCH_CLK U3900 UDFN-COMBO 2 201 2 201 J8500 R5282 1
0 2 PWR_SCL_R0 R5284 1
0 2
CKPLUS_WAIVE=I2C_PULLUP
I2C_PWR_SCL_R1
D
12 IN
(MASTER) 2 IO/VL1 IO/VCC1 7
(0x10-0x1F)
IN
5% 1/20W MF 0201 5% 1/20W MF 0201 OUT 63
D
12 SMBUS_PCH_DATA 3 IO/VL2 IO/VCC2 6 CKPLUS_WAIVE=I2C_PULLUP
BI
35 I2C_DISP_SCL R5283 0 R5285 0
IN 1 2 PWR_SDA_R0 1 2 I2C_PWR_SDA_R1 63
CRITICAL I2C_DISP_3V3_SCL 76
BI
5% 1/20W MF 0201 5% 1/20W MF 0201 BI
35 I2C_DISP_SDA OUT
BI I2C_DISP_3V3_SDA BI 76

I2C_DISP_LS_EN 5 EN Battery Charger

GND CALPE
U7800 ISL9240 - U7000

4
(Write: 0x12 Read: 0x13)
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP R5286 1
0 2 I2C_PWR_SCL_R2 64
83 72 35 OUT
I2C_PWR_SCL 5% 1/20W MF 0201 OUT
CKPLUS_WAIVE=I2C_PULLUP CKPLUS_WAIVE=I2C_PULLUP
I2C_PWR_SDA R5287 1
0 2 I2C_PWR_SDA_R2
83 72 35 BI BI 64
5% 1/20W MF 0201
SMC I2C "6" G3H Connections (Write: 0xE8 Read: 0xE9)

89 86
47 44 43 42 40 34 29 28 27
83 81 74 72 71 70 64 63 60
PP1V8_SLPS2R

SSD0
SMC R52301 1
R5231
2.2K
5% 5%
2.2K U9000 SMC I2C "5" G3S Connections
U3900 1/20W
MF
1/20W
MF
(Write: 0xF2 Read: 0xF3)
(MASTER) 201 2 2 201 (10K IPU)
81 35 I2C_SSD_SCL
IN
(10K IPU)
OUT
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S PP5V_S4SW 52 74

81 35 BI
I2C_SSD_SDA BI BYPASS=U5272.8::3MM
BYPASS=U5272.1::5MM
LOADISNS
LOADISNS LOADISNS
C5272 1 1
1 C5273 NOSTUFF
C 0.1UF
R5272 0.1UF C
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S 100K 10% 1
R5273
83 76 74 68 62 61 60 59 10%
6.3V 2 5% 2 10V
X5R-CERM
CERM-X5R 1/20W 0201 4.7K
1 1 Trackpad 0201 MF 5%
R5290 R5291 2 201 1/20W
MF
SMC 2.2K
5% 5%
2.2K J6801 2 201
U3900 1/20W
MF
1/20W
MF
(Write: 0x98 Read: 0x99)
(MASTER) 201 2 2 201
CFL I2C PCH "SML0" CONNECTIONS 35 IN
I2C_SENSE_SCL
R5265 1
20
2
CKPLUS_WAIVE=I2C_PULLUP
I2C_SENSE_SCL_R1 OUT 62 I2C_SENSE_5V_SCL
5% 1/20W MF 201
47 43 42 18 14 13 12 11 7 5 4
89 83 74 73 71 69
PP3V3_S5
I2C_SENSE_SDA
R5266 1
20
2
CKPLUS_WAIVE=I2C_PULLUP
I2C_SENSE_SDA_R1 NOSTUFF

8
35 BI BI 62
5% 1/20W MF 201 1
VL VCC R5274
U5272 5%
4.7K
LOADISNS NLSX4402 1/20W
1 1 EADC2
R5218 R5217 R5262 0 2 CKPLUS_WAIVE=I2C_PULLUP
2 IO/VL1
UDFN-COMBO MF
2 201
2.2K 2.2K 1 I2C_SENSE_SCL_R2 IO/VCC1 7
CNL PCH 5% 5% 5% 1/20W
0
MF 0201CKPLUS_WAIVE=I2C_PULLUP 3 IO/VL2 IO/VCC2 6 I2C_SENSE_5V_SDA U5710
1/20W
MF
1/20W
MF R5263 1 2 I2C_SENSE_SDA_R2 (Write: 0x12 Read: 0x13)
U0500 201 2 2 201
5% 1/20W MF 0201 CRITICAL LOADISNS
CKPLUS_WAIVE=I2C_PULLUP
(MASTER) LOADISNS LOADISNS R5269 0 5% 1/20W MF 0201
I2C_SENSE_5V_SCL_R2

2
OUT 52

SMBUS_5_OE 5 EN LOADISNS
GND CKPLUS_WAIVE=I2C_PULLUP
12 SML_PCH_0_CLK R5264 0 5% 1/20W MF 0201
IN I2C_SENSE_5V_SDA_R2

2
BI 52

4
12 BI
SML_PCH_0_DATA

B B

SMC I2C "2" S0 Connections

32 18 17 16 15 14 13 12 11 7 PP1V8_S5 SMC I2C "1" S0 Connections
83 74 73 72 70 69 65 53 47 42
PP1V8_S5
SMC I2C "0" G3H CONNECTIONS 1 1 THERMAL SENSORS A
32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42
R5260 R5261
2.2K 2.2K
SMC 5%
1/20W
5%
1/20W
TMP464: U5850
U3900 MF
201 2
MF (Write: 0x90 Read: 0x91) SMC R52701 R52711
2 201 2.2K 2.2K
89
60 47 44 43 42 40 34 29 28 27
86 83 81 74 72 71 70 64 63
PP1V8_SLPS2R USB-C PORT CONTROLLER XA (MASTER)
CKPLUS_WAIVE=I2C_PULLUP CKPLUS_WAIVE=I2C_PULLUP
U3900 5%
1/20W
5%
1/20W
U3100 - ADDR: 0X38 35 I2C_THMSNS_SCL R5202 1
0 2 I2C_THMSNS_SCL_R0 R5204 1
0 2 I2C_THMSNS_SCL_R1 53
(MASTER) MF
201 2
MF
201 2
1 1 IN OUT
R5220 R5221 (WRITE: 0X70 READ: 0X71)
CKPLUS_WAIVE=I2C_PULLUP
5% 1/20W MF 0201 5% 1/20W MF 0201
CKPLUS_WAIVE=I2C_PULLUP 35 IN
I2C_SNS0_S0_SCL
2.2K 2.2K I2C_THMSNS_SDA R5203 1
0 2 I2C_THMSNS_SDA_R0 R5205 1
0 2 I2C_THMSNS_SDA_R1
5% 5% 35 53
1/20W 1/20W USB-C PORT CONTROLLER XB BI
5% 1/20W MF 0201 5% 1/20W MF 0201 BI
35 BI
I2C_SNS0_S0_SDA
MF MF
SMC 2 201 2 201 U3200 - ADDR: 0X3F
U3900 (WRITE: 0X7E READ: 0X7F)
(MASTER)
CFL PCH (NOTE:NO DEVICE ON THIS BUS)
U0500
35 29 28 27 BI
UPC_I2C_INT_L BI (WRITE:0X88 READ:0X89)
I2C_UPC_SCL SML_PCH_1_CLK R5210 1
0 2
NOSTUFF
83 35 29 27 IN OUT 12 OUT
5% 1/20W MF 0201

R5211 0 NOSTUFF
A 83 35 29 27 BI
I2C_UPC_SDA BI 12 BI
SML_PCH_1_DATA
5%
1
1/20W
2
MF 0201 A
THERMAL SENSORS B SYNC_MASTER=

PAGE TITLE
SYNC_DATE=

(NOTE:ALSO CONNECT TO ARKANOID DEBUG CONN, J3000) TMP464: U5870 I2C CONNECTIONS 1
(Write: 0x92 Read: 0x93) DRAWING NUMBER SIZE
(NOTE:R1375,R1376 PU TO PP1V8_S5) 051-05309 D
CKPLUS_WAIVE=I2C_PULLUP
Apple Inc. REVISION
R5208 0
5%
1
1/20W
2 I2C_THMSNS_SCL_R2
MF 0201 OUT 53 5.1.0
CKPLUS_WAIVE=I2C_PULLUP NOTICE OF PROPRIETARY PROPERTY: BRANCH
R5209 1
0 2 I2C_THMSNS_SDA_R2 BI 53 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 0201 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SMC IV ALL RIGHTS RESERVED 47 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

Device SMC IF ADDR. (8b)

AP I2C "0" G3S Connections
ACE XA I2C0 0X70/1
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S
Left Speaker Amps ACE XB I2C0 0X7E/F
U6400
1 1
AP (SoC) R5300
2.2K
R5301
2.2K
(WRITE:0X62,READ 0X63)
5% 5%
U3900 1/20W 1/20W U6450
MF MF
(MASTER) 201 201 (WRITE:0X64,READ 0X65)
2 2
I2C_SPKRAMP_L_SCL NC. I2C1 D
D 58 36 IN OUT

58 36 BI
I2C_SPKRAMP_L_SDA BI TEMP. SENSOR A I2C2 0X90/1

TEMP. SENSOR B I2C2 0X92/3

AP I2C "1" G3S Connections

TCON I2C3 0X10-1F
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S
Right Speaker Amps Charger I2C4 0X12/3
U6500
AP (SoC) R5305
1 1
R5306 (WRITE:0X66,READ 0X67)
Battery I2C4 0X16/7
2.2K 2.2K
5% 5%
U3900 1/20W
MF
1/20W
MF
U6550 Calpe I2C4 0XE8/9
(MASTER) 2012 2 201 (WRITE:0X68,READ 0X69)
59 36 I2C_SPKRAMP_R_SCL Trackpad I2C5 0X98/9
IN OUT

59 36 BI
I2C_SPKRAMP_R_SDA BI EADC1 I2C5 0X10/1
EADC2 I2C5 0X12/3
SSD I2C6 0XF2/3
SOC IF (AP)
C AP I2C "2" Codec Connections C
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S Left Spkr Amp.(U6400) I2C0 0X62/3
83 76 74 68 62 61 60 59
ISP I2C "0" G3S Connections Left Spkr Amp.(U6450) I2C0 0X64/5
1 1 PP1V8_G3S
AP (SoC) R5310
2.2K
R5311
2.2K
Audio Codec 58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59 Right Spkr Amp.(U6500) I2C1 0X66/7
5% 5%
U3900 1/20W 1/20W U6300
(MASTER)
MF MF 1 1 Right Spkr Amp.(U6550) I2C1 0X68/9
2012 2 201 (WRITE:0X90,READ 0X91) ISP (SoC) R5335 R5336
57 36 I2C_CODEC_SCL 1.1K
5% 5%
1.1K FaceTime Camera Audio Codec I2C2 0X90/1
IN OUT
U3900 1/20W 1/20W J8500(I2C_FTCAM_ISOL)
MF MF
I2C_CODEC_SDA (MASTER) 2012 2 201 (Write: 0x6C Read:0x6D)
57 36 BI BI
CKPLUS_WAIVE=I2C_PULLUP
0 ALS I2C3 0X52/3
36 IN
I2C_FTCAM_SCL R5342 1 2 I2C_FTCAM_SCL_R OUT
CKPLUS_WAIVE=I2C_PULLUP 5% 1/20W MF 0201
36 I2C_FTCAM_SDA R5343 1 0 2 I2C_FTCAM_SDA_R DFR Display I2C4 0X98/9
BI BI
5% 1/20W MF 0201
DFR Touch I2C4 0XA0/1
AP I2C "3" G3S Connections NC. I2C5
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S
FHSi2 PMU Spkr ID1 I2C6
83 76 74 68 62 61 60 59
J8500(I2C_FTCAM_ISOL)
1 1 (Write: 0x90 Read: 0x91)
Spkr ID0 I2C6
R5315
1.1K
R5316
1.1K ALS
AP (SoC) 5%
1/20W
5%
1/20W J8500 OUT 76
SIP IF (ISP)
MF MF
U3900 2012 2 201 (See camera flex) BI 76

B (MASTER) B
CKPLUS_WAIVE=I2C_PULLUP R53402 (WRITE:0x52,READ 0x53) FT Camera I2C0 0X6C/D
36 IN
I2C_ALS_SCL 1 0 I2C_ALS_SCL_R OUT 76
CKPLUS_WAIVE=I2C_PULLUP 1/20W 0201 MF 5%
36 I2C_ALS_SDA 1 2 0 I2C_ALS_SDA_R 76
FHSi2 I2C0 0X90/1
BI BI
1/20W 0201 MF 5%
R5341 NC. I2C1
AOP IF

AP I2C "4" DFR Connections NC. I2C0

87 83 46 PP1V8_DFR

R53201 1 R5321
AP (SoC) 1.5K
5% 5%
1.5K DFR Display
1/20W 1/20W
U3900 MF MF J5110
2012 2 201
(MASTER) (Write:0x98 Read:0x99)
CKPLUS_WAIVE=I2C_PULLUP
15
36 IN I2C_DFR_SCL
5%
R5322
1/20W MF 201
1 2 I2C_DFR_SCL_R OUT
15
36 BI I2C_DFR_SDA
5%
R5323
1/20W MF 201
1 2 I2C_DFR_SDA_R BI
CKPLUS_WAIVE=I2C_PULLUP

A DFR Touch SYNC_MASTER= SYNC_DATE=

A
PAGE TITLE
J5100
(Write:0xA0 Read:0xA1)
I2C CONNECTIONS 2
DRAWING NUMBER SIZE

OUT 46 83 051-05309 D
Apple Inc. REVISION
46 83
BI
5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SMC IV ALL RIGHTS RESERVED 48 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

CPU High Side Current Sense (IC0R) LCD Backlight Current Sense (IBLR)
Gain: 100x, EDP: 8.868 A Gain: 100x. EDP: 0.902 A
BYPASS=U5450.6::5MM
Rsense: 0.002 (R5400) [Production] 74 54 52 51 50 49 PP3V3_S4SW_SNS Rsense: 0.025 (R8400) 74 54 52 51 50 49 PP3V3_S4SW_SNS
BYPASS=U5400.6::5MM LOADISNS
Vsense: 17.7 mV, Range: 12.5 A Vsense: 22.6 mV, Range: 1.32 A
SMC ADC: 00
1 C5401 1 C5450
0.1UF 0.1UF

6
10% 10% PLACE_NEAR=U5710.22:5MM
75 72 64 62 49 PPBUS_G3H V+ 2 6.3V
CERM-X5R V+ 2 6.3V
CERM-X5R
87 86 83 PLACE_NEAR=U5400.2:5MM 0201 PLACE_NEAR=U3900.AE1:7.5MM 0201 LOADISNS
NO_XNET_CONNECTION=1 U5400 R5409 PLACE_NEAR=R8400.4:5MM U5450 R5459
CRITICAL INA214A 9.09K 2 INA214A 45.3K 2
1 3 ISNS_HS_CPU_P UQFN 10 CPUHI_IOUT SMC_CPU_HS_ISENSE ISNS_LCDBKLT_P UQFN 10 LCDBKLT_IOUT EADC2_LCDBKLT_ISENSE
R5400 54 2 IN+
CRITICAL
OUT 1 OUT 35 75 54 IN
2 IN+
CRITICAL
OUT 1 OUT 52
0.002 3 IN+ 1% 3 IN+ 1%
1% REF 8 1/20W REF 8 1/20W
1W
ISNS_HS_CPU_N
MF R5408 1 1 C5409 1
R5455 MF 1 C5459 D
D CYN
0612 2 4
54
4 IN- NC 1 NC
201
9.09K
1%
0.022UF
10% 75 54 IN
ISNS_LCDBKLT_N 4 IN-
LOADISNS
NC 1 NC 1%
6.04K
201
20%
2.2UF
5 IN- NC 7 1/20W 2 6.3V 5 IN- NC 7 1/20W 2 6.3V
69 67 66 65 43
87 85 73
PPBUS_HS_CPU
PLACE_NEAR=U5400.4:5MM
100x NC MF
201 2
X5R-CERM
0201 100x NC MF X5R-CERM
0201
GND PLACE_NEAR=R8400.3:5MM GND 2 201 PLACE_NEAR=U5710.22:5MM
PLACE_NEAR=U3900.AE1:7.5MM PLACE_NEAR=U3900.AE1:7.5MM PLACE_NEAR=U5450.10:5MM

9
LOADISNS
GND_SMC_AVSS LOADISNS GND_EADC2_COM
35 42 49 50 51 52 50 51 52 54

OTHER 5V High Side Current Sense (IO5R) Left AMP Current Sense (IALR)
Gain: 100x, EDP: 5.227 A LOADISNS Gain: 200x, EDP: 2.6 A BYPASS=U54A0.6::5MM
Rsense: 0.005 (R5410) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS Rsense: 0.005 (R54A0) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS
BYPASS=U5410.6::5MM LOADISNS
Vsense: 26.1 mV, Range: 6.0 A 1 C5411 Vsense: 13 mV, Range: 3.3 A 1 C54A0
MUX: A1 0.1UF 0.1UF

6
10% 10%
75 72 64 62 49 PPBUS_G3H V+ 2 6.3V PLACE_NEAR=U7800.A15:7.5MM 87 86 83 75 72 64 62 49 PPBUS_G3H V+ 2 6.3V
87 86 83 CERM-X5R LOADISNS PLACE_NEAR=U54A0.2:5MM CERM-X5R
CRITICAL PLACE_NEAR=U5410.2:5MM 0201 0201
U5410 R5419
NO_XNET_CONNECTION=1 U54A0
INA214A INA210A P2MM PP54A0
R5410 2 4 54 ISNS_HS_OTHER5V_P 2 IN+ UQFN 10 HS_OTHER5V_IOUT 1
9.09K 2 PMU_OTHER5V_HI_ISENSE OMIT 2 4 54 ISNS_SPKRAMP_LEFT_P 2 IN+ UQFN 10 SPKRAMPL_IOUT 1
SM
OUT OUT 72 OUT PP
0.005
1% 3 IN+
CRITICAL 1% R54A0
0.005 3 IN+ CRITICAL
1W REF 8 1/20W REF 8
MF
54 ISNS_HS_OTHER5V_N LOADISNS
MF
201 R54181 1 C5419 1%
54 ISNS_SPKRAMP_LEFT_N LOADISNS
1
R54A5
1206-1 4 IN- NC 1 9.09K 2.2UF 1/3W
MF 4 IN- NC 1 15K
1 3 NC 1% 20%
0306-SHORT 1 3
NC 5%
5 IN- NC 7 1/20W 2 6.3V 5 IN- NC 7 1/20W
86 68 PPVIN_G3H_P5VG3S 100x NC MF
201 2
X5R-CERM
0201 58 PPBUS_G3H_SPKRAMP_LEFT 200x NC MF
PLACE_NEAR=U5410.4:5MM GND GND 2 201
PLACE_NEAR=U7800.A15:7.5MM PLACE_NEAR=U7800.A15:7.5MM PLACE_NEAR=U54A0.4:5MM PLACE_NEAR=U54A0.10:5MM

9
LOADRC:YES LOADISNS
LOADISNS

C OTHER 3.3V High Side Current Sense (IO3R) Right AMP Current Sense (IARR) C
Gain: 100x, EDP: 6.736 A LOADISNS Gain: 200x, EDP: 2.6 A BYPASS=U54B0.6::5MM
Rsense: 0.003 (R5440) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS Rsense: 0.005 (R54B0) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS
BYPASS=U5440.6::5MM LOADISNS
Vsense: 20.2 mV, Range: 10 A 1 C5441 Vsense: 13 mV, Range: 3.3 A 1 C54B0
MUX: A0 0.1UF 0.1UF
6

6
10% 10%
75 72 64 62 49 PPBUS_G3H V+ 2 6.3V
CERM-X5R LOADISNS 87 86 83 75 72 64 62 49 PPBUS_G3H V+ 2 6.3V
CERM-X5R
87 86 83 PLACE_NEAR=U5440.2:5MM 0201 PLACE_NEAR=U54B0.2:5MM 0201
CRITICAL U5440 PLACE_NEAR=U7800.A16:7.5MM U54B0
INA214A R5449 INA210A P2MM PP54B0
1 3 ISNS_HS_OTHER3V3_P UQFN 10 HS_OTHER3V3_IOUT 9.09K 2 PMU_OTHER3V3_HI_ISENSE ISNS_SPKRAMP_RIGHT_P UQFN 10 SPKRAMPR_IOUT 1
SM
R5440 54 2 IN+ OUT 1 OUT 72 0306-SHORT 2 4 54 2 IN+ OUT PP
0.003 3 IN+
CRITICAL 1%
MF 3 IN+
CRITICAL
1/3W
1% REF 8 1/20W 1% REF 8
1W
CYN 54 ISNS_HS_OTHER3V3_N LOADISNS
MF
201 R54481 1 C5449 0.005 54 ISNS_SPKRAMP_RIGHT_N LOADISNS
1
R54B5
0612 2 4 4 IN- NC 1 9.09K 2.2UF R54B0 4 IN- NC 1 15K
NC 20% 1 3 NC
5 IN- NC 7
1%
1/20W 2 6.3V
OMIT 5 IN- NC 7
5%
1/20W
86 68 PPVIN_G3H_P3V3G3H
PLACE_NEAR=U5440.4:5MM
100x NC MF
201 2
X5R-CERM
0201 59 PPBUS_G3H_SPKRAMP_RIGHT 200x NC MF
GND NO_XNET_CONNECTION=1 PLACE_NEAR=U54B0.4:5MM GND 2 201
PLACE_NEAR=U7800.A16:7.5MM PLACE_NEAR=U7800.A16:7.5MM PLACE_NEAR=U54B0.10:5MM
9

9
LOADISNS
LOADRC:YES LOADISNS

3.3V RTC High Side Current Sense (IR3R) PBUS Voltage Sense & Enable (VP0R) DC In Voltage Sense (VD0R)
Gain: 100x, EDP: 2.413 A BYPASS=U5420.6::5MM
GAIN: 0.089X GAIN: 0.058X
Rsense: 0.01 (R5420) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS VNOMINAL: 12.6 V, RANGE: 14.05 V CRITICAL VNOMINAL: 16.5 V, RANGE: 21.45 V
LOADISNS
Vsense: 24.1 mV, Range: 3.3 A 1 C5420 SMC ADC: 01 Q5480 SMC ADC: 04 87 83 64 27 PPDCIN_G3H Rthevenin = 4586 Ohms
EADC1: CH4 0.1UF NTUD3169CZ
6

75 72 64 62 49 PPBUS_G3H V+
10%
2 6.3V
SOT-963
N-CHANNEL R54981
87 86 83 PLACE_NEAR=U5420.2:5MM CERM-X5R
0201
6 PBUSVSENS_EN_L 78.7K
B OMIT
U5420
INA214A P2MM PP5401 Enables PBUS VSense D
1%
1/20W
MF
B
divider when in S0. 1
R5420 1 3 54 ISNS_HS_3V3RTC_P 2 IN+ UQFN
OUT 10 HS_3V3RTC_IOUT 1
SM
R5482 PLACE_NEAR=U3900.Y7:7.5MM
201 2

0.005
PP
100K SMC_DCIN_VSENSE 35
3 IN+ CRITICAL 83 74 72 50 IN
SENSOR_PWR_EN 2 G 1%
OUT
1% REF 8 1 S 1/20W PLACE_NEAR=U3900.Y7:7.5MM 1 PLACE_NEAR=U3900.Y7:7.5MM
1/3W
MF 54 ISNS_HS_3V3RTC_N LOADISNS R5425 MF
201 2 R5499 1 C5499
0306-SHORT 2 4 4 IN- NC 1 NC 1%
15K XW5480
SM
1 4.87K
1% 0.022UF
5 IN- NC 7 1/20W 3 PBUS_S0_VSENSE 1/20W 10%
87 63 PPVIN_G3H_P3V3G3HRTC
PLACE_NEAR=U5420.4:5MM
100x NC MF 87 86 83 75 72 64 62 49 PPBUS_G3H 1 2 PBUS_S0_VSENSE_IN MF 2 6.3V
X5R-CERM
GND 2 201 PLACE_NEAR=R5400.1:10 MM D 201 2 0201
1 GND_SMC_AVSS
PLACE_NEAR=U5420.10:5MM R5488 35 42 49 50 51 52
9

LOADISNS R5481 R5483 51.1K

5 G 0 1% PLACE_NEAR=U3900.Y5:7.5MM
2
100K 1 S
1 2 1/20W
MF
1% 4
5%
1/20W
201 2 Rthevenin = 4546 Ohms
1/20W MF SMC_PBUS_VSENSE
NAND Current Sense (IHNR) MF
201
P-CHANNEL 0201
NOSTUFF
OUT 35

Gain: 100x, EDP: 1.471 A BYPASS=U5460.6::5MM R54891 1 C5489

Rsense: 0.02 (R5460) [Production] 74 54 52 51 50 49 PP3V3_S4SW_SNS 4.99K 0.022UF
LOADISNS 1% 10% PLACE_NEAR=U3900.Y5:7.5MM
Vsense: 29.4 mV, Range: 1.5 A 1/20W 2 6.3V
MUX: A6
1 C5460 PBUSVSENS_EN_L_DIV MF
201 2
X5R-CERM
0201 PLACE_NEAR=U3900.Y5:7.5MM
0.1UF
DC-IN (AMON) Current Sense (ID0R)
6

83 75 72 64 62 49 PPBUS_G3H 10%
PLACE_NEAR=U7800.E14:7.5MM GND_SMC_AVSS 35 42 49 50 51 52
87 86 V+ 2 6.3V
CERM-X5R
PLACE_NEAR=U5460.2:5MM 0201 LOADISNS R5439 PLACE_NEAR=U3900.AB5:7.5MM
U5460 R5469 4.53K 2
OMIT INA214A 64 54 IN
CHGR_AMON 1 SMC_DCIN_ISENSE OUT 35
1 3 ISNS_SSDNAND_P UQFN 10 SSDNAND_IOUT 9.09K 2 PMU_SSDNAND_ISENSE
R5460 54 2 IN+
CRITICAL
OUT 1 OUT 72
Charger Gain: 20x
1%
1/20W
PLACE_NEAR=U3900.AB5:7.5MM
0.005
1%
3 IN+
REF 8
1%
1/20W EDP: 4.6 A
MF
201
1 C5439
1/3W MF R5468 1 1 C5469 0.022UF
MF 54 ISNS_SSDNAND_N LOADISNS 201
2.2UF Rsense: 0.010 (R7020) 10%
0306-SHORT 2 4 4 IN- NC 1 NC 9.09K 20% 2 6.3V
X5R-CERM
5 IN- NC 7
1%
1/20W 2 6.3V
SMC ADC: 03 0201
85 81 PPBUS_G3H_SSD0 100x NC MF X5R-CERM
A PLACE_NEAR=U5460.4:5MM GND
PLACE_NEAR=U7800.E14:7.5MM
201 2 0201
PLACE_NEAR=U7800.E14:7.5MM
GND_SMC_AVSS 35 42 49 50 51 52
A
Charger (BMON) Current Sense (IPBR)
SYNC_MASTER= SYNC_DATE=
9

Stuff 0.005 for PVT per <rdar://49214265> LOADISNS PAGE TITLE

LOADRC:YES
R5479 PLACE_NEAR=U3900.AE2:7.5MM POWER SENSORS HIGH SIDE
CHGR_BMON 1
4.53K 2 SMC_BMON_ISENSE DRAWING NUMBER SIZE
64 54 35
IN OUT
051-05309 D
Charger Gain: 7.9x
1%
1/20W Apple Inc. REVISION

EDP: 20.83 A
MF
201 R54781 1 C5479 5.1.0
9.09K 0.022UF
10%
Rsense: 0.005 (R7060) 1%
1/20W 2 6.3V
NOTICE OF PROPRIETARY PROPERTY: BRANCH
X5R-CERM
SMC ADC: 02 MF
201 2 0201 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PLACE_NEAR=U3900.AE2:7.5MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE

117S0008 3 RES,MTL FLIM,100K,1/16W,0201,SMD,LFR5418,R5448, R5468 LOADRC:NO

NOSTUFF
PLACE_NEAR=U3900.AE2:7.5MM GND_SMC_AVSS 35 42 49 50 51 52
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 49 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

CPU VCCIO Current Sense (IC1C) CPU Core Current Sense (ICAC)
Gain: 200x, EDP: 3.6 A Gain: 104.38x, EDP: 64 A
BYPASS=U5560.6::5MM
Rsense: 0.003 (R8102) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375
LOADISNS
Vsense: 10.8 mV, Range: 5 A Vsense: 24 MV, Range: 76.64 A
PMU AMUX: A3
1 C5560 BYPASS=U5540.5::5MM
0.1UF PMU AMUX: B7 R5545 74 54 52 51 50 49 PP3V3_S4SW_SNS LOADISNS

6
10% 4.42K 2
V+ 2 6.3V PLACE_NEAR=U7800.B14:7.5MM 66 CPUCORE_ISNS1_P 1
CERM-X5R
0201 LOADISNS IN
LOADISNS 1 C5540
PLACE_NEAR=R8102.3:6MM U5560 R5569
PLACE_NEAR=R7210:5MM 0.1%
1/20W CRITICAL 0.1UF
10%
INA210A LOADISNS MF PLACE_NEAR=U7800.H13:7.5MM
9.09K 2 0201 LOADISNS 2 6.3V
73 IN
ISNS_CPUVCCIO_P 2 IN+ UQFN
OUT 10 CPUVCCIO_IOUT 1 PMU_CPUVCCIO_ISENSE OUT 72
R5546 R5542 U5540 CERM-X5R
0201 LOADISNS
CRITICAL ISL28133

5
3 IN+ 1%
CPUCORE_ISNS2_P 4.42K 2 54 ISNS_CPUVR_P 4.64K 2 ISNS_CPUVR_R_P SC70-5 R5549
REF 8 1/20W 66 1 1 1
MF R5568 1 1 C5569 IN
V+ 4 CPUVR_ISUM_IOUT 9.09K 2 PMU_CPU_ISENSE D
D 73 IN
ISNS_CPUVCCIO_N 4 IN-
LOADISNS
NC 1 NC
201
9.09K
1% 20%
2.2UF PLACE_NEAR=R7220:5MM
LOADISNS
0.1%
1/20W
MF
1%
1/20W
MF 3 V-
1
1%
OUT 72

5 IN- NC 7 1/20W 2 6.3V 0201 201 1/20W

200x NC MF X5R-CERM
0201 R5547 R5543 MF 1 C5549

2
201 2 201
PLACE_NEAR=R8102.4:6MM GND 4.42K 2 4.64K 2 2.2UF
PLACE_NEAR=U7800.B14:7.5MM PLACE_NEAR=U7800.B14:7.5MM 66 CPUCORE_ISNS1_N 1 54 ISNS_CPUVR_N 1 ISNS_CPUVR_R_N R554A 1 20%
IN
2 6.3V

9
LOADRC:YES LOADISNS PLACE_NEAR=R7210:5MM 0.1% 1% 9.09K X5R-CERM
1 0201
LOADISNS
1/20W
MF
1/20W
MF R5544 R5541
1%
1/20W PLACE_NEAR=U7800.H13:7.5MM
0201 201 715K MF
R5548 LOADISNS 0.1%
1
715K 2 201 2 LOADISNS
1/20W
4.42K 2
DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C) 66 IN
CPUCORE_ISNS2_N 1 MF
0201
2 LOADISNS 0.1%
1/20W
PLACE_NEAR=U7800.H13:7.5MM
LOADRC:YES
Gain: 200x, EDP: 6.9 A PLACE_NEAR=R7220:5MM 0.1%
1/20W
NO_XNET_CONNECTION=1 MF
0201 NO_XNET_CONNECTION=1
Rsense: 0.002 (R8118) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS LOADISNS MF
BYPASS=U5500.6::5MM 0201 LOADISNS
Vsense: 13.8 mV, Range: 7.5 A PLACE_NEAR=U7800.G13:7.5MM
PMU AMUX: A4
1 C5500
0.1UF XW5550
CPU Core Voltage Sense (VCAC) R5559

6
10% SM
V+ 2 6.3V PLACE_NEAR=U7800.D13:7.5MM 4.53K 2
CERM-X5R
0201 LOADISNS PMU AMUX: B4 87 83 66 9 7 PPVCC_S0_CPU 1 2 CPUVSENSE_IN 1 PMU_CPU_VSENSE OUT 72

PLACE_NEAR=R8118.4:5MM U5500 R5509 PLACE_NEAR=R7210.2:5 MM 1%

INA210A 1/20W
ISNS_CPUDDR_P 2 IN+ UQFN
OUT 10 ISNS_DDR_IOUT 1
9.09K 2 PMU_DDR1V2_ISENSE
MF
201
1 C5559
73 54 IN
CRITICAL OUT 72
2.2UF
3 IN+ 1% 20%
REF 8 1/20W 2 6.3V
LOADISNS
MF
201 R5508 1 1 C5509 X5R-CERM
0201
73 54 ISNS_CPUDDR_N 4 IN- NC 1 9.09K 2.2UF PLACE_NEAR=U7800.G13:7.5MM
IN NC 1% 20%
5 IN- NC 7 1/20W 2 6.3V
200x NC MF
201 2
X5R-CERM
0201
PLACE_NEAR=R8118.3:5MM GND
PLACE_NEAR=U7800.D13:7.5MM PLACE_NEAR=U7800.D13:7.5MM

9
LOADRC:YES LOADISNS

CPU GT+GTX Current Sense (ICGC)

C CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC) Gain: 104.38x, EDP: 64 A C
Gain: 200x, EDP: 2.6 A Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375
BYPASS=U5510.6::5MM Vsense: 24 mV, Range: 76.64 A
Rsense: 0.005 (R5510) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS BYPASS=U5580.5::5MM
LOADISNS PMU AMUX: B6 R5585 PP3V3_S4SW_SNS
Vsense: 13 mV, Range: 3 A 74 54 52 51 50 49 LOADISNS
PMU AMUX: B2
1 C5510 CPUGT_ISNS1_P 1
4.42K 2
0.1UF 67 IN
LOADISNS 1 C5580
6

10% PLACE_NEAR=R7410.4:5MM 0.1%

23 22 21 20 19 PP1V2_S3 V+ 2 6.3V
CERM-X5R
PLACE_NEAR=U7800.E12:7.5MM 1/20W CRITICAL 0.1UF PLACE_NEAR=U7800.H14:7.5MM
88 83 74 73 LOADISNS LOADISNS MF LOADISNS 10%
0201 2 6.3V LOADISNS
OMIT PLACE_NEAR=U5510.2:5MM U5510 R5519
0201
R5586 R5582 U5580 CERM-X5R
0201
INA210A ISL28133

5
R5510 2 4 54 ISNS_CPUVDDQ_P 2 IN+ UQFN 10 CPUDDR_IOUT 1
9.09K 2 PMU_CPUDDR_ISENSE CPUGT_ISNS2_P 1
4.42K 2 54 ISNS_CPUGT_P 1
4.64K 2 ISNS_CPUGT_R_P 1 SC70-5 R5589
OUT OUT 72 67 IN
0.005 3 IN+
CRITICAL 1% 0.1% 1%
V+ 4 CPUGT_ISUM_IOUT 1
9.09K 2 PMU_CPUGT_ISENSE
PLACE_NEAR=R7420.4:5MM OUT 72
1% REF 8 1/20W 1/20W 1/20W
1/3W
54 ISNS_CPUVDDQ_N LOADISNS
MF
201 R5518 1 1 C5519 LOADISNS MF
0201
MF
201
3 V- 1%
1/20W
MF 4 IN- NC 1 9.09K 2.2UF 1 C5589
0306-SHORT 1 3 NC 20% R5588 R5583 MF

2
1% 201
5 IN- NC 7 1/20W 2 6.3V 4.42K 2 4.64K 2 2.2UF
88 83 9 7 6 PP1V2_S3_CPUDDR 200x NC MF
201 2
X5R-CERM
0201 67 IN
CPUGT_ISNS1_N 1 54 ISNS_CPUGT_N 1 ISNS_CPUGT_R_N R558A 1 20%
2 6.3V
PLACE_NEAR=U5510.4:5MM GND PLACE_NEAR=R7410.3:5MM 0.1% 1% 9.09K X5R-CERM
1 0201
PLACE_NEAR=U7800.E12:7.5MM PLACE_NEAR=U7800.E12:7.5MM 1/20W 1/20W R5584 1%
9

LOADISNS MF MF
715K R5581 1/20W PLACE_NEAR=U7800.H14:7.5MM
LOADRC:YES LOADISNS 0201 201
715K MF
0.1%
1 2 201 2 LOADISNS
R558C LOADISNS 1/20W PLACE_NEAR=U7800.H14:7.5MM
MF
CPUGT_ISNS2_N 1
4.42K 2 2 0201
0.1%
1/20W
LOADRC:YES
67 IN
LOADISNS
DFR Current Sense (IF3C) PLACE_NEAR=R7420.3:5MM 0.1%
1/20W
NO_XNET_CONNECTION=1
MF
0201
NO_XNET_CONNECTION=1
Gain: 100x, EDP: 0.75 A LOADISNS MF
PP3V3_S4SW_SNS BYPASS=U5520.6::5MM 0201 LOADISNS
Rsense: 0.025 (R5520) or SHORT 74 54 52 51 50 49
LOADISNS PLACE_NEAR=U7800.G14:7.5MM
Vsense: 18.8 mV, Range: 1.32 A 1 C5520
0.1UF
CPU GT Voltage Sense (VCGC) XW5590 R5599
PMU AMUX: B5 SM
6

10% 4.53K 2 PMU_CPUGT_VSENSE

89 86 83 76
57 54 29 28 27 PP3V3_G3H_RTC V+ 2 6.3V PLACE_NEAR=U5710.24:5MM 87 83 67 10 7 PPVCCGT_S0_CPU 1 2 CPUGTVSENSE_IN 1 72
74 72 71 63 61 PLACE_NEAR=U5520.2:5MM CERM-X5R LOADISNS OUT
0201
B OMIT
U5520
INA214A R5529
PLACE_NEAR=R7410.1:5 MM 1%
1/20W
MF 1 C5599 B
45.3K 2 201
2.2UF
R5520 1 3 54 ISNS_DFR3V3_P 2 IN+
CRITICAL
UQFN
OUT 10 DFR3V3_IOUT 1 EADC2_P3V3_DFR_ISENSE OUT 52
20%
0.005 3 IN+ 1% 2 6.3V
X5R-CERM
1% REF 8 1/20W
1/3W
MF 54 ISNS_DFR3V3_N LOADISNS
1
R5525 MF
201
1 C5529 0201
PLACE_NEAR=U7800.G14:7.5MM
0306-SHORT 2 4 4 IN- NC 1 20K 2.2UF
NC 5% 20%
5 IN- NC 7 1/20W 2 6.3V
46 PP3V3_G3H_RTC_DFR
PLACE_NEAR=U5520.4:5MM
100x NC MF X5R-CERM
0201
GND 2 201
PLACE_NEAR=U5520.10:5MM PLACE_NEAR=U5710.24:5MM
9

LOADISNS
NOSTUFF
GND_EADC2_COM 49 51 52 54

WLANBT 3.3V Current Sense (IW3C) LOADISNS

Gain: 163.3x, EDP: 1.698 A
D5530 LOADISNS MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
Rsense: 0.003 (R5530) or Rsense SHORT LGA NO_XNET_CONNECTION=1
VSENSE: 5.09 MV, RANGE: 2.55 A 75 68 55 54 52 51 46 29 28 PP5V_G3S A K PLACE_NEAR=R5531.2:5MM PP5V_WLAN_ISNS_D 50
86 83
SMC ADC: 05 LOADISNS
RB522ES-30 Q5530 2
BYPASS=U5530.6::5MM
DMP31D0UFB4
U5530
DFN1006H4-3
1 C5530
ISNS_WLANBTP3V3_R_P S 0.1UF
LTC2050HV 10%
PP3V3_G3S_WLANBT LOADISNS TSOT23-6 2 10V LOADISNS
83 32 PLACE_NEAR=U5530.3:5MM
R5531 CRITICAL 1
X5R-CERM
0201 PP5V_WLAN_ISNS_D 50
LOADISNS PLACE_NEAR=U3900.AD4:7.5MM
6

ISNS_WLANBTP3V3_P 1
120 2 3 G
NO_XNET_CONNECTION=1
OMIT
54
0.1% 1/20W MF 0201 + V+
R5539 LOADISNS LOADISNS
1 3 CKPLUS_WAIVE=PDIFPR_BADTERM 1 WLANBTP3V3_IOUT 4.53K 2 SMC_PP3V3_WLANBT_ISENSE 1 1
R5530 CKPLUS_WAIVE=PDIFPR_BADTERM SHDN*
D
1 OUT 35 R5535 R5536
0.005 LOADISNS 1% LOADRC:YES 100K 100K
1% ISNS_WLANBTP3V3_R_N 4
- V- 3 1/20W 5% 5%
1/3W 1
R5534 MF 1 C5539 1/20W 1/20W
5

A MF
0306-SHORT 2 4
LOADISNS
R5532 1
R5533 19.6K
201
0.022UF MF
2 201
MF
2 201
A
2

0.1% 10% SYNC_MASTER= SYNC_DATE=

120 100K 1/20W 2 6.3V WLAN_OP_EN_L PAGE TITLE

ISNS_WLANBTP3V3_N 1 2 ISNS_WLAN_OP X5R-CERM
75 74 62 57 51 45
83 76
PP3V3_G3S
54

MF
5%
1/20W
MF
MF
2 0201
0201
PLACE_NEAR=U3900.AD4:7.5MM D 6
WLAN_OP_EN 50 POWER SENSORS LOAD SIDE
PLACE_NEAR=U5530.4:5MM 0201 LOADISNS LOADISNS
1/20W WLAN_OP_EN 2 201 CRITICAL CRITICAL
DRAWING NUMBER SIZE
0.1%
50
LOADISNS D 3 051-05309 D
GND_SMC_AVSS 35 42 49 51 52
Q5531VER-1
Q5531 Apple Inc. REVISION
SSM6N15AFEAP SSM6N15AFEAP
SOT563 VER-1
SOT563 5.1.0
2 G S 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH

5 G S 4 THE INFORMATION CONTAINED HEREIN IS THE

83 74 72 49 IN
SENSOR_PWR_EN PROPRIETARY PROPERTY OF APPLE INC.
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION THE POSESSOR AGREES TO THE FOLLOWING: PAGE

117S0008 6 RES,MTL FLIM,100K,1/16W,0201,SMD,LF R5508,R5518,R5568,R554A,R558A,C5539 LOADRC:NO

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 50 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

Thunderbolt TBD Left Current Sense (IULC) CPU Reg. ALSCAM, LCD 5V Current Sense (IC5C)
Gain: 200x. EDP: 0.7 A Gain: 200x. EDP: 0.42+0.1+0.1 A
Rsense: 0.025 (R5640) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS BYPASS=U5640.6::5MM Rsense: 0.025 (R5660) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS BYPASS=U5660.6::5MM
Vsense: 17.5 mV, Range: 0.66 A LOADISNS Vsense: 15.5 mV, Range: 0.60 A LOADISNS
1 C5640 PMU AMUX: A7 1 C5660
0.1UF 0.1UF

6
74 PP3V3_S0_TBT_X_ISNS_R V+ 10% 83 75 68 55 54 52 50 46 29 28 PP5V_G3S V+ 10% PLACE_NEAR=U7800.F14:7.5MM
PLACE_NEAR=U5640.2:5MM 2 6.3V
CERM-X5R
86 PLACE_NEAR=U5660.2:5MM 2 6.3V
CERM-X5R LOADISNS
U5640 0201 U5660 0201
R5669
OMIT INA210A P2MM PP5601 OMIT INA210A
1 3 ISNS_TBTX_P UQFN 10 TBTXP3V3_IOUT 1
SM
1 3 ISNS_P5VCPUREGMISC_P UQFN 10 CPUREGMISCP5V_IOUT 9.09K 2 PMU_P5V_CPUREGMISC_ISENSE
R5640 54 2 IN+
CRITICAL
OUT PP R5660 54 2 IN+
CRITICAL
OUT 1 OUT 72
0.005 3 IN+ 0.005 3 IN+ 1%
1% REF 8 1% REF 8 1/20W
1/3W
ISNS_TBTX_N
1
R5645 1/3W
ISNS_P5VCPUREGMISC_N
MF R5668 1 1 C5669 D
D MF
0306-SHORT 2 4
54
4 IN-
LOADISNS
NC 1 NC 5%
20K
MF
0306-SHORT 2 4
54
4 IN-
LOADISNS
NC 1 NC
201
9.09K
1%
2.2UF
20%
5 IN- NC 7 5 IN- NC 7 2 6.3V
88 27 26 PP3V3_TBT_X_S0 PLACE_NEAR=U5640.4:5MM 200x NC 1/20W
MF 86 83 76 74 73 69 67 66 65 PP5V_G3S_CPUREG_MISC PLACE_NEAR=U5660.4:5MM 200x NC 1/20W
MF X5R-CERM
0201
GND 2 201 GND
201 2
PLACE_NEAR=U5640.10:5MM PLACE_NEAR=U7800.F14:7.5MM
PLACE_NEAR=U7800.F14:7.5MM

9
LOADISNS
NOSTUFF LOADRC:YES

LCD Panel 3.3V Current Sense (ILDC)

Gain: 200x. EDP: 1 A
BYPASS=U5620.6::5MM
LPDDR 1.8V Current Sense (IM1C)
RSENSE: 0.01 (R8520) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS Gain: 200x. EDP: 0.45 A
LOADISNS PP3V3_S4SW_SNS
Vsense: 10 mV, Range: 1.5 A Rsense: 0.005 (R5630) or SHORT 74 54 52 51 50 49 BYPASS=U5630.6::5MM
1 C5620 Vsense: 2.25 mV, Range: 3.3 A LOADISNS
0.1UF

6
V+
10%
2 6.3V
PLACE_NEAR=U7800.C13:7.5MM 1 C5630
0.1UF

6
CERM-X5R LOADISNS
U5620 0201 70 PP1V8_S3 V+ 10%
PLACE_NEAR=R8520.3:5MM R5629 PLACE_NEAR=U5630.2:5MM 2 6.3V
CERM-X5R
INA210A 9.09K 2 U5630 0201
76 54 IN
ISNS_LCDPANEL_P 2 IN+ UQFN
OUT 10 LCDPANEL_IOUT 1 PMU_LCDPANEL_ISENSE OUT 72 OMIT INA210A P2MM PP5630
CRITICAL 1 3 ISNS_P1V8LPDDR_P UQFN 10 LPDDRP1V8_IOUT 1
SM
3 IN+
REF 8
1%
1/20W R5630 54 2 IN+
CRITICAL
OUT PP

LOADISNS
MF
201 R5628 1 1 C5629 0.005
1%
3 IN+
REF 8
76 54 ISNS_LCDPANEL_N 4 IN- NC 1 9.09K 2.2UF 1/3W 1
R5635
IN NC 1% 20% MF 54 ISNS_P1V8LPDDR_N LOADISNS
5 IN- NC 7 2 6.3V 0306-SHORT 2 4 4 IN- NC 1 20K
200x NC 1/20W
MF X5R-CERM
0201 5 IN- NC 7
NC 5%
PLACE_NEAR=R8520.4:5MM GND
PLACE_NEAR=U7800.C13:7.5MM
201 2
PLACE_NEAR=U7800.C13:7.5MM 88 83 23 22 21 20 PP1V8_S3_MEM PLACE_NEAR=U5630.4:5MM 200x NC 1/20W
MF
2 201

9
GND
LOADRC:YES LOADISNS PLACE_NEAR=U5630.10:5MM

9
NOSTUFF

C Trackpad 3V Current Sense (IT3C) C

Gain: 200x, EDP: 0.05 A
LOADISNS
Rsense: 0.1 (R5650) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS
BYPASS=U5650.6::5MM
1.8V Standby Current Sense
Vsense: 5 mV, Range: 0.17 A Gain: None. EDP: 0.65 A
1 C5650 Rsense: 0.025 (R56B0) or SHORT
0.1UF
6

10% Vsense: 16.25 mV

62 57 51 50 45 PP3V3_G3S V+ 2 6.3V PLACE_NEAR=U5710.23:5MM
83 76 75 74 PLACE_NEAR=U5650.2:5MM CERM-X5R LOADISNS
0201
NO_XNET_CONNECTION=1 U5650 R5659 74 PP1V8_G3S_REG
OMIT INA210A 45.3K 2 PLACE_NEAR=U8220:5MM
1 3 ISNS_TPADP3V3_P UQFN 10 TPADP3V3_IOUT EADC2_P3V3_TPAD_ISENSE
R5650 54 2 IN+
CRITICAL
OUT 1 OUT 52
OMIT
0.005 3 IN+ 1%
1%
1/3W
REF 8 1
R5655
1/20W
MF 1 C5659 R56B0 2 4 ISNS_P1V8G3S_P 54
MF 54 ISNS_TPADP3V3_N LOADISNS 201
2.2UF 0.005
OUT
0306-SHORT 2 4 4 IN- NC 1 NC 20K 20%
5% 1%
5 IN- NC 7 1/20W 2 6.3V
83 62 PP3V3_G3S_TPAD PLACE_NEAR=U5650.4:5MM 200x NC MF X5R-CERM
0201
1/3W
MF ISNS_P1V8G3S_N OUT 54
GND 2 201 0306-SHORT 1 3
PLACE_NEAR=U5650.10:5MM PLACE_NEAR=U5710.23:5MM PP1V8_G3S
9

58 57 55 51 48 47 45 44 43 18
NOSTUFF LOADISNS 83 76 74 68 62 61 60 59

GND_EADC2_COM 49 50 51 52 54

WLANBT 1.8V Current Sense (IW2C)

Gain: 200x, EDP: 0.0085 A
PP3V3_S4SW_SNS LOADISNS
Rsense: 1 (R5680) or SHORT 74 54 52 51 50 49
BYPASS=U5680.6::5MM
Vsense: 8.5 mV, Range: 0.013 A
SMC ADC: 06
1 C5680
0.1UF
6

10% LOADISNS
68 62 61 60
47 45 44 43
59
18 PP1V8_G3S V+ 2 6.3V
CERM-X5R
58 57 55 51
83 76
48
74 PLACE_NEAR=U5680.2:5MM 0201 PLACE_NEAR=U3900.AF1:7.5MM
B NO_XNET_CONNECTION=1
OMIT
U5680
INA210A R5689 B
9.09K 2
R5680 1 3 54 ISNS_WLANBTP1V8_P 2 IN+ UQFN
CRITICAL
OUT 10 WLANBTP1V8_IOUT 1 SMC_PP1V8_WLANBT_ISENSE OUT 35
0.005 3 IN+ 1%
1% REF 8 1/20W
1/3W
MF 54 ISNS_WLANBTP1V8_N LOADISNS
MF
201 R5688 1 1 C5689
0306-SHORT 2 4 4 IN- NC 1 9.09K 0.022UF
NC 1% 10%
5 IN- NC 7 1/20W 2 6.3V
83 32 PP1V8_G3S_WLANBT PLACE_NEAR=U5680.4:5MM 200x NC MF
201 2
X5R-CERM
0201
GND
PLACE_NEAR=U3900.AF1:7.5MM PLACE_NEAR=U3900.AF1:7.5MM
9

LOADRC:YES LOADISNS
GND_SMC_AVSS 35 42 49 50 52

Keyboard 3.3V Current Sense (IK3C)

Gain: 200x, EDP: 0.043 A
PP3V3_S4SW_SNS LOADISNS
Rsense: 0.1 (R5690) or SHORT 74 54 52 51 50 49
BYPASS=U5690.6::5MM
Vsense: 4.3 mV, Range: 0.17 A 1 C5690
0.1UF
6

10%
62 57 51 50 45 PP3V3_G3S V+ 2 6.3V PLACE_NEAR=U5710.4:5MM
83 76 75 74 PLACE_NEAR=U5690.2:5MM CERM-X5R LOADISNS
0201
NO_XNET_CONNECTION=1 U5690 R5699
OMIT INA210A 45.3K 2
R5690 1 3 54 ISNS_KBDP3V3_P 2 IN+ UQFN
CRITICAL
OUT 10 KBDP3V3_IOUT 1 EADC2_P3V3_KBD_ISENSE OUT 52
0.005 3 IN+ 1%
1% REF 8 1
1/20W
1/3W
MF 54 ISNS_KBDP3V3_N LOADISNS R5695 MF
201 LOADISNS
0306-SHORT 2 4 4 IN- NC 1 20K
5 IN- NC 7
NC 5%
1/20W
1 C5699
61 PP3V3_G3S_KBD PLACE_NEAR=U5690.4:5MM 200x NC MF 2.2UF
A GND 2 201
20%
2 6.3V
X5R-CERM SYNC_MASTER= SYNC_DATE=
A
PLACE_NEAR=U5690.10:5MM 0201
9

PAGE TITLE
NOSTUFF PLACE_NEAR=U5710.4:5MM POWER SENSORS EXTENDED
GND_EADC2_COM 49 50 51 52 54 DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION THE POSESSOR AGREES TO THE FOLLOWING: PAGE

117S0008 3 RES,MTL FLIM,100K,1/16W,0201,SMD,LF R5628,R5668,R5688 LOADRC:NO

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
56 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 51 OF 98
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QQ微信：181806465
 8 7 6 5 4 3 2 1

Calpe 3.3V Input Current Left (IP3C) CPU SA Current Sense (ICSC)
Gain: 100x. EDP: 10.224 A Gain: 100X, EDP: 9.5 A
BYPASS=U5780.6::5MM BYPASS=U5770.6::5MM
Rsense: 0.002 (R5780) 74 54 52 51 50 49 PP3V3_S4SW_SNS Rsense: 0.002 (R7270) 74 54 52 51 50 49 PP3V3_S4SW_SNS
LOADISNS LOADISNS
Vsense: 20.448 mV, Range: 12.5 A Vsense: 19 mV, Range: 15 A
1 C5780 PMU AMUX: B1
1 C5770
0.1UF 0.1UF

6
10% PLACE_NEAR=U3900.Y6:7.5MM 10% LOADISNS
83 74 68 63 54 PP3V3_G3H V+ 2 6.3V
CERM-X5R V+ 2 6.3V
CERM-X5R PLACE_NEAR=U7800.E13:7.5MM
86 PLACE_NEAR=U5780.2:5MM 0201 LOADISNS 0201
OMIT NO_TEST=1 U5780 R5789 PLACE_NEAR=R7270.3:5MM U5770 R5779
R5780 INA214A 9.09K 2 INA214A 9.09K 2
0306-SHORT 2 4 54 ISNS_CALPE_P 2 IN+ UQFN
OUT 10 ISNS_CALPE_IOUT 1 SMC_CALPE_ISENSE OUT 35 66 IN
CPUSA_ISNS_P 2 IN+ UQFN
OUT 10 ISNS_CPUSA_IOUT 1 PMU_CPUSA_ISENSE OUT 72
MF 3 IN+
CRITICAL 1% 3 IN+
CRITICAL 1%
1/3W NO_TEST=1
1% REF 8 1/20W REF 8 1/20W
0.005 ISNS_CALPE_N
MF R5788 1 1 C5789 MF R5777 1 1 C5779 D
D 1 3
54
4 IN-
LOADISNS
NC 1 NC
201
9.09K
1%
0.022UF
10% 66 IN
CPUSA_ISNS_N 4 IN-
LOADISNS
NC 1 NC
201
9.09K
1%
2.2UF
20%
5 IN- NC 7 2 6.3V 5 IN- NC 7 2 6.3V
86 71 70 PP3V3_G3H_PMU_VDDMAIN 100x NC 1/20W
MF
201 2
X5R-CERM
0201 PLACE_NEAR=R7270.4:5MM 100x NC 1/20W
MF
201 2
X5R-CERM
0201
PLACE_NEAR=U5780.4:5MM GND GND
PLACE_NEAR=U7800.E13:7.5MM
PLACE_NEAR=U3900.Y6:7.5MM PLACE_NEAR=U3900.Y6:7.5MM PLACE_NEAR=U7800.E13:7.5MM

9
LOADISNS
LOADRC:YES LOADISNS LOADRC:YES
GND_SMC_AVSS 35 42 49 50 51

CPU SA Voltage Sense (VCSC) PLACE_NEAR=U7800.F13:7.5MM

KB backlite Current Sense (IKBC) PMU AMUX: B3

XW5778 R5778
Gain: 200x, EDP: 0.17 A SM
PP3V3_S4SW_SNS BYPASS=U5730.6::5MM
PPVCCSA_S0_CPU 1 2 CPUSAVSENSE_IN 1
4.53K 2 PMU_CPUSA_VSENSE
Rsense: 0.05 (R5730) 74 54 52 51 50 49 87 83 66 9 7 OUT 72
LOADISNS PLACE_NEAR=R7270.2:5 MM
Vsense: 8.5 mV, Range: 0.33 A 1%
1 C5730 1/20W
MF
1 C5778
0.1UF 201 2.2UF

6
10% 20%
V+ 2 6.3V PLACE_NEAR=U5710.1:5MM 2 6.3V
54 51 50 46 29 28 PP5V_G3S CERM-X5R
0201 LOADISNS X5R-CERM
0201
86 83 75 68 55 PLACE_NEAR=U5730.2:5MM U5730 R5739 PLACE_NEAR=U7800.F13:7.5MM
OMIT
R5730 1 3 54 ISNS_KBBLT_P 2 IN+
INA210A
UQFN
OUT 10 ISNS_KBBLT_IOUT 1
45.3K 2 EADC2_KBBLT_ISENSE 52
CPU EDRAM Current Sense (ICEC)
0.005 3 IN+
CRITICAL 1%
Gain: 200x, EDP: 6.2 A
BYPASS=U5790.6::5MM
1% REF 8 1/20W Rsense: 0.002 (R7702) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS
1/3W
MF 54 ISNS_KBBLT_N LOADISNS
1
R5735 MF
201
1 C5739 Vsense: 12.4 mV, Range: 7.5 A LOADISNS
0306-SHORT 2 4 4 IN- NC 1 20K 2.2UF 1 C5790
NC 5% 20% PMU AMUX: A2
5 IN- NC 7 1/20W 2 6.3V 0.1UF
200x

6
85 83 75 PP5V_G3S_KBD NC MF X5R-CERM
0201
10% LOADISNS
PLACE_NEAR=U5730.4:5MM GND 2 201 V+ 2 6.3V
CERM-X5R
PLACE_NEAR=U5710.1:5MM 0201 PLACE_NEAR=U7800.A14:7.5MM
PLACE_NEAR=U5730.10:5MM U5790
9
LOADISNS PLACE_NEAR=R7702.4:5MM R5799
NOSTUFF GND_EADC2_COM INA210A 9.09K 2
49 50 51 52 54
69 54 IN
ISNS_CPUEDRAM_P 2 IN+ UQFN
OUT 10 ISNS_CPUEDRAM_IOUT 1 PMU_CPUEDRAM_ISENSE OUT 72
3 IN+
CRITICAL 1%
REF 8 1/20W
C LOADISNS
MF
201 R5798 1 1 C5799
2.2UF
C
69 54 IN
ISNS_CPUEDRAM_N 4 IN- NC 1 NC 9.09K 20%
1%
5 IN- NC 7 1/20W 2 6.3V
PLACE_NEAR=R7702.3:5MM 200x NC MF
201 2
X5R-CERM
0201
GND
PLACE_NEAR=U7800.A14:7.5MM
PLACE_NEAR=U7800.A14:5MM

9
LOADISNS
LOADRC:YES

EADC2
(Write: 0x12 Read: 0x13)
B BYPASS=U5710.12::5MM
B
LOADISNS
R5710 BYPASS=U5710.21::3MM BYPASS=U5710.13::3MM

PP5V_S4SW 1
0 2 PP5V_EADC2_AVDD LOADISNS LOADISNS
74 47

5%
1/20W
MF
C5712 1 1 C5713 1 C5711 1
R5712
0201 4.7UF 0.1UF 0.1UF 100K
20% 10% 10% 5%
10V 2 2 10V 2 10V 1/20W
X5R X5R-CERM X5R-CERM MFNOSTUFF
0402 0201 0201
2 201

12
13

21
BYPASS=U5710.12::5MM
LOADISNS
AVDD DVDD
U5710
EADC2_LCDBKLT_ISENSE 22 LTC2309 14 EADC2_AD0
49 CH0 QFN AD0
51 EADC2_P3V3_TPAD_ISENSE 23 CH1 CRITICAL AD1 15
50 EADC2_P3V3_DFR_ISENSE 24 CH2 LOADISNS
52 EADC2_KBBLT_ISENSE 1 CH3 SDA 17 I2C_SENSE_5V_SDA_R2 47

54 EADC2_MESA_ISENSE 2 CH4 SCL 16 I2C_SENSE_5V_SCL_R2 47

54 EADC2_P5V_TPAD_ISENSE 3 CH5
51 EADC2_P3V3_KBD_ISENSE 4 CH6 VREF 7 PP2V5_ADC2_VREF
54 EADC2_P5V_LCD_ISENSE 5 CH7
REFCOMP 8 ADC2_REFCOMP
1 C5710
54 52 51 50 49 GND_EADC2_COM 6 COM 2.2UF
20%
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 THRM
1 C5715 1 C5716 2 6.3V
X5R-CERM
GND PAD 0.1UF 10UF 0201
10% 20% LOADISNS
2 6.3V 2 10V
9
10
11
18
19
20

25
A XW5710
SM
CERM-X5R
0201
X5R-CERM
0402-10 BYPASS=U5710.7::5MM
SYNC_MASTER= SYNC_DATE=
A
2 1 PAGE TITLE

PLACE_NEAR=U5710.6:1MM BYPASS=U5710.10::3MM POWER SENSORS EXTENDED 2

PLACE_NEAR=U5710.25:1MM LOADISNS BYPASS=U5710.10::5MM DRAWING NUMBER SIZE

LOADISNS 051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
57 OF 500
117S0008 3 RES,MTL FLIM,100K,1/16W,0201,SMD,LF R5777,R5788,R5798 LOADRC:NO III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 52 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

Thermal Sensor A:
TBT Die, NAND, WIFI, I/O proximity R5850
PP1V8_S5 1
0 2 PP1V8_S0_THMSNSA_R BYPASS=U5850.1::5MM
I2C Write: 0x90, I2C Read: 0x91 32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42 MIN_LINE_WIDTH=0.2000
5% MIN_NECK_WIDTH=0.1000
1/20W
MF
1 C5850
0.1UF
TBT Die Thermal Diode (TTLD) 0201
PLACE_SIDE=TOP 10%

14
53 25 BI
TBTTHMSNS_D1_P 2 6.3V
CERM-X5R
NO_XNET_CONNECTION=1 0201
PLACE_NEAR=U5850.6:5MM V+
Placement Note:
The P leg connects to THERMDA of TBT die.
C5851 1 NO_XNET_CONNECTION=1 U5850
2200PF PLACE_NEAR=U5850.7:5MM TMP464
The N leg connectd to GND pin close to THERMDA. 10%
10V VQFN
D X7R-CERM 2
0201 XW5851
SM
53 25 TBTTHMSNS_D1_P 6 D1+ SCL
13 I2C_THMSNS_SCL_R1 IN 47 D
PLACE_NEAR=U5850.7:5MM 53 THMSNSA_D2_P 5 D2+ CRITICAL
26 TBTTHMSNS_D1_N 2 1 THMSNSA_DN 53 SDA
12 I2C_THMSNS_SDA_R1 47
BI
53 THMSNSA_D3_P 4 D3+ BI

WIFI Proximity (TW0P) THMSNSA_D2_P 53

53 THMSNSA_D4_P 3 D4+ THERM2* 11
NC
NO_XNET_CONNECTION=1
PLACE_NEAR=U5850.5:5MM THERM* 10
Placement Note: 3 NC
BOTTOM side of WIFI/BT module
C5852 1 NO_XNET_CONNECTION=1
Q5852 1 100PF
BC846BMB
5%
25V 2
PLACE_NEAR=U5850.7:5MM
NC1 2
NC Thermal Sensor: LEFT IO proximity (TI0P)
SOT883
2
CRITICAL C0G
0201 XW5852
SM 53 THMSNSA_DN 7 D-
NC0 1
NC
PLACE_SIDE=BOTTOM PLACE_NEAR=U5850.7:5MM NC3 16 Placement Note:
THMSNSA_D2_N 2 1 THMSNSA_DN 53
15
NC
THMSNSA_ADDR_SEL 9 ADD NC2 NC TOP side, close to TBT die.
NAND Proximity #1 (TH0b) THMSNSA_D3_P 53
1
GND EPAD
NO_XNET_CONNECTION=1 R5851

17
3 PLACE_NEAR=U5850.4:5MM
Placement note: 100K
BOTTOM side between NAND devices
C5853 1 NO_XNET_CONNECTION=1 5%
1/20W
Q5853 1 100PF PLACE_NEAR=U5850.7:5MM MF
5%
BC846BMB 25V 2 2 201
SOT883
2
CRITICAL C0G
0201 XW5853
SM
PLACE_SIDE=BOTTOM PLACE_NEAR=U5850.7:5MM
THMSNSA_D3_N 2 1 THMSNSA_DN 53

NAND Proximity #2 (TH0a) THMSNSA_D4_P 53

NO_XNET_CONNECTION=1
3 PLACE_NEAR=U5850.3:6MM
Placement note:
TOP side between NAND devices
C5854 1 NO_XNET_CONNECTION=1
Q5854 1 100PF PLACE_NEAR=U5850.7:5MM
5%
BC846BMB 25V 2
SOT883
2
CRITICAL C0G
0201 XW5854
SM
PLACE_SIDE=TOP PLACE_NEAR=U5850.7:6MM
THMSNSA_D4_N 2 1 THMSNSA_DN 53

C C

Thermal Sensor B
Fin Stack, CPU Proximity, Memory Proximity, and CPU VR
I2C Write: 0x92, I2C Read: 0x93

R5870
PP1V8_S5 1
0 2 PP1V8_S0_THMSNSB_R
32 18 17 16 15 14 13 12 11 7

Thermal Diode: Ambient (TMLB) 83 74 73 72 70 69 65 53 47 42

5%
1/20W
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 BYPASS=U5870.14::5MM
MF
0201
1 C5870
Placement Note: PLACE_SIDE=TOP 0.1UF 1
R5871

14
10%
Airflow thermal indicator, TOP side. THMSNSB_D1_P 53 2 6.3V
CERM-X5R 100K
B 3
NO_XNET_CONNECTION=1
PLACE_NEAR=U5870.6:5MM
V+ 0201 5%
1/20W B
C5871 1 NO_XNET_CONNECTION=1 U5870 MF
2 201
100PF TMP464
Q5871 1
5% PLACE_NEAR=U5870.7:5MM VQFN
BC846BMB CRITICAL 25V 2 THMSNSB_D1_P 6 D1+ 13 I2C_THMSNS_SCL_R2
SOT883
2
C0G
0201 XW5871
SM
53

53 THMSNSB_D2_P 5 D2+ CRITICAL

SCL 47

12 I2C_THMSNS_SDA_R2
CPU Proximity (TC0P) PLACE_SIDE=TOP THMSNSB_D1_N PLACE_NEAR=U5870.7:5MM
2 1 THMSNSB_DN 53 53 THMSNSB_D3_P 4 D3+ SDA 47

53 THMSNSB_D4_P 3 D4+ THERM2* 11

NC
Placement Note: THMSNSB_D2_P 53
10
NO_XNET_CONNECTION=1 THERM* NC
TOP side of CPU. 3 PLACE_NEAR=U5870.5:5MM
C5872 1 NO_XNET_CONNECTION=1
Q5872 1 100PF PLACE_NEAR=U5870.7:5MM NC1 2
5% NC
BC846BMB CRITICAL 25V 2 NC0 1
SOT883
2
C0G
0201 XW5872
SM
53 THMSNSB_DN 7 D-
NC3 16
NC
NC
Memory Proximity (TM0P) PLACE_SIDE=TOP THMSNSB_D2_N PLACE_NEAR=U5870.7:5MM
2 1 THMSNSB_DN 53 THMSNSB_ADDR_SEL 9 ADD NC2 15
NC
GND EPAD
Placement Note: THMSNSB_D3_P 53

17
NO_XNET_CONNECTION=1
TOP side between main memory devices. 3 PLACE_NEAR=U5870.4:5MM
C5873 1 NO_XNET_CONNECTION=1
Q5873 1 100PF PLACE_NEAR=U5870.7:5MM
5%
BC846BMB CRITICAL 25V 2
SOT883
2
C0G
0201 XW5873
SM
Memory Proximity (TM1P) PLACE_SIDE=TOP
THMSNSB_D3_N PLACE_NEAR=U5870.7:5MM
2 1 THMSNSB_DN 53

Placement Note: THMSNSB_D4_P 53

NO_XNET_CONNECTION=1
BOTTOM side between main memory devices. 3 PLACE_NEAR=U5870.3:5MM
C5874 1 NO_XNET_CONNECTION=1
A Q5874 1 100PF
5% PLACE_NEAR=U5870.7:5MM Thermal Sensor: Fin Stack (Th1H) SYNC_MASTER= SYNC_DATE=
A
BC846BMB CRITICAL 25V 2 PAGE TITLE
SOT883
2
C0G
0201 XW5874
SM Placement Note: THERMAL SENSORS
PLACE_SIDE=BOTTOM PLACE_NEAR=U5870.7:5MM
THMSNSB_D4_N 2 1 THMSNSB_DN 53 TOP side, top right of MLB. DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
58 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 53 OF 98
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 8 7 6 5 4 3 2 1

Trackpad 5V Current Sense (IT5C) Probe Points for Power Validation

Gain: 200x, EDP: 0.0055 A BYPASS=U5940.6::5MM TP5901 TP5939
Rsense: 0.1 (R5940) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS LOADISNS 49 IN
ISNS_HS_CPU_P 1 TP PLACE_SIDE=TOP 76 51 IN
ISNS_LCDPANEL_P TP PLACE_SIDE=TOP
PLACE_NEAR=R5400:5MM PLACE_NEAR=R8520:5MM
Vsense: 0.55 mV, Range: 0.17 A TP-P5 TP-P5
1 C5940 TP5902 TP5940
0.1UF 49 ISNS_HS_CPU_N 1 PLACE_SIDE=TOP 76 51 ISNS_LCDPANEL_N PLACE_SIDE=TOP

6
10% IN TP IN TP
PLACE_NEAR=U5710.3:5MM PLACE_NEAR=R5400:5MM PLACE_NEAR=R8520:5MM
52 51 50 46 29 28 PP5V_G3S V+ 2 6.3V
CERM-X5R
TP-P5 TP-P5
86 83 75 68 55 PLACE_NEAR=U5940.2:5MM 0201 LOADISNS TP5903 TP5941
U5940 R5949 49 IN
ISNS_HS_OTHER5V_P 1 TP PLACE_SIDE=TOP 51 IN
ISNS_TPADP3V3_P TP PLACE_SIDE=TOP
OMIT INA210A 45.3K 2 TP-P5
PLACE_NEAR=R5410:6MM
TP-P5
PLACE_NEAR=R5650:10MM
R5940 1 3 54 ISNS_TPADP5V_P 2 IN+ UQFN
CRITICAL
OUT 10 TPADP5V_IOUT 1 EADC2_P5V_TPAD_ISENSE OUT 52
TP5904 TP5942
0.005 3 IN+ 1% 49 IN
ISNS_HS_OTHER5V_N 1 TP PLACE_SIDE=TOP 51 IN
ISNS_TPADP3V3_N TP PLACE_SIDE=TOP
1% REF 8 1/20W PLACE_NEAR=R5410:6MM PLACE_NEAR=R5650:10MM
1/3W
ISNS_TPADP5V_N
1
R5945 MF 1 C5949 TP-P5 TP-P5
D
D MF
0306-SHORT 2 4
54
4 IN-
LOADISNS
NC 1 NC 5%
20K
201
2.2UF
20% 49 ISNS_HS_OTHER3V3_P
TP5905
1 PLACE_SIDE=TOP 51 ISNS_WLANBTP1V8_P
TP5943
PLACE_SIDE=TOP
5 IN- NC 7 1/20W 2 6.3V IN TP
PLACE_NEAR=R5440:5MM IN TP
PLACE_NEAR=R5680:5MM
87 62 PP5V_G3S_TPAD 200x NC MF X5R-CERM
0201
TP-P5 TP-P5
PLACE_NEAR=U5940.4:5MM GND 2 201
PLACE_NEAR=U5710.3:5MM ISNS_HS_OTHER3V3_N
TP5906 ISNS_WLANBTP1V8_N
TP5944
49 IN 1 PLACE_SIDE=TOP 51 IN PLACE_SIDE=TOP

9
TP TP
PLACE_NEAR=U5940.10:5MM LOADISNS TP-P5
PLACE_NEAR=R5440:5MM
TP-P5
PLACE_NEAR=R5680:5MM
NOSTUFF GND_EADC2_COM 49 50 51 52 54
TP5907 TP5945
49 IN
ISNS_HS_3V3RTC_P 1 TP PLACE_SIDE=TOP 52 IN
ISNS_CALPE_P 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5420:5MM PLACE_NEAR=R5780:5MM
TP-P5 TP-P5
LCD Panel 5V Current Sense (IL5C) 49 IN
ISNS_HS_3V3RTC_N
TP5908
1 TP PLACE_SIDE=TOP 52 IN
ISNS_CALPE_N
TP5946
1 TP PLACE_SIDE=TOP
Gain: 200x, EDP: 0.1 A BYPASS=U5960.6::5MM
TP-P5
PLACE_NEAR=R5420:5MM
TP-P5
PLACE_NEAR=R5780:5MM
Rsense: 0.1 (R8521) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS LOADISNS TP5909 TP5947
Vsense: 10 mV, Range: 0.17 A 49 ISNS_SSDNAND_P PLACE_SIDE=TOP 52 ISNS_KBBLT_P 1 PLACE_SIDE=TOP
1 C5960 IN TP
TP-P5
PLACE_NEAR=R5460:5MM IN TP
TP-P5
PLACE_NEAR=R5730:5MM
0.1UF
TP5910 TP5948

6
10%
V+ 2 6.3V PLACE_NEAR=U5710.5:5MM 49 ISNS_SSDNAND_N PLACE_SIDE=TOP 52 ISNS_KBBLT_N 1 PLACE_SIDE=TOP
CERM-X5R LOADISNS IN TP
PLACE_NEAR=R5460:5MM IN TP
PLACE_NEAR=R5730:5MM
0201 TP-P5 TP-P5
PLACE_NEAR=R8521.3:5MM U5960 R5969 TP5911 TP5949
INA210A 45.3K 2 75 49 ISNS_LCDBKLT_P PLACE_SIDE=TOP 66 CPUSA_ISNS_R_P PLACE_SIDE=TOP
76 54 IN
ISNS_PP5V_LCD_P 2 IN+ UQFN
OUT 10 LCDP5V_IOUT 1 EADC2_P5V_LCD_ISENSE OUT 52
IN TP
PLACE_NEAR=R8400:30MM IN TP
PLACE_NEAR=R7274:5MM
3 IN+
CRITICAL 1%
TP-P5 TP-P5
REF 8 1 1/20W 1 C5969 ISNS_LCDBKLT_N
TP5912 CPUSA_ISNS_R_N
TP5950
LOADISNS R5965 MF
201 2.2UF 75 49 IN TP PLACE_SIDE=TOP
PLACE_NEAR=R8400:30MM
66 IN TP PLACE_SIDE=TOP
PLACE_NEAR=R7272:5MM
76 54 ISNS_PP5V_LCD_N 4 IN- NC 1 20K 20% TP-P5 TP-P5
IN NC 5% 2 6.3V
X5R-CERM TP5913 TP5951
5 IN- NC 7 1/20W
PLACE_NEAR=R8521.4:5MM
200x NC MF 0201 49 IN
ISNS_SPKRAMP_LEFT_P TP PLACE_SIDE=TOP
PLACE_NEAR=R54A0:5MM
69 52 IN
ISNS_CPUEDRAM_P TP
PLACE_NEAR=R7702:5MM
GND 2 201 PLACE_NEAR=U5710.5:5MM TP-P5 TP-P5
LOADISNS TP5914 TP5952
9
PLACE_NEAR=U5960.10:5MM 49 ISNS_SPKRAMP_LEFT_N PLACE_SIDE=TOP 69 52 ISNS_CPUEDRAM_N
GND_EADC2_COM 49 50 51 52 54
IN TP
PLACE_NEAR=R54A0:5MM IN TP
PLACE_NEAR=R7702:5MM
NOSTUFF TP-P5 TP-P5

ISNS_SPKRAMP_RIGHT_P
TP5915 ISNS_TPADP5V_P
TP5953
PLACE_SIDE=TOP PLACE_SIDE=TOP
C Ocarina Current Sense (IHCC)
49 IN TP
TP-P5
PLACE_NEAR=R54B0:5MM
54 TP
TP-P5
PLACE_NEAR=R5940:10MM C
Gain: 100x, EDP: 2.139 A ISNS_SPKRAMP_RIGHT_N
TP5916 ISNS_TPADP5V_N
TP5954
BYPASS=U5920.6::5MM 49 PLACE_SIDE=TOP 54 PLACE_SIDE=TOP
Rsense: 0.01 (R5920) [Production] 74 54 52 51 50 49 PP3V3_S4SW_SNS IN TP
PLACE_NEAR=R54B0:5MM TP
PLACE_NEAR=R5940:10MM
LOADISNS TP-P5 TP-P5
Vsense: 21.4 mV, Range: 3.0 A 1 C5920 CHGR_CSI_R_P
TP5917 ISNS_PP5V_LCD_P
TP5955
MUX: A5 0.1UF 64 IN TP PLACE_SIDE=TOP 76 54 TP PLACE_SIDE=TOP
PLACE_NEAR=R7020:5MM PLACE_NEAR=R8521:5MM
6

83 74 68 63 52 PP3V3_G3H 10%
PLACE_NEAR=U7800.C14:7.5MM TP-P5 TP-P5
86 V+ 2 6.3V
CERM-X5R TP5918 TP5956
0201 LOADISNS CHGR_CSI_R_N ISNS_PP5V_LCD_N
PLACE_NEAR=U5920.2:5MM U5920 R5929
64 IN TP
TP-P5
PLACE_SIDE=TOP
PLACE_NEAR=R7020:5MM
76 54 TP
TP-P5
PLACE_SIDE=TOP
PLACE_NEAR=R8521:5MM
INA214A 9.09K 2
0306-SHORT 2 4 54 ISNS_OCARINA_P 2 IN+ UQFN
OUT 10 ISNS_OCARINA_IOUT 1 PMU_OCARINA_ISENSE OUT 72
CHGR_AMON
TP5919 ISNS_OCARINA_P
TP5957
MF 3 IN+
CRITICAL 1%
64 49 IN TP PLACE_SIDE=TOP 54 TP PLACE_SIDE=TOP
1/3W PLACE_NEAR=R5920:5MM
1% REF 8 1/20W TP-P5 TP-P5
0.005 54 ISNS_OCARINA_N LOADISNS
MF
201 R59281 1 C5929 TP5981 TP5958
R5920 1 4 IN- NC 1 9.09K 2.2UF PLACE_SIDE=TOP 54 ISNS_OCARINA_N PLACE_SIDE=TOP
3 NC 1% 20% TP
PLACE_NEAR=TP5919:5MM TP
PLACE_NEAR=R5920:5MM
OMIT 5 IN- NC 7 1/20W 2 6.3V TP-P5 TP-P5
81 PP3V3_G3H_SSD0 100x NC MF
201 2
X5R-CERM
0201 TP5920 TP5959
PLACE_NEAR=U5920.4:5MM GND
PLACE_NEAR=U7800.C14:7.5MM 64 IN
CHGR_CSO_R_P TP PLACE_SIDE=TOP 54 ISNS_MESA_P TP PLACE_SIDE=TOP
PLACE_NEAR=U7800.C14:7.5MM PLACE_NEAR=R7060:30MM PLACE_NEAR=R5930:5MM
9

Stuff 0.005 for PVT per <rdar://49214265> LOADISNS TP-P5 TP-P5

LOADRC:YES CHGR_CSO_R_N
TP5921 ISNS_MESA_N
TP5960
64 IN TP PLACE_SIDE=TOP 54 TP PLACE_SIDE=TOP
PLACE_NEAR=R7060:30MM PLACE_NEAR=R5930:5MM
TP-P5 TP-P5
TP5922 TP5961
MESA Current Sense (IIDC) 64 49 IN
CHGR_BMON TP
TP-P5
PLACE_SIDE=TOP 86 83 70 11 7 IN
PPVPCORE_S5 TP
TP-P5
PLACE_SIDE=TOP
PLACE_NEAR=L7820:5MM
Gain: 200x, EDP: 0.176 A BYPASS=U5930.6::5MM
Rsense: 0.050 (R5530) or SHORT 74 54 52 51 50 49 PP3V3_S4SW_SNS LOADISNS TP5982 PVCC_FB_P
TP5962
TP PLACE_SIDE=TOP 7 IN TP PLACE_SIDE=TOP
Vsense: 8.8 mV, Range: 0.33 A PLACE_NEAR=TP5922:5MM PLACE_NEAR=R0850:10MM
1 C5930 TP-P5 TP-P5
0.1UF TP5923 TP5963
6

10% PLACE_NEAR=U5710.2:5MM 73 PVCCIOS0_CS_P PLACE_SIDE=TOP 86 83 73 70 16 11 7 PP1V_PRIM PLACE_SIDE=TOP

89 86 83 76
57 50 29 28 27 PP3V3_G3H_RTC V+ 2 6.3V
CERM-X5R
IN TP
PLACE_NEAR=R8102:5MM
IN TP
PLACE_NEAR=L7821:5MM
74 72 71 63 61 NO_XNET_CONNECTION=1 PLACE_NEAR=U5930.2:5MM 0201 LOADISNS TP-P5 TP-P5
B OMIT
U5930
INA210A R5939 73 PVCCIOS0_CS_N
TP5924
PLACE_SIDE=TOP 7 P1VPRIM_FB_R
TP5964
PLACE_SIDE=TOP
B
IN IN
45.3K 2 TP
PLACE_NEAR=R8102:5MM TP
PLACE_NEAR=R0853:10MM
R5930 1 3 54 ISNS_MESA_P 2 IN+ UQFN
CRITICAL
OUT 10 ISNS_MESA_IOUT 1 EADC2_MESA_ISENSE OUT 52 TP-P5 TP-P5
0.005 3 IN+ 1%
ISNS_CPUDDR_P
TP5925 ISNS_KBDP3V3_P
TP5965
1% REF 8 1/20W 73 50 PLACE_SIDE=TOP 51 1 PLACE_SIDE=TOP
1/3W
MF 54 ISNS_MESA_N LOADISNS
1
R5935 MF
201
1 C5939 IN TP
TP-P5
PLACE_NEAR=R8118:5MM
IN TP
TP-P5
PLACE_NEAR=R5690:5MM
0306-SHORT 2 4 4 IN- NC 1 51K 2.2UF
NC 5% 20%
ISNS_CPUDDR_N
TP5926 ISNS_KBDP3V3_N
TP5966
5 IN- NC 7 1/20W 2 6.3V PLACE_SIDE=TOP 1 PLACE_SIDE=TOP
44 PP3V3_G3H_RTC_MESA
PLACE_NEAR=U5930.4:5MM
200x NC MF X5R-CERM
0201
73 50 IN TP
TP-P5
PLACE_NEAR=R8118:5MM
51 IN TP
TP-P5
PLACE_NEAR=R5690:5MM
GND 2 201
PLACE_NEAR=U5710.2:5MM
ISNS_CPUVDDQ_P
TP5927 ISNS_P5VCPUREGMISC_P
TP5967
9

PLACE_NEAR=U5930.10:5MM LOADISNS 50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP

PLACE_NEAR=R5510:5MM PLACE_NEAR=R5660:5MM
NOSTUFF GND_EADC2_COM 49 50 51 52 54 TP-P5 TP-P5

ISNS_CPUVDDQ_N
TP5928 ISNS_P5VCPUREGMISC_N
TP5968
50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5510:5MM PLACE_NEAR=R5660:5MM
TP-P5 TP-P5

ISNS_DFR3V3_P
TP5929 ISNS_P1V8LPDDR_P
TP5969
50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5520:5MM PLACE_NEAR=R5630:5MM
TP-P5 TP-P5

ISNS_DFR3V3_N
TP5930 ISNS_P1V8LPDDR_N
TP5970
50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5520:5MM PLACE_NEAR=R5630:5MM
TP-P5 TP-P5

ISNS_WLANBTP3V3_P
TP5931 ISNS_P1V8G3S_P
TP5971
50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5530:5MM PLACE_NEAR=R56B0:5MM
TP-P5 TP-P5

ISNS_WLANBTP3V3_N
TP5932 ISNS_P1V8G3S_N
TP5972
50 IN TP PLACE_SIDE=TOP 51 IN 1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5530:5MM PLACE_NEAR=R56B0:5MM
TP-P5 TP-P5
TP5983 ISNS_CPUVR_P
TP5933
TP PLACE_SIDE=TOP 50 IN TP PLACE_SIDE=TOP
PLACE_NEAR=R5542:30MM
TP-P5 TP-P5

TP5984 TP5934
A TP PLACE_SIDE=TOP
50 IN
ISNS_CPUVR_N TP
TP-P5
PLACE_SIDE=TOP
PLACE_NEAR=R5543:30MM SYNC_MASTER= SYNC_DATE=
A
TP-P5 PAGE TITLE
TP5935
TP5985 50 IN
ISNS_CPUGT_P TP PLACE_SIDE=TOP
PLACE_NEAR=R5582:10MM
POWER SENSORS EXTENDED 3
1 PLACE_SIDE=TOP TP-P5 DRAWING NUMBER SIZE
TP
TP-P5
ISNS_CPUGT_N
TP5936 051-05309 D
TP5986
50 IN TP PLACE_SIDE=TOP
PLACE_NEAR=R5583:10MM Apple Inc. REVISION
TP-P5
1 TP PLACE_SIDE=TOP TP5937 5.1.0
TP-P5 51 IN
ISNS_TBTX_P TP PLACE_SIDE=TOP NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACE_NEAR=R5640:5MM
TP-P5 THE INFORMATION CONTAINED HEREIN IS THE

ISNS_TBTX_N
TP5938 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 51 PLACE_SIDE=TOP
IN TP
TP-P5
PLACE_NEAR=R5640:5MM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
59 OF 500
117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF R5928 LOADRC:NO III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

BOM_COST_GROUP=SENSORS IV ALL RIGHTS RESERVED 54 OF 98

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 8 7 6 5 4 3 2 1

FAN CONTROL
PP1V8_G3S 18 43 44 45 47 48 51 57 58 59

D
60 61 62 68 74 76 83
D

1
R6000
47K
5%
1/20W
MF
R6005 201 2

SMC_FAN_0_TACH 1
47K 2
60 35 OUT
5%
1/20W
MF
201
FAN_RT_TACH 55 83

NOSTUFF
R6001 1
100K Q6000
5%
G 1

1/20W
MF
DMN32D2LFB4
DFN1006H4-3
201 2 SYM_VER_3

C C
2 S

FAN_RT_PWM 55 83
3

35 IN
SMC_FAN_0_PWM
R6002 1
100K
5%
1/20W
MF
201 2

518S0818 DBG_FAN
B J6001 J6000 B
FF14A-6C-R11DL-B-3H FF14A-5C-R11DL-B-3H
F-RT-SM F-RT-SM
7 6
XW6098
SM
NC

75 68 55 54 52 51 50 46 29 28
86 83
PP5V_G3S 1 2 83 PP5V_G3S_FAN 1 75 68 55 54 52 51 50 46 29 28
86 83
PP5V_G3S 1

83 55 FAN_RT_PWM 2
NC
2
3 3

83 55 FAN_RT_TACH 4
NC
4
TP_FAN_RT_OTP1 5
NC
5
TP_FAN_RT_OTP2 6
7
NC
8

XW6099
SM
518S0769
1 2 83 GND_FAN

A SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

Fans/SMC/AMUX Support
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
60 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=FAN IV ALL RIGHTS RESERVED 55 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
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 8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER= SYNC_DATE= A
PAGE TITLE

AUDIO PLACEHOLDER
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
62 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO IV ALL RIGHTS RESERVED 56 OF 98
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 8 7 6 5 4 3 2 1

AUDIO JACK CODEC I2C ADDRESS

AD1 AD0 ADDRESS
GND GND 0x48 <--
GND 1.8V 0x49
1.8V GND 0x4A
1.8V 1.8V 0x4B

D 58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S D

L6300 XW6300
FERR-22-OHM-1A-0.055OHM SHORT-8L-0.25MM-SM
1 2 GND_AUDIO_CODEC 57
1 2 PP1V8_CODEC_VCP
MIN_LINE_WIDTH=0.2000 0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
VOLTAGE=1.89

BYPASS=U6300.B1:C2:4MM
1 C6301
2.2UF
20%
10V
2 X5R-CERM
402
57
GND_AUDIO_CODEC

L6301
FERR-22-OHM-1A-0.055OHM
1 2 PP1V8_CODEC_VL
MIN_LINE_WIDTH=0.2000 0201 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
BYPASS=U6300.A3:B3:5MM C6303 1
CRITICAL
0.1UF
10%
16V
BYPASS=U6300.D6:F6:4MM C6302 XW6301
X7R-CERM 2 2.2UF SM
0402 1 2 L83_VCP_FILT_GND 1 2
TP6307
1 PP3V3_G3S MIN_LINE_WIDTH=0.5000
A 45 50 51 62 74 75 76 83
20% MIN_NECK_WIDTH=0.1130
TP-P5
PLACE_NEAR=L6302.1:20MM 10V
L6302 X5R-CERM
402
C TP6308
1 PP1V8_G3S
FERR-22-OHM-1A-0.055OHM NO_XNET_CONNECTION=1 C
A 18 43 44 45 47 48 51 55 57
TP-P5
58 59 60 61 62 68 74 76 83 74 72 71 63 61 54 50 29 28 27 PP3V3_G3H_RTC 1 2 PP3V3_CODEC_VP
89 86 83 76
0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 CRITICAL
TP6309 BYPASS=U6300.D7:C7:5MM 1 C6304 BYPASS=U6300.E6:F6:4MM C6305
A
1 CODEC_RESET_L 35 57
10UF 4.7UF
TP-P5
PLACE_NEAR=U6300.C5:20MM 20% L83_VCP_FILTP 1 2
PP1V8_G3S 18 43 44 45 47 48 51 55 57 58
59 60 61 62 68 74 76 83
10V
2 X5R-CERM MIN_LINE_WIDTH=0.5000
0402-7 MIN_NECK_WIDTH=0.2000 20%
10V
X5R-CERM
60 OUT
AUD_HP_PORT_L 0402 PP1V8_G3S 18 43 44 45 47 48 51 55 57 58
NO_XNET_CONNECTION=1 59 60 61 62 68 74 76 83

1 CRITICAL 1 1
R6300 BYPASS=U6300.G6:F6:4MM C6306 R6302 R6303
1K 4.7UF 47K 47K
5% 5% 5%

NC
1/20W L83_VCP_FILTN 1 2 1/20W 1/20W
MF MIN_LINE_WIDTH=0.5000 MF MF

D6
MIN_NECK_WIDTH=0.2000

D7

A3

A7

B1
2 201 20% 2 201 2 201
10V
57 GND_AUDIO_CODEC VP VL VD_FILT VA VCP
X5R-CERM
0402 CODEC_INT_L 34
+VCP_FILT E6 NO_XNET_CONNECTION=1
OUT

1 CRITICAL G6 CODEC_WAKE_L
R6301 -VCP_FILT OUT 35

1K 60 IN
AUD_HP_SENSE_L D5 HPSENSA U6300 F6 CODEC_RESET_L
5% E5 GNDCP IN 35 57
1/20W HPOUTA CS42L83A
MF WLCSP-SKT C4
2 201 VL_SEL
60 IN
AUD_HP_SENSE_R F5 HPSENSB 1
60 OUT
AUD_HP_PORT_R G5 HPOUTB DIGLDO_PDN* D4 R6304 1 C6320
47K 1000PF
B7 5% 10%
INT* 1/20W
60 BI
AUD_HP_PORT_CH_GND F1 HS4 MF 2 25V
X7R
E2 HS_CLAMP2 WAKE* C6 2 201 0201

60 IN
AUD_HS_MIC_P E1 HSIN+ C5
RESET*
60 BI
AUD_HP_PORT_US_GND G2 HS3
B F2 HS_CLAMP1
SPDIF_TX A6
B
60
AUD_HS_MIC_N D1 HSIN- NC
IN
PLACE_NEAR=FL6609.1:5MM SWIRE_SEL D3
XW6302 I2S_CODEC_LRCLK_R 43 57
AUD_HS4_REF F4 HS4_REF
IN
SHORT-8L-0.25MM-SM B5
ASP_LRCK/FSYNC
1 2 AUD_HS3_REF G4 HS3_REF I2S_CODEC_R2D 43 57
G3 A5 IN
XW6303 PLACE_NEAR=FL6610.1:5MM RING_SENSE SWIRE_SD/ASP_SDIN
PLACE_NEAR=U6300.A4:5mm R6307
SHORT-8L-0.25MM-SM E4 A4 L83_SDOUT 1
33 2 I2S_CODEC_D2R
1 2 TIP_SENSE ASP_SDOUT OUT 36 57

5% 1/20W MF 201
SWIRE_CLK/ASP_SCLK B4
L83_HSBIAS_FILT F3 HSBIAS_FILT I2S_CODEC_BCLK IN 43 57
MIN_LINE_WIDTH=0.2000 E3
MIN_NECK_WIDTH=0.1000 HSBIAS_FILT_REF C3
AD0
AD1 B2
1 C6309 CRITICAL
4.7UF BYPASS=U6300.F3:E3:4MM SDA A1 I2C_CODEC_SDA 36 48 57
60 IN
AUD_RING_SENSE 20%
10V A2 I2C_CODEC_SCL
BI
2 X5R-CERM SCL IN 36 48 57
0402 FLYP E7 L83_FLYP
L83_HSBIAS_FILT_REF F7 MIN_LINE_WIDTH=0.2000
60 IN AUD_TIP_SENSE FLYC L83_FLYC MIN_NECK_WIDTH=0.1000
TP6300 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 G7 L83_FLYN CRITICAL
FLYN
A
1 I2S_CODEC_LRCLK_R
PLACE_NEAR=U6300.B5:30MM BYPASS=U6300.E7:F7:4MM
C6307 1
TP-P5 FILT_P C1 L83_FILT 2.2UF
20%
TP6301
1 I2S_CODEC_R2D
GNDL GNDD GNDHS GNDA MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 10V
X5R-CERM 2
A 43 57 MIN_LINE_WIDTH=0.2000 402
B3

B6
C7

G1

C2
D2
TP-P5
PLACE_NEAR=U6300.A5:30MM MIN_NECK_WIDTH=0.1000
TP6302 CRITICAL
A
1 I2S_CODEC_D2R
PLACE_NEAR=U3900.Y33:30MM
36 57
BYPASS=U6300.G7:F7:4MM
C6308 1
TP-P5 BYPASS=U6300.C1:C2:3 MM 2.2UF
20%
TP6303
1 I2S_CODEC_BCLK CRITICAL 10V
X5R-CERM 2
MIN_LINE_WIDTH=0.2000
A PLACE_NEAR=U6300.B4:30MM C6310 1 MIN_NECK_WIDTH=0.1000 402
A TP-P5
TP6304 10UF
20% SYNC_MASTER= SYNC_DATE= A
A
1 I2C_CODEC_SDA 36 48 57
10V
X5R 2
PAGE TITLE
PLACE_NEAR=U6300.A1:30MM
TP-P5 0603 AUDIO JACK CODEC
TP6305
1 I2C_CODEC_SCL GND_AUDIO_CODEC DRAWING NUMBER SIZE
36 48 57 57
A PLACE_NEAR=U6300.A2:30MM 051-05309 D
TP-P5
TP6306 Apple Inc. REVISION

A
1
PLACE_NEAR=TP6303.1:20MM
5.1.0
TP-P5 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
63 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO IV ALL RIGHTS RESERVED 57 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

2X MONO SPEAKER LEFT AMPLIFIERS

APN: 353S01252
GAIN: 0DBFS = xxVRMS
PLACE_NEAR=U6400.C1:5 MM
PLACE_NEAR=U6400.C1:3 MM PLACE_NEAR=U6400.C4:10 MM
PLACE_NEAR=U6400.D2:5 MM PLACE_NEAR=U6400.C4:10 MM
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S PLACE_NEAR=U6400.D2:3 MM PLACE_NEAR=U6400.C4:3 MM PPBUS_G3H_SPKRAMP_LEFT 49 58
83 76 74 68 62 61 60 59

1 C6404 1 C6405 1 C6406

0.1UF 10UF 10UF
1 C6400 1 C6401 1 C6402 1 C6403 10% 20% 20%
D
D 20%
1UF
10%
0.1UF 1UF
20%
0.1UF
10% 2 25V
X5R
25V
2 X5R-CERM
0603
25V
2 X5R-CERM
0603
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
0201
0201 0201 0201 0201

C6411 BYPASS=U6400.B2:B3:5 MM

C1

D2

C4
C5
NO_XNET_CONNECTION=1
59 58 34 IN
SPKRAMP_RESET_L 0.1UF
AVDD IOVDD VBAT 1 2
1 NOSTUFF
R6402 1 U6400 10%
47K R6400 25V
5%
47K PTAS5770LB2 X5R
1/20W CSP 0201 MIN_LINE_WIDTH=0.4000
MF 5% C3 SDZ* B2 MIN_NECK_WIDTH=0.1500
2 201 1/20W BST_P SPKRAMP_RL_BSTP DIDT=TRUE 83 SPKRCONN_RL_OUTP
MF A3
2 201 I2C_SPKRAMP_L_SDA F3 SDA CRITICAL OUT_P 1 2
58 48 36 BI B3 DIDT=TRUE
I2C_SPKRAMP_L_SCL F4 SCL OMIT_TABLE OUT_P DIDT=TRUE SHORT-8L-0.25MM-SM
58 48 36 IN
VSNS_P A1 SPKRAMP_RL_SNSP XW6400
PLACE_NEAR=J6410.13:5 MM
59 58 34 SPKRAMP_INT_L D4 IRQZ
A2
OUT
BST_N SPKRAMP_RL_BSTN C6412 BYPASS=U6400.A2:A5:5 MM
NO_XNET_CONNECTION=1
58 SPKRAMP_RL_MODE D3 MODE OUT_N A5 DIDT=TRUE 0.1UF
OUT_N B5 1 2
58 43 I2S_SPKRAMP_L_R2D F2 SDIN
IN B1 SPKRAMP_RL_SNSN
R6401 E1 SDOUT VSNS_N
DIDT=TRUE 10%
25V
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
I2S_SPKRAMP_L_D2R 33 I2S_SPKRAMP_L_D2R_R1
59 58 36 OUT
1 2
E2 FSYNC AREG D5 X5R
0201 83 SPKRCONN_RL_OUTN
5% 1/20W MF 201 DIDT=TRUE
F1 SBCLK DREG D1
58 43 IN
I2S_SPKRAMP_L_LRCLK_R 1 2 APN:518S00019
SHORT-8L-0.25MM-SM NOSTUFF NOSTUFF
CRITICAL
I2S_SPKRAMP_L_BCLK
E4 PDMD0
SPKRAMP_RL_AREG XW6401
PLACE_NEAR=J6410.10:5 MM
C6413 1 1 C6414 J6410
58 43 IN E3 PDMCK0 220PF 220PF
10% 10% FF14A-14C-R11DL-B-3H
E5 PDMD1
SPKRAMP_RL_DREG 25V
X7R-CERM 2 2 25V
X7R-CERM F-RT-SM1
201 201 16
F5 PDMCK1 PLACE_NEAR=U6400.D1:5 MM PLACE_NEAR=U6400.D5:5 MM
PGND PLACE_NEAR=U6400.D1:3 MM PLACE_NEAR=U6400.D5:3 MM

C GND 1 C6407
0.1UF
1 C6408
1UF
1 C6409
0.1UF
1 C6410
1UF
14 C
13

C2

A4
B4
10% 20% 10% 20% 58 57 55 51 48 47 45 44 43 18 PP1V8_G3S
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
83 76 74 68 62 61 60 59 12
0201 0201 0201 0201 NOSTUFF 11
R64901 10
47K 9
5%
1/20W 8
MF
201 2 7
PLACE_NEAR=U6450.C1:5 MM
PLACE_NEAR=U6450.C1:3 MM PLACE_NEAR=U6450.C4:10 MM 6
PLACE_NEAR=U6450.D2:5 MM PLACE_NEAR=U6450.C4:10 MM
PP1V8_G3S PLACE_NEAR=U6450.D2:3 MM PLACE_NEAR=U6450.C4:3 MM PPBUS_G3H_SPKRAMP_LEFT 5
58 57 55 51 48 47 45 44 43 18 49 58
83 76 74 68 62 61 60 59 4
1 C6454 1 C6455 1 C6456 3
0.1UF 10UF 10UF 2
1 C6450 1 C6451 1 C6452 1 C6453 10% 20%
25V
20%
25V SPKR_ID0 1
1UF 0.1UF 1UF 0.1UF 2 25V
X5R 2 X5R-CERM 2 X5R-CERM
83 36 OUT
20% 10% 20% 10% 0603 0603
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
0201
0201 0201 0201 0201 15

C1 C6461 BYPASS=U6450.B2:B3:5 MM

D2

C4
C5
NO_XNET_CONNECTION=1
0.1UF
AVDD IOVDD VBAT 1 2

U6450 10%
25V
PTAS5770LB2 X5R
CSP 0201 MIN_LINE_WIDTH=0.4000
SPKRAMP_RESET_L C3 SDZ* B2 MIN_NECK_WIDTH=0.1500
59 58 34 BST_P SPKRAMP_FL_BSTP DIDT=TRUE 83 SPKRCONN_FL_OUTP
CRITICAL A3 1 2
58 48 36
I2C_SPKRAMP_L_SDA F3 SDA OUT_P
DIDT=TRUE
OMIT_TABLE OUT_P B3 DIDT=TRUE SHORT-8L-0.25MM-SM
I2C_SPKRAMP_L_SCL F4 SCL
58 48 36
VSNS_P A1 SPKRAMP_FL_SNSP XW6450
SPKRAMP_INT_L D4 IRQZ PLACE_NEAR=J6410.7:5 MM
B 59 58 34
BST_N A2 SPKRAMP_FL_BSTN C6462 BYPASS=U6450.A2:A5:5 MM
NO_XNET_CONNECTION=1
B
58 SPKRAMP_FL_MODE D3 MODE OUT_N A5 DIDT=TRUE 0.1UF
OUT_N B5 1 2
58 43 I2S_SPKRAMP_L_R2D F2 SDIN
B1
IN
R6451 E1 SDOUT VSNS_N SPKRAMP_FL_SNSN 10%
DIDT=TRUE 25V MIN_LINE_WIDTH=0.4000
I2S_SPKRAMP_L_D2R 33 I2S_SPKRAMP_L_D2R_R2 MIN_NECK_WIDTH=0.1500
59 58 36 OUT
1 2
E2 FSYNC AREG D5 X5R
0201 83 SPKRCONN_FL_OUTN
5% 1/20W MF 201 DIDT=TRUE
I2S_SPKRAMP_L_LRCLK_R F1 SBCLK DREG D1 1 2
58 43 IN
SHORT-8L-0.25MM-SM NOSTUFF NOSTUFF
I2S_SPKRAMP_L_BCLK
E4 PDMD0
SPKRAMP_FL_AREG XW6451
PLACE_NEAR=J6410.4:5 MM
C6463 1 1 C6464
58 43 IN E3 PDMCK0 220PF 220PF
10% 10%
E5 PDMD1
SPKRAMP_FL_DREG 25V
X7R-CERM 2 2 25V
X7R-CERM
201 201
F5 PDMCK1 PLACE_NEAR=U6450.D1:5 MM PLACE_NEAR=U6450.D5:5 MM
PGND PLACE_NEAR=U6450.D1:3 MM PLACE_NEAR=U6450.D5:3 MM
GND 1 C6457 1 C6458 1 C6459 1 C6460
0.1UF 1UF 0.1UF 1UF PP6407
C2

A4
B4

10% 20% 10% 20% P5MM-SP

2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
TP6400
1 I2S_SPKRAMP_L_LRCLK_R 1
SM-SP
PPBUS_G3H_SPKRAMP_LEFT
0201 0201 0201 0201 A 43 58 PP 49 58
TP-P5
PLACE_NEAR=U6400.E2:30MM PLACE_NEAR=U6400.C4:20MM
PP6401
P5MM-SP SM-SP TP6408
PP
1 I2S_SPKRAMP_L_R2D 43 58 A
1 PP1V8_G3S 18 43 44 45 47 48 51 55 57 58
PLACE_NEAR=U6400.F2:30MM TP-P5
PLACE_NEAR=U6400.C1:20MM 59 60 61 62 68 74 76 83

PP6402
P5MM-SP SM-SP TP6409
PP
1 I2S_SPKRAMP_L_D2R 36 58 A
1 SPKRAMP_RESET_L 34 58 59
PLACE_NEAR=U3900.Y28:30MM 59
TP-P5
PLACE_NEAR=U6400.C3:20MM
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S PP6403
P5MM-SP SM-SP
1 NOSTUFF 1 NOSTUFF PP
1 I2S_SPKRAMP_L_BCLK 43 58
R6480 R6482 PLACE_NEAR=U6400.F1:30MM
10K 2.2K TP6404
5% 5%
A LEFT BULK CAPACITANCE
1/20W
MF
1/20W
MF
MODE PIN I2C ADDR CHANNEL A
1
TP-P5
I2C_SPKRAMP_L_SDA
PLACE_NEAR=U6400.F3:30MM
58
36
48 SYNC_MASTER= SYNC_DATE= A
2 201 2 201 GND 0x31 REAR LEFT PAGE TITLE
PPBUS_G3H_SPKRAMP_LEFT SPKRAMP_RL_MODE 470 to GND 0x32 FRONT LEFT TP6405
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
49 58 58

58 SPKRAMP_FL_MODE 470 to IOVDD 0x33 REAR RIGHT A

1 I2C_SPKRAMP_L_SCL
PLACE_NEAR=U6400.F4:30MM
58
36
48
AUDIO LEFT AMPLIFIERS
TP-P5 DRAWING NUMBER SIZE
1 1 1 1 1 1
C6483 C6484 C6485 C6486 C6487 C6488 1
R6481 1
R6483
2k2 to GND 0x34 FRONT RIGHT TP6406 051-05309 D
33UF 33UF 33UF 33UF 33UF 33UF 2k2 to IOVDD 0x35 A
1
Apple Inc.
20% 20% 20% 20% 20% 20% 0 470 TP-P5
PLACE_NEAR=PP6403.1:20MM REVISION
2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 5% 5% 10k to GND 0x36
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
1/20W
MF
1/20W
MF 10k to IOVDD 0x37
5.1.0
2 0201 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
47k to IOVDD 0x38
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
64 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO IV ALL RIGHTS RESERVED 58 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

2X MONO SPEAKER RIGHT AMPLIFIERS

APN: 353S01252
GAIN: 0DBFS = xxVRMS
PLACE_NEAR=U6500.C1:5 MM
PLACE_NEAR=U6500.C1:3 MM PLACE_NEAR=U6500.C4:10 MM
PLACE_NEAR=U6500.D2:5 MM PLACE_NEAR=U6500.C4:10 MM
PP1V8_G3S PLACE_NEAR=U6500.D2:3 MM PLACE_NEAR=U6500.C4:3 MM PPBUS_G3H_SPKRAMP_RIGHT
58 57 55 51 48 47 45 44 43 18 49 59
83 76 74 68 62 61 60 59

1 C6504 1 C6505 1 C6506

0.1UF 10UF 10UF
1 C6500 1 C6501 1 C6502 1 C6503 10% 20% 20%
D
D 1UF
20% 10%
0.1UF 1UF
20% 10%
0.1UF 2 25V
X5R
25V
2 X5R-CERM
0603
25V
2 X5R-CERM
0603
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
0201
0201 0201 0201 0201

C6511 BYPASS=U6500.B2:B3:5 MM

C1

D2

C4
C5
NO_XNET_CONNECTION=1
0.1UF
AVDD IOVDD VBAT 1 2

U6500 10%
25V
PTAS5770LB2 X5R
CSP 0201 MIN_LINE_WIDTH=0.4000
C3 SDZ* B2 MIN_NECK_WIDTH=0.1500
59 58 34 IN
SPKRAMP_RESET_L BST_P SPKRAMP_RR_BSTP DIDT=TRUE 83 SPKRCONN_RR_OUTP
CRITICAL OUT_P A3
I2C_SPKRAMP_R_SDA F3 SDA 1 2
59 48 36 BI B3 DIDT=TRUE
I2C_SPKRAMP_R_SCL F4 SCL OMIT_TABLE OUT_P DIDT=TRUE SHORT-8L-0.25MM-SM
59 48 36 IN
VSNS_P A1 SPKRAMP_RR_SNSP XW6500
PLACE_NEAR=J6510.13:5 MM
59 58 34 SPKRAMP_INT_L D4 IRQZ
A2
OUT
BST_N SPKRAMP_RR_BSTN C6512 BYPASS=U6500.A2:A5:5 MM
NO_XNET_CONNECTION=1
59 SPKRAMP_RR_MODE D3 MODE OUT_N A5 DIDT=TRUE 0.1UF
OUT_N B5 1 2
59 43 I2S_SPKRAMP_R_R2D F2 SDIN
IN B1 SPKRAMP_RR_SNSN
R6501 E1 SDOUT VSNS_N
DIDT=TRUE 10%
25V
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
I2S_SPKRAMP_L_D2R 33 I2S_SPKRAMP_R_D2R_R1
59 58 36 OUT
1 2
E2 FSYNC AREG D5 X5R
0201 83 SPKRCONN_RR_OUTN
5% 1/20W MF 201 DIDT=TRUE
I2S_SPKRAMP_R_LRCLK_R F1 SBCLK DREG D1
59 43 IN 1 2 APN:518S00019
SHORT-8L-0.25MM-SM NOSTUFF NOSTUFF
CRITICAL
I2S_SPKRAMP_R_BCLK
E4 PDMD0
SPKRAMP_RR_AREG XW6501
PLACE_NEAR=J6510.10:5 MM
C6513 1 1 C6514 J6510
59 43 IN E3 PDMCK0 220PF 220PF
10% 10% FF14A-14C-R11DL-B-3H
E5 PDMD1
SPKRAMP_RR_DREG 25V
X7R-CERM 2 2 25V
X7R-CERM F-RT-SM1
201 201 16
F5 PDMCK1 PLACE_NEAR=U6500.D1:5 MM PLACE_NEAR=U6500.D5:5 MM
PGND PLACE_NEAR=U6500.D1:3 MM PLACE_NEAR=U6500.D5:3 MM

C GND 1 C6507
0.1UF
1 C6508
1UF
1 C6509
0.1UF
1 C6510
1UF
14 C
13

C2

A4
B4
10% 20% 10% 20% 58 57 55 51 48 47 45 44 43 18 PP1V8_G3S
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
83 76 74 68 62 61 60 59 12
0201 0201 0201 0201 NOSTUFF 11
R65901 10
47K 9
5%
1/20W 8
MF
201 2 7
PLACE_NEAR=U6550.C1:5 MM
PLACE_NEAR=U6550.C1:3 MM PLACE_NEAR=U6550.C4:10 MM 6
PLACE_NEAR=U6550.D2:5 MM PLACE_NEAR=U6550.C4:10 MM
PP1V8_G3S PLACE_NEAR=U6550.D2:3 MM PLACE_NEAR=U6550.C4:3 MM PPBUS_G3H_SPKRAMP_RIGHT 5
58 57 55 51 48 47 45 44 43 18 49 59
83 76 74 68 62 61 60 59 4
1 C6554 1 C6555 1 C6556 3
0.1UF 10UF 10UF 2
1 C6550 1 C6551 1 C6552 1 C6553 10% 20%
25V
20%
25V SPKR_ID1 1
1UF 0.1UF 1UF 0.1UF 2 25V
X5R 2 X5R-CERM 2 X5R-CERM
83 36 OUT
20% 10% 20% 10% 0603 0603
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
0201
0201 0201 0201 0201 15

C1 C6561 BYPASS=U6550.B2:B3:5 MM

D2

C4
C5
NO_XNET_CONNECTION=1
0.1UF
AVDD IOVDD VBAT 1 2

U6550 10%
25V
PTAS5770LB2 X5R
CSP 0201 MIN_LINE_WIDTH=0.4000
SPKRAMP_RESET_L C3 SDZ* B2 MIN_NECK_WIDTH=0.1500
59 58 34 BST_P SPKRAMP_FR_BSTP DIDT=TRUE 83 SPKRCONN_FR_OUTP
CRITICAL A3 1 2
59 48 36
I2C_SPKRAMP_R_SDA F3 SDA OUT_P
DIDT=TRUE
OMIT_TABLE OUT_P B3 DIDT=TRUE SHORT-8L-0.25MM-SM
I2C_SPKRAMP_R_SCL F4 SCL
59 48 36
VSNS_P A1 SPKRAMP_FR_SNSP XW6550
SPKRAMP_INT_L D4 IRQZ PLACE_NEAR=J6510.7:5 MM
B 59 58 34
BST_N A2 SPKRAMP_FR_BSTN C6562 BYPASS=U6550.A2:A5:5 MM
NO_XNET_CONNECTION=1
B
59 SPKRAMP_FR_MODE D3 MODE OUT_N A5 DIDT=TRUE 0.1UF
OUT_N B5 1 2
59 43 I2S_SPKRAMP_R_R2D F2 SDIN
B1
IN
R6551 E1 SDOUT VSNS_N SPKRAMP_FR_SNSN 10%
DIDT=TRUE 25V MIN_LINE_WIDTH=0.4000
33 I2S_SPKRAMP_R_D2R_R2 MIN_NECK_WIDTH=0.1500
59 58 36 OUT
I2S_SPKRAMP_L_D2R 1 2
E2 FSYNC AREG D5 X5R
0201 83 SPKRCONN_FR_OUTN
5% 1/20W MF 201 DIDT=TRUE
I2S_SPKRAMP_R_LRCLK_R F1 SBCLK DREG D1 1 2
59 43 IN
SHORT-8L-0.25MM-SM NOSTUFF NOSTUFF
I2S_SPKRAMP_R_BCLK
E4 PDMD0
SPKRAMP_RW_AREG XW6551
PLACE_NEAR=J6510.4:5 MM
C6563 1 1 C6564
59 43 IN E3 PDMCK0 220PF 220PF
10% 10%
E5 PDMD1
SPKRAMP_RW_DREG 25V
X7R-CERM 2 2 25V
X7R-CERM
201 201
F5 PDMCK1 PLACE_NEAR=U6550.D1:3 MM PLACE_NEAR=U6550.D5:3 MM
PGND PLACE_NEAR=U6550.D1:5 MM PLACE_NEAR=U6550.D5:5 MM
GND 1 C6557 1 C6558 1 C6559 1 C6560
0.1UF 1UF 0.1UF 1UF
C2

A4
B4

10% 20% 10% 20%

2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
0201 0201 0201 0201 TP6500
1 I2S_SPKRAMP_R_LRCLK_R
TP6507
1 PPBUS_G3H_SPKRAMP_RIGHT
A 43 59 A 49 59
TP-P5
PLACE_NEAR=U6500.E2:30MM TP-P5
PLACE_NEAR=U6500.C4:20MM
TP6501
1 I2S_SPKRAMP_R_R2D
TP6508
1 PP1V8_G3S
A 43 59 A 18 43 44 45 47 48 51 55 57 58
TP-P5
PLACE_NEAR=U6500.F2:30MM TP-P5
PLACE_NEAR=U6500.C1:20MM 59 60 61 62 68 74 76 83

TP6509
1 SPKRAMP_RESET_L
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S A PLACE_NEAR=U6500.C3:20MM
34 58 59
83 76 74 68 62 61 60 59 TP-P5
1 1 NOSTUFF TP6503
R6580 R6582 1
A I2S_SPKRAMP_R_BCLK 43 59
470 2.2K TP-P5
PLACE_NEAR=U6500.F1:30MM
5% 5%
A RIGHT BULK CAPACITANCE
1/20W
MF
1/20W
MF
MODE PIN I2C ADDR CHANNEL TP6504
1 I2C_SPKRAMP_R_SDA SYNC_MASTER= SYNC_DATE= A
2 201 2 201 GND 0x31 LEFT REAR A 36 48
PAGE TITLE
SPKRAMP_RR_MODE PLACE_NEAR=U6500.F3:30MM 59
PPBUS_G3H_SPKRAMP_RIGHT 49 59 470 to GND 0x32 LEFT FRONT TP-P5
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
59

59 SPKRAMP_FR_MODE 470 to IOVDD 0x33 RIGHT REAR TP6505 AUDIO RIGHT AMPLIFIERS
1 1 1 1 1 1
1
A I2C_SPKRAMP_R_SCL 36 48 DRAWING NUMBER SIZE
C6583 C6584 C6585 C6586 C6587 C6588 1
R6581
NOSTUFF 1
R6583
2k2 to GND 0x34 RIGHT FRONT TP-P5
PLACE_NEAR=U6500.F4:30MM 59
051-05309 D
33UF 33UF 33UF 33UF 33UF 33UF 2k2 to IOVDD 0x35 TP6506 Apple Inc.
20% 20% 20% 20% 20% 20% 0 2.2K 1 REVISION
2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 5% 5% 10k to GND 0x36
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
TANT-POLY
CASE-B3-1
1/20W
MF
1/20W
MF 10k to IOVDD 0x37
A
TP-P5
PLACE_NEAR=TP6503.1:20MM 5.1.0
2 0201 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
47k to IOVDD 0x38
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO IV ALL RIGHTS RESERVED 59 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

89
60 47 44 43 42 40 34 29 28 27
86 83 81 74 72 71 70 64 63
PP1V8_SLPS2R
PLACE_NEAR=U6650.1:5MM
BYPASS=U6650.1:U6650.7:8MM
DMIC Secure Disable
C6650 1 1
R6651
0.1UF 1K
10%
10V 5%
X5R-CERM 2 1/20W
0201 MF

1
2 201
SEP_CAM_DISABLE_DFF_L OUT 76
PP1V8_G3S
VDD 58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59 PLACE_NEAR=U6640.5:5MM
U6650 BYPASS=U6640.5:U6640.3:8MM
SLG4AP41496V 1 C6641
SEP_CAM_DISABLE_L 2 CAM_DIS* CAM_DIS_OUT* 12 0.1UF
D
34 IN (IPD) STQFN
10% D
34 IN
SEP_DMIC_DISABLE_L 3 DMIC_DIS* (IPD) DMIC_DIS_OUT* 7 SEP_DMIC_DISABLE_OUT_L U6640 10V
2 X5R-CERM
74LVC1G08FW5 0201
4 DIS_STROBE DFN1010
34 IN
SEP_DISABLE_STROBE (IPD) CAM_DIS_OUT 10 NC 6 PLACE_NEAR=U6640.4:5MM
9 PMU_COLD_RST*
2 R6647
85 83 72 35 IN
PMU_COLD_RESET_L DMIC_DIS_OUT 11 NC B
4 PDM_DMIC_DATA0_RR 33 PDM_DMIC_DATA0
1 2 OUT 35 60
Y
60 43 LID_OPEN_RIGHT 13 LID_RIGHT 1 1/20W 5%
A
14 LID_LEFT CRITICAL NC MF 201
43 IN
LID_OPEN_LEFT (IPD) RFU 5 NC 5 3
LID_CTRL_DMIC 6 SEL (IPD)
NC
GND NOSTUFF
R6648

8
PDM_DMIC_DATA0_UNSEC 1 0 2
60

1/20W 5%
MF 0201

Digital Mic Flex Connector

58 57 55 51 48 47 45 44 43 18 PP1V8_G3S
83 76 74 68 62 61 60 59 PLACE_NEAR=U6641.5:5MM
BYPASS=U6641.5:U6641.3:8MM
APN: 518S0818 1 C6642
0.1UF
J6640 10%
FF14A-6C-R11DL-B-3H U6641 10V
F-RT-SM 2 X5R-CERM
7
PDM_DMIC_CLK0 IN 43 60 83 74LVC1G08FW5 0201
R6641 PLACE_NEAR=J6640.2:8MM DFN1010
6 PLACE_NEAR=U6641.4:5MM
1 0 2 PDM_DMIC_DATA0_UNSEC 2
1 60
L6640 B R66492 PDM_DMIC_DATA1
1/20W 5% FERR-470-OHM 4 PDM_DMIC_DATA1_RR 1 35 60
2 83 AUD_DMIC0_DATA_CONN MF 0201 Y OUT

C 3 83 PP1V8_DMIC 1 2 PP1V8_G3S 18 43 44 45 47 48 51 55 57 58
1
A NC 1/20W
33
5%
C
59 60 61 62 68 74 76 83 MF 201
4 0201 5 3
5 83 AUD_DMIC1_DATA_CONN
6
PDM_DMIC_CLK1 IN 43 60 83
1 C6640 NC
R6643 PLACE_NEAR=J6640.5:8MM
20%
1UF
0 PDM_DMIC_DATA1_UNSEC NOSTUFF
8
1 2 60 2 16V
CER-X5R R6650
1/20W 5% 0201
PDM_DMIC_DATA1_UNSEC 1 0 2
TP6600
1 PDM_DMIC_DATA0
MF 0201 60 A PLACE_NEAR=U3900.F1:30MM
1/20W 5% TP-P5
MF 0201 TP6601
1 PDM_DMIC_DATA1
A PLACE_NEAR=U3900.J1:30MM
TP-P5
TP6602
1 PDM_DMIC_CLK0
A 43 60 83
PLACE_NEAR=R4859.2:30MM
TP-P5
TP6603
NOSTUFF AUDIO JACK FLEX CONNECTOR A
1
TP-P5
PP6606
PDM_DMIC_CLK1
PLACE_NEAR=R4860.2:30MM
43 60 83

R6600 P5MM-SP SM-SP

1
SMC_FAN_0_TACH 0 PP
55 35 IN
1 2 APN: 516S1064 PLACE_NEAR=TP6602.1:30MM
1/20W 5% MATES WITH APN: 516S0573 ON FLEX
MF 0201
NO_XNET_CONNECTION=1
PLACE_NEAR=FL6601.2:10MM J6600
51338-0374
F-ST-SM
CRITICAL 32 31
FL6601
120-OHM-25%-1.3A
1 2 83 60 AUD_CONN_HP_LEFT 2 1 AUD_CONN_HP_LEFT 60 83
57 AUD_HP_PORT_L AUD_CONN_HP_LEFT 60 83
IN 4 3 AUD_CONN_SLEEVE 60 83
0402 CRITICAL AUD_CONN_SLEEVE 6 5 AUD_CONN_HP_RIGHT
B FL6602 83 60

AUD_CONN_HP_RIGHT 8 7
60 83
B
120-OHM-25%-1.3A 83 60

1 2 83 60 AUD_CONN_RING2 10 9 AUD_CONN_RING2 60 83
57 AUD_HP_PORT_R AUD_CONN_HP_RIGHT 60 83
IN
83 60 AUD_CONN_RING_SENSE 12 11 AUD_CONN_TIP_SENSE 60 83
CRITICAL 0402
AUD_CONN_HP_SENSE_R 14 13 AUD_CONN_HP_SENSE_L
FL6603 83 60

AUD_CONN_SLEEVE_XW 16 15 AUD_CONN_RING2_XW
60 83

120-OHM-25%-1.3A 83 60 60 83
18 17
57 AUD_HP_PORT_US_GND 1 2 AUD_CONN_RING2 60 83 MIN_LINE_WIDTH=0.2000
OUT 20 19 MIN_NECK_WIDTH=0.1000 PP1V8_MESA_FILT_CONN 44 83
0402 CRITICAL PMU_ONOFF_R_L_CONN 22 21 MESA_INT_CONN
FL6604 89 83 44

SPI_MESA_MOSI_CONN 24 23 SPI_MESA_MISO_CONN
44 83

120-OHM-25%-1.3A 83 44 44 83

1 2 83 44 SPI_MESA_CLK_CONN 26 25 MESA_BOOST_EN_CONN 44 83
57 AUD_HP_PORT_CH_GND AUD_CONN_SLEEVE 60 83
OUT
MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
OUT
83 44 PP16V0_MESA_FILT_CONN MIN_LINE_WIDTH=0.2000 28 27 MIN_LINE_WIDTH=0.2000 PP1V8_SLPS2R 27 28 29 34 40 42 43 44 47 60
CRITICAL 0402
PP3V0_MESA_FILT_CONN MIN_NECK_WIDTH=0.1000 30 29 LID_OPEN_RIGHT
63 64 70 71 72 74 81 83 86 89
MIN_LINE_WIDTH=0.2000
FL6605 83 60 44 OUT 43 60

120-OHM-25%-1.3A MIN_NECK_WIDTH=0.1000
1 2 83 60 44 PP3V0_MESA_FILT_CONN MIN_LINE_WIDTH=0.2000 34 33
57 OUT
AUD_HP_SENSE_L AUD_CONN_HP_SENSE_L 60 83
0402 CRITICAL
FL6606
120-OHM-25%-1.3A 1 C6690 1 C6691 1 C6692 1 C6693 1 C6694 1 C6695 1 C6696 1 C6697
57 OUT
AUD_HP_SENSE_R 1 2 AUD_CONN_HP_SENSE_R 60 83
100PF 100PF 100PF 100PF 100PF 100PF 100PF 100PF
5% 5% 5% 5% 5% 5% 5% 5%
0402 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G
L6607 0201 0201 0201 0201 0201 0201 0201 0201
FERR-470-OHM
57 AUD_TIP_SENSE 1 2 AUD_CONN_TIP_SENSE 60 83
OUT
0201
L6608
FERR-470-OHM
A 57 OUT AUD_RING_SENSE 1 2 AUD_CONN_RING_SENSE 60 83 SYNC_MASTER= SYNC_DATE=
A
CRITICAL 0201 PAGE TITLE

FL6609
120-OHM-25%-1.3A
AUDIO FLEX CONNECTORS
DRAWING NUMBER SIZE

57 OUT
AUD_HS_MIC_P 1 2 AUD_CONN_SLEEVE_XW 60 83 051-05309 D
0402 CRITICAL Apple Inc. REVISION
FL6610 5.1.0
120-OHM-25%-1.3A NOTICE OF PROPRIETARY PROPERTY: BRANCH

57 OUT
AUD_HS_MIC_N 1 2 AUD_CONN_RING2_XW 60 83 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
0402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
66 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO IV ALL RIGHTS RESERVED 60 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

3.3V RSLOC ISOLATION KEYS/ASIC RESET MEMBRANE ZIF CONNECTOR

61 51 PP3V3_G3S_KBD PLACE_NEAR=U6700.8:5mm
PLACE_NEAR=U6700.8:5mm
FF14A-30C-R11DL-B-3H
PP3V3_G3H_RTC 1 C6770 1 C6771
72 71 63 61 57 54 50 29 28 27
89 86 83 76 74 R6703 58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S R67701
1.0UF 0.1UF
518S0752 J6700
PLACE_NEAR=U6703.10:2MM PP3V3_G3H_RTC 1
0 2
PP3V3_G3H_RSLOC 10K 20% 10% CRITICAL
F-RT-SM
72 71 63 61 57 54 50 29 28 27 61 83 5% 2 10V 2 10V
PLACE_NEAR=U6703.10:5MM C6751 89 86 83 76 74 0201 1/20W MF 5% 1
R6771 X5R-CERM 31

8
1 MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000 Q6770 1/20W
MF 0201-1
X5R-CERM
0201

G 1
1 C6750 0.1UF
10% KBD_INT_L
VOLTAGE=3.3V 100K
5%
DMN32D2LFB4
DFN1006H4-3
2012 VCC
2 10V 83 62 61 1/20W SYM_VER_3 U6700 58 57 55 51 48 47 45 44 43 18 PP1V8_G3S 1
60 59
83
58
76
57
PP1V8_G3S 1.0UF X5R-CERM MF
4KB-1.8V-5.5V 83 76 74 68 62 61 60 59
2
45 44 43 18 20% 0201 I2C_KBD_SDA PLACE_NEAR=J6801.6:10MM 2 201 83 61 KBD_ID1
55 51 48 47 2 10V 83 62 61 7 WC* M24C04-R
SDA 5

2 S

3 D
74 68 62 61
X5R-CERM 61 WC_L IOXP_I2C_SDA 61 83
3
0201-1 I2C_KBD_SCL PLACE_NEAR=J6801.8:10MM EEPROM_WC_L MLP8
4
D 1
R6750
83 62 61

PLACE_NEAR=J6801.12:10MM
DZ6710 DZ6711 IOXP_I2C_SCL 6 SCL NC 1 83 61 KBD_DRIVE_Y2
NC
5
D
0 2 5.5V-0.28PF 2 5.5V-0.28PF 2 376S1128 NC

10
0201-THICKSTNCL 0201-THICKSTNCL 83 61 KBD_DRIVE_Y1 6
5% 2 E1 7
1/20W VDD 83 61 KBD_DRIVE_Y3
MF
2 0201
U6703 DZ6712 3 E2 83 61 KBD_DRIVE_Y4 8

1 1 5.5V-0.28PF 1 83 61 KBD_SENSE_X0 9
SLG4AP4815V 0201-THICKSTNCL VSS EPAD 10
TQFN 83 61 KBD_SENSE_X1

9
OUT123_EN 4 335S00254 83 61 KBD_SENSE_X2 11
OE
83 61 KBD_SENSE_X5 12
9 13
KBD_RIGHT_SHIFT_KEY 1 OUT_1 KBD_RIGHT_SHIFT_L 61 83 61 KBD_SENSE_X3
83 61 IN_1
8 83 61 KBD_SENSE_X9 14
KBD_LEFT_OPTION_KEY 2 OUT_2 KBD_LEFT_OPTION_L 61
83 61 IN_2 83 61 KBD_SENSE_X12 15
7 16
KBD_CONTROL_KEY 3 OUT_3 KBD_CONTROL_L 61 83 61 KBD_SENSE_X4
83 61 IN_3
R6752 83 61 KBD_SENSE_X11 17

33 KBD_SENSE_X10 18
OUT_ALL# 6 RSLOC_RST_L MF 1 2
PMU_RSLOC_RST_L
83 61

1/20W 1% 201
OUT 63 72 83 89
DZ6701 83 61 KBD_SENSE_X6 19

PESD3V3L5UF PLACE_NEAR=J6700.30:5MM 83 61 KBD_SENSE_X7 20

GND EPAD SOT886 83 61 KBD_SENSE_X8 21
5

11
343S00073 IN_1/IN_2/IN_3 = 100K INTERNAL PULLDOWN
1 6 KBD_CONTROL_KEY 61 83 83 61 KBD_DRIVE_Y5 22
OUT_1/OUT_2/OUT_3 = 12.5K INTERNAL PULL-UP NC
83 61 KBD_DRIVE_Y7 23

83 61 KBD_DRIVE_Y6 24

83 61 KBD_DRIVE_Y0 25
PP1V8_G3S 5 KBD_LEFT_OPTION_KEY 61 83
KBD_CAP_CATHODE 26
KEYBOARD INTERFACE - IO EXPANDER 83 61

83 61 PP3V3_G3H_RSLOC 27

83 61 KBD_RIGHT_SHIFT_KEY 28
PP3V3_G3S_KBD
61 51 83 61 PP3V3_G3H_RSLOC 3 4 KBD_RIGHT_SHIFT_KEY 61 83 83 61 KBD_LEFT_OPTION_KEY 29

1 1 83 61 KBD_CONTROL_KEY 30
76 1
C6720 R6722 C6721 C6722 1 1 1 1 1 1 1 1 1 1
C R6720
1 68
61
59
1
1.0UF 100K
0.1UF
10%
0.1UF
10%
1

R6730 R6731 R6732 R6733 R6734 R6735 R6736 R6737 R6738 R6739 R6740 R6741 R6742
1
1
C
VDD/I2C-BUS 23
VDD/P 21

57 32
10K 51
47
20% 5% 10V 10V 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
5% 44 2 10V 1/20W 2 X5R-CERM 2 X5R-CERM 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
PP1V8_G3S

2
1/20W 18 X5R-CERM MF 0201 0201 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF 43 0201-1 201 MF MF MF MF MF MF MF MF MF MF MF MF MF
201 2
45 2 201 201 201 201 201 201 201 201 201 201 201 201 201
48
55 2 2 2 2 2 2 2 2 2 2 2 2
58 1 2
60
62
R6721
74
83
1K
1%
1/20W
MF IOXP2_INT_L 22 1
DZ6702
201
2 83 61 INT* P0_0
2
KBD_SENSE_X0 61 83 PESD3V3L5UF PLACE_NEAR=J6700.25:5MM
IOXP2_ADDR 18 P0_1 KBD_SENSE_X1 61 83
SOT886
ADDR U6702 P0_2
3
KBD_SENSE_X2 61 83 83 61 KBD_CAP_CATHODE 1 6 KBD_DRIVE_Y0 61 83
IOXP_I2C_SCL 19 PCAL6416A 4
83 61 SCL P0_3 KBD_SENSE_X3 61 83
IOXP_I2C_SDA 20 HWQFN 5
83 61 SDA P0_4 KBD_SENSE_X4 61 83
6
IOXP2_RESET_L 24 P0_5 KBD_SENSE_X5 61 83 5
RESET* 7 KBD_DRIVE_Y6 61 83
P0_6 KBD_SENSE_X6 61 83
8
P0_7 KBD_SENSE_X7
C6723 1
10
61 83
DZ6706
0.1UF
10%
P1_0
11
KBD_SENSE_X8 61 83
83 61 KBD_DRIVE_Y5 3 4 KBD_DRIVE_Y7 61 83
PESD3V3L5UF
10V 2 P1_1 KBD_SENSE_X9 61 83
SOT886
X5R-CERM 12 1 6
0201 P1_2 KBD_SENSE_X10 61 83 83 61 KBD_DRIVE_Y4 KBD_DRIVE_Y3 61 83
13
311S0665 P1_3
14
KBD_SENSE_X11 61 83
PLACE_NEAR=J6700.8:5MM
P1_4 KBD_SENSE_X12 61 83

2
15
P1_5 KBD_CONTROL_L 61 5
WRITE ADDRESS = 0X42 P1_6
16
KBD_LEFT_OPTION_L 61
KBD_DRIVE_Y1 61 83

READ ADDRESS = 0X43 17

THRM
PAD
VSS

P1_7 KBD_RIGHT_SHIFT_L 61

R6723 DZ6703 PP1V8_G3S 3 4 KBD_DRIVE_Y2

9

25

58 57 55 51 48 47 45 44 43 18 61 83

33 IOXP2_INT_L
PESD3V3L5UF 83 76 74 68 62 61 60 59

SOT886
B 83 62 61 KBD_INT_L MF 1
1/20W 1%
2
201
61 83

83 61 KBD_SENSE_X8 1 6
PLACE_NEAR=J6700.20:5MM
KBD_SENSE_X7 61 83
B

2
5 KBD_SENSE_X6 61 83

61 51 PP3V3_G3S_KBD 83 76 74 68 62 61 60
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S PLACE_NEAR=J6700.13:5MM
DZ6705
138S0706
59
1
132S0320
1
138S0847 3 4 KBD_ID1 61 83
PESD3V3L5UF
R6714 1 1
R6715 1 C6712 C6713 1 C6714 NC SOT886
23
21

10K 100K
C6710 0.1UF 0.1UF 10UF KBD_SENSE_X3 1 6 KBD_SENSE_X5
1.0UF 10% 10% 20% 83 61 61 83
VDD/I2C-BUS
VDD/P

5% 5% 20% 10V 10V

1/20W 1/20W 10V 2 X5R-CERM 2 X5R-CERM 2 10V
X5R-CERM
MF MF 2 X5R-CERM 0201 0201 0402-7
R6710 1 1
R6711 201 2 2 201 0201-1

2
1.3K 1.3K 5 KBD_SENSE_X2
1% 1% 61 83
1/20W 1/20W
MF MF
201 2 2 201 22 1
R6712 IOXP1_INT_L INT* P0_0
2
KBD_DRIVE_Y0 OUT 61 83

33
201
18
ADDR U6701 P0_1
3
KBD_DRIVE_Y1 OUT 61 83 DZ6704 83 61 KBD_SENSE_X0 3 4 KBD_SENSE_X1 61 83

MF 2
1/20W
1 1% 19 PCAL6416A
P0_2
4
KBD_DRIVE_Y2 OUT 61 83 PESD3V3L5UF
83 62 61 I2C_KBD_SCL 83 61 IOXP_I2C_SCL SCL P0_3 KBD_DRIVE_Y3 61 83
SOT886
OUT
20 HWQFN 5 1 6
83 62 61 I2C_KBD_SDA 2 1 83 61 IOXP_I2C_SDA SDA P0_4 KBD_DRIVE_Y4 OUT 61 83 61 51 PP3V3_G3S_KBD 83 61 KBD_SENSE_X10 KBD_SENSE_X11 61 83
6
MF 1/20W 1% 24 P0_5 KBD_DRIVE_Y5 61 83
IOXP1_RESET_L OUT 1 C6705

2
201 RESET* 7
P0_6 KBD_DRIVE_Y6 OUT 61 83
1UF
33 8 20%
P0_7 KBD_DRIVE_Y7 61 83
R6713 C6711 1
10
OUT
2 10V
X5R
5 KBD_SENSE_X4 61 83
0.1UF P1_0 0201
KBD_ID PIN CONNECTION ON MEMBRANE KBD 10% 11 NC
10V P1_1 PLACE_NEAR=J6700.14:5MM
3

X5R-CERM 2 12
ANSI FLOAT NC 0201 P1_2 HW_ID1 61 VIN
A P1_3
13
EEPROM_WC_L 61
U6705
83 61 KBD_SENSE_X9 3 4 KBD_SENSE_X12 61 83
SYNC_MASTER=X1412_SHAN SYNC_DATE=05/17/2019
A
ISO HIGH PP1V8_G3S 14 PAGE TITLE
P1_4 NC FAN5622
R6761
JIS GND GND P1_5
15
16 NC 1
1K 201
2 LED_CTRL 1 CTRL
SSOT23
LED1 6 KBD_CAPSLOCK_LED 61 83
KEYBOARD & TRACKPAD 1
P1_6 KBD_ID_DETECT1 61 DRAWING NUMBER SIZE
LED2 4

2
17
THRM

MF 1/20W 5%
5 ISET 051-05309 D
PAD

R6717 1 CAPSLOCK_LED_EN
VSS

1K P1_7
61 KBD_ID_DETECT1
201 MF 1/20W5%
2 KBD_ID1 61 83 LED_ISET
GND
Apple Inc. REVISION

R6719 1 1 1 5.1.0
9

25

1K R6762 R6760
2
2

61 HW_ID1
201 MF 1/20W5% WRITE ADDRESS = 0X40 311S0665 200K
5%
19.1K
1%
NOTICE OF PROPRIETARY PROPERTY: BRANCH

NOSTUFF READ ADDRESS = 0X41 1/20W 1/20W THE INFORMATION CONTAINED HEREIN IS THE
R6718 1.00 MF
201
MF
201
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
83 61 KBD_CAPSLOCK_LED 1 2 KBD_CAP_CATHODE 61 83
2 2
1%
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
67 OF 500
1/16W SHEET
MF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 BOM_COST_GROUP=KEYBOARD IV ALL RIGHTS RESERVED 61 OF 98
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 8 7 6 5 4 3 2 1

Trackpad Level Shifting TPAD CONNECTOR

J6801
DF40C-50DS-0.4V-51
F-ST-SM

CKPLUS_WAIVE=I2C_PULLUP I2C_TPAD_3V3_SCL 2 1 IPD_LID_OPEN 43 46 83

CKPLUS_WAIVE=I2C_PULLUP I2C_TPAD_3V3_SDA 4 3 TPAD_KBD_WAKE_L 35 62 83

SIGNAL_MODEL=CUSTOM_SN74AVC4T774 83 61 KBD_INT_L 6 5 TPAD_3V3_ACTUATOR_DISABLE_L 62 83

CKPLUS_WAIVE=I2C_PULLUP I2C_KBD_SDA 8 7 TPAD_3V3_SPI_INT_L 62 83

72 70 43 42 40 37 27
83
PP1V8_AWAKE PP3V3_G3S 45 50 51 57 62 74 75 76 83
10 9
OUT

BYPASS=U6860::5MM NOSTUFF I2C_KBD_SCL 12 11 SPI_TPAD_3V3_MOSI

D R68031 C6860 1 BYPASS=U6860::5MM R68741 R68711 R68721 R68731
CKPLUS_WAIVE=I2C_PULLUP
14 13 SPI_TPAD_3V3_CS_L
62 83

62 83
D
100K 1 C6861 100K 100K 100K 100K

14

13
5% 0.1UF 5% 5% 5% 5% 16 15 SPI_TPAD_3V3_MISO
1/20W 10%
VCCA VCCB
0.1UF 1/20W 1/20W 1/20W 1/20W
62 83

MF 10V
X5R-CERM 2
10% MF MF MF MF 18 17 TPAD_3V3_SPI_EN 62 83
201 2 0201 U6860 2 10V
X5R-CERM 201 2 201 2 201 2 201 2
20 19 SPI_TPAD_3V3_CLK
SN74AVC4T774-COMBO 0201 62 83 85

QFN 22 21 83 PP5V_G3S_TPAD_CONN NOSTUFF

36 SPI_TPAD_CS_L 1 A1 B1 12 SPI_TPAD_3V3_CS_L 62 83 VOLTAGE=5V
IN
15 DIR1
OUT 24 23 1 C6702
26 25 PP3V3_G3S_TPAD 51 83
12PF
PLACE_NEAR=U6860.9:2MM 5%
43 42 SPI_TPAD_CLK 2 A2 B2 11 SPI_TPAD_3V3_CLK_R 28 27 2 25V
IN
16 DIR2
R6875 30 29
NP0-C0G
0201
1
20 2 SPI_TPAD_3V3_CLK L6700
OUT 62 83 85 32 31 FERR-120-OHM-1.5A
43 42 IN
SPI_TPAD_MOSI 3 A3 B3 10 SPI_TPAD_3V3_MOSI_R 5% 34 33
NC
5 PLACE_NEAR=U6860.8:2MM 1/20W 1 2 PP5V_G3S_TPAD
DIR3 MF 54 87
36 35
R6876 201 0402A
43 OUT
SPI_TPAD_MISO_R 4 A4 B4 9 SPI_TPAD_3V3_MISO IN 62 83
1
20 2 SPI_TPAD_3V3_MOSI
38 37
XW6701 C6700 1
6 DIR4 OUT 62 83
40 39 SM 0.1UF
7
R68701 R68801 5%
1/20W 83 62 ACT_GND 42 41 83 62 ACT_GND 1 2
10%
25V 2
X5R
OE* 100K 100K MF
201 PPBUS_G3H 44 43 PPBUS_G3H 402
GND 5% 5% 87 86 83 75 72 64 62 49 49 62 64 72 75
1/20W 1/20W 83 86 87
MF MF 46 45

8
201 2 201 2
NOSTUFF 48 47
50 49

516S00187, MATE WITH 516S00188

C C
PP1V8_G3S 83 76 75 74 62 57 51 50 45 PP3V3_G3S
PP3V3_G3S 45 50 51 57 62 74 75 76 83
58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59

Q6861 R68121 1
R6813 R68631 1
R6864
Q6862

VER-1
PP1V8_G3S 2.2K 2.2K 10K 100K
G 2

VER-1
58 57 55 51 48 47 45 44 43 18 SSM6N15AFEAP 5% 5% 5% 5%

G 5
83 76 74 68 62 61 60 59
SOT563 CRITICAL 1/20W 1/20W PLACE_NEAR=Q6861.6:2MM 1/20W SSM6N15AFEAP 1/20W
MF MF MF CRITICAL MF
201 2 2 201 R6877 201 2 SOT563
2 201
30
1 S

6 D
47 I2C_SENSE_SCL_R1 I2C_TPAD_3V3_SCL_R 1 2 I2C_TPAD_3V3_SCL 62 83

4 S

3 D
IN OUT
35 OUT
TPAD_SPI_INT_L
5%
1/20W TPAD_3V3_SPI_INT_L
MF
Q6861 201 IN
VER-1
G 5

83 62
SSM6N15AFEAP
SOT563 CRITICAL PLACE_NEAR=Q6861.3:2MM 58 57 55 51 48 47 45 44 43 18
83 76 74 68 62 61 60 59
PP1V8_G3S
R6878
I2C_TPAD_3V3_SDA_R 30
R68651
4 S

3 D

47 BI
I2C_SENSE_SDA_R1 1 2 I2C_TPAD_3V3_SDA BI 62 83

5% 10K
1/20W 5%
MF 1/20W
201 MF
201 2

83 62 35 TPAD_KBD_WAKE_L

58 57 55 51 48 47 45 44 43 18 PP1V8_G3S 83 76 75 74 62 57 51 50 45 PP3V3_G3S
83 76 74 68 62 61 60 59 NOSTUFF
B R6867 1 1
R6868 B
10K 100K
5% Q6862 5%

VER-1
1/20W 1/20W

G 2
MF SSM6N15AFEAP MF
201 2 SOT563 CRITICAL 2 201

1 S

6 D
35 BI BI 62 83

PP3V3_G3S 45 50 51 57 62 74 75 76 83 TPAD_ACTUATOR_DISABLE_L TPAD_3V3_ACTUATOR_DISABLE_L

BYPASS=U6855::5MM Pull-Up on IPD module
C6856 1 NOSTUFF
0.1UF 1
10% R6854
10V 100K
X5R-CERM 2
U6855 0201
5%
1/20W
74AUP1T97 MF
5

SOT891 2 201
34 IN
TPAD_SPI_EN 1 4 TPAD_3V3_SPI_EN OUT 62 83
6

1
R6853
3

1
R6852
2

100K
100K 5%
5% 1/20W
1/20W MF
MF 2 201
201 2

A SYNC_MASTER= SYNC_DATE= A
PAGE TITLE

Keyboard & Trackpad 2

DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
68 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TRACKPAD IV ALL RIGHTS RESERVED 62 OF 98
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 8 7 6 5 4 3 2 1
BMU LOGIC CONNECTOR NOSTUFF
R6958
72 71 63 61 57 54 50 29 28 27
89 86 83 76 74
PP3V3_G3H_RTC 2
0 1
BATTERY (BMU) FLEX SOLDER PADS
5%
0201 1/20W MF
BMU POWER FLEX IS SOLDERED TO MLB.
<RDAR://45444338> 60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R
R6957 89 86 83 81 74 72 71 70 64

0
518S00014 86 83 74 68 54 52 PP3V3_G3H 2 1 PP3V3_G3H_BMU CRITICAL
Q6950
TP6906
1
A
998-03828
CRITICAL

VER-1
5%
CRITICAL TP6903 TP-P5

G 2
0201 1/20W MF SSM6N15AFEAP
J6951 TP-P5
A
1 1 SOT563
PLACE_SIDE=BOTTOM J6950
FF18-10A-R11AD-B-3H
F-RT-SM-A PLACE_SIDE=BOTTOM R6951 R6952 PWR-MLB-X520 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
4.7K 4.7K PLACE_SIDE=BOTTOM

6 D

1 S
11 I2C_PWR_SCL_R1 HB-SM
D 1/20W
5%
MF
5%
1/20W
MF
TP6904
1
IN 47
632-00731 1 PCBA,FLEX,BMU PWR,X502 J6950 CRITICAL D
1 201 2 2 201
A TP6907 11 10
TP-P5 1
CRITICAL A
2 SMBUS_3V3_BATT_SCL TP-P5
83
Q6950

VER-1
3 PLACE_SIDE=BOTTOM
SMBUS_3V3_BATT_SDA 12

G 5
83
SSM6N15AFEAP 9
4 SOT563

2
5
NC CRITICAL TP6905
1 1
D6950 A

3 D

4 S
6 I2C_PWR_SDA_R1 47
8
NC TP-P5 BI
7 RCLAMP3552T PLACE_SIDE=BOTTOM
8 SLP1006N3T TP6908
1
NC FUTURE DESIGNS SHOULD USE
A 2 7
9 A BETTER LVL SHIFT DESIGN TP-P5
NC <RDAR://49154606> PLACE_SIDE=BOTTOM
10
6 PPVBAT_G3H_CONN

3
64 83
3
12
1 C6950 1 C6960 1 C6961 1 C6962 1
R6956 4 5
0.1UF
10%
1UF
10%
3PF
+/-0.1PF
3PF
+/-0.1PF
SYS_DETECT_L 10K 25V 2 25V 2 25V 2 25V 2
TP6900 83 86 5% X5R X5R C0G C0G
1 1/16W 402 603-1 0201 0201
A MF-LF
TP-P5
1
NOSTUFF 3 D Q6955 2 402
PLACE_SIDE=BOTTOM R6955 DMN32D2LFB4
DFN1006H4-3
TP6902
1
10K SYM_VER_2 A
5%
1/16W TP-P5
MF-LF PLACE_SIDE=BOTTOM
TP6901 2 402 G 1
1 2 S
A SYS_DETECT 83
TP-P5
PLACE_SIDE=BOTTOM

C C
SMC Reset Circuit
Right Shift & Left Option Control
followed by ON OFF button press.
72 71 63 61 57 54 50 29 28 27
PP3V3_G3H_RTC
89 86 83 76 74
BYPASS=U6940::3MM
C6940 1
1

0.1UF VDD
10%
25V 2
X5R
0201 U6940
SLG4AP41183
STQFN R6940
3 CHGR_RST_IN_R 1K CHGR_RST_IN
72 44 IN
PMU_ONOFF_L BTN1 RESET 10 1 2 OUT 64

89 83 72 61 PMU_RSLOC_RST_L 4 BTN2 5%
IN
1/20W
NC 2 MF
CRITICAL NC 201
NC 5
NC
NC 6
NC
R6941
8 1
1K 2 UPC_PMU_RESET
NC NC OUT 28 29 72 83 85

NC 9 5%
NC 1/20W
NC 11 MF
NC 201
NC 12
NC
GND
PPVIN_G3H_P3V3G3HRTC
7

87 49
PP3V3_G3H_RTC_REG_R 63 87 PP3V3_G3H_RTC 27 28 29 50 54 57 61 63 71 72
74 76 83 86 89

B 1 R6908 VOUT = 3.304V B

R6900 1 100K R6934 1 1
R6935
0
0% 3.3V G3H RTC VR 5%
1/20W
6A Max Output 0
0% 0%
0
1/4W MF 1/4W 1/4W
MF
0603 2
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000 2
201
CRITICAL
f = 1.25 MHZ MF
0603 2
MF
2 0603
86 PPVIN_G3H_P3V3G3HRTC_R L6900 MIN_NECK_WIDTH=0.1000
U6903 1UH-20%-4.8A-0.032OHM MIN_LINE_WIDTH=0.2000
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1 2 PP3V3_G3H_RTC_REG_R
TPS62180 P3V3G3HRTC_PHASE1 87 63
1 C6900 1 C6902 1
C6907 1 C6905 1 C6906 1 C6901 1 C6909 A1 VIN1
BGA
SW1 A2
DIDT=TRUE 1210
152S00386
2.2UF 2.2UF 68UF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
20% 20% 20% 2.2UF 2.2UF 0.1UF 0.1UF B1 VIN1 CRITICAL SW1 B2
2 25V
X5R-CERM 2 25V
X5R-CERM 2 16V
POLY-TANT
20%
2 25V
20%
2 25V
10%
2 25V
10%
2 25V C1 VIN1 SW1 C2
L6901 1
C6912 1 C6914 1 C6915 1
C6916 1
C6917 1 C6918 1 C6919
0402-1 0402-1 CASE-D2E-SM-1 X5R-CERM X5R-CERM X6S-CERM X6S-CERM 1UH-20%-4.8A-0.032OHM 150UF 10UF 10UF 150UF 150UF 10UF 10UF
0402-1 0402-1 0201 0201 20% 20% 20% 20% 20% 20% 20%
D1 VIN2 SW2 D2 P3V3G3HRTC_PHASE2 1 2 2 6.3V 2 10V 2 10V 2 6.3V 2 6.3V 2 10V 2 10V
DIDT=TRUE 1210 TANT X5R-CERM X5R-CERM TANT TANT X5R-CERM X5R-CERM
E1 VIN2 SW2 E2 152S00386 CASE-B-SM 0402-1 0402-1 CASE-B-SM CASE-B-SM 0402-1 0402-1

R6907 F1 VIN2 SW2 F2 CRITICAL R6912 1

0 10 VOUT = 0.8 * (1 + <RA>/<RB>) = 3.304V
83 64 IN
CHGR_EN_MVR 2 1 CHGR_EN_MVR_R E4 EN VO A4 5%
1/20W
5% MF
1/20W P3V3G3HRTC_SS D4 SS/TR PG F4 P3V3G3HRTC_PGOOD 201
MF 2
0201 P3V3G3HRTC_FB_R
FB B4 P3V3G3HRTC_FB
C6903
AGND

PGND
PGND
PGND
PGND
PGND
PGND

0.033UF 1 R6913 1
10% 0.00
50V 1%
2
C4

A3
B3
C3
D3
E3
F3

X7R 1/20W
0402 MF
<Ra> 0201 2
C6910 1
P3V3G3HRTC_RA_R
220PF
10%
XW6900
SM
16V
CER-X7R
2 R6910 1
0201 360K
A 1 2 0.1%
1/20W SYNC_MASTER= SYNC_DATE=
A
MF PAGE TITLE
<Rb> 0201
2
BATTERY CONN, 3V3 G3H RTC VR
DRAWING NUMBER SIZE
R6911 1
051-05309 D
115K Apple Inc.
0.1% REVISION
1/20W
GND_P3V3G3HRTC_AGND MF
0201
5.1.0
MIN_LINE_WIDTH=0.2000 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MIN_NECK_WIDTH=0.1000
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
69 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=PLATFORM POWER IV ALL RIGHTS RESERVED 63 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

PLACE NEARS FOR C7033, C7034

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000 REQUIRE UPDATE FOR P1 PER <RDAR://42934724>
83 PPDCIN_G3H_CHGR
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D 1
C7024 1
C7025 1
C7026 1
C7027 1
C7028 1
C7029 1 C7032 1 C7033 1 C7034 1 C7035 D
6.8UF 6.8UF 6.8UF 6.8UF 6.8UF 6.8UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% CRITICAL CRITICAL
2 35V-0.09OHM 2 35V-0.09OHM 2 35V-0.09OHM 2 35V-0.09OHM 2 35V-0.09OHM 2 35V-0.09OHM 2 35V 2 35V 2 35V 2 35V
POLY-TANT
CASE-B1-2-SM
POLY-TANT
CASE-B1-2-SM
POLY-TANT
CASE-B1-2-SM
POLY-TANT
CASE-B1-2-SM
POLY-TANT
CASE-B1-2-SM
POLY-TANT
CASE-B1-2-SM
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
1
C7050 1
C7051 1 C7053 1 C7055 1 C7054
68UF 68UF 2.2UF 2.2UF 1000PF
20% 20% 20% 20% 10%
2 16V 2 16V 2 25V
X5R
25V
2 X5R 2 25V
X7R
POLY-TANT POLY-TANT
CASE-D2E-SM-1 CASE-D2E-SM-1 0402-1 0402-1 0201
NO_XNET_CONNECTION=1
CRITICAL L7030
R7020 2.7UH-20%-12.5A-0.0196OHM
(AMON) 0.01 CHGR_LX1 1 2 CHGR_LX2 CRITICAL
64 64
0.5%
FROM USB-C SOURCE 1W
MF
IHLP4040BD-PIMA102D-COMBO F7000 TO SYSTEM
0612-1-COMBO CRITICAL 12AMP-32V
87 83 64 49 27 PPDCIN_G3H 1 2 83 64 PPVBAT_G3H_CHGR_REG 1 2 PPBUS_G3H 49 62 72 75 83 86 87
MIN_LINE_WIDTH=0.2000 3 4 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000

10

10
7
1206

3
2
3
4

5
6
7

2
5
PENDING DE-SENSE CAPS ADDITION CHGR_CSI_R_P CHGR_CSI_R_N

PWRPAIR-3X3-COMBO

PWRPAIR-3X3-COMBO
D1

D1
S2

S2
PENDING DE-SENSE CAPS ADDITION

SIZ342DT

SIZ342DT
CRITICAL CRITICAL

Q7030

Q7040
R70211 1
R7022
1.00 1.00
1% 1%

S1/D2

S1/D2
1/20W 1/20W
MF-LF MF-LF
0201 2 2 0201

1 G1

8 G2

G2

G1
1
8

9
9
CHGR_CSI_P CHGR_CSI_N 1
1
CHGR_GATE_Q2 CHGR_GATE_Q3
C7021 1 1 C7022 CHGR_GATE_Q1
CHGR_GATE_Q4
P2MM P2MM 0.047UF 0.047UF
SM SM 10% 10%
1 CHGR_GATE_Q1 1 50V 2 50V CHGR_LX1 CHGR_LX2
CER-X7R 2
C PP7011 PP PP
PP7001 0402
CER-X7R
0402 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 C7066
2.2UF
1 C7069
2.2UF
1 C7067
0.1UF
1 C7068
0.01UF
1
C
P2MM P2MM
1 C7030 C7040 1
20% 20% 10% 10%
SM SM 0.1UF 0.1UF 25V 2
X5R
25V 2
X5R
25V 2
X5R
25V
X5R-CERM 2
1 CHGR_GATE_Q2 1 10% 10%
PP7012 PP PP
PP7002 2 25V 25V 2 0402-1 0402-1 0201 0201
1 X7R-CERM-1
0402
X7R-CERM-1
1 0402 NO_XNET_CONNECTION=1
P2MM P2MM DIDT=TRUE DIDT=TRUE CRITICAL
SM
1 CHGR_GATE_Q3 1
SM CRITICAL
PP7013 PP PP
PP7003 SWITCH_NODE=TRUE SWITCH_NODE=TRUE
R7060 Q7065
CHGR_BOOT1_RC CHGR_BOOT2_RC 0.005 SI7655DN-COMBO
1 1%
P2MM
SM
P2MM
SM R7030 R70401
(BMON) 1W PWRPK-1212-8
1 CHGR_GATE_Q4 1 0 MF
PP7014 PP PP
PP7004 5% 0 (PBUS) 0612-5
PPVBAT_G3H_CHGR_R TO/FROM BATTERY

S
1/16W 5% 1 2

3
MF-LF 1/16W MIN_LINE_WIDTH=0.2000
3 4 PPVBAT_G3H_CONN

D
P2MM P2MM 2 402 MF-LF MIN_NECK_WIDTH=0.1000 63 83

2
SM SM 402 2 MIN_LINE_WIDTH=0.2000

5
1 64 CHGR_LX1 1 MIN_NECK_WIDTH=0.1000
PP7015 PP PP
PP7005 CHGR_BOOT1

1
CHGR_BOOT2 CHGR_CSO_R_P CHGR_CSO_R_N PLACE_NEAR=Q7065.5:2MM

G
P2MM
SM
P2MM
SM
1 C7060
0.1UF

4
PP
1 64 CHGR_LX2 1
PP R70611 1
R7062 C7064 10%
PP7016 PP7006
1.00 1.00 1000PF 2 25V
X5R
1% 1% 1 2 0201
P2MM 1/20W 1/20W
SM MF-LF MF-LF
83 64 63 CHGR_EN_MVR 1 0201 2 2 0201
PP
PP7007 R7075 10%
25V
CHGR_BGATE
4.7 CHGR_CSO_P CHGR_CSO_N X7R 1
P2MM
1 2 0201 1 C7063 R7063
SM 5% C7061 1 1 C7062 4700PF 1K
CHGR_INT_L 1 1/20W 10% 5%
72 64 PP
PP7008 MF 0.047UF 0.047UF 2 25V
CER-X5R
1/20W
201 10% 10% MF
50V 2 50V 0201 2 201

SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
CHGR_VDDA CHGR_VDDP CER-X7R 2 CER-X7R
1 0402 0402
R7015
1%
750K 1 C7075 C7077 1
2.2UF 10UF
1/20W 20% 20% Q7070
B MF
2 201 2 25V 25V
X5R-CERM 2
3 D
DMN32D2LFB4 B

GATE_NODE=TRUE
X6S-CERM
CHGR_AUX_DET 0402 0603 DFN1006H4-3

GATE_NODE=TRUE
SYM_VER_2
NO STUFF
VDDA A2

VDDP D2
PLACE_NEAR=U7000.C5:1MM

C7016 1 1
R7016

DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
0.01UF 255K G 1
10% 2 S
25V
X5R-CERM 2
1%
1/20W C7023 R7071
0201 MF 0.47UF SAVE_BAT_S SAVE_BAT_G 1
200K 2 PPDCIN_G3H
2 201 2 1 U7000 27 49 64 83 87

1%

DIDT=TRUE
B5 P_IN ISL9240 GATE_Q1 H1 1/20W

K
20% WCSP R7070 1 MF

DIDT=TRUE
4V
CERM-X5R-1
C5 CSIN
CRITICAL
BOOT1 F1
24K D7070 201
201 D5 CSIP LX1 G1 5% GDZ5V6LP3-55
1/16W DFN0201-COMBO
83 64 PPVBAT_G3H_CHGR_REG A5 PBUS_PWR GATE_Q2 E1 MF-LF

A
D3 D1 PLACE_NEAR=U7000.A4:1MM 402 2
PLACE_NEAR=U7000.A5:2MM AUX_DET GATE_Q3
C7081 1 LX2 B1 DIDT=TRUE SWITCH_NODE=TRUE C7020
2.2UF OMIT_TABLE C1 DIDT=TRUE SWITCH_NODE=TRUE 0.47UF
20% BOOT2 2 1
35V A1 DIDT=TRUE SWITCH_NODE=TRUE
X5R-CERM 2 GATE_Q4
0402 PBUS A3 20%
4V
CSOP A4 CERM-X5R-1
60 47 44 43 42 40 34 29 28 27 PP1V8_SLPS2R F5 VDDIO1P8 B4
201
89 86 83 81 74 72 71 70 63 CSON
47 BI
I2C_PWR_SDA_R2 G5 SDA B3
BGATE
C7080 1 47 IN
I2C_PWR_SCL_R2 H5 SCL
VBAT C3 CHGR_VBAT
1UF 63 CHGR_RST_IN G2 SMC_RST_IN
20%
10V 2
IN
G3 EN_VR1 F2 NC_CHGR_EN_VR1
X5R HPWR_EN*
0201 E5 SMC_RST* H4 NC_CHGR_SMC_RST_L
COMP
IRQ* H3 CHGR_INT_L OUT 64 72
G4 CELL CBC_ON H2 CHGR_CBC_ON 72
OUT
EN_MVR F4 CHGR_EN_MVR OUT 63 64 83

A CHGR_COMP B2 NC0
C2 NC1
AUX_OK F3
D4
NC_TP_CHGR_AUX_OK
CHGR_AMON SYNC_MASTER= SYNC_DATE=
A
AMON OUT 49 54
PAGE TITLE
AGND

PGND

E4 NC2 BMON C4 CHGR_BMON OUT 49 54

PBUS SUPPLY & BATTERY CHARGER
DRAWING NUMBER SIZE
E3

E2

NO STUFF
C7070 1 1 C7071 051-05309 D
0.12UF 0.12UF
Apple Inc. REVISION
10%
10V 2
10%
2 10V
5.1.0
X5R X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
0402 0402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
70 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=PLATFORM POWER IV ALL RIGHTS RESERVED 64 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

P2MM
SM
R7143 66 65 CPUCORE_PWM1 1
FB_B_CPUCORE 65
PP
PP7100
FB_CORE_R 2
3.16K 1
P2MM
R7142 1% 66 65 CPUSA_PWM 1
SM
PP R7147
CPU_VCCSENSE_P 0 1/20W PP7102 FB_A_CPUGT
7 IN
1 2
C7144 MF 65
1
2.67K 2 FB_GT_R
5% 1000PF
201
R7144 R7145 P2MM
SM
1/20W
1 FB_B_CORE_R 1K 715 67 65 CPUGT_PWM2 1 1%
R7146
MF 2 2 1 1 2 FB_B_CORE_RC PP
PP7104 1/20W
0201 MF 0 CPU_VCCGTSENSE_P
1% NOSTUFF 1% P2MM 201
C7147 2 1 7
10%
16V
1/20W
1
1/20W C7143 1
CPUGT_PWM1 1
SM
R7149 R7148 1000PF
IN

X7R-1
MF
201 R7139 MF
201 680PF
10%
67 65 PP
PP7103 715 1K
5%
1/20W
0201 330K 25V FB_A_GT_RC 1 2 1 2 FB_A_GT_R 1 2 MF

D XW7140
SM
5%
1/20W
MF
CERM 2
201 C7148 1
1%
1/20W
NOSTUFF 1%
1/20W 10%
0201
D
1 16V
7 IN
CPU_VCCSENSE_N 1 2 RTN_B_CPUCORE 65
2 201 680PF
10%
MF
201 R7141 MF
201 X7R-1
0201
25V 330K
X7R-CERM 2 5%
1/20W XW7141
C7141 1 1 C7142 0201 MF SM
330PF 330PF 2 201 65 RTN_A_CPUGT 2 1 CPU_VCCGTSENSE_N 7
10% 10% IN
16V 2 2 16V
X7R X7R
0201 0201
R7101 R7100 C7146 1 1 C7145
PPBUS_HS_CPU 1
10 2 PPVIN_S0_CPUVR_VIN PP5V_COREVR_VCC 1
1 2 PP5V_G3S_CPUREG_MISC 330PF 330PF
87 85 73 69 67 66 49 43 51 65 66 67 69 73 74 76 83 86
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 10% 10%
5% MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 5% 16V 2 2 16V
1/20W VOLTAGE=13.05 VOLTAGE=5.355 1/20W X7R X7R
66 65 IN
CPUCORE_ISUMP MF MF 32 18 17 16 15 14 13 12 11 7 PP1V8_S5 0201 0201
201 201 83 74 73 72 70 69 53 47 42

VIN 41

VCC 42
C7151 1 1 C7101 1 C7100 1
R7163
220PF 0.22UF 1UF 100K
10% 10% 10% 5%
25V 2 25V 2 10V
X7R-CERM 2 X7R CER-X6S 1/20W
201 R7150 0402 0402 MF
2 201
66 IN
CPUCORE_ISUMN 2
499 1 CPUCORE_ISUMN_R 65
U7100 83 72 65 CPU_VR_READY
1%
ISL95828 OUT

1/20W 66 CPUCORE_FCCM 11 FCCM_B TQFN FCCM_A 24 CPUGT_FCCM 67

66 65 IN
CPUCORE_ISEN1 MF OUT OUT
201
CPUCORE_PWM1 12 CRITICAL 25 CPUGT_PWM1
R7151 C7150 66 65 OUT PWM1_B PWM1_A OUT 65 67

66 65 CPUCORE_ISEN2 3300PF 66 CPUCORE_PWM2 13 PWM2_B PWM2_A 26 CPUGT_PWM2 65 67 CPUGT_ISUMP 65 67

IN
1
1K 2 CORE_ISUMN_R 1 2
OUT
PWM3_A 27
OUT
CPU VCC GT + GTx Merged IN

NC
C7154 1 C7153 1 1%
1/20W 10% CPUCORE_ISUMP 7 ISUMP_B ISUMP_A 19 CPUGT_ISUMP
1 C7156
0.01UF 0.01UF MF 10V 66 65 IN IN 65 67
220PF
10% 10% 201 X7R-CERM 65 CPUCORE_ISUMN_R 8 ISUMN_B ISUMN_A 20 CPUGT_ISUMN_R 65
10%
10V 10V 0201 2 25V
X7R-CERM 2 X7R-CERM 2
9 21
R7154 X7R-CERM
0201 0201 66 65 CPUCORE_ISEN1 ISEN1_B ISEN1_A CPUGT_ISEN1 65 67 499 201
CPU VCC Core IN
CPUCORE_ISEN2 10 ISEN2_B ISEN2_A 22 CPUGT_ISEN2
IN
65 CPUGT_ISUMN_R 2 1 CPUGT_ISUMN IN 67

C C7152 1
66 65 IN
ISEN3_A 23
IN 65 67
1%
1/20W C
0.01UF C7155 MF CPUGT_ISEN1 IN 65 67
10% 65 COMP_B_CPUCORE 4 COMP_B COMP_A 16 COMP_A_CPUGT 65 3300PF
201
R7155
10V
X7R-CERM 2 1K CPUGT_ISEN2 65 67
5 17
2 1 GT_ISUMN_R 2 1 IN
NOSTUFF 0201 65 FB_B_CPUCORE FB_B FB_A FB_A_CPUGT 65
1%
10%
R7169 65 RTN_B_CPUCORE 6 RTN_B RTN_A 18 RTN_A_CPUGT 65
10V
X7R-CERM
1/20W
MF
51.1K 2 201
1
IMON_B_CPUCORE 2 IMON_B IMON_A 14 IMON_A_CPUGT
0201 1 C7157 1 C7158
1%
65 65
0.01UF 0.01UF
10% 10%
1/20W
MF C7162 65 NTC_B_CPUCORE 3 NTC_B NTC_A 15 NTC_A_CPUGT 65 2 10V
X7R-CERM 2 10V
X7R-CERM
201 68PF R7102 0201 0201
2 1 COMP_B_CPUCORE 65
34 100
66 OUT
CPUSA_FCCM FCCM_C VR_HOT* 46 CPU_VR_PROCHOT_L 1 2 SMC_PROCHOT_L OUT 35 42 43
5% 5%
C7161 25V
C0G 66 65 OUT
CPUSA_PWM 35 PWM_C VR_READY 47 CPU_VR_READY 65 72 83
R7103 1/20W 1 C7149
6800PF 0201 R7161 32 0
MF
201 0.01UF
9.09K 1 66 65 CPUSA_ISUMP ISUMP_C VR_ENABLE 48 CPU_VR_EN_R 1 2 ALL_SYS_PWRGD_R 18 69
10%
2 1 COMP_B_CPUCORE_L 2 IN
33 2 10V
65 CPUSA_ISUMN_R ISUMN_C 5% X7R-CERM
0201
1% 1/20W
10% 1/20W MF
10V MF 65 COMP_C_CPUSA 29 COMP_C SDA 43 CPUVR_VIDSOUT_R 0201
X7R-CERM
0201
201 PP1V_S3 5 7 9 17 18 42 69 70 83

CPU VCC SA 65 FB_C_CPUSA 30 FB_C ALERT* 44 CPUVR_VIDALERT_L_R NOSTUFF

1 1 1
65 RTN_C_CPUSA 31 RTN_C SCLK 45 CPUVR_VIDSCLK_R R7110 R7199 R7109
66 65 IN
CPUSA_ISUMP 45.3 45.3 100
28 1 1% 1% 1%
65 IMON_C_CPUSA IMON_C PSYS 1/20W 1/20W 1/20W
C7181 1 MF MF MF
220PF
10% 65 PROG1_CPUCOREVR 40 PROG1 353S00928 R7104 2 201 2 201 2 201
25V PROG2_CPUCOREVR 39 1
10 2 CPU_VIDSOUT
X7R-CERM 2 65 PROG2 BI 7
201 R7180 65 PROG3_CPUCOREVR 38 PROG3 5% NOSTUFF

THRM_PAD
CPUSA_ISUMN 499 CPUSA_ISUMN_R 37 R7105 1/20W
66 IN
2 1 65 65 PROG4_CPUCOREVR PROG4
0
MF
201 R7196
1% 65 PROG5_CPUCOREVR 36 PROG5 1 2 CPU_VIDALERT_L 7 51.1K 2
IN
B 1/20W
MF
C7180 5%
1
B
R7181 201
3300PF R7106 1/20W 1%
C7193

49
MF 1/20W
1
1K 2 SA_ISUMN_R 1 2 1
49.9 2
0201
CPU_VIDSCLK
MF
201
68PF
7
IN
65 COMP_A_CPUGT 1 2
1%
1/20W 10% NOSTUFF 1%
1/20W
10V 5%
C7182 1
MF
201 X7R-CERM
0201
R7177 MF
201 25V
C0G C7194
0.01UF 51.1K 2 R7193 0201
10%
1
PP5V_G3S_CPUREG_MISC 9.09K 1 6800PF
51 65 66 67 69 73 74 76 83 86
10V
X7R-CERM 2 1%
C7192 2 COMP_A_CPUGT_L 1 2
0201 1/20W NOSTUFF
MF 150PF 1
1%
10%
201
2 1 COMP_C_CPUSA 65
R7107 1/20W
MF 10V
X7R-CERM
12.1K 201
0201
10% 1%
25V 1/20W

R7190 C7191 X7R-CERM

0201 R7191 R7160 MF
2 201
NO_XNET_CONNECTION=1
6800PF 100K IMON_B_CPUCORE CPUCORE_PSYS R7121
100K IMON_C_CPUSA 2 1 COMP_C_CPUSA_L 2.7K 2 1 65
2 1 65 2 1
NTC_A_CPUGT 1
14K 2 NTC_A_CPUGT_RP
1% 1%
1%
1/20W
C7160 1
R7108
65
R7194
1/20W
MF C7190 10%
10V
1/20W
MF
MF
201 150PF
1 C7108 12.1K
1%
1/20W IMON_A_CPUGT 2
100K 1
201 150PF X7R-CERM 201 4700PF 1% MF
65
0201 2 1 10% 1/20W 201 1 1%
2 1 2 10V
X7R MF NO_XNET_CONNECTION=1 C7195 1/20W
MF
10% 201 2 201 150PF
10%
25V
25V
X7R-CERM
R7124 2 1
201

X7R-CERM
0201
R7173 FB_C_CPUSA 65
0201 220KOHM-3%
FB_SA_R 2
2.49K 1 NO_XNET_CONNECTION=1 0201 10%
25V
R7172 1% R7175 887 OHM PER R7120 2 X7R-CERM
CPU_VCCSASENSE_P 1
0 2
1/20W <RDAR://54002856>
NTC_B_CPUCORE 1
14K 2 NTC_B_CPUCORE_RP XW7124 0201
7 IN C7174 MF
201
R7174 R7175
65 SM
5% 2200PF 1% NTC_A_CPUGT_RN 1 2
1/20W
MF 2 1 FB_C_SA_R 2
1K 1 1
887 2 FB_C_SA_RC
1/20W
MF
0201 201 1
1% NOSTUFF 1% NO_XNET_CONNECTION=1
10% 1/20W 1/20W C7173 1
A 10V
X7R-CERM
0201
MF
201
1
R7176
330K
MF
201 560PF
10%
PROG1_CPUCOREVR 65
R7123 SYNC_MASTER= SYNC_DATE=
A
5% 50V
X7R-CERM 2 PROG2_CPUCOREVR 220KOHM-3% PAGE TITLE
XW7170
SM
1/20W
MF 0201
65

PROG3_CPUCOREVR 65
0201 VR CORE & SA IMVP CTRL
7 CPU_VCCSASENSE_N 1 2 RTN_C_CPUSA 65
2 201 PROG4_CPUCOREVR 65
2 XW7123 DRAWING NUMBER SIZE
IN
SM
PROG5_CPUCOREVR 65
NTC_B_CPUCORE_RN 051-05309 D
C7171 1 1 C7172 1
R7111 1
R7112 1
R7113 1
R7114 1
R7115
1 2
Apple Inc. REVISION
330PF 330PF 78.7K 121K 24.3K 182K 121K 5.1.0
10% 10% 1% 1% 1% 1% 1%
16V 2 2 16V 1/20W 1/20W 1/20W 1/20W 1/20W NOTICE OF PROPRIETARY PROPERTY: BRANCH
X7R X7R MF MF MF MF MF
0201 0201
2 201 2 201 2 201 2 201 2 201 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
71 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 65 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU
CRITICAL CRITICAL CRITICAL CRITICAL
83 76 74 73 69 67 66 65 51
86
PP5V_G3S_CPUREG_MISC 1
C7210 1
C7212 1
C721A 1
C721B 1 C7213 1 C7214
33UF 33UF 33UF 33UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2 16V 2 16V 2 16V 2 16V 2 25V
X6S-CERM 2 25V
X6S-CERM
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
R7215 1 C7216 NO_XNET_CONNECTION=1 CASED12-SM-1 CASED12-SM-1 CASED12-SM-1 CASED12-SM-1 0402 0402
1 PP5V_MAIN_VCORE1 2.2UF
1 2
20% CRITICAL
5%
1/16W C7217 1 2 25V
X6S-CERM R7210
MF-LF 0402 0.00075
2.2UF L7210 1%
D
402
20%
25V 0.22UH-20%-44A-0.0019OHM 1W
MF
D
X6S-CERM 2

PVCC 29
0612-1

VCC 3
0402 CPUCORE_SW1 1 2 PPVCC_CPU_PH1 2 1 PPVCC_S0_CPU 7 9 50 83 87
DIDT=TRUE PILA082D-SM 4 3
66 PVCCCORE_PH1_AGND
SWITCH_NODE=TRUE
CPUCORE_ISNS1_P OUT 50
Vout = 0.55 - 1.5V
U7210 1
R7218 1
CPUCORE_ISNS1_N OUT 50 66 IccMax = 64A
8 VIN FDMF5808A BOOT 5 CPUCORE_BOOT1 2.2 R7211 NO_XNET_CONNECTION=1 F = 750kHz
9 VIN DIDT=TRUE 5% 2.2
OMIT_TABLE SWITCH_NODE=TRUE 1/10W 1%
PHASE 7 MF-LF 1/20W
2 FCCMPQFN-COMBO-THICKSTNCL 2 603 NOSTUFF MF
66 65 CPUCORE_FCCM R7219 1 2 201
IN
SW 16 CPUCORE_ISUMN 65 66 NO_XNET_CONNECTION=1
1 PWM 0 CPUCORE_SW1_SNUB OUT
65 IN
CPUCORE_PWM1 SW 24 5% SWITCH_NODE=TRUE R7214
1/16W DIDT=TRUE NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
MF-LF 200K
353S00519 GL0 27 CPUCORE1_GL0 66 402 2 R7212 1 1
R7213 2 1 CPUCORE_ISNS2_N 50 66
30 NC 353S00831 GL1 33
DIDT=TRUE
GATE_NODE=TRUE
1 C7218 1K 200K 1%
NC NC CPUCORE_BP1 0.001UF 1% 1% 1/20W
31 NC 10% 1/20W 1/20W MF
NC GH 6 2 50V
X7R-CERM MF MF 201
DIDT=TRUE 0402 201 2 2 201

AGND
AGND

PGND
PGND
SWITCH_NODE=TRUE
CPU VCC Phase 1 DIDT=TRUE
C7219
0.22UF
1 NOSTUFF CPUCORE_ISEN1 OUT 65

4
32

12
28
SWITCH_NODE=TRUE 10%
CPUCORE1_DRVH 66
25V 2
X7R CPUCORE_ISUMP OUT 65 66
0402

XW7210
SM
DIDT=TRUE
SWITCH_NODE=TRUE
66 PVCCCORE_PH1_AGND 2 1 CPUCORE_PHASE1
PLACE_NEAR=U7210.32:2MM
87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU
83 76 74 73 69 67 66 65 51
86
PP5V_G3S_CPUREG_MISC CRITICAL CRITICAL CRITICAL
C 1
C7220 1
C7221 1
C7222 1 C7223
2.2UF
1 C7224
2.2UF
C
33UF 33UF 33UF 20% 20%
R7225 1 C7226 20%
2 16V
20%
2 16V
20%
2 16V 2 25V
X6S-CERM 2 25V
X6S-CERM
1 PP5V_MAIN_VCORE2 2.2UF POLY-TANT POLY-TANT POLY-TANT
0402 0402
1 2
20% CRITICAL CASED12-SM-1 CASED12-SM-1 CASED12-SM-1
5%
1/16W C7227 1 2 25V
X6S-CERM R7220
MF-LF 0402 0.00075
402 2.2UF L7220 1%
20% 1W
25V 0.22UH-20%-44A-0.0019OHM NO_XNET_CONNECTION=1 MF
X6S-CERM 2
PVCC 29

0612-1
VCC 3

0402 CPUCORE_SW2 1 2 PPVCC_CPU_PH2 1 2

DIDT=TRUE PILA082D-SM 3 4
SWITCH_NODE=TRUE
66 PVCCCORE_PH2_AGND CPUCORE_ISNS2_P OUT 50

CPUCORE_ISNS2_N 50 66
U7220 1
R7228 1
OUT

8 VIN FDMF5808A BOOT 5 CPUCORE_BOOT2 2.2 NOSTUFF

R7221 P2MM
SM
9 VIN DIDT=TRUE 5% 2.2 NO_XNET_CONNECTION=1 66 CPUCORE1_GL0 1
PP
OMIT_TABLE 1/10W 1% PP7210
PHASE 7 SWITCH_NODE=TRUE MF-LF 1/20W
2 FCCMPQFN-COMBO-THICKSTNCL 2 603 MF P2MM
66 65 CPUCORE_FCCM R7229 1 2 201
SM
SW 16 CPUCORE_SW2_SNUB CPUCORE_ISUMN CPUCORE2_GL0
IN 1
OUT 65 66 NO_XNET_CONNECTION=1 66 PP
CPUCORE_PWM2 1 PWM 0 SWITCH_NODE=TRUE PP7220
65 IN SW 24 5% DIDT=TRUE NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 R7224
1/16W P2MM
MF-LF 200K SM
353S00519 GL0 27 CPUCORE2_GL0
DIDT=TRUE
66 402 2 1 C7228 R7222 1 1
R7223 2 1 CPUCORE_ISNS1_N 50 66 66 CPUSA_GL0 1
PP
PP7270
30 NC 353S00831 GL1 33 GATE_NODE=TRUE 1K 200K 1%
NC NC CPUCORE_BP2 0.001UF 1% 1% 1/20W P2MM
CPU VCC Phase 2 NC
31 NC
GH 6
DIDT=TRUE
10%
2 50V
X7R-CERM
0402
1/20W
MF
201 2
1/20W
MF
2 201
MF
201 66 CPUCORE1_DRVH 1
SM
PP
PP7211
AGND
AGND

PGND
PGND

SWITCH_NODE=TRUE
NOSTUFF CPUCORE_ISEN2 65 P2MM
DIDT=TRUE
C7229 1 OUT
CPUCORE2_DRVH 1
SM
0.22UF 66 PP
PP7221
4
32

12
28

SWITCH_NODE=TRUE 10%
CPUCORE2_DRVH 66
25V 2
X7R CPUCORE_ISUMP OUT 65 66 P2MM
SM
0402 66 65 CPUCORE_FCCM 1
PP
PP7212
B XW7220
SM
DIDT=TRUE
SWITCH_NODE=TRUE P2MM B
SM
66 PVCCCORE_PH2_AGND 2 1 CPUCORE_PHASE2 66 65 CPUSA_FCCM 1
PP
PP7272
PLACE_NEAR=U7220.32:2MM P2MM
SM
87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU 66 CPUSA_DRVH 1
PP
PP7271
83 76 74 73 69 67 66 65 51
86
PP5V_G3S_CPUREG_MISC CRITICAL CRITICAL
1
C7270 1
C7271 1 C7272 1 C7273
33UF 33UF 2.2UF 2.2UF
20% 20%
R7275 20%
2 16V
20%
2 16V 2 25V 2 25V
1
1 2 PP5V_MAIN_VCCSA
1 C7276 CRITICAL POLY-TANT
CASED12-SM-1
POLY-TANT
CASED12-SM-1
X6S-CERM
0402
X6S-CERM
0402
2.2UF R7270
5% 20% OMIT_TABLE
1/16W C7277 1 2 25V 0.002
MF-LF
402 2.2UF
X6S-CERM
0402 L7270 1%
1W
20% 0.47UH-20%-17.5A-0.0047OHM CYN
VDRV 11

25V 0612
VCIN 2

X6S-CERM 2 CPUVR_SWSA 1 2 PPVCCSA_CPU_R 2 1 PPVCCSA_S0_CPU 7 9 52 83 87

0402 DIDT=TRUE PIMA052D-SM 4 3
SWITCH_NODE=TRUE
152S00389 FOOTPRINT
PER <RDAR://43666396>
54 CPUSA_ISNS_R_P Vout = 0.55 - 1.15V
PVCCCSA_AGND CPUSA_ISNS_R_N
66

U7270 NOSTUFF
54

1
1
R7277 ICCMAX = 8.5A
R7276 10
SIC532CD 1
R7278 10 1%
1/20W
F = 750kHz
6
MLP4535
CPUSA_BOOTSA 2.2 1% MF
VIN BOOT 4 5% 1/20W 2 201
OMIT_TABLE DIDT=TRUE 1/10W MF
SWITCH_NODE=TRUE MF-LF R7272 201 2 CPUSA_ISNS_P 52
CPUSA_FCCM PHASE 5
1 ZCD_EN* OUT
66 65 IN 2 603 0 CPUSA_ISNS_N 52
8 1 2 CPUSA_ISUMN 65
OUT
65 IN
CPUSA_PWM 12 PWM VSWH CPUSA_SW_SNUB NO_XNET_CONNECTION=1
OUT

R7279 1 DIDT=TRUE
SWITCH_NODE=TRUE
5%
1/20W
66 CPUSA_DRVH 3 NC 353S00525 GL 9 CPUSA_GL0 66 0 MF
DIDT=TRUE DIDT=TRUE 5% NOSTUFF 0201
SWITCH_NODE=TRUE 353S00832 GL 14 NC GATE_NODE=TRUE 1/16W R7274
A MF-LF 1 C7278 A
7 PGND
10 PGND

1K
13 CGND

402 2 0.001UF
CPU VCCSA CPUSA_BPSA
10%
2 50V
X7R-CERM
1
1%
1/20W
2 CPUSA_ISUMP
NO_XNET_CONNECTION=1
OUT 65
SYNC_MASTER=

PAGE TITLE

VR CORE & SA IMVP

SYNC_DATE=

0402 MF
201 DRAWING NUMBER SIZE
DIDT=TRUE
SWITCH_NODE=TRUE 051-05309 D
XW7270 C7279 1 Apple Inc. REVISION
SM 0.22UF
2 1 PVCCCSA_AGND 66
10% 5.1.0
25V 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
DIDT=TRUE X7R
SWITCH_NODE=TRUE 0402 THE INFORMATION CONTAINED HEREIN IS THE
PLACE_NEAR=U7270.13:2MM CPUSA_PHASESA PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
72 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 66 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU Vout = 0.55 - 1.5V

86 83 76 74 73 69 67 66 65 51 PP5V_G3S_CPUREG_MISC CRITICAL CRITICAL CRITICAL IccMax = 64A
R7416 NO_XNET_CONNECTION=1 1
C7410 1
C7411 1
C7412 1 C7413 1 C7414 F = 750kHz
1 R7410 33UF 33UF 33UF 2.2UF 2.2UF
1 2 PP5V_MAIN_VGT1 0.00075 20% 20% 20% 20% 20%
1 C7416 L7410 2 16V 2 16V 2 16V 2 25V 2 25V

PVCC 29
5% 1% POLY-TANT POLY-TANT POLY-TANT X6S-CERM X6S-CERM

VCC 3
1/16W 2.2UF 0.22UH-20%-44A-0.0019OHM 1W CASED12-SM-1 CASED12-SM-1 CASED12-SM-1 0402 0402
MF-LF 20% MF
402 C7417 1 2 25V
X6S-CERM CPUGT_SW1 1 2 PPVCCGT_CPU_PH1 2
0612-1
1 PPVCCGT_S0_CPU
2.2UF 0402 DIDT=TRUE
7 10 50 83 87
20% SWITCH_NODE=TRUE PILA082D-SM 4 3
25V
X6S-CERM 2 U7410 CPUGT_ISNS1_P 50
0402 OUT
67 PVCCCGT_PH1_AGND 8 VIN FDMF5804 BOOT 5 CPUGT_BOOT1 CPUGT_ISNS1_N 50 67
1 OUT
9 VIN DIDT=TRUE R7418 1 D
D PQFN-COMBO
OMIT_TABLE
PHASE 7
SWITCH_NODE=TRUE
5%
2.2 NOSTUFF R7411
2.2
CPUGT_FCCM 2 FCCM
67 65 IN
SW 16 R7419 1 1/10W
MF-LF
1%
1/20W
NO_XNET_CONNECTION=1

1 PWM 0 2 603 MF NO_XNET_CONNECTION=1

65 CPUGT_PWM1 SW 24 5% 2 201
IN
1/16W CPUGT_ISUMN 65 67
MF-LF CPUGT_SW1_SNUB OUT
353S00519 GL0 27 CPUGT1_GL0 67 402 2 SWITCH_NODE=TRUE R7414
30 NC DIDT=TRUE DIDT=TRUE NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
353S00831 GL1 33 NC SWITCH_NODE=TRUE 200K
NC CPUGT_BP1 R7412 1 1
R7413 2 1 CPUGT_ISNS2_N 50 67
NC
31 NC
GH 6 CPUGT1_DRVH DIDT=TRUE
SWITCH_NODE=TRUE
1 C7418 1K 200K 1%
67
0.001UF
CPU VCCGT/GTx Phase 1 DIDT=TRUE 1% 1% 1/20W

AGND
AGND

PGND
PGND
SWITCH_NODE=TRUE 10% 1/20W 1/20W MF
2 50V
X7R-CERM MF MF 201
0402 201 2 2 201
2018/07/17 NOTE: DRIVER CONNECTIONS PRELIMINARY CPUGT_ISEN1

4
32

12
28
NOSTUFF 65
C7419 1 OUT

0.22UF
XW7410
SM
10%
25V 2 CPUGT_ISUMP 65 67
DIDT=TRUE X7R OUT
67 PVCCCGT_PH1_AGND 2 1 SWITCH_NODE=TRUE 0402

PLACE_NEAR=U7410.32:2MM CPUGT_PHASE1

87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU
CRITICAL CRITICAL
R7426 PP5V_G3S_CPUREG_MISC 51 65 66 67 69 73 74 76 83 86

1 NO_XNET_CONNECTION=1 1
C7420 1
C7421 1 C7423 1 C7424 1 C7425
86 83 76 74 73 69 67 66 65 51 PP5V_G3S_CPUREG_MISC
1 2 PP5V_MAIN_VGT2 1 C7426 R7420 33UF 33UF 2.2UF 2.2UF 12PF
20% 20% 20% 20% 5%
2.2UF 0.00075

PVCC 29
5% 2 16V 2 16V 2 25V 2 25V 2 25V

VCC 3
1/16W
MF-LF
20%
2 25V
L7420 1%
1W
POLY-TANT
CASED12-SM-1
POLY-TANT
CASED12-SM-1
X6S-CERM
0402
X6S-CERM
0402
NP0-C0G
0201
C7427 0.22UH-20%-44A-0.0019OHM C
C 402
2.2UF
1 X6S-CERM
0402
CPUGT_SW2 1 2 PPVCCGT_CPU_PH2 2
MF
0612-1
1
20% DIDT=TRUE
25V SWITCH_NODE=TRUE PILA082D-SM 4 3
X6S-CERM 2 U7420
0402
8 VIN
CPUGT_ISNS2_P 50
67 PVCCCGT_PH2_AGND FDMF5804 BOOT 5 CPUGT_BOOT2 OUT

9 VIN DIDT=TRUE 1
CPUGT_ISNS2_N OUT 50 67
PQFN-COMBO
PHASE 7
SWITCH_NODE=TRUE R7428 1
R7421
CPUGT_FCCM 2 FCCM OMIT_TABLE 1 2.2 NOSTUFF
67 65 R7429 5% 2.2 NO_XNET_CONNECTION=1
IN
SW 16 1/10W 1%
1 PWM 0 MF-LF 1/20W
65 IN
CPUGT_PWM2 SW 24 5% 2 603 MF
1/16W 2 201 NO_XNET_CONNECTION=1
MF-LF CPUGT_ISUMN 65 67
353S00519 GL0 27 CPUGT2_GL0 67 402 2 CPUGT_SW2_SNUB OUT

NC
30 NC 353S00831 GL1 33 NC
DIDT=TRUE
SWITCH_NODE=TRUE CPUGT_BP2
DIDT=TRUE
SWITCH_NODE=TRUE NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 R7424
31 NC DIDT=TRUE 1 1 200K CPUGT_ISNS1_N
NC GH 6 CPUGT2_DRVH SWITCH_NODE=TRUE 1 C7428 R7422 R7423 2 1 50 67

DIDT=TRUE 0.001UF 1K 200K 1%

CPU VCCGT/GTx Phase 2
AGND
AGND

PGND
PGND

SWITCH_NODE=TRUE 1% 1% 1/20W
10% 1/20W 1/20W MF
2 50V MF MF 201
2018/07/17 NOTE: DRIVER CONNECTIONS PRELIMINARY C7429 1 X7R-CERM
0402 201 2 2 201
4
32

12
28

0.22UF NOSTUFF CPUGT_ISEN2 OUT 65

10%
DIDT=TRUE 25V 2
XW7420
SM
SWITCH_NODE=TRUE X7R
0402
CPUGT_PHASE2 CPUGT_ISUMP 65 67
67 PVCCCGT_PH2_AGND 2 1 OUT

PLACE_NEAR=U7420.32:2MM

B B
87 85 73 69 67 66 65 49 43 PPBUS_HS_CPU
CRITICAL CRITICAL CRITICAL
1 1 1
C7430 C7431 C7432
33UF 33UF 33UF
20% 20% 20%
2 16V 2 16V 2 16V
POLY-TANT POLY-TANT POLY-TANT
CASED12-SM-1 CASED12-SM-1 CASED12-SM-1

A CPUGT1_GL0 1
P2MM
SM SYNC_MASTER= SYNC_DATE=
A
67 PP
PP7433 PAGE TITLE

P2MM
SM
VR GT & GTX IMVP
67 65 CPUGT_FCCM 1
PP DRAWING NUMBER SIZE
PP7412
051-05309 D
P2MM Apple Inc. REVISION
SM
67 CPUGT1_DRVH 1
PP
PP7411 5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
P2MM THE INFORMATION CONTAINED HEREIN IS THE
SM PROPRIETARY PROPERTY OF APPLE INC.
67 CPUGT2_GL0 1
PP THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PP7430 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
74 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 67 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
5V G3S 3V3 G3H
Vout = 5.1V Vout = 3.3V
IOUT MAX = 7.997A Iout Max = 10.9A
F = 500 KHZ F = 500 KHZ

PP5V_G3S 28 29 46 50 51 52 54 55 68 75
83 86 86 83 74 68 63 54 52 PP3V3_G3H
CRITICAL CRITICAL PPVIN_G3H_P3V3G3H
86 49 CRITICAL CRITICAL
1 C7671 1 C7670 C7690 1 C7691 1
2.2UF 2.2UF
20% 20% 2.2UF 2.2UF
2 25V
X6S-CERM 2 25V
X6S-CERM PP5V_G3S
20%
25V
20%
25V
D 0402 0402 28 29 46 50 51 52 54 55 68 75
83 86 X6S-CERM 2
0402
X6S-CERM 2
0402 D

CRITICAL CRITICAL CRITICAL

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1 1
1
C7675 1
C7676 1 C7650 1 C7680 1 C7681 1
C7685 1
C7686 1
C7687 C7695 C7696 C7613 1
PPVIN_G3H_P5VG3S 49 86
2.2UF 2.2UF 2.2UF 150UF 150UF 150UF
220UF-25MOHM 220UF-25MOHM VOUT = 5V 20% 20% 20%
33UF 33UF 33UF 20% 20% 20%
20% 20% CRITICAL CRITICAL CRITICAL CRITICAL 20% 20% 20% 6.3V 2 6.3V 2 6.3V 2
2 6.3V 2 6.3V 100MA MAX OUTPUT 2 25V 2 25V 2 25V 2 16V 2 16V 2 16V TANT TANT TANT
POLY-TANT
CASE-B2-SM
POLY-TANT
CASE-B2-SM
1
C7665 1
C7666 1 C7660 1 C7661 X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
POLY-TANT
CASED12-SM-1
POLY-TANT
CASED12-SM-1
POLY-TANT
CASED12-SM-1
CASE-B-SM CASE-B-SM CASE-B-SM
33UF 33UF 2.2UF 2.2UF PP5V_G3H_LDO
20% 20% 20% 20%
2 16V 2 16V 2 25V
X6S-CERM 2 25V
X6S-CERM CRITICAL
POLY-TANT POLY-TANT
CASED12-SM-1 CASED12-SM-1 0402 0402 1 C7651 CRITICAL CRITICAL CRITICAL
CRITICAL 10UF C7611 1
C7697 1
C7612 1
20%
1
C7677 2 16V
X6S-CERM
150UF 150UF 150UF
20% 20% 20%
220UF-25MOHM 0603 6.3V 2 6.3V 2 6.3V 2
20% TANT TANT TANT
2 6.3V CASE-B-SM CASE-B-SM CASE-B-SM
POLY-TANT
CASE-B2-SM
P5VP3V3_VREG3
P5VP3V3_VREF2
AUDIBLE SKIPPING INAUDIBLE SKIPPING
NOSTUFF
1 1 CRITICAL CRITICAL
R7651 R7650

23

29

22

13
0 0 C7652 1 1 C7653

2
CRITICAL P5VG3S_VBST_R 5% 5% 0.22UF 2.2UF CRITICAL
MIN_LINE_WIDTH=0.2500

V5SW

VIN

VREG5

VREG3

VREF2
1/20W 1/20W
Q7660 MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
MF MF 10%
16V
20%
2 25V
P3V3G3H_VBST_R
MIN_LINE_WIDTH=0.2500
Q7680
CSD58873Q3D DIDT=TRUE
0201 2 2 0201 CERM 2 X6S-CERM MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000 CSD58873Q3D
Q3D 402 0402 DIDT=TRUE SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.2000 Q3D
MIN_LINE_WIDTH=0.6000 CRITICAL GATE_NODE=TRUE
CRITICAL 1 VIN MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE 1 C7669 R7665 1 P5VP3V3_SKIPSEL 6 SKIPSEL1
CRITICAL
1
R7685 C7689
1 DIDT=TRUE VIN 1 CRITICAL
C DIDT=TRUE R7666 0 19 SKIPSEL2 0 0.1UF
R7686 C
PLACE_NEAR=C7675.1:5.3MM

L7670 0.1UF 5% DIDT=TRUE U7650 5% 10% L7690

PLACE_NEAR=L7690.2:3MM
PLACE_NEAR=L7690.1:3MM
1.5UH-20%-12.5A-0.017OHM TG 3 1 10% 1/16W SWITCH_NODE=TRUE 14 OCSEL EN 12 P5VXX_EN 68 1/16W 25V
X7R-CERM-1 2 1 3 TG 1.0UH-20%-14A-0.0107OHM
P5VG3S_DRVH 2 1 2 25V MIN_NECK_WIDTH=0.2000 QFN 2 1 P3V3G3H_DRVH

PLACE_NEAR=C7695.1:6.6MM
X7R-CERM-1 MF-LF MF-LF 0402
6 402 2 MIN_LINE_WIDTH=0.2500 2 402 6

TPS51980B
1 2 P5VG3S_VSW 5% 0402 CRITICAL 5% P3V3G3H_VSW 2 1
PIMB062D-SM 7 VSW TGR 4 1/16W P5VG3S_VBST 31 VBST1 VBST2 26 P3V3G3H_VBST 1/16W 4 TGR VSW 7 PIMB062D-SM
MF-LF DIDT=TRUE SWITCH_NODE=TRUE MF-LF
152S00268 8 402
P5VG3S_DRVH_R P3V3G3H_DRVH_R
402 8
1 DRVH1 DRVH2 24 152S0269
MIN_LINE_WIDTH=0.6000 GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
P5VG3S_SW 32 SW1 P3V3G3H_SW MIN_NECK_WIDTH=0.2000 NOSTUFF
NOSTUFF SW2 25
1
R7674 BG 5
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 5 BG
R76941 NO_XNET_CONNECTION=1
P5VG3S_DRVL P5VG3S_DRVL_R 30 DRVL1 DRVL2 27 P3V3G3H_DRVL_R P3V3G3H_DRVL 2.2 NO_XNET_CONNECTION=1
PGND

PGND
PLACE_NEAR=L7670.1:3MM

2.2 MIN_LINE_WIDTH=0.6000 GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000 5%

PLACE_NEAR=L7670.2:3MM

5%
1/10W R7664 MIN_NECK_WIDTH=0.2000
P5VG3S_CSP1 7 CSP1 CSP2 18 P3V3G3H_CSP2 MIN_NECK_WIDTH=0.2000 1/10W
MF-LF
2 2
2 MF-LF 0 DIDT=TRUE DIDT=TRUE R7684 603 2 XW7690 XW7691
376S1038 2 1 8 CSN1 353S01936 CSN2 17 376S1038
9

9
2 603 0 SM SM
XW7675 P5VG3S_SNUBR 5% 2 1 2
SM MIN_LINE_WIDTH=0.1160 1/16W CRITICAL 11 MODE RF 3 P3V3G3H_RF CRITICAL P3V3G3H_SNUBR 1 1
1
MIN_NECK_WIDTH=0.0600
DIDT=TRUE
DIDT=TRUE
GATE_NODE=TRUE
MF-LF
402 NO_XNET_CONNECTION=1 P5VG3S_VFB1 9 VFB1 VFB2 16 P3V3G3H_VFB2 NO_XNET_CONNECTION=1
5%
1/16W
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 XW7695
SM
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 C7673 P5VG3S_COMP1 10 COMP1 COMP2 15 P3V3G3H_COMP2 C7693 MF-LF
402
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE
NOSTUFF 0.1UF 1
P5VG3S_VFB1_R 1 C7674 0.1UF
68 P5VG3S_EN_DLY 4 EN1 EN2 21 TP_P3V3G3H_EN2 R76551 1 2 NOSTUFF
0.001UF
1 2
P5VG3S_PGOOD 5 PGOOD1 PGOOD2 20 P3V3MAIN_PGOOD 200K
1%
C7694 1
P3V3G3H_VFB2_R
2 2 10% 83 72 68 OUT OUT 68 72
1/20W 10% 0.001UF
2 50V 10%
GND THRM_PAD MF 25V 10%
XW7671 XW7670 CERM
402
25V
X6S-CERM 201 2 X6S-CERM
0201
50V
CERM 2 R76911
SM SM 0201 402 10

28
NOSTUFF

33
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NOSTUFF 1 1 1 R7693 5%
1
R7671
1 1 R7673 1
R7676 R7675 R7695 R7696 1.37K 2 1/20W
MF
1.2K 5.49K 5.49K 10K 1 201 2
10 1 2 10K 1% 1% 1%
1%
5% 1% 1/20W 1/20W 1/20W
1/20W 1% 1/20W MF MF MF 1/20W P3V3G3H_VFB2_R2
MF 1/20W MF 201 2 MF
MF 2 201 201 2
201
2 201 2 201
R7672
201
NO_XNET_CONNECTION=1 P5VG3S_COMP1_R P3V3G3H_COMP2_R NO_XNET_CONNECTION=1 R76971
P5VG3S_VFB1_R2 DIDT=TRUE 3.09K
P5VG3S_CS1_L_P 2
4.42K 1 CRITICAL CRITICAL CRITICAL CRITICAL 1%
1/20W
B 1
1 C7678 1 C7679 C7699 1 1 C7698 R7692 MF
B
R7677 1%
1/20W 330PF 4700PF 2700PF 270PF 3.83K 2 DIDT=TRUE
201 2
6.34K 10% 10% 10% 10% 1 P3V3G3H_CS2_L_P

PLACE_NEAR=U7650.28:1MM
MF
1% 201 2 16V
X7R 2 10V
X7R
16V 2
X7R 2 16V
X7R-CERM
1/20W NO_XNET_CONNECTION=1 1%
MF 0201 201 0201 0201-1 1/20W P3V3G3H_VFB2_RR
(P5VP3V3_VREF2) (P5VP3V3_VREF2) MF
2 201 201
P5VG3S_CS1_L_N NO_XNET_CONNECTION=1 CRITICAL
P3V3G3H_CS2_L_N
P5VG3S_VFB1_RR
CRITICAL R76981
1 105K
R7678 0.1%
1/20W
34.8K MF
0.1% 0201-1 2
1/20W
MF
2 0201-1
CRITICAL
2 R76991
CRITICAL XW7650 47K
1 SM 0.1%
R7679 1/20W
MF
10K 1 0201 2
0.1%
1/20W GND_5V3V3_AGND
MF MIN_LINE_WIDTH=0.2000
2 0201-1 MIN_NECK_WIDTH=0.1500

86 83 74 68 63 54 52 PP3V3_G3H
58 57 55 51 48 47 45 44 43 18 PP1V8_G3S R7660
83 76 74 62 61 60 59 BYPASS=U7610::5mm
3.3K
1 83 72 IN
PMU_PVDDMAIN_EN 1 2 P5VXX_EN 68 C7610 1
R7600 5% 0.1UF
10%
100K 1/20W
MF 10V
5% 1 1 C7664 X5R-CERM 2
1/20W
MF R7661 201
1000PF
0201
A 2 201 47K
5% 10% SYNC_MASTER= SYNC_DATE= A
1/20W 2 16V U7610
P5VG3S_PGOOD X7R-1 PAGE TITLE
68 72 83 MF
201 2 0201
R7613 74AUP1T97 VR 5V, 3V3

5
0 SOT891
83 72 P5VG3S_EN 1 2 P5VG3S_EN_R 1 4 P5VG3S_EN_DLY 68 DRAWING NUMBER SIZE
86 83 74 68 63 54 52 PP3V3_G3H IN
5% 051-05309 D

6
1/20W R76101 1
R7611 Apple Inc.

3
MF REVISION

2
1 47K 47K
R7601 0201
5% 5% 5.1.0
100K 1/20W 1/20W
5% MF MF NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/20W 201 2 2 201
MF THE INFORMATION CONTAINED HEREIN IS THE
2 201 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
P3V3MAIN_PGOOD 68 72
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
76 OF 500
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=PLATFORM POWER IV ALL RIGHTS RESERVED 68 OF 98
8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1

1V EDRAM & EOPIO

86 83 76 74 73 67 66 65 51 PP5V_G3S_CPUREG_MISC C7744
0.1UF
R7744 1 1
R7747 PVCCEDRAM_BOOT_RC 1 2
D 2.2
5% 5%
2.2 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
D
1/20W 1/20W DIDT=TRUE 20%
MF MF SWITCH_NODE=TRUE 16V
201 2 2 201
X6S-CERM
0201
PPBUS_HS_CPU 43 49 65 66 67 73 85 87

PP5V_G3S_EDRAMPVCC CRITICAL
R7750 1 C7751 1 C7750 1
C7752
CPU_VCCEOPIOSENSE_P 1
10 2 CPU_VCCEOPIOSENSE_R
1 C7743 2.2UF 2.2UF 33UF
7 IN 10UF 20% 20% 20%
5% 20% 2 25V 2 25V 2 16V
1/20W 2 10V PVCCEDRAM_DRVH_R X6S-CERM X6S-CERM POLY-TANT
MF
201
PP5V_G3S_EDRAMVCC X5R-CERM
0402-7 R7745 1 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000
0402 0402 CASED12-SM-1
2.2 DIDT=TRUE SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1000 5%
XW7702
SM
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1/20W
MF
1
R7746

13

14
201 2 1
7 IN
CPU_VCCEOPIOSENSE_N 1 2 CPU_VCCEOPIOSENSE_XW
NO_XNET_CONNECTION=1
1 C7762 VCC PVCC
5%
1/20W
Q7702
PLACE_NEAR=R7750.1:1mm 2.2UF PVCCEDRAM_VBST MF CSD58873Q3D
R7760 1 1
R7761 20%
2 25V
X6S-CERM U7710 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 2 201 Q3D
4.99K 4.99K 0402 DIDT=TRUE VIN 1
NO_XNET_CONNECTION=1 1% 0.1% ISL95870HRUZ SWITCH_NODE=TRUE CRITICAL
1/20W 1/20W
MF
201 2
MF
PVCCEDRAMS0_EN_FILT_BUF 3 EN
UTQFN
BOOT 12
PVCCEDRAM_DRVH
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000 CRITICAL R7702 Vout = 1V
2 0201 69
MIN_NECK_WIDTH=0.2000 3 TG DIDT=TRUE 0.002 6.2A MAX OUTPUT
<Ra> <Ra> PVCCEDRAMS0_FB 6 FB
-TR5720
UGATE 11
SWITCH_NODE=TRUE
DIDT=TRUE 6 SWITCH_NODE=TRUE L7702 1%
1/2W F = 600 KHZ
0.56UH-20%-16A-0.0072OHM MF
Vout = 0.5V * (1 + Ra / Rb) PVCCEDRAM_LL 4 TGR VSW 7 0306
PVCCEDRAMS0_SREF 4 SREF PHASE 10 MIN_LINE_WIDTH=0.6000 PVCCEDRAM_PHASE 1 2 PPVCCEDRAM_S0_REG_R 1 2 PPVCCEDRAM_S0_CPU 7 9 83 86
MIN_NECK_WIDTH=0.1000 8 MIN_LINE_WIDTH=0.2000
SWITCH_NODE=TRUE PILA052D-SM MIN_NECK_WIDTH=0.1000 3 4
PVCCEDRAMS0_VO 8 VO LGATE 15 DIDT=TRUE NOSTUFF
1
PVCCEDRAMS0_OCSET 7 OCSET 353S01077 5 BG
R7716
PVCCEDRAM_DRVL_R 2.2

PGND
9 MIN_LINE_WIDTH=0.6000 5%
69 PVCCEOPIO_EDRAM_PGOOD PGOOD CRITICAL MIN_NECK_WIDTH=0.2000 1/10W
DIDT=TRUE MF-LF
2 GATE_NODE=TRUE 2 603
PVCCEDRAMS0_RTN

9
RTN
5 PVCCEDRAM_LL_SNUB
PVCCEDRAMS0_FSEL FSEL R7748 DIDT=TRUE
C R7762 1 1
R7763 C7770 GND PGND 1 SWITCH_NODE=TRUE
CRITICAL CRITICAL CRITICAL C
4.99K 4.99K PVCCEDRAM_DRVL 1 2 PVCCEDRAMS0_CS_P
3300PF 1
R7764 1 C7774 1 C7775 1
C7765

16
1% 0.1%
1/20W 1/20W 1 2 MIN_NECK_WIDTH=0.1300 5% NOSTUFF PVCCEDRAMS0_CS_N 10UF 10UF 220UF
MF MF 100K MIN_LINE_WIDTH=0.6000 1/16W NO_XNET_CONNECTION=1
201 2 2 0201 1% DIDT=TRUE MF-LF C7720 1
1
20%
2 4V
20%
2 4V
20%
<Rb> <Rb> 5.0%
50V
1/20W
MF
GATE_NODE=TRUE 402
0.001UF
10%
R7742 R7772 1 1
R7773 X6S
0402
X6S
0402
2 2V
ELEC
CERM 2 201 50V 3.83K SM
0603 X7R-CERM 2 1% 10 10 128S00041
0402 1/20W 1% 1%
MF 1/20W 1/20W
C7760 1 1 C7761 1 C7763 2 201 MF
201 2
MF
10PF 10PF 270PF 2 201
5% 5% 5% C7742 ISNS_CPUEDRAM_N
50V 2
C0G 2 50V
C0G 2 50V
C0G XW7701
SM
470PF OUT 52 54

0201 0201 0402 1 2

PVCCEDRAMS0_AGND 1 2 ISNS_CPUEDRAM_P OUT 52 54
MIN_LINE_WIDTH=0.6000 10% NO_XNET_CONNECTION=1
MIN_NECK_WIDTH=0.2000 PLACE_NEAR=U7710.1:1mm
16V 1
X5R-X7R-CERM
0201
R7743
(PCHVCCIOS0_OCSET) 3.83K
NO_XNET_CONNECTION=1 1%
1/20W
MF
2 201

47 43 42 18 14 13 12 11 7 5 4
89 83 74 73 71 69
PP3V3_S5
1 C7776 PP3V3_S5
0.1UF 47 43 42 18 14 13 12 11 7 5 4
89 83 74 73 71 69
10%
2 6.3V
CERM-X5R
1 C7777 U7712 U7712
0201 0.1UF
U7711 10% 74AUP2G17FZ4-55-COMBO 74AUP2G17FZ4-55-COMBO
74AUP1T97GM 2 6.3V
CERM-X5R X2-DFN1410 X2-DFN1410

5
5

0201
B 69 PM_OPC_ZVM_L 6
SOT886
R7758
3.92K 1
B
4 PVCCEDRAMS0_EN 2 PVCCEDRAMS0_EN_R 1 6 PVCCEDRAMS0_EN_FILT 3 4 PVCCEDRAMS0_EN_FILT_BUF 69

69 65 18 ALL_SYS_PWRGD_R 3 NOSTUFF 201 MF 1% 1/20W

1
1 C7778 1
R7766
R7765 330PF
1
2

47K
EDRAM EN BYPASS
2

2
100K 5%
5% 2 25V
C0G
C7779 5%
1/20W
1/20W 0201 100PF MF
MF 1 2 2 201 NOSTUFF
201 2

5% 25V C0G 0201

R7759
ALL_SYS_PWRGD_R 2
0 1 PVCCEDRAMS0_EN_FILT_BUF
69 65 18 69

0201 MF 5% 1/20W

LEVEL SHIFT
83 70 65 42 18 17 9 7 5 PP1V_S3
PP1V8_S5 7 11 12 13 14 15 16 17 18 32 42
47 53 65 69 70 72 73 74 83

32 18 17 16 15 14 13 12 11 7 PP1V8_S5 C7790 1
1
83 74 73 72 70 69 65 53 47 42
0.1UF R7792

6
1
R7752 10%
10V VCC 100K
100K X5R-CERM 2 5%
5%
1/20W 0201 U7790 1/20W
MF
MF 74AUP1G07GF 2 201
201 2 SOT891
69 PVCCEOPIO_EDRAM_PGOOD 5 IN
CPU_ZVM_L 2 A Y 4 PM_OPC_ZVM_L 69
(OD)
SLG5AP031 EN:
ZVM is CMOS DC Output: 1 NC NC 5
NC NC V_IL Max = 1V
V_OL Max = Vcc * 0.1V GND V_IH Min = 2V
V_OH Min = Vcc * 0.9V

3
A Vcc referred to in these specs refers to VccST/IO
SYNC_MASTER= SYNC_DATE=
A
PAGE TITLE

VR EOPIO EDRAM
DRAWING NUMBER SIZE

051-05309 D
Apple Inc. REVISION

5.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
77 OF 500
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 69 OF 98

8 7 6 5 www.haojiyoubbs.com 4 3 2 1
QQ微信：181806465
 8 7 6 5 4 3 2 1
Note : Design based on Calpe ERS - D2449-A0-110-00_0v3.pdf (Radar# 24696002) CRITICAL
System Block Diagram - T290 Power System Architecture .v9 OMIT_TABLE Vout = 0.625V - 1.06V
Optimize components for individual projects based on EDP(A) CRITICAL Iout_Max = 13.4A
Buck 0, 2, 5, 7, 8, 9 and 10 have option for Remote Sense. U7800 1UH-20%-3.8A-0.055OHM F = 2MHz & 4MHz
PP3V3_G3H_PMU_VDDMAIN P6 VDD_MAIN_E D2449A0P0FUAVAE2 C3 84 PVDDCPUAWAKE_SW0 1 2 L7806 PPVDDCPU_AWAKE
71 52 38 43 83 86
86 WLCSP SWITCH_NODE=TRUE
E10 VDD_MAIN_N SYM 2 OF 4 BUCK0_LX0 C2 MIN_NECK_WIDTH=0.2000 2016-COMBO
1 C7801 1 C7802 1 C7803 1 C7804 1 C7805 1 C7806 1 C7807 P10 VDD_MAIN_S C1 MIN_LINE_WIDTH=0.1750
DIDT=TRUE
1 C7811 1 C7812 1 C7813 1 C7821 1 C7822 1 C7823
10UF 10UF 10UF 10UF 10UF 10UF 10UF Resistor Divider from PBUS 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% K14 VDD_MAIN_W 20% 20% 20% 20% 20% 20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402 0402 0402 0402 0402 0402 0402 PMU_VDD_HI K13 VDD_HI CRITICAL 0402 0402 0402 0402 0402 0402
72 IN 0.22UH-20%-6.7A-0.023OHM
83 70 PP1V8_SLPS2R_PMUVDDGPIO J11 VDD_GPIO E3 84 PVDDCPUAWAKE_SW1 1 2 L7807
E2 SWITCH_NODE=TRUE PINA20121T-SM
MIN_LINE_WIDTH=0.2000 D3 BUCK0_LX1 MIN_NECK_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.1750
1 C7808 1 C7809 1 C7810 1 C7891 1 C7895 1 C78A3 1 C78E2 VOLTAGE=1.89 1 C7800 D2
E1 DIDT=TRUE 1 C7824 1 C7825 1 C7826 1 C7827 1 C7828 D
D 10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20% 10%
0.1UF
D1 VDD_BUCK0_01 20UF
20%
20UF
20%
20UF
20%
20UF
20%
20UF
20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
X6S CRITICAL 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0201 G1 0.22UH-20%-6.7A-0.023OHM 0402 0402 0402 0402 0402
G2 F1 84 PVDDCPUAWAKE_SW2 1 2 L7808
VDD_BUCK0_23 SWITCH_NODE=TRUE
G3 F2 MIN_NECK_WIDTH=0.2000 PINA20121T-SM
BUCK0_LX2 MIN_LINE_WIDTH=0.1750
F3 DIDT=TRUE
1 C7892 1 C7893 1 C7894 1 C78A0 1 C78A1 1 C78A2 1 C78CA 1 C78A4 1 C78A5 P2
VDD_BUCK16
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF P1
20% 20% 20% 20% 20% 20% 20% 20% 20% CRITICAL
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V L1
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM 0.22UH-20%-6.7A-0.023OHM
0201 0201 0201 0201 0201 0201 0201 0201 0201 L2
VDD_BUCK2 H1 84 PVDDCPUAWAKE_SW3 1 2 L7809
PLACE_SIDE=BOTTOM L3 SWITCH_NODE=TRUE

BUCK INPUT
H2 MIN_NECK_WIDTH=0.2000 PINA20121T-SM
C18 BUCK0_LX3 MIN_LINE_WIDTH=0.1750
H3 DIDT=TRUE
C17 VDD_BUCK3 PLACE_NEAR=L7806.2:5MM
1 C78A6 1 C78A7 1 C78A8 1 C78A9 1 C78B0 1 C78B1 1 C78E1 1 C78E3 1 C78E4 C16 0
1UF
20%
1UF
20%
1UF
20%
1UF
20%
1UF
20%
1UF
20%
1UF
20%
1UF
20% 20%
1UF
A7 BUCK0_FB G5 PVDDCPUAWAKE_FB 1 2 R7806
0201 5% MF 1/20W
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM B7 Vout = 0.8V - 1.06V
0201 0201 0201 0201 0201 0201 0201 0201 0201 IN 43

PLACE_SIDE=BOTTOM C7 VDD_BUCK4 CRITICAL Iout_Max = 1A

1.0UH-20%-2.6A-0.095OHM F = 3MHz
A11
B11 BUCK1_LX0 N2 84 PVDDCPUSRAMAWAKE_SW0
SWITCH_NODE=TRUE
1 2 L7810 PPVDDCPUSRAM_AWAKE 38 83 86

VDD_BUCK5 BUCK1_LX0 N1 MIN_NECK_WIDTH=0.2000 0805-COMBO

1 C78C2 1 C78C3 1 C78C4 1 C78C5 1 C78C6 1 C78C7 1 C78C8 1 C78C9 1 C78CB 1 C78CC C11 MIN_LINE_WIDTH=0.1750
DIDT=TRUE
PLACE_NEAR=L7810.2:5MM 1 C7829 1 C7830
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF F17 0 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
F18 BUCK1_FB P5 PVDDCPUSRAMAWAKE_FB 1 2 R7811 20% 20%
2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM 0201 5% MF 1/20W 2 4V
X6S 2 4V
X6S
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 G16 VDD_BUCK7 0402-1 0402-1 Vout = 0.82V
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM K16 CRITICAL Iout_Max = 6A
1UH-20%-4.7A-0.04OHM F = 3MHz
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM K17 VDD_BUCK8
VOUT = 0.7-1 V K18
K1 84 P0V8SLPDDR_SW0
SWITCH_NODE=TRUE
1 2 L7811 PP0V82_SLPDDR 38 43 83 86
K2 MIN_NECK_WIDTH=0.2000 2520
IOUT_MAX = 4 A BUCK2_LX0 MIN_LINE_WIDTH=0.1750 1 C7833 1 C7834 1 C7835 1 C7836 1 C7837 1 C7838 C
C F = 3MHz
N18
N17
K3 DIDT=TRUE 20UF
20%
20UF
20%
20UF
20%
20UF
20%
20UF
20%
20UF
20%
86 83 54 11 7 PPVPCORE_S5 VDD_BUCK910 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V
N16 CRITICAL X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM
0402 0402 0402 0402 0402 0402
1 C7860 1 C7861 1 C7862 1 C7863 1 C7864 1 C7865 1 C7889 1 C7890 0.47UH-20%-4.8A-0.034OHM
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF M1 84 P0V8SLPDDR_SW1 1 2 L7812
20% 20% 20% 20% 20% 20% 20% 20% R2 SWITCH_NODE=TRUE
2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V NC M2 MIN_NECK_WIDTH=0.2000 0806-COMBO
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM R1 BUCK6_LX0 BUCK2_LX1 MIN_LINE_WIDTH=0.1750
0402 0402 0402 0402 0402 0402 0402 0402 NC M3 DIDT=TRUE PLACE_NEAR=L7812.2:5MM 1 C7814 1 C7815 1 C7831 1 C7832
NOSTUFF 20UF 20UF 20UF 20UF
R7 0 20% 20% 20% 20%
BUCK6_IN
BUCK2_FB L5 P0V8SLPDDR_FB 1 2 R7812 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0201 5% MF 1/20W 0402 0402 0402 0402
1 C7866 1 C7867 1 C7868 1 C7869 1 C7870 1 C7871 CRITICAL R5 BUCK6_FB 43
Vout = 1.8V
NC IN
CRITICAL Iout_Max = 2.5A
20UF 20UF 20UF 20UF 20UF 20UF 0.47UH-20%-4.8A-0.034OHM
20% 20% 20% 20% 20% 20% 1UH-20%-3.8A-0.055OHM F = 3MHz
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM L7819 1 84 2 PVPCORES5_SW0
MIN_LINE_WIDTH=0.6000 84 D18 P1V8SLPS2R_SW0 1 2 L7813 PP1V8_SLPS2R 72 74 81 83 86 89
27 28 29 34 40 42 43
0402 0402 0402 0402 0402 0402 0806-COMBO MIN_NECK_WIDTH=0.1000 SWITCH_NODE=TRUE 44 47 60 63 64 70 71
SWITCH_NODE=TRUE D17 MIN_NECK_WIDTH=0.2000 2016-COMBO
CRITICAL
DIDT=TRUE E17
BUCK3_LX0
D16 MIN_LINE_WIDTH=0.1750
DIDT=TRUE
1 C7839 1 C7840 1 C7841 1 C7842 1 C7843 1 C7844 1 C7845
0.47UH-20%-4.8A-0.034OHM PLACE_NEAR=L7813.2:5MM 20UF 20UF 20UF 20UF 20UF 20UF 20UF
E18 BUCK7_LX0 20% 20% 20% 20% 20% 20% 20%
0 R7813 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V
L7820 1 84 2 PVPCORES5_SW1
MIN_LINE_WIDTH=0.6000
BUCK3_FB D14 P1V8SLPS2R_FB
0201 5%
1 2
MF 1/20W
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
VOUT = 1.05 V PLACE_NEAR=L7819.1:6MM
0806-COMBO MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
IOUT_MAX = 6 A DIDT=TRUE R9 PP1V8_SLPS2R 27 28 29 34 40 42 43 44 47 60
NOSTUFF G17 T10
63 64 70 71 72 74 81 83 86 89
F = 3MHz R7819 1
0 2 PVPCORES5_FB_P
86 83 73 70 54 16 11 7 PP1V_PRIM 0201 5% MF 1/20W G18 BUCK7_LX1 T9
7 BUCK3_IN U10
1 C78D0 1 C78D1 1 C78D2 1 C78D3 1 C78D4 1 C78D5 PLACE_NEAR=U7800.G15:6MM IN
F15 BUCK7_RTP U9
20UF 20UF 20UF 20UF 20UF 20UF NOSTUFF
20% 20% 20% 20% 20% 20% 0 V10
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
R7821 1 2 PVPCORES5_FB_N G15 BUCK7_RTN V9
0402 0402 0402 0402 0402 0402 0201 5% MF 1/20W
CRITICAL
Vout = 1.1V
CRITICAL
7 IN Iout_Max = 4A
1UH-20%-3.8A-0.055OHM F = 3MHz
B 0.47UH-20%-4.8A-0.034OHM L16
A8 84 P1V1SLPS2R_SW0 1 2 L7814 PP1V1_SLPS2R
B
1 C7898 1 C7872 1 C7873 1 C7874 1 C7875 1 C7876 L7821 1 2 P1VPRIM_SW0
MIN_LINE_WIDTH=0.6000
L17
BUCK8_LX0 BUCK4_LX0 B8 SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000 2016-COMBO
39 40 71 83 86

20UF 20UF 20UF 20UF 20UF 20UF 0806-COMBO MIN_NECK_WIDTH=0.1000

SWITCH_NODE=TRUE
L18 MIN_LINE_WIDTH=0.1750
DIDT=TRUE
1 C7846 1 C7847 1 C7848 1 C7849 1 C7850 1 C7851
20% 20% 20% 20% 20% 20% DIDT=TRUE 20UF 20UF 20UF 20UF 20UF 20UF
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM CRITICAL 20% 20% 20% 20% 20% 20%
0402 0402 0402 0402 0402 0402 CRITICAL 0.47UH-20%-4.8A-0.034OHM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0.47UH-20%-4.8A-0.034OHM 0402 0402 0402 0402 0402 0402

L7822 1 84 2 P1VPRIM_SW1 J16

A6 84 P1V1SLPS2R_SW1
SWITCH_NODE=TRUE
1 2 L7815
MIN_LINE_WIDTH=0.6000 BUCK4_LX1 B6 MIN_NECK_WIDTH=0.2000 0806-COMBO
0806-COMBO MIN_NECK_WIDTH=0.1000 J17 MIN_LINE_WIDTH=0.1750 PLACE_NEAR=L7815.2:5MM
1 C7899 1 C7877 1 C7878 1 C7879 1 C7880 1 C7881 SWITCH_NODE=TRUE J18
BUCK8_LX1 DIDT=TRUE
0
1 C7816 1 C7817
20UF 20UF 20UF 20UF 20UF 20UF
PLACE_NEAR=L7822.1:5MM DIDT=TRUE
BUCK4_FB D7 P1V1SLPS2R_FB 1 2 R7814 20UF
20%
20UF
20%
NOSTUFF 0201 5% MF 1/20W
20% 20% 20% 20% 20% 20%
R7820 0 L14 2 2.5V 2 2.5V Vout = 0.9V
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
1 2 P1VPRIM_FB BUCK8_FB P8
X6S-CERM
0402
X6S-CERM
0402
0402 0402 0402 0402 0402 0402 0201 5% MF 1/20W BUCK4_IN
CRITICAL
Iout_Max = 4A
7 IN F = 3MHz
BUCK5_LX0
84 A10 P0V9SLPDDR_SW0
MIN_LINE_WIDTH=0.1750
1 2 L7816 PP0V9_SLPDDR 39 43 83 86

VOUT = 0.9 V R7823 should be stuffed when Buck9 is unused B10 MIN_NECK_WIDTH=0.2000 2016-COMBO
IOUT_MAX = 3 A 86 83 73 70 54 16 11 7 PP1V_PRIM R12 SWITCH_NODE=TRUE
DIDT=TRUE 1UH-20%-3.8A-0.055OHM 1 C7852 1 C7853 1 C7854 1 C7855 1 C7856 1 C7818 1 C7819
T12 20UF 20UF 20UF 20UF 20UF 20UF 20UF
F = 3MHz CRITICAL U12 BUCK8_IN CRITICAL 20%
2 2.5V
20%
2 2.5V
20%
2 2.5V
20%
2 2.5V
20%
2 2.5V
20%
2 2.5V 2 2.5V
20%
PP0V9_SSD0 0.47UH-20%-4.8A-0.034OHM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM
81 80 79 78 77
85 83 82 0.47UH-20%-4.8A-0.034OHM V12 0402 0402 0402 0402 0402 0402 0402
1 C7882 1 C7883 1 C7884 1 C7885 1 C7886 1 C7887 L7823 1 2 P0V9SSD_SW0 BUCK5_LX1
84 A12 P0V9SLPDDR_SW1
MIN_LINE_WIDTH=0.1750
1 2 L7817
MIN_LINE_WIDTH=0.6000 B12 MIN_NECK_WIDTH=0.2000 0806-COMBO
20UF 20UF 20UF 20UF 20UF 20UF SSD:2L 0806-COMBO MIN_NECK_WIDTH=0.1000 SWITCH_NODE=TRUE PLACE_NEAR=L7816.2:5MM
20% 20% 20% 20% 20% 20% DIDT=TRUE DIDT=TRUE
2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V SWITCH_NODE=TRUE D12 0 R7816
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402 PLACE_NEAR=L7823.1:10MM M18 BUCK5_FB P0V9SLPDDR_FB 1 2
0201 5% MF 1/20W
SSD:2L 0 M17
SSD:2L SSD:2L SSD:2L SSD:2L SSD:2L SSD:2L R7822 1 2 P0V9SSD_FB_P BUCK9_LX0 IN 43 NOSTUFF
0201 5% MF 1/20W NO_TEST=1 M16
82 Supplied Current
1 C78B4 1 C78B5 PLACE_NEAR=U7800.N14:10MM
IN
P14 BUCK9_RTP BUCK3_SW1 T8 PP1V8_AWAKE 0.3A
A 1 C78B2 1 C78B3 20UF 20UF 27 37 40 42 43 62 72 83

20UF 20UF
20%
2 2.5V
20%
2 2.5V R7823 1
0 2 P0V9SSD_FB_N N14 BUCK9_RTN
BUCK3_SW2 R11 PP1V8_SLPS2R_PMUVDDGPIO 70 83 0.3A SYNC_MASTER= SYNC_DATE=