= 10 Chap. 2 Basic MOS Dey, Pa, 2.1 General Considerations ee 2.1.1 MOSFET as a Switch Before delving into the actual operation of the MOSFET, we consider a simpli the device so as to gain a feeling for what the transistor is expected to be and, whittle of its behavior are important. ich asp, ‘Shown in Fig. 2.1 is the symbol for an n-type MOSFET, revealing thre t gate (G), source (S) and drain (D). The later two are interchangeable because the oe Gate L Figure 2.1 Simple view of a MOS Source «3 L—« Drain device. symmetric. When operating as a switch, the transistor “connects” the source andthe ds together if the gate voltage, Vo, is “high” and isolates the source and the dain i Vi “low.” L ‘Even with this simplified view, we must answer several questions, For what valued Ve does the device turn on? In other words, what is the “threshold” voltage? What ite reaistance between § and D when the device is on (or off)? How does this resistance dpe ‘on the terminal voltages? Can we always model the path between S and D by a simple ina resistor? What limits the speed of the device? ‘While all of these questions arise at the circuit level, they can be answered only by analyzing the structure and physics of the transistor. 2.1.2 MOSFET Structure Fig. 2.2 shows a simplified structure of an n-type MOS (NMOS) device. Fabricated 01° p-type substrate (also called the “bulk” or the “body”), the device consists of 189 heal doped n regions forming the source and drain terminals, a heavily-doped (conductive i Oxide Figure 2.2. Structure of a MOS deviceSec. 2.1 General Considerations 1" of polysilicon! (often simply called “poly”) operating as the gate, and a thin layer of silicon dioxide (SiO. insulating the gate from the substrate. The useful action of the device occurs in the substrate region under the gate oxide. Note that the structure is symmetric with respect to Sand D. The dimension of the gate along the source-drain path is called the length, L, and that perpendicular to the length is called the width, W. Since during fabrication the S/D june- tions “side-diffuse,” the actual distance between the source and the drain is slightly less than L. To avoid confusion, we write, Leyy = Laraun ~ 2L.p, where Ley; is the “effective” Fength, Laravn is the total length,? and Lp is the amount of side diffusion. As we will see later, Leyy and the gate oxide thickness, ,,. play an important role in the performance of MOS circuits. Consequently, the principal thrust in MOS technology development is to reduce both of these dimensions from one generation to the next without degrading other parameters of the device. Typical values at the time of this writing are Lesy © 0.15 um and fox © 50 A. In the remainder of this book, we denote the effective length by L. If the MOS structure is symmetric, why do we call one n region the source and the other the drain? This becomes clear if the source is defined as the terminal that provides the charge carriers (electrons in the case of NMOS devices) and the drain as the terminal that collects them. Thus, as the voltages at the three terminals of the device vary, the source and the drain may exchange roles. These concepts are practiced in the problems at the end of the chapter. We have thus far ignored the substrate on which the device is fabricated. In reality, the substrate potential greatly influences the device characteristics. That is, the MOSFET is a four-terminal device. Since in typical MOS operation the S/D junction diodes must be reverse-biased, we assume the substrate of NMOS transistors is connected to the most negative supply in the system. For example, if a circuit operates between zero and 3 volts, Vius.vMos = 0. The actual connection is usually provided through an ohmic p* region, as depicted in the side view of the device in Fig. 2.3 p-substrate Figure 2.3 Substrate connection In complementary MOS (CMOS) technologies, both NMOS and PMOS transistors are available. From a simplistic view point, the PMOS device is obtained by negating all of "Polysilicon is silicon in amorphous (non-crystal) form. As explained in Chapter 17, when the gate silicon is ‘grown on top of the oxide, it cannot form a crystal se this is the dimension that we draw in the layout of the transistor 2 The subscript “drawn” iy used be (Section 2.4.1)n-substrate (a) p-substrate (b) Figure 2.4 (a) Simple PMOS device, (b) PMOS inside an n-well. the doping types (including the substrate) (Fig. 2.4(a)], but in practice, NMOS and PMOS devices must be fabricated on the same wafer, i.e. the same substrate. For this reason, one device type can be placed in a “local substrate,” usually called a “well.” In most of today’s CMOS processes, the PMOS device is fabricated in an n-well [Fig. 2.4(b)]. Note that the ‘n-well must be connected to a potential such that the $/D junction diodes of the PMOS transistor remain reverse-biased under all conditions. In most circuits, the n-well is ted the most positive supply voltage. For the sake of brevity, we sometimes call NMOS and PMOS devices “NFETs” and “PFETs,” respectively. Fig. 2.4(b) indicates an interesting difference between NMOS and PMOS transistor while all NFETS share the same substrate, each PFET can have an independent n-well. This flexibility of PFETs is exploited in some analog circuits. 2.1.3 MOS Symbols. The circuit symbols used to represent NMOS and PMOS transistors are shown in Fig. The symbols in Fig. 2.5(a) contain all four terminals, with the substrate denoted Dae (bulk) rather than “S” to avoid confusion with the source. The source of the Les i a is positioned on top as a visual aid because it has a higher potential than its gate- : Von: most circuits the bulk terminals of NMOS and PMOS devices are tied to ground ane respectively, we usually omit these connections in drawing (Fig. 2.5(b)]. In digitel — itis customary to use the “switch” symbols depicted in Fig. 2.5(¢) forthe (Wo WP in prefer those in Fig. 2.5(b) because the visual distinction between S and D proves understanding the operation of circuits. 25.wee . gec.2.2 MOSIN Characteristics 3 Nos PMs. Mos PMOS D s D D et! a4 st — s D s s ° ) © Figure 2.5 MOS symbols. 2.2 MOS WV Characteristics Intthis section, we analyze the generation and transport of charge in MOSFETS as a function of the terminal voltages. Our objective is to derive equations for the I/V characteristics such that we can elevate our abstraction from device physics level to circuit level. 2.2.1 Threshold Voltage Consider an NFET connected to external voltages as shown in Fig. 2.6(a). What happens as the gate voltage, Vc, increases from zero? Since the gate and the substrate form a capacitor, +0.1V p-substrate o) © Figure 2.6. (a) A MOSFET driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, (4) formation of inversion layer.14 se Chap. 2 Basic MOS Device Physg, as Vg becomes more positive, the holes in the p-substrate are repelled from the gate ane, leaving negative ions behind so as to mirror the charge on the gate. In other words, depletion region is created (Fig. 2.6(b)]. Under this condition, no current flows because yy charge carriers are available. ‘AS Vc; increases, so do the width of the depletion region and the potential at the oxide silicon interface. In a sense, the structure resembles two capacitors in series: the gate oxide capacitor and the depletion region capacitor [Fig. 2.6(c)]. When the interface potential reaches a sufficiently positive value, electrons flow from the source to the interface ang eventually to the drain. Thus, a “channel” of charge carriers is formed under the gate oxide between S and D, and the transistor is “turned on.” We also say the interface is “inverted” ‘The value of Vg for which this occurs is called the “threshold voltage,” Vr y. If Ve, rises further, the charge in the depletion region remains relatively constant while the channel charge density continues to increase, providing a greater current from S to D. In reality, the turn-on phenomenon is a gradual function of the gate voltage, making difficult to define Vp y unambiguously, In semiconductor physics, the Vp, of an NFET is usually defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type.” Itcan be proved (1] that® Ven = bys + 20% + Se, 24) where ys is the difference between the work functions of the polysilicon gate and the silicon substrate, ®¢ = (kT /q) In(Neap/n:).q is electron charge, Nyy is the doping con centration of the substrate, Qyey is the charge in the depletion region, and C,, is the gate ‘oxide capacitance per unit area. From pn junction theory, Oey = V/4qe,1-[Nyun, where é; denotes the dielectric constant of silicon, Since C,, appears very frequently in device and circuit calculations, itis helpful to remember that for fn, ® 50 A, C,, * 6.9 fFljam? The value of C,, can then be scaled proportionally for other oxide thicknesses. In practice, the “native” threshold value obtained from the above equation may not be suited to circuit design, e.g., Vry = 0 and the device does not turn off for Ve > 0. For this reason, the threshold voltage is typically adjusted by implantation of dopants into the ‘channel area during device fabrication, in essence altering the doping level of the substrate near the oxide interface. For example, as shown in Fig. 2.7, if thin sheet of p* is created, the gate voltage required to deplete this region increases, ate p-substrate Figure 2.7 Implantation of Pp! dopants to alter the threshold. 2.640). eal The above definition is not directly applicable to the measurement of Vr. {In Fig, only the drain current can indicate whether the device is “on” or “off,” thus failing at what Vos the interface is as much n-type as the bulk is p-type. As a result, the calculation * Charge wapping inthe oxide is neglected hereSec. 2.2 MOS I/V Characteristics 15 of Vw from I/V measurements is somewhat ambiguous. We return to this point later but assume in our preliminary analysis that the device turns on abruptly for Vos > Vrw The turn-on phenomenon in a PMOS device is similar to that of NFETs but with all of the polarities reversed. As shown in Fig. 2.8, ifthe gate-source voltage becomes sufficiently ie n-substrate Holes Figure 2.8 Formation of inversion layer in a PFET. negative, an inversion layer consisting of holes is formed at the oxide-silicon interface, providing a conduction path between the source and the drain. 2.2.2 Derivation of /V Characteristics In order to obtain the relationship between the drain current of a MOSFET and its terminal voltages, we make two observations. First, consider a semiconductor bar carrying acurrent J (Fig. 2.9(a)]. Ifthe charge density along the direction of current is Q4 coulombs per meter and the velocity of the charge is v meters per second, then 1=Qa-v. (2.2) ‘To understand why, we measure the total charge that passes through a cross section of the bar in unit time. With a velocity v, all of the charge enclosed in v meters of the bar must flow through the cross section in one second [Fig. 2.9(b)]. Since the charge density is Qu, the total charge in v meters equals Qg-v. This lemma proves useful in analyzing semiconductor devices, v meters ( co S One second later @) ) Figure 2.9 (a) A semiconductor bar carrying a current 1, (b) snapshots of the carriers one second apart.; Figure 2.10 Channel change with (a) equal source and drain voltages. (b) unequal source and drain voltages ‘Second, consider an NFET whose source and drain are connected to ground (Fig. 2.103) ‘What is the charge density in the inversion layer? Since we assume the onset of inversion, ‘occurs at Ves = Vrw. the inversion charge density produced by the gate oxide capacitance is proportional to Vs — Vrw. For Vcs > Vrw. any charge placed on the gate must be ‘mirrored by the charge in the channel, yielding a uniform channel charge density (charge per unit length) equal to Qe = WCar(Ves — Ven). e where C,, is multiplied by W to represent the total capacitance per unit length Now suppose, as depicted in Fig. 2.10(b), the drain voltage is greater than zero. Since the channel potential varies from zero at the source to Vp at the drain, the local voltage difference between the gate and the channel varies from Vg to Vc — Vi. Thus. the chars® density at a point x along the channel can be written as 24) Qex) = WCoiLVos — Vox) — Ven). a where V(x) is the channel potential at x From (2.2), the current is given by Ip = —WCalVes — Vix) — VrulvSec. 2.2 MOS IN Characteristics 7 where the negative sign is inserted because the charge carriers are negative and v denotes the velocity of the electrons in the channel. For semiconductors, v = wE, where pis the mobility of charge carriers and E is the electric field. Noting that E(x) = —dV/dx and representing the mobility of electrons by jin, we have dV(x) dx subject to boundary conditions V(0) = 0and V(L) = Vps. While V(x) can be easily found from this equation, the quantity of interest is in fact J. Multiplying both sides by dV and performing integration, we obtain Ip = WCorlVas — V(x) — Vriln , (2.6) L Vos [ Ipdx = WCoxbnlVos — V(x) — VruldV- (2.7) =o v=0 Since Zp is constant along the channel: w Ip = HnCox [ves — Vru)Vos — (2.8) Note that L is the effective channel length. Triode Region = eS Yos 11 Tt ae Figure 2.11 Drain current versus vs 2 drain-source voltage in the triode region. Fig. 2.11 plots the parabolas given by (2.8) for different values of Ves, indicating that the “current capability” of the device increases with Ves. Calculating 1p /8 Vp. the reader can show that the peak of each parabola occurs at Vps = Ves ~ Vrw and the peak current is, Ww inCon7-(Ves ~ Ven? (2.9) Tomax = We call Vos ~ Vr the “overdrive voltage” and W/L the “aspect ratio." If Vos < Vos — Vim. we say the device operates in the “triode region."> “Sometimes called the “effective voltage." This is also called the “Iinear region.”18 Ee Chap. 2 Basic MOS Device Physics Equations (2.8) and (2.9) serve as the foundation for analog CMOS design, describing the dependence of Ip upon the constant of the technology, /4nCor, the device dimensions, w and L, and the gate and drain potentials with respect to the source. Note that the integration in (2.7) assumes 1, and Vry are independent of x and the gate and drain voltages, an approximation that we will revisit in Chapter 16. If in (2.8), Vos « 2(Vos — Vr), we have w Ip * UnCox 7 (Vos — Vru)Vps. (2.10) that is, the drain current is a linear function of Vps. This is also evident from the character. istics of Fig. 2.11 for small Vps: as shown in Fig. 2.12, each parabola can be approximated by a straight line. The linear relationship implies that the path from the source to the drain can be represented by a linear resistor equal to 1 Ron = 11) Wy, 7 Un Cox (Vos -Vru) A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive voltage [so long as Vps < 2(Vos — Vru)]. This is conceptually illustrated in Fig. 2.13 Note that in contrast to bipolar transistors, a MOS device may be on even if it carries no Figure 2.12 Linear operation in deep triode region. G I Yes silo > —\-» Figure 2.13 MOSFETas controled linear resistor. current, With the condition Vos « 2(Vas~ Vr). we say the device operates in deep tode region. Assume plot the on-resistance of My as @ function of Vo MnCox = 50 wA/V?, W/L = 10, and Vr = 0.7 V. Note that the drain terminal is open.Sec.22 MOS IN Characteristics 19 (@) Figure 2.14 Solution Since the drain terminal is open, Jp = 0 and Vps = 0. Thus, if the device is on, it operates in the deep triode region. For Vq <1 V + Vry1, Mj is off and Ron = 00. For Vg > 1 V + Vr, we have Ron = ———, —________, 50 uA/V? x 10(VG = 1 V=0.7 V) (2.12) ‘The result is plotted in Fig. 2.14(b). _— oo The utility of MOSFETs as controllable resistors and hence switches plays a crucial role in many analog circuits. This is studied in Chapter 12. What happens if in Fig. 2.11 the drain-source voltage exceeds Ves — Vr? In reality, the drain current does not follow the parabolic behavior for Vps > Vos — Vr. In fact, as shown in Fig. 2.15, Ip becomes relatively constant and we say the device operates in the “saturation” region.® To understand this phenomenon, recall from (2.4) that the local Figure 2.15 Saturation of drain current, “Note the difference between saturation in bipolar and MOS devices.Chap.2 Basic MOS Device Physe, Yo Vose> Voq, (x4) = Vos Vr Figure 2.16 Pinch-off behavior. density of inversion layer charge is proportional to Ves ~ V(x) ~ Vr. Thus. if Vis) approaches Vas — Vriz. then Qa(x) drops to zero. In ‘other words, as depicted in Fig. 2.16, if Vos is slightly greater than Vos — Vra then the inversion layer stops at x = Land we say the channel is “pinched off.” As Vps increases further, the point at which Qs equal zero gradually moves toward the source. Thus, at some point along the channel, the lca potential difference between the gate and the oxide-silicon interface is not sufficient 10 support an inversion layer. With the above observations, we re-examine (2.7) for a saturated device. Since Qs s the density of mobile charge, the integral on the left-hand side of (2.7) must be taken from x = 010 x = L’, where L’ is the point at which Q drops to zero, and that on the right from to V(x) = Ves — Ven. Asa result: v(x) 1 Ww 2 7 I = 5 HnCox 7 (Vos ~ Ven). 2.13) indicating that /p is relatively independent of Vps if L' remains close to L. For PMOS devices, Eqs. (2.8) and (2.13) are respectively written as qa) Ww Li I =~ pCoore [os Ven Vos - $vis| and 1 w > Ip = — FH Cox F (Vos ~ Ven) ‘The negative sign appears here because we assume Ip flows from the drain to the source. whereas holes flow in the reverse direction. Since the mobility of holes is about one-half to one-fourth of the mobility of electrons, PMOS devices suffer from lower “current eS capability. a waaSec. 2.2 MOS I/V Characteristics 24 Yoo Yoo 7 Yor > On ; wk o> f h iC Figure 2.17 Saturated MOSFETs operating as current sources. With the approximation L ~ L’, a saturated MOSFET can be used as a current source connected between the drain and the source (Fig. 2.17), an important component in analog design. Note that the current sources inject current into ground or draw current from Vp. In other words, only one terminal of each current source is “floating.” Since a MOSFET operating in saturation produces a current in response to its gate- source overdrive voltage, we may define a figure of merit that indicates how well a device converts a voltage to a current. More specifically, since in processing signals we deal with the changes in voltages and currents, we define the figure of merit as the change in the drain current divided by the change in the gate-source voltage. Called the “transconductance” and denoted by gm, this quantity is expressed as: aly m= (2.16) Bm Bes lvoscom w = UnCox (Vas ~ Vru). (2.17) Ina sense, gq represents the sensitivity of the device: for a high gq, a small change in Vgs results in a large change in Jp. Interestingly, g», in the saturation region is equal to the inverse of Ron in deep triode region. The reader can prove that gm can also be expressed as 8m = Vf HnCor Io (2.18) 2 =o (2.19) Vos ~ Vrw Plotted in Fig. 2.18, each of the above expressions proves useful in studying the behavior Of gm as a function of one parameter while other parameters remain constant. For example, (2.17) suggests that gq, increases with the overdrive if W/L is constant whereas (2.19) im- plies that gm decreases with the overdrive if I is constant. The concept of transconductanceee, Chap.2 Basic MOS Device Physicg Om! Om! 9m Ves Ip Ves: WAL Constant WIL Constant ‘p Constant Figure 2.18 MOS transconductance as a function of overdrive and drain current, can also be applied to a device operating in the triode region, as illustrated in the following example. Example 2.2 For the arrangement shown in Fig. 2.19, plot the transconductance as a function of Vps. Vo- Van Vos Figure 2.19 Solution vis simpler to study gm as Vps decreases from infinity. So long as Vps > Vs — Vrs Mi isin saturation, Ip is relatively constant, and, from (2.18), sO is gm. For Vos < Vs — Vr. My is in the triode region and: a 1 we a 8m = Tye | HnCon 7 [2Vas ~ Vrw Vos — vas] 2.20) w inCox = Vos- 1) HnCox 7 Vos ‘Thus, as plotted in Fig. 2.19, the transconductance drops if the device enters the triode region. For amplification, therefore, we usually employ MOSFETs in saturation. — ‘The distinction between saturation and triode regions can be confusing, especially for PMOS devices. Intuitively, we note that the channel is pinched off ifthe difference betwee” the gate and drain voltages is not sufficient to create an inversion layer. As depicted conceP” tually in Fig. 2.20, as Vg ~ Vp of an NFET drops below V7, pinch-off occurs. ‘Similarly.Sec.2.3 Second-Order Effects 23 Saturation Edge of Triode Region Saturation Edge of Triode Region + + Vrnn - L > ’ J ok > ah oS Lr oo Ar, 1 } - ' [Yen] @ (b) Figure 2.20 Conceptual visualization of saturation and triode regions, if Vp — Vo of a PFET is not large enough (< |Viyp|), the device is saturated. Note this view does not require knowledge of the source voltage. This m priori which terminal operates as the drain 2.3 Second-Order Effects Our analysis of the MOS structure has thus far entailed various simplifying assumptions, some of which are not valid in many analog circuits. In this section, we describe three second-order effects that are essential in our subsequent citcuit analyses. Other phenomena that appear in submicron devices are studied in Chapter 16. wh Body Effect In the analysis of Fig. 2.10, we tacitly assumed that the bulk and the source of the transistor were tied to ground. What happens if the bulk voltage of an NFET drops below the source voltage (Fig. 2.21)? Since the S and D junctions remain reverse-biased, we surmise that the device continues to operate properly but certain characteristics may p-substrate — Fvg<0 Figure 2.21 NMOS device with negative bulk voltage. change, To understand the effect, suppose Vs = Vp = 0, and Vg is somewhat less than Vr so that a depletion region is formed under the gate but no inversion layer exists. As Vu becomes more negative, more holes are attracted to the substrate connection, leavin, larger negative charge behind, i.e., as depicted in Fig. 2.22, the depletion region becomes wider. Now recall from Eq. (2.1) that the threshold voltage is a function of the total charge in the depletion region because the gate charge must mirror Q, before an inversion layer isChap. 2 Basic MOS Device Physics p-substrate Q% Figure 2.22. Variation of depletion region charee with bulk voltage. formed. Thus, as Vp drops and Qq increases, Vr also increas effect” or the “backgate effec It can be proved that with body effect: Ven = Vane +» (VBbr + Veri - VP FI) (22) s. This is called the “body where Vro is given by (2.1), 7 = V2GeiNow/Cox denotes the body effect coefficient, nd Ver isthe source-bulk potential difference [1]. The value of y typically lies inthe range of 0.3 100.4 V7, In Fig. 2.23(a), plot the drain current if Vy varies from ~oo to 0. Assume Vio vi? and 20p = 0.7 V. 'p (@) (b) Figure 2.23 Solution IF Vy is suficiently negative, the threshold voltage of My exceeds 1.2 V and the device is off That 12V = 06+404(Y0.7= Vi - YO7), e2) 7Sec. 2.3 Second-Order Effects 25 and hence Vy; = —4.76 V. For Vy; < Vx < 0, Ip increases according to 1 w 2 Ip = 5h [Yes ~Vrno~v (V24r ~ Vx v%*)| (2.24) Fig. 2.23(b) shows the resulting bet For body effect to manifest itself, the bulk potential, V,,», need not change: if the source voltage varies with respect to V,yp, the same pheriomenon occurs. For example, consider the circuit in Fig. 2.24(a), first ignoring body effect. We note that as Vin varies, Vjy closely follows the input because the drain current remains equal to /,. In fact, we can write 1 Ww = sbnCor—(Vin — Vour ~ Ven), (2.25) Nh = FH aCon 7 THY concluding that Vin — Vous is constant if /; is constant [Fig. 2.24(b)]. (a) (b) «© Figure 2.24 (a) A circuit in which the source-bulk voltage varies with input level, (b) input and output voltages with no body effect, (c) input and output voltages with body effect. Now suppose the substrate is tied to ground and body effect is significant. Then, as Vix and hence Vj4; become more positive, the potential difference between the source and the bulk increases, raising the value of Vz. Eq. (2.25) therefore implies that Vig — Voy must increase so as to maintain Ip constant (Fig. 2.24(c)]. Body effect is usually undesirable. The change in the threshold voltage, e.g., as in Fig. 2.24(a), often complicates the design of analog (and even digital) circuits. Device technologists balance Ny» and C,, to obtain a reasonable value for y. Channel-Length Modulation In the analysis of channel pinch-off in Section 2.2, we noted that the actual length of the inverted channel gradually decreases as the potential difference between the gate and the drain increases. In other words, in (2.13), L’ is in fact a function of Vps. This effect is called “channel-length modulation.” Writing L’ = L — AL, 1/L’ = (1 + AL/L)/L, and assuming a first-order relationship between AL/L and Vos such as AL/L = }.Vps, we have, in saturation, w 9, (Ves ~ Ven Vl + 4¥ps). (2.26) 1 Ip * halo_ = Chap.2 Basic MOS Device Physicg Figure 2.25 Finite saturation region slope resulting from channel-length modulation. where 2 is the channel-length modulation coefficient. Illustrated in Fig. 2.25. this phe. nomenon results in a nonzero slope in the Zp/Vps characteristic and hence a nonidea current source between D and S in saturation. The parameter 2 represents the relative variation in length for a given increment in Vps. Thus, for longer channels, 4 is smaller, With channel-length modulation, some of the expressions derived for gm must be mod- ified. Equations (2.17) and (2.18) are respectively rewritten as fn = HaCor (Vos ~ Vey + A¥o9) eat eee — PaeGectW/ Et a2) 7 T+2Vps_ / while Eq. (2.19) remains unchanged. Example 2.4 ————__ Keeping all other parameters constant, plot [p/Vps characteristic of a MOSFET for L = Ly and L=2hy. Solution Writing 1 Ww Tp = 5HnCox (Ves ~ Vrn)*(1 + AVps) 229) and A o 1/L, we note that if the length is doubled, the sloy cause 7 5 pe of I1p vs. Vps is divided by four becat 41p/AVps & A/L cx 1/L? (Fig. 2.26). For a given gate-source overdrive, a larger L gives @ mot Figure 2.26 Effect of doubling char Vos nel length. ‘deal current source while degrading the current capability of the device. Thus, W may need | le : bility of . y ta ate2.3. Second-Order Effects 27 The linear approximation AL/L & Vps becomes less accurate in short-channel transis- tors, resulting in a variable slope in the saturated Ip / Vps characteristics. We return to this issue in Chapter 16. The dependence of Jp upon Vps in saturation may suggest that the bias current of a MOSFET can be defined by the proper choice of the drain-source voltage, allowing freedom in the choice of Ves — Vr#. However, since the dependence on Vps is much weaker, the drain-source voltage is not used to set the current. The effect of Vps on Ip is usually considered an error and it is studied in Chapter 5. Subthreshold Conduction _In our aralysis of the MOSFET, we have assumed that the device turns off abruptly as Ves drops below Vry. In reality, for Ves © Vru, a “weak” inversion layer still exists and some current flows from D to S. Even for Ves < Vruy Ip is finite, but it exhibits an exponential dependence on Ves [2, 3]. Called “subthreshold conduction,” this effect can be formulated for Vps greater than roughly 200 mV as Vos = aos 2.30) Ip = Inexp rv," (2.30) where ¢ > 1 is a nonideality factor and Vr = kT/q. We also say the device operates in “week inversion.” Except for £, (2.30) is similar to the exponential Ic/ Vax relationship in a bipolar transistor. The key point here is that as Vas falls below Vrj, the drain current drops at a finite rate. With typical values of ¢, at room temperature Vos must decrease by approximately 80 mV for [p to decrease by one decade (Fig. 2.27). For example, if a Square aS Figure 2.27 MOS subthreshold char- eomv TH Ves acteristics. threshold of 0.3 V is chosen in a process to allow low-voltage operation, then when Vcs is reduced to zero, the drain current decreases by only a factor of 10°7°. Especially problematic in large circuits such as memories, subthreshold conduction can result in significant power dissipation (or loss of analog information). Tt is appropriate at this point to return to the definition of the threshold voltage. One definition is to plot the inverse on-resistance of the device Rjq! = 4Cox(W/L)(Vos — Vr) as a function of Vos and extrapolate the result to zero, for which Vgs = Vru. In rough calculations, we often view Vry as the gate-source voltage yielding Ip/W = 1A/um in saturation. For example, if a device with W = 100 jzm operates with Jp = 100 2A, itis in the vicinity of the subthreshold region. This view is nonetheless vague, especially as device length scales down in every technology generation,nd 2.18) for the tansco! ‘We now Eq. ¢ re-examine 7 ble 10 Fld region, 15 it poss — ‘ile maintaining [0 : ine I / Vz) biased at a ; cea to sist eT oe Ip = (1/2)HaCoxW/L Vos — vas derived a Howevet if W increases while Ip re! 5 red from ibthreshol it, the transcol r eee 7 sree 5 NOSTETS ae aferior to bipolar transistors in this respec, p/( Yr) 7 renee subthreshold operation may sugzes, al dependence of Ip upon Vos ; £5 ae os ices in this regime So as tO achieve @ higher gain. However, since such conditions are met by only 2 large device width or Jow drain current, the speed of subthreshold circuits is severely limited. Voltage Limitations MOSFETs experience various breakdown effects if their terminal voltage differences exceed certain’ limits. Athigh gate-source voltages, the gate oxide breaks Gown imeversibly, damaging the transistor. In short-channel devices, an excessively large Grain-source voltage widens the depletion region around the drain so much that it touches that around the source, creating a very large drain current. (This effect is called “punchthrough.”) Other limitations relate to “hot electron effects” and are described in Chapter 16. OS Device Models 2.4.1 MOS Device Layout For the developments in subsequent iti i Forth developmen in subsequent sation, its beneficial to have some understanding of ly a simple view here, c details and structural subtleties to Chapters 17 and 18 eet lL ‘The layout of a MOSFET is determined , device in the circuit and the “design rules” is Shosen toset the transconductance or ot ictated by the process. In additi Properly as well. i by both the electrical properties required of the cancel by the technology. For example, W/L paatasds it parameters, while the minimum L is Sate, the source and drain areas must be defined Fig. 2.28 that total .28 that one di i limension Jjunctioy ° re enough "S00 of the junctions oh MUSE be minimized, We see from ign rules? nmodate the contact wind Mal to W. The other di t nig ose jimension must lows and is speci S and is specified by the technology ——— "This dimer MNO" cally thee to four ti 'mes the minimum attimran ain esinetinet gec.2.4 MOS Device Models i Channel Area wi a > Contact = Windows + Lgrawn OO) o Figure 2.28 Bird's eye and vertical views of a MOS device. Example 2.5 Draw the layout of the circuit shown in Fig. 2.29(a) E F Aluminum E a) Ao m, 1 My c a {fo Ms C 1M, Boh m. N i oe My N (a) (b) te) Figure 2.29 Solution Noting that Mf, and Mz share the same S/D junctions at node C and Mz and Ms also do so at node NV, we surmise that the three transistors can be laid out as shown in Fig. 2.29(b). Connecting the remaining terminals, we obtain the layout in Fig. 2.29(c). Note that the gate polysilicon of Ms cannot be directly tied to the source material of Mj, thus requiring a metal interconnect. 2.4.2 MOS Device Capacitances ~ ‘The basic quadratic IV relationships derived in the previous section along with corrections for body effect and channel-length modulation provide a reasonable model for understand- ing the “de” behavior of CMOS circuits. In many analog circuits, however, the capacitances associated with the devices must also be taken into account so as to predict the “ac” behavior as well,Chap. 2 Basie MOS Dovca Fry, oO Can Con t+ o B Ly Cos | Coa! Coe s Figure 2.30 MOS capacitances We expect that a capacitance exists between every two of the four terminals of a MOSFE} (Fig. 2.30).* Moreover, the value of each of these capacitances may depend on the bias cow ditions of the transistor, Considering the physical structure in Fig. 2.31(a), we identify the following. (1) Oxide capacitance between the gate and the channel, Cy = WLC,.: (2) De pletion capacitance between the channel and the substrate, C> = WLJ/qeu Nuun) (3) Capacitance due to the overlap of the gate poly with the source and drain areas, C) and C4. Owing to fringing electric field lines, Cs and Cy cannot be simply written as WL pC. and are usually obtained by more elaborate calculations. The overlap capacitance per unt width is denoted by Cy; (4) Junction capacitance between the source/drain areas and the substrate. As shown in Fig. 2.31(b). this capacitance is usually decomposed into wo compe ‘nents: bottom-plate capacitance associated with the bottom of the junetion, Cand sidewall capacitance due to the perimeter of the junction, Cj... The distinction is necessary because different transistor geometries yield different area and perimeter values for the S/D jun ti00 We typically specify C, and C,,... as capacitance per unit area and unit length, respectively Note that each junction capacitance can be expressed as C, = Cjo/[1 + Vi_/ yl". where Vp is the reverse voltage across the junction, ®g is the junction built-in potential, and © 4 power typically in the range of 0.3 and 0.4. o Figure 2.31 (a) MOS device capacitances, (b) decomposition of S/D junction capacitance into boctom plate sidewall componentssec. 2.4 MOS Device Models 31 Example 2.6 Calculate the source and drain junction capacitances of the two structures shown in Fi Drain Terminal (a) () Figure 2.32 Solution For the transistor in Fig. 2.32(a), we have Cpa = Csp = WEC; + UW + BC jou. 3p whereas for that in Fig. 2.32(b), Ww Ww Con = VEC, +2(F +E) Cow (2.32) Ww Ww Csp = 2] FEC +2(5 +6) Cine] (2.33) = WEC) +2W + 2E)Cjsw. (2.34) Called a “folded” structure, the geometry in Fig. 2.32(b) exhibits substantially less drain junction capacitance than that in Fig, 2.32(a) while providing the same W/L. Th the above calaculations, we have assumed that the total source or drain perimeter, 2(W + E), is multiplied by C jw, In reality, the capacitance of the sidewall facing the channel may be less than ‘ofthe other three sidewalls because of the channel-stop implant (Chapter 17). Nonetheless, we ve the same unit capacitance, The error resulting from this assumption ina circuit is connected to a number of other device capacitances as typically assume all four sides ha is negligible because each node iChap.2 Basie MOS Device Phys, Ww Wor Wey, it vai) a __ ‘' Vr YorV¥m Yes Figure 8d Variation ‘at gate souree: ‘andl gate-drain capacitances versus Vas sy terminals of a MOSFET in different region of poration Hthe atovive Nott, Cop = Cas Coy W, and the gate-bulk capacitance consists AL the series combination ot the gate oxide capacitance ‘and the depletion region capac- YCy/WLCos ob Cade Where Eis the effective length and Gt yp anxd Cpa is & function of the source and We now alorive the eapacttances betwee! wanes boy Con = WEE Cy = When Nw Jy), The value Atrainy vuattagies WARN FeNpeet 10 the substrate, Tr he devioe ts tn oop trle region, he. if $ and D have approximately equal vol ages, then the gateschannel capacitance WLCou is divided equally between the gate A wou teemninals and the gate and drain terminals, ‘This is because a change AV in Ww gato voltage rays equal amounts of charge from S and D. Thus, Cop = Cas = WEES 24 Ws We av saturation, & MOSKRT exhibits @ gate-drain capacitance of roughly WCoo. The potential ditforonee between the gate and the channel varies from Vas at the source © Vex = Vew at the pinetyott point, resulting ina nonuniform vertical electric field 19 he gate orate along the channel, It ean be proved that the equivalent caps itance of Ais ~~ ‘excluding the gate-soutve overlap capacitance equals 2W LCox /3 [1]. Ths: Coy = Whe Co i ' ‘ satdraca ener Seca ae The behavior of Co and Cos indifferent regions of ope” Paci sh ae ae that the above equations do not provide a smooth transition ‘one region of operation to another, creating convergence difficulties in simulation weve This ignuie is revisited in Chapter 16, convergence diclties in Simul he gaatesbuith capatoitan sted i cause the fian ap et 2V— 0.6 V. The variation of the capacitances is plotted in Figs. 2.35(b) and (©). eee / 2.4.3 MOS Small-Signal Model ‘The quadratic characteristics described by (2.8) and (2.9) along with the voltage-dependent capacitances derived above form the large-signal model of MOSFETs. Such a model proves essential in analyzing circuits in which the signal significantly disturbs the bias points, particularly if nonlinear effects are of concem, By contrast, if the perturbation in bi Conditions is small, a small-signal model, ic., an approximation of the large-signal model around the operating point, can be employed to simplify the calculations. Since in many analog circuits, MOSFET are biased in the saturation region, we derive the corresponding SimalJ-signal model here. For transistors operating as switches, a linear resistor given by (2.11) together with device capacitances serves as a rough small-signal equivalent, We derive the small-signal model by producing a small increment in a bias point and calculating the resulting increment in other bias parameters. Since the drain current is @ function of the gate-source voltage, we incorporate a voltage-dependent current source equal tO ga Vos (Fig. 2.36(a)]. Note that the low-frequency impedance between G and S is very high, This is the small-signal model of an ideal MOSFET. Owing to channel-length modulation, the drain current also varies with the drain-source voltage. Thiseffect can also be modeled by a voltage-dependent current source [Fig, 2.36(b)], but a current source whose value linearly depends on the voltage across it is equivalent toGo—_ o oo o Vos 9m¥as Vos @ onton Vg Figure 2.36 (a) Basic MOS small-signal model, (b) channel-length modulation represented by » dependent current source, (c) channel-length modulation represented by a resistor. (d) body effect represented by a dependent current source. a linear resistor (Fig. 2.36(c)]. Tied between D and S, the resistor is given by aVps = 238) 0= Fp — 236) 81p/3Vos ! Qn 1 Ww 5HaCon T-(Vos — Vea? -® : aw ilo ‘As seen throughout this book, the output resistance, ro, impacts the performance of aA? analog circuits. For example, ro limits the maximum voltage gain of most ampliners. Now recall that the bulk potential influences the threshold voltage and hence the £4 source overdrive. As demonstrated in Example 2.3, with all other terminals beld 3 aconstaat voltage, the drain current is a function of the bulk voltage, That is, the balk vee 2 second gate. Modeling this dependence by a current source connected berweeh Oe [Fig. 2.36(d)]. we write the value as gms Vo.. Where gan = 81p/IVas In the sal TegiONn, Smb can be - eimai a”