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The document contains 10 multiple choice questions about digital logic gates and flip-flops. It tests knowledge of which logic gates can be used to add two bits, when the master is enabled on a master-slave flip-flop, how the output of a gated D flip-flop behaves, what type of triggering occurs on different flip-flop symbols, requirements for edge-triggered flip-flops, disadvantages of an S-R flip-flop, how a positive edge-triggered D flip-flop stores a value, what edge-triggering means, how the output of a gated S-R flip-flop changes, and how to build an XOR gate using only "X" and

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Himanshu Chauhan
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112 views3 pages

Questions

The document contains 10 multiple choice questions about digital logic gates and flip-flops. It tests knowledge of which logic gates can be used to add two bits, when the master is enabled on a master-slave flip-flop, how the output of a gated D flip-flop behaves, what type of triggering occurs on different flip-flop symbols, requirements for edge-triggered flip-flops, disadvantages of an S-R flip-flop, how a positive edge-triggered D flip-flop stores a value, what edge-triggering means, how the output of a gated S-R flip-flop changes, and how to build an XOR gate using only "X" and

Uploaded by

Himanshu Chauhan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. Which type of gate can be used to add two bits? A.Ex-OR C.

Ex-NAND
Ans A

B. Ex-NOR D.NOR

2. On a master-slave flip-flop, when is the master enabled? A.when the gate is LOW B. when the gate is HIGH C. both of the above D.neither of the above
Ans- B

3. Which of the following is correct for a gated D flip-flop? A.The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D.Q output follows the input D when the enable is HIGH.
Ans- D

4. The symbols on this flip-flop device indicate ________.

A.triggering takes place on the negative-going edge of the CLK pulse B. triggering takes place on the positive-going edge of the CLK pulse C. triggering can take place anytime during the HIGH level of the CLK waveform D.triggering can take place anytime during the LOW level of the CLK waveform
Ans A

5. Edge-triggered flip-flops must have: A.very fast response times B. at least two inputs to handle rising and falling edges C. positive edge-detection circuits D.negative edge-detection circuits
Ans- C

6. What is one disadvantage of an S-R flip-flop? A.It has no enable input. B. It has an invalid state. C. It has no clock input. D.It has only a single output.
Ans- B

7. A positive edge-triggered D flip-flop will store a 1 when ________. A.the D input is HIGH and the clock transitions from HIGH to LOW B. the D input is HIGH and the clock transitions from LOW to HIGH C. the D input is HIGH and the clock is LOW D.the D input is HIGH and the clock is HIGH
Ans-B

8. If an input is activated by a signal transition, it is ________. A.edge-triggered B. toggle triggered C. clock triggered D.noise triggered
Ans-A

9. The output of a gated S-R flip-flop changes only if the: A.flip-flop is set B. control input data has changed C. flip-flop is reset D.input data has no change
Ans-B

10. Due to the war in the land of Logicia there is a shortage of XOR gates. Unfortunately, the only logic gates available are two weird components called X and Y. The truth table of both components is presented below Z represents a High-Z value on the output. Could you help the poor engineers of Logicia to build an XOR gate?

Ans-Connect 2 [ X , Y ] to get inverter use inverter for to get not A , not B .. now use Y for not A , B to get nand [ not exactly nand but sort of ] .. and invert the nand to get and and we get (not A and B ).. similarly get (A and not B ) .. Now connect both the outputs to get .. {NotA and B} + {A and notB} XOR

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