Atmega809/1609/3209/4809 - 48-Pin: 48-Pin Data Sheet - Megaavr® 0-Series
Atmega809/1609/3209/4809 - 48-Pin: 48-Pin Data Sheet - Megaavr® 0-Series
48-pin
                     48-pin Data Sheet – megaAVR® 0-series
Introduction
                                                                  ®                            ®
The ATmega809/1609/3209/4809 microcontrollers of the megaAVR 0-series are using the AVR
processor with hardware multiplier, running at up to 20 MHz, with a wide range of Flash sizes up to 48
KB, up to 6 KB of SRAM, and 256 bytes of EEPROM in 28-, 32-, 40-, or 48-pin package. The series uses
the latest technologies from Microchip with a flexible and low-power architecture including Event System
and SleepWalking, accurate analog features and advanced peripherals.
The devices described here offer Flash sizes from 8 KB to 48 KB in a 48-pin package.
Features
           ®
  • AVR CPU
     – Single-cycle I/O access
     – Two-level interrupt controller
     – Two-cycle hardware multiplier
  • Memories
     – Up to 48 KB In-system self-programmable Flash memory
     – 256B EEPROM
     – Up to 6 KB SRAM
     – Write/Erase endurance:
         • Flash 10,000 cycles
         • EEPROM 100,000 cycles
     – Data retention: 40 Years at 55°C
  • System
     – Power-on Reset (POR) circuit
     – Brown-out Detector (BOD)
       – Clock options:
          • 16/20 MHz low-power internal oscillator
          • 32.768 kHz Ultra Low-Power (ULP) internal oscillator
          • 32.768 kHz external crystal oscillator
          • External clock input
       – Single pin Unified Program Debug Interface (UPDI)
       – Three sleep modes:
          • Idle with all peripherals running for immediate wake-up
          • Standby
               – Configurable operation of selected peripherals
                – SleepWalking peripherals
            • Power-Down with limited wake-up functionality
  •   Peripherals
        – One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare
           channels
        – Four 16-bit Timer/Counter type B with input capture (TCB)
        – One 16-bit Real-Time Counter (RTC) running from an external crystal or an internal RC oscillator
        – Four USART with fractional baud rate generator, auto-baud, and start-of-frame detection
        – Master/slave Serial Peripheral Interface (SPI)
        – Dual mode Master/Slave TWI with dual address match
            • Standard mode (Sm, 100 kHz)
            • Fast mode (Fm, 400 kHz)
            • Fast mode plus (Fm+, 1 MHz)
        – Event System for CPU independent and predictable inter-peripheral signaling
        – Configurable Custom Logic (CCL) with up to four programmable Look-up Tables (LUT)
        – One Analog Comparator (AC) with a scalable reference input
        – One 10-bit 150 ksps Analog to Digital Converter (ADC)
        – Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3V
        – CRC code memory scan hardware
            • Optional automatic scan before code execution is allowed
        – Watchdog Timer (WDT) with Window mode, with separate on-chip oscillator
        – External interrupt on all general purpose pins
  •   I/O and Packages:
        – 41 programmable I/O lines
        – 48-pin UQFN 6x6 and TQFP 7x7
  •   Temperature Range: -40°C to 125°C
  •   Speed Grades -40°C to 105°C:
        – 0-5 MHz @ 1.8V – 5.5V
        – 0-10 MHz @ 2.7V – 5.5V
        – 0-20 MHz @ 4.5V – 5.5V
  •   Speed Grades -40°C to 125°C:
        – 0-8 MHz @ 2.7V - 5.5V
        – 0-16 MHz @ 4.5V - 5.5V
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Block Diagram........................................................................................................... 5
2. Pinout........................................................................................................................ 6
     2.1.     48-pin UQFN/TQFP......................................................................................................................6
4. Electrical Characteristics........................................................................................... 9
     4.1.     Disclaimer.....................................................................................................................................9
     4.2.     Absolute Maximum Ratings .........................................................................................................9
     4.3.     General Operating Ratings ..........................................................................................................9
     4.4.     Power Considerations................................................................................................................ 11
     4.5.     Power Consumption................................................................................................................... 11
     4.6.     Peripherals Power Consumption................................................................................................13
     4.7.     BOD and POR Characteristics................................................................................................... 14
     4.8.     External Reset Characteristics................................................................................................... 15
     4.9.     Oscillators and Clocks................................................................................................................15
     4.10.    I/O Pin Characteristics................................................................................................................17
     4.11.    USART....................................................................................................................................... 19
     4.12.    SPI..............................................................................................................................................20
     4.13.    TWI.............................................................................................................................................21
     4.14.    VREF..........................................................................................................................................23
     4.15.    ADC............................................................................................................................................25
     4.16.    AC.............................................................................................................................................. 28
     4.17.    UPDI Timing............................................................................................................................... 29
     4.18.    Programming Time..................................................................................................................... 30
5. Typical Characteristics.............................................................................................31
     5.1.     Power Consumption................................................................................................................... 31
     5.2.     GPIO.......................................................................................................................................... 39
     5.3.     VREF Characteristics................................................................................................................. 46
     5.4.     BOD Characteristics...................................................................................................................48
     5.5.     ADC Characteristics................................................................................................................... 51
     5.6.     AC Characteristics......................................................................................................................61
     5.7.     OSC20M Characteristics............................................................................................................63
     5.8.     OSCULP32K Characteristics..................................................................................................... 65
6. Ordering Information................................................................................................67
8. Package Drawings...................................................................................................69
     8.1.     48-Pin TQFP.............................................................................................................................. 69
     8.2.     48-Pin UQFN..............................................................................................................................73
9. Conventions.............................................................................................................77
     9.1.     Memory Size and Type...............................................................................................................77
     9.2.     Frequency and Time...................................................................................................................77
Customer Support......................................................................................................... 79
Legal Notice...................................................................................................................80
Trademarks................................................................................................................... 81
1. Block Diagram
            UPDI                        UPDI
                                                   CRC                  CPU
                                                             OCD
                                                                                                      Flash
                                               M                   M          M
                                                                                      S
                          SRAM           S                BUS Matrix
                                                                                                     EEPROM
                                                                                      S
                                                     S
                                                                                                     NVMCTRL
                                                                                  I
                                                                                  N                                   PAn
                                                                                  /                                   PBn
             AINPn                                            PORTS               O
                                                                                  U
                                                                                                                      PCn
                                                                                                                      PDn
             AINNn            ACn                                                 T                                   PEn
               OUT
                                                                                                                      PFn
                                                               GPIOR              D
              AINn                                                                A
                             ADCn              E     D                            T
            VREFA                                    A
                                               V                                  A
                                               E     T                            B
                                                     A
                                               N
                                                     B        CPUINT              U
                                                                                            Detectors/
                                               T                                  S
          EVOUTx             EVSYS                   U                                      References
                                               R     S
                                                                                                                      RESET
                                               O
                                               U
                                                              System                        RST        POR
         LUTn-INn
        LUTn-OUT              CCL              T            Management
                                               I                                                       BOD/
                                                                                           Bandgap
                                               N             RSTCTRL                                   VLM
                                               G
             WOn             TCAn                            CLKCTRL
                                               N
                                               E
                                               T              SLPCTRL
              WO             TCBn              W
                                               O                                          Clock Generation
                                               R
             RXD                               K                                                                      CLKOUT
              TXD
             XCK            USARTn                              WDT
                                                                                             OSC20M
                                                                                                                      EXTCLK
             XDIR
                                                                                             OSC32K
            MISO
            MOSI                                                                                                     TOSC1
             SCK              SPIn                              RTC                         XOSC32K
              SS
                                                                                                                    TOSC2
      SDA (master)
      SCL (master)
       SDA (slave)            TWIn
       SCL (slave)
2. Pinout
PA0 (EXTCLK)
                                                                                UPDI
                                                                  GND
                                                                         VDD
                                PA3
                                      PA2
                          PA4
PA1
                                                                                       PF6
                                                                                             PF5
                                                                                                   PF4
                                                                                                         PF3
                                                  44
                                                                  43
                                                                         42
                                                                                41
                                                                                       40
                                                                                             39
                                                                                                   38
                                                                                                         37
                          48
                                47
                                      46
                                            45
      PA5           1                                                                                          36   PF2
      PA6           2                                                                                          35   PF1 (TOSC2)
      PA7           3                                                                                          34   PF0 (TOSC1)
      PB0           4                                                                                          33   PE3
      PB1           5                                                                                          32   PE2
      PB2           6                                                                                          31   PE1
      PB3           7                                                                                          30   PE0
      PB4           8                                                                                          29   GND
      PB5           9                                                                                          28   AVDD
      PC0          10                                                                                          27   PD7
      PC1          11                                                                                          26   PD6
      PC2          12                                                                                          25   PD5
                          13
                                14
                                      15
                                            16
                                                  17
                                                                  18
                                                                         19
                                                                                20
                                                                                       21
                                                                                             22
                                                                                                   23
                                                                                                         24
                          PC3
                                            PC4
                                                  PC5
                                                                  PC6
                                                                         PC7
                                                                                PD0
                                                                                       PD1
                                                                                             PD2
                                                                                                   PD3
                                                                                                         PD4
                                      GND
                                VDD
      Power                                                      Functionality
           Input supply                                                 Programming, debug
Analog functions
14 VDD
15 GND
28 AVDD
29 GND
...........continued
 UQFN48/                Pin name (1,2)   Special     ADC0    AC0   USARTn        SPI0    TWI0         TCA0       TCBn       EVSYS       CCL-LUTn
 TQFP48
41 UPDI
42 VDD
43 GND
                       Note: 
                        1. Pin names are of type Pxn, with x being the PORT instance (A,B,C, ...) and n the pin number.
                            Notation for signals is PORTx_PINn. All pins can be used as event input.
                        2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full
                            asynchronous detection.
                        3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
4. Electrical Characteristics
4.1        Disclaimer
           All typical values are measured at T = 25°C and VDD = 3V unless otherwise specified. All minimum and
           maximum values are valid across operating temperature and voltage unless otherwise specified.
           Typical values given should be considered for design guidance only, and actual part variation around
           these values is expected.
           Note: 
            1.    – If VPIN is lower than GND-0.6V, then a current limiting resistor is required. The negative DC
                    injection current limiting resistor is calculated as R = (GND-0.6V – Vpin)/ICn.
                  – If VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC
                    injection current limiting resistor is calculated as R = (Vpin-(VDD+0.6))/ICn.
Note: 
 1. Operation is guaranteed down to 1.8V or VBOD with BODLEVEL0, whichever is lower.
Table 4-3. Operating Voltage and Frequency
Note: 
 1. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL0.
 2. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL2.
 3. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL7.
 4. These specifications do not apply to automotive range parts (-VAO).
The maximum CPU clock frequency depends on VDD. As shown in the figure below, the Maximum
Frequency vs. VDD is linear between 1.8V < VDD < 2.7V and 2.7V < VDD < 4.5V.
20MHz
      10MHz
                                                 Safe Operating Area
5MHz
  • System power consumption measured with peripherals disabled and I/O ports driven low with inputs
    disabled
Table 4-5. Power Consumption in Active and Idle Mode
      ...........continued
       Mode           Description          Condition                         Typ.    Max.          Max.         Unit
                                                                             25°C    85°C(1)       125°C
       Power          Power down/         All peripherals         VDD=3V 0.1         5.0           15.0         µA
       Down/          Standby power       stopped
       Standby        consumption are the
                      same when all
                      peripherals are
                      stopped
       Reset          Reset power          RESET line pulled low VDD=3V 100          -             -            µA
                      consumption
      Note: 
       1. These parameters are for design guidance only and are not tested.
      ...........continued
       Peripheral                          Conditions                                       Typ.(1)      Unit
       XOSC32K                             CL=7.5 pF                                        0.5          µA
       OSCULP32K                                                                            0.4          µA
       USART                               Enable @ 9600 Baud                               13.0         µA
       SPI (Master)                        Enable @ 100 kHz                                 2.1          µA
       TWI (Master)                        Enable @ 100 kHz                                 24.0         µA
       TWI (Slave)                         Enable @ 100 kHz                                 17.0         µA
       Flash programming                   Erase Operation                                  1.5          mA
                                           Write Operation                                  3.0
      Note: 
       1. Current consumption of the module only. To calculate the total internal power consumption of the
           microcontroller, add this value to the base power consumption given in “Power Consumption”
           section in electrical characteristics.
       2. CPU in Standby mode.
       3. Average power consumption with ADC active in Free-Running mode.
      Note: 
       1. For design guidance only and not tested in production.
       2. A slope faster than the maximum rating can trigger a reset of the device if changing the voltage
           level after an initial power-up.
      Table 4-9. Power-on Reset (POR) Characteristics
      Note: 
       1. For design guidance only and not tested in production.
      Note: 
       1. These parameters are for design guidance only and are not production tested.
...........continued
 Symbol      Description                         Condition                                  Min. Typ. Max. Unit
 fCAL        Frequency calibration range         OSC16M(2)                                  14.5           17.5 MHz
                                                 OSC20M(2)                                  18.5           21.5 MHz
 ETOTAL      Total error with 16 MHz and 20 From target               TA=25°C, 3.0V         -1.5           1.5   %
             MHz frequency selection        frequency
                                                                      TA=[0, 70]°C,   -2.0                 2.0   %
                                                                      VDD=[1.8, 3.6]V
                                                                      Full operation        -4.0           4.0
                                                                      range
 EDRIFT      Accuracy with 16 MHz and 20         Factory calibrated   TA=[0, 70]°C,   -1.8                 1.8   %
             MHz frequency selection             VDD=3V(1)            VDD=[1.8, 5.5]V
             relative to the factory-stored
             frequency value
 ΔfOSC20M Calibration step size                                                             -        0.75 -      %
 DOSC20M Duty cycle                                                                         -        50    -     %
 tstartup    Start-up time                       Within 2%                                  -        12    -     µs
                                                 accuracy
Note: 
 1. See also the description of OSC20M on calibration.
 2. Oscillator Frequencies above speed specification must be divided so the CPU clock is always
     within specification.
Table 4-13. 32.768 kHz Internal Oscillator (OSCULP32K) Characteristics
       ...........continued
        Symbol            Description                                          Condition          Min. Typ.               Max. Unit
        ESR(1)            Equivalent Series Resistance - Safety Factor=3       CL=7.5 pF          -           -           80   kΩ
                                                                           
                                                                               CL=12.5 pF -                   -           40
                                                                                  
       Note: 
        1. This parameter is for design guidance only and not production tested.
       Figure 4-2. External Clock Waveform Characteristics
V IH1
V IL1
        Symbol Description                    Condition VDD=[1.8, 5.5]V VDD=[2.7, 5.5]V VDD=[4.5, 5.5]V Unit
                                                         Min.    Max.          Min.      Max.             Min.        Max.
        fCLCL       Frequency                            0       5.0           0.0       10.0             0.0         20.0     MHz
        tCLCL       Clock Period                         200     -             100       -                50          -        ns
        tCHCX(1)    High Time                            80      -             40        -                20          -        ns
        tCLCX(1)    Low Time                             80      -             40        -                20          -        ns
        tCLCH(1)    Rise Time (for                       -       40            -         20               -           10       ns
                                                                                              
                    maximum frequency)
        tCHCL(1)    Fall Time (for maximum               -       40            -         20               -           10       ns
 
                    frequency)
        ΔtCLCL(1) Change in period from                  -       20            -         20               -           20       %
                  one clock cycle to the
                  next
       Note: 
        1. This parameter is for design guidance only and not production tested.
...........continued
 Symbol Description                                Condition              Min.      Typ.     Max.       Unit
 IIH / IIL   I/O pin Input Leakage Current         VDD=5.5V, pin high     -         < 0.05 -            µA
                                                   VDD=5.5V, pin low      -         < 0.05 -
 VOL         I/O pin drive strength                VDD=1.8V, IOL=1.5 mA   -         -        0.36       V
                                                   VDD=3.0V, IOL=7.5 mA   -         -        0.6
                                                   VDD=5.0V, IOL=15 mA    -         -        1
 VOH         I/O pin drive strength                VDD=1.8V, IOH=1.5 mA 1.44        -        -          V
                                                   VDD=3.0V, IOH=7.5 mA 2.4         -        -
                                                   VDD=5.0V, IOH=15 mA    4         -        -
 Itotal      Maximum combined I/O sink/            TA=125°C               -         -        100        mA
             source current per pin group(1,2)
             Maximum combined I/O sink/            TA=25°C                -         -        200
             source current per pin group(1,2)
 tRISE       Rise time                             VDD=3.0V, load=20 pF   -         2.5      -          ns
                                                   VDD=5.0V, load=20 pF   -         1.5      -
                                                   VDD=3.0V, load=20 pF, -          19       -
                                                   slew rate enabled
                                                   VDD=5.0V, load=20 pF, -          9        -
                                                   slew rate enabled
 tFALL       Fall time                             VDD=3.0V, load=20 pF   -         2.0      -          ns
                                                   VDD=5.0V, load=20 pF   -         1.3      -
                                                   VDD=3.0V, load=20 pF, -          21       -
                                                   slew rate enabled
                                                   VDD=5.0V, load=20 pF, -          11       -
                                                   slew rate enabled
 Cpin        I/O pin capacitance except for                               -         3.5      -          pF
             TOSC, VREFA, and TWI pins
 Cpin        I/O pin capacitance on TOSC pins                             -         4        -          pF
 Cpin        I/O pin capacitance on TWI pins                              -         10       -          pF
 Cpin        I/O pin capacitance on VREFA pin                             -         14       -          pF
 Rp          Pull-up resistor                                             20        35       50         kΩ
       Note: 
        1. Pin group A (PA[7:0]), PF[6:2]), pin group B (PB[7:0], PC[7:0]), pin group C (PD:7:0, PE[3:0],
            PF[1:0]). For 28-pin and 32-pin devices pin group A and B should be seen as a single group. The
            combined continuous sink/source current for each individual group should not exceed the limits.
        2. These parameters are for design guidance only and are not production tested.
4.11   USART
       Figure 4-3. USART in SPI Mode - Timing Requirements in Master Mode
                             SS
                          SCK
                     (CPOL = 0)
                                                                                                            tSCKW
                          SCK
                     (CPOL = 1)
                                                                                        tSCKW
                                          tMIS     tMIH                                           tSCK
                          MISO
                                                 MSb                                              LSb
                    (Data Input)
tMOH tMOH
                          MOSI
                   (Data Output)                  MSb                                                 LSb
       Note: 
        1. These parameters are for design guidance only and are not production tested.
4.12   SPI
       Figure 4-4. SPI - Timing Requirements in Master Mode
                             SS
                          SCK
                     (CPOL = 0)
                                                                                                                    tSCKW
                          SCK
                     (CPOL = 1)
                                                                                               tSCKW
                                              tMIS     tMIH                                                tSCK
                          MISO
                                                     MSb                                                   LSb
                    (Data Input)
tMOH tMOH
                          MOSI
                   (Data Output)                      MSb                                                     LSb
SS
                          SCK
                     (CPOL = 0)
                                                                                                                    tSSCKW
                          SCK
                     (CPOL = 1)
                                                                                               tSSCKW
                                              tSIS          tSIH                                           tSSCK
                          MOSI
                                                      MSb                                                     LSb
                    (Data Input)
                          MISO
                   (Data Output)                           MSb                                                LSb
       ...........continued
        Symbol(1)           Description                                 Condition         Min.          Typ.              Max.   Unit
        fSSCK               Slave SCK clock frequency                   Slave             -             -                 5      MHz
        tSSCK               Slave SCK period                            Slave             4*t Clkper    -                 -      ns
        tSSCKW              SCK high/low width                          Slave             2*t Clkper    -                 -      ns
        tSSCKR              SCK rise time                               Slave             -             -                 1600   ns
        tSSCKF              SCK fall time                               Slave             -             -                 1600   ns
        tSIS                MOSI setup to SCK                           Slave             3.0           -                 -      ns
        tSIH                MOSI hold after SCK                         Slave             t Clkper      -                 -      ns
        tSSS                SS setup to SCK                             Slave             21            -                 -      ns
        tSSH                SS hold after SCK                           Slave             20            -                 -      ns
        tSOS                MISO setup to SCK                           Slave             -             8.0               -      ns
        tSOH                MISO hold after SCK                         Slave             -             13                -      ns
        tSOSS               MISO setup after SS low                     Slave             -             11                -      ns
        tSOSH               MISO hold after SS low                      Slave             -             8.0               -      ns
       Note: 
        1. These parameters are for design guidance only and are not production tested.
4.13   TWI
       Figure 4-6. TWI - Timing Requirements
                                            t of          t HIGH                                                     tr
t LOW t LOW
       SCL
                 t SU;STA              t HD;STA              t HD;DAT               t SU;DAT
                                                                                                               t SU;STO
       SDA
t BUF
...........continued
 Symbol(1) Description               Condition                    Min.           Typ. Max.            Unit
 VHYS          Hysteresis of                                      0.1×VDD            0.4×VDD          V
               Schmitt trigger
               inputs
 VOL           Output low voltage Iload=20 mA, Fast mode+         -              -   0.2xVDD          V
                                     Iload=3 mA, Normal mode,     -              -   0.4V
                                     VDD>2V
                                     Iload=3 mA, Normal mode,     -              -   0.2×VDD
                                     VDD≤2V
 IOL           Low-level output      fSCL≤400 kHz, VOL=0.4V       3              -   -                mA
               current
                                     fSCL≤1 MHz, VOL=0.4V         20             -   -
 CB            Capacitive load for fSCL≤100 kHz                   -              -   400              pF
               each bus line
                                   fSCL≤400 kHz                   -              -   400
                                     fSCL≤1 MHz                   -              -   550
 tR            Rise time for both    fSCL≤100 kHz                 -              -   1000             ns
               SDA and SCL
                                     fSCL≤400 kHz                 20             -   300
                                     fSCL≤1 MHz                   -              -   120
 tOF           Output fall time      10 pF <          fSCL≤400    20+0.1×CB      -   300              ns
               from VIHmin to        capacitance of   kHz
               VILmax                bus line < 400
                                                      fSCL≤1 MHz 20+0.1×CB       -   120
                                     pF
 tSP           Spikes suppressed                                  0              -   50               ns
               by the input filter
 IL            Input current for     0.1×VDD<VI<0.9×VDD           -              -   1                µA
               each I/O pin
 CI            Capacitance for                                    -              -   10               pF
               each I/O pin
 RP            Value of pull-up      fSCL≤100 kHz                 (VDD-          -   1000 ns/         Ω
               resistor                                           VOL(max)) /I       (0.8473×CB)
                                                                  OL
       ...........continued
        Symbol(1) Description               Condition                    Min.          Typ. Max.                    Unit
        tLOW          Low period of SCL fSCL≤100 kHz                     4.7           -        -                   µs
                      Clock
                                        fSCL≤400 kHz                     1.3           -        -
                                            fSCL≤1 MHz                   0.5           -        -
        tHIGH         High period of SCL fSCL≤100 kHz                    4.0           -        -                   µs
                      Clock
                                         fSCL≤400 kHz                    0.6           -        -
                                            fSCL≤1 MHz                   0.26          -        -
        tSU;STA       Setup time for a      fSCL≤100 kHz                 4.7           -        -                   µs
                      repeated Start
                                            fSCL≤400 kHz                 0.6           -        -
                      condition
                                            fSCL≤1 MHz                   0.26          -        -
        tHD;DAT       Data hold time        fSCL≤100 kHz                 0             -        3.45                µs
                                            fSCL≤400 kHz                 0             -        0.9
                                            fSCL≤1 MHz                   0             -        0.45
        tSU;DAT       Data setup time       fSCL≤100 kHz                 250           -        -                   ns
                                            fSCL≤400 kHz                 100           -        -
                                            fSCL≤1 MHz                   50            -        -
        tSU;STO       Setup time for        fSCL≤100 kHz                 4             -        -                   µs
                      Stop condition
                                            fSCL≤400 kHz                 0.6           -        -
                                            fSCL≤1 MHz                   0.26          -        -
        tBUF          Bus free time       fSCL≤100 kHz                   4.7           -        -                   µs
                      between a Stop
                                          f ≤400 kHz                     1.3           -        -
                      and Start condition SCL
                                          fSCL≤1 MHz                     0.5           -        -
       Note: 
        1. These parameters are for design guidance only and are not production tested.
4.14   VREF
       Table 4-20. Internal Voltage Reference Characteristics
...........continued
 Symbol(1)           Description                                        Min.     Typ.       Max.    Unit
 VDD                 Power supply voltage range for 0V55                1.8      -          5.5     V
                     Power supply voltage range for 1V1                 1.8      -          5.5
                     Power supply voltage range for 1V5                 1.8      -          5.5
                     Power supply voltage range for 2V5                 3.0      -          5.5
                     Power supply voltage range for 4V3                 4.8      -          5.5
Note: 
 1. These parameters are for design guidance only and are not production tested.
Table 4-21. ADC Internal Voltage Reference Characteristics(1)
Note: 
 1. These values are based on characterization and not covered by production test limits.
 2. The symbols xxxx refer to the respective values of the ADC0REFSEL bit field in the VREF.CTRLA
     register.
Table 4-22. AC Internal Voltage Reference Characteristics(1)
         Note: 
          1. These values are based on characterization and not covered by production test limits.
          2. The symbols xxxx refer to the respective values of the AC0REFSEL bit field in the VREF.CTRLA
              register.
4.15 ADC
...........continued
 Symbol Description                            Conditions                   Min. Typ. Max. Unit
 TSTART      Start-up time                     Internal VREF                -        22    -       µs
Note: 
 1. These parameters are for design guidance only and are not production tested.
Table 4-25. Accuracy Characteristics Internal Reference(2)
         ...........continued
          Symbol Description                Conditions                              Min.     Typ.     Max.     Unit
          EABS        Absolute              REFSEL =            T=[0-105]°C         -        <10      -        LSB
                      accuracy              INTERNAL
                                                                VDD = [1.8V-3.6V]
                                            VREF = 1.1V
                                                                VDD = [1.8V-3.6V]   -        <15      -
                                            REFSEL = VDD                            -        2.5      -
                                            REFSEL =                                -        <35      -
                                            INTERNAL
          EGAIN       Gain error            REFSEL =            T=[0-105]°C         -        ±15      -        LSB
                                            INTERNAL
                                                                VDD = [1.8V-3.6V]
                                            VREF = 1.1V
                                                                VDD = [1.8V-3.6V]   -        ±20      -
                                            REFSEL = VDD                            -        2        -
                                            REFSEL =                                -        ±35      -
                                            INTERNAL
          EOFF        Offset error          REFSEL =                                -        -1       -        LSB
                                            INTERNAL
                                            VREF = 0.55V
                                            REFSEL =                                -        -0.5     -        LSB
                                            INTERNAL
                                            1.1V ≤ VREF
         Note: 
          1. A DNL error of less than or equal to 1 LSB ensures a monotonic transfer function with no missing
              codes.
          2. These parameters are for design guidance only and are not production tested.
          3. Reference setting and fADC must fulfill the specification in “Clock and Timing Characteristics” and
              “Power supply, Reference, and Input Range” tables.
       Note: 
        1. A DNL error of less than or equal to 1 LSB ensures a monotonic transfer function with no missing
            codes.
        2. These parameters are for design guidance only and are not production tested.
4.16   AC
       Table 4-27. Analog Comparator Characteristics, Low-Power Mode Disabled
       ...........continued
        Symbol        Description                 Condition                     Min.       Typ.      Max.    Unit
        VHYS          Hysteresis                  HYSMODE=0x0                   -          0         -       mV
                                                  HYSMODE=0x1                   -          10        -
                                                  HYSMODE=0x2                   -          25        -
                                                  HYSMODE=0x3                   -          50        -
        tPD           Propagation delay           25 mV Overdrive, VDD≥2.7V     -          50        -       ns
       Note: 
        1. These parameters are for design guidance only and are not production tested.
5. Typical Characteristics
6.0
5.0
4.0
3.0
2.0
1.0
                0.0
                      0     2      4        6     8         10          12   14    16     18    20
                                                      Frequency [MHz]
        Figure 5-2.  Active Supply Current vs. Frequency [0.1, 1.0] MHz at T=25°C
               600                                                                                VDD [V]
                                                                                                         1.8
               550                                                                                       2.2
               500                                                                                       2.7
                                                                                                         3
               450                                                                                       3.6
                                                                                                         4.2
               400                                                                                       5
               350                                                                                       5.5
300
250
200
150
100
50
                 0
                     0.0   0.1    0.2      0.3   0.4        0.5      0.6     0.7   0.8    0.9   1.0
                                                   Frequency [MHz]
Figure 5-3.  Active Supply Current vs. Temperature (f=20 MHz OSC20M)
       12.0                                                                              VDD [V]
                                                                                            4.5
       11.0                                                                                 5
       10.0                                                                                 5.5
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
        0.0
           -40      -20       0     20         40            60     80     100     120
                                          Temperature [°C]
Figure 5-4.  Active Supply Current vs. VDD (f=[1.25, 20] MHz OSC20M) at T=25°C
       12.0                                                                              Frequency [MHz]
                                                                                            1.25
       11.0                                                                                 2.5
       10.0                                                                                 5
                                                                                            10
        9.0                                                                                 20
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
        0.0
              1.5   2.0       2.5   3.0          3.5          4.0    4.5     5.0     5.5
                                              Vdd [V]
16
12
                0
                    1.5    2.0         2.5       3.0            3.5           4.0        4.5        5.0        5.5
                                                              Vdd [V]
2.5
2.0
1.5
1.0
0.5
                0.0
                      0    2       4         6         8         10          12     14         16         18    20
                                                           Frequency [MHz]
Figure 5-7.  Idle Supply Current vs. Low Frequency (0.1-1.0 MHz) at T=25°C
       250                                                                                                   VDD [V]
                                                                                                                1.8
       225                                                                                                      2.2
                                                                                                                2.7
       200                                                                                                      3
                                                                                                                3.6
       175                                                                                                      4.2
                                                                                                                5
       150                                                                                                      5.5
125
100
75
50
25
         0
             0.0   0.1     0.2       0.3        0.4     0.5      0.6      0.7        0.8         0.9     1.0
                                                  Frequency [MHz]
Figure 5-8.  Idle Supply Current vs. Temperature (f=20 MHz OSC20M)
        5.0                                                                                                  VDD [V]
                                                                                                                4.5
        4.5                                                                                                     5
                                                                                                                5.5
        4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
        0.0
           -40       -20         0         20          40            60         80         100         120
                                                  Temperature [°C]
        Figure 5-9.  Idle Supply Current vs. VDD (f=32.768 kHz OSCULP32K)
               20                                                                            Temperature [°C]
                                                                                                 -40
               18                                                                                -20
                                                                                                 0
               16                                                                                25
                                                                                                 70
               14                                                                                85
                                                                                                 105
               12                                                                                125
10
                0
                    1.5    2.0       2.5   3.0         3.5          4.0   4.5    5.0     5.5
                                                    Vdd [V]
4.0
3.0
2.0
1.0
                0.0
                   -40      -20       0    20         40            60    80    100    120
                                                 Temperature [°C]
Figure 5-11.  Power-Down Mode Supply Current vs. VDD (all functions disabled)
        8.0                                                                                 Temperature [°C]
                                                                                                      -40
                                                                                                      -20
        7.0
                                                                                                      0
                                                                                                      25
        6.0                                                                                           70
                                                                                                      85
                                                                                                      105
        5.0
                                                                                                      125
4.0
3.0
2.0
1.0
        0.0
              1.5         2.0         2.5    3.0     3.5         4.0         4.5    5.0   5.5
                                                   Vdd [V]
Figure 5-12.  Power-Down Mode Supply Current vs. VDD (all functions disabled)
              8.0                                                                                 Temperature [°C]
                                                                                                        -40
                                                                                                        -20
              7.0
                                                                                                        0
                                                                                                        25
              6.0                                                                                       70
                                                                                                        85
                                                                                                        105
              5.0
                                                                                                        125
4.0
3.0
2.0
1.0
              0.0
                    2.5         3.0         3.5            4.0         4.5         5.0          5.5
                                                     Vdd [V]
5.0
4.0
3.0
2.0
1.0
                0.0
                      1.5   2.0       2.5   3.0     3.5        4.0     4.5    5.0   5.5
                                                  Vdd [V]
        Figure 5-14.  Standby Mode Supply Current vs. VDD (Sampled BOD running at 125 Hz)
               10.0                                                                   Temperature [°C]
                                                                                          -40
                9.0                                                                       -20
                                                                                          0
                8.0                                                                       25
                                                                                          70
                7.0                                                                       85
                                                                                          105
                6.0                                                                       125
5.0
4.0
3.0
2.0
1.0
                0.0
                      1.5   2.0       2.5   3.0     3.5        4.0     4.5    5.0   5.5
                                                  Vdd [V]
        Figure 5-15.  Standby Mode Supply Current vs. VDD (Sampled BOD running at 1 kHz)
               10.0                                                                                               Temperature [°C]
                                                                                                                      -40
                9.0                                                                                                   -20
                                                                                                                      0
                8.0                                                                                                   25
                                                                                                                      70
                7.0                                                                                                   85
                                                                                                                      105
                6.0                                                                                                   125
5.0
4.0
3.0
2.0
1.0
                0.0
                      1.5    2.0          2.5         3.0           3.5           4.0         4.5     5.0   5.5
                                                                  Vdd [V]
200
160
120
80
40
                 0
                     0.0    0.5     1.0         1.5         2.0             2.5         3.0     3.5   4.0   4.5
                                                              Vdd [V]
5.2 GPIO
1.0
0.8
0.6
0.4
0.2
                         0.0
                            1.5   2.0   2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                                    Vdd [V]
65
60
                         55
         Threshold [%]
50
45
40
35
30
                         25
                           1.5    2.0   2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                                    Vdd [V]
50
45
40
35
30
                   25
                     1.5   2.0   2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                             Vdd [V]
50
45
40
35
30
                   25
                     1.5   2.0   2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                             Vdd [V]
                                                                                                     125
                0.25
0.20
0.15
0.10
0.05
                0.00
                       0.0   0.2   0.4   0.6   0.8        1.0      1.2     1.4   1.6   1.8   2.0
                                                Sink current [mA]
0.25
0.20
0.15
0.10
0.05
                0.00
                       0     1     2     3     4           5           6    7     8     9    10
                                                   Sink current [mA]
0.5
0.4
0.3
0.2
0.1
                0.0
                      0   2   4    6   8          10       12    14    16      18   20
                                           Sink current [mA]
0.5
0.4
0.3
0.2
0.1
                0.0
                      0   2   4    6   8          10       12   14    16       18   20
                                       Sink current [mA]
1.55
1.50
1.45
1.40
1.35
       1.30
              0.0   0.2   0.4      0.6   0.8      1.0       1.2   1.4   1.6     1.8   2.0
                                          Source current [mA]
2.5
2.4
2.3
2.2
2.1
       2.0
             0      1     2        3     4        5        6      7     8       9     10
                                         Source current [mA]
4.5
4.4
4.3
4.2
4.1
                4.0
                      0   2   4    6   8       10       12    14    16       18   20
                                       Source current [mA]
2.5
2.0
1.5
1.0
0.5
                0.0
                      0   2   4    6   8        10       12   14    16       18   20
                                       Source current [mA]
1.0
0.8
0.5
0.3
        0.0
              0    5      10       15       20        25        30      35   40    45   50
                                        Pull-up resistor current [µA]
Figure 5-30. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD=3.0V)
       3.0                                                                                   Temperature [°C]
                                                                                                 -40
                                                                                                 -20
       2.8
                                                                                                 0
                                                                                                 25
       2.5                                                                                       70
                                                                                                 85
                                                                                                 105
       2.3
                                                                                                 125
2.0
1.8
1.5
1.3
       1.0
             0    5      10        15      20        25        30       35   40    45   50
                                        Pull-up resistor current [µA]
      Figure 5-31. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD=5.0V)
                          5.0                                                                                               Temperature [°C]
                                                                                                                                -40
                                                                                                                                -20
                          4.8
                                                                                                                                0
                                                                                                                                25
                          4.5                                                                                                   70
                                                                                                                                85
                                                                                                                                105
                          4.3
                                                                                                                                125
4.0
3.8
3.5
3.3
                          3.0
                                0   5         10       15      20        25        30       35        40         45    50
                                                            Pull-up resistor current [µA]
0.4
                           0.2
         Vref error [%]
0.0
-0.2
-0.4
-0.6
-0.8
                          -1.0
                              -40       -20        0         20          40            60        80        100        120
                                                                    Temperature [°C]
0.4
                    0.2
   Vref error [%]
0.0
-0.2
-0.4
-0.6
-0.8
                    -1.0
                        -40   -20   0   20        40            60   80   100   120
                                             Temperature [°C]
0.6
0.4
                    0.2
   Vref error [%]
0.0
-0.2
-0.4
-0.6
-0.8
                    -1.0
                        -40   -20   0   20        40            60   80   100   120
                                             Temperature [°C]
0.6
0.4
                          0.2
         Vref error [%]
0.0
-0.2
-0.4
-0.6
-0.8
                          -1.0
                              -40   -20    0    20         40            60    80    100    120
                                                      Temperature [°C]
25
20
15
10
                           0
                            1.5     2.0   2.5   3.0        3.5           4.0   4.5    5.0    5.5
                                                         Vdd [V]
2.5
2.0
1.5
1.0
0.5
              0.0
                 1.5   2.0    2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                          Vdd [V]
2.5
2.0
1.5
1.0
0.5
              0.0
                 1.5   2.0    2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                          Vdd [V]
1.86
1.84
                   1.82
   BOD level [V]
1.80
1.78
1.76
1.74
1.72
                   1.70
                       -40   -20   0   20        40            60   80   100   120
                                            Temperature [°C]
2.70
                   2.68
   BOD level [V]
2.66
2.64
2.62
2.60
2.58
2.56
4.30
                                   4.28
         BOD level [V]
4.26
4.24
4.22
4.20
4.18
4.16
6.0
5.0
4.0
3.0
2.0
1.0
                                    0.0
                                       1.5   2.0   2.5   3.0          3.5          4.0    4.5     5.0     5.5
                                                                   Vdd [V]
Figure 5-43. Absolute Accuracy vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
                             10.0                                                                           Temperature [°C]
                                                                                                                -40
                              9.0                                                                               25
                                                                                                                85
                              8.0                                                                               105
                              7.0
   Absolute Accuracy [LSb]
6.0
5.0
4.0
3.0
2.0
1.0
                              0.0
                                      1.1          1.5            2.5             4.3           VDD
                                                               Vref [V]
Figure 5-44. DNL Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
                             2.0                                                                        Vref [V]
                                                                                                              1.1
                             1.8                                                                              1.5
                                                                                                              2.5
                             1.6                                                                              4.3
                                                                                                              VDD
                             1.4
                             1.2
   DNL [LSb]
1.0
0.8
0.6
0.4
0.2
                             0.0
                                1.5    2.0   2.5         3.0     3.5        4.0         4.5   5.0     5.5
                                                               Vdd [V]
Figure 5-45. DNL vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
                2.0                                                                           Temperature [°C]
                                                                                                   -40
                1.8                                                                                25
                                                                                                   85
                1.6                                                                                105
1.4
                1.2
   DNL [LSb]
1.0
0.8
0.6
0.4
0.2
                0.0
                          1.1               1.5           2.5              4.3         VDD
                                                        Vref [V]
Figure 5-46. Gain Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
                8.0                                                                            Vref [V]
                                                                                                   1.1
                7.0                                                                                1.5
                                                                                                   2.5
                6.0                                                                                4.3
                                                                                                   VDD
                5.0
                4.0
   Gain [LSb]
3.0
2.0
1.0
0.0
-1.0
                -2.0
                    1.5         2.0   2.5         3.0      3.5       4.0         4.5   5.0   5.5
                                                         Vdd [V]
Figure 5-47. Gain Error vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
                8.0                                                                       Temperature [°C]
                                                                                              -40
                7.0
                                                                                              25
                                                                                              85
                                                                                              105
                6.0
                5.0
   Gain [LSb]
4.0
3.0
2.0
1.0
                0.0
                         1.1           1.5           2.5              4.3         VDD
                                                   Vref [V]
Figure 5-48. INL vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
                2.0                                                                       Vref [V]
                                                                                              1.1
                1.8                                                                           1.5
                                                                                              2.5
                1.6                                                                           4.3
                                                                                              VDD
                1.4
                1.2
   INL [LSb]
1.0
0.8
0.6
0.4
0.2
                0.0
                   1.5     2.0   2.5         3.0     3.5        4.0         4.5   5.0   5.5
                                                   Vdd [V]
Figure 5-49. INL vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
                     2.0                                                                               Temperature [°C]
                                                                                                            -40
                     1.8                                                                                    25
                                                                                                            85
                     1.6                                                                                    105
1.4
                     1.2
   INL [LSb]
1.0
0.8
0.6
0.4
0.2
                     0.0
                               1.1               1.5               2.5              4.3         VDD
                                                       Vref [V]
Figure 5-50. Offset Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
                     2.0                                                                                Vref [V]
                                                                                                            1.1
                     1.6                                                                                    1.5
                                                                                                            2.5
                     1.2                                                                                    4.3
                                                                                                            VDD
                     0.8
                     0.4
      Offset [LSb]
0.0
-0.4
-0.8
-1.2
-1.6
                     -2.0
                         1.5         2.0   2.5         3.0          3.5       4.0         4.5   5.0   5.5
                                                                  Vdd [V]
Figure 5-51. Offset Error vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
                             2.0                                                                          Temperature [°C]
                                                                                                              -40
                             1.6                                                                              25
                                                                                                              85
                             1.2                                                                              105
0.8
                             0.4
   Offset[LSb]
0.0
-0.4
-0.8
-1.2
-1.6
                             -2.0
                                       1.1               1.5           2.5            4.3         VDD
                                                                     Vref [V]
Figure 5-52. Absolute Accuracy vs. VDD (fADC=115 ksps, T=25°C), REFSEL = External Reference
                              7.0
   Absolute Accuracy [LSb]
6.0
5.0
4.0
3.0
2.0
1.0
                              0.0
                                 1.5         2.0   2.5         3.0      3.5     4.0         4.5   5.0   5.5
                                                                     Vdd [V]
Figure 5-53. Absolute Accuracy vs. VREF (VDD=5.0V, fADC=115 ksps, REFSEL = External Reference)
                              7.0
   Absolute Accuracy [LSb]
6.0
5.0
4.0
3.0
2.0
1.0
                              0.0
                                      1.8          2.6                4.096              4.3
                                                         Vref [V]
Figure 5-54. DNL vs. VDD (fADC=115 ksps, T=25°C, REFSEL = External Reference)
1.4
                             1.2
   DNL [LSb]
1.0
0.8
0.6
0.4
0.2
                             0.0
                                1.5   2.0   2.5   3.0      3.5        4.0     4.5    5.0       5.5
                                                         Vdd [V]
Figure 5-55. DNL vs. VREF (VDD=5.0V, fADC=115 ksps, REFSEL = External Reference)
1.4
                1.2
   DNL [LSb]
1.0
0.8
0.6
0.4
0.2
                0.0
                          1.8         2.6              4.096          4.3
                                            Vref [V]
Figure 5-56. Gain vs. VDD (fADC=115 ksps, T=25°C, REFSEL = External Reference)
5.0
                4.0
   Gain [LSb]
3.0
2.0
1.0
0.0
-1.0
                -2.0
                    1.5   2.0   2.5   3.0      3.5      4.0    4.5    5.0   5.5
                                             Vdd [V]
Figure 5-57. Gain vs. VREF (VDD=5.0V, fADC=115 ksps, REFSEL = External Reference)
                5.0
   Gain [LSb]
4.0
3.0
2.0
1.0
                0.0
                         1.8         2.6               4.096           4.3
                                           Vref [V]
Figure 5-58. INL vs. VDD (fADC=115 ksps, T=25°C, REFSEL = External Reference)
1.4
                1.2
   INL [LSb]
1.0
0.8
0.6
0.4
0.2
                0.0
                   1.5   2.0   2.5   3.0     3.5        4.0    4.5     5.0   5.5
                                           Vdd [V]
Figure 5-59. INL vs. VREF (VDD=5.0V, fADC=115 ksps, REFSEL = External Reference)
1.4
                  1.2
   INL [LSb]
1.0
0.8
0.6
0.4
0.2
                  0.0
                            1.8         2.6              4.096          4.3
                                              Vref [V]
Figure 5-60. Offset vs. VDD (fADC=115 ksps, T=25°C, REFSEL = External Reference)
0.8
                  0.4
   Offset [LSb]
0.0
-0.4
-0.8
-1.2
-1.6
                  -2.0
                      1.5   2.0   2.5   3.0      3.5      4.0    4.5    5.0   5.5
                                               Vdd [V]
Figure 5-61. Offset vs. VREF (VDD=5.0V, fADC=115 ksps, REFSEL = External Reference)
0.8
                           0.4
         Offset [LSb]
0.0
-0.4
-0.8
-1.2
-1.6
                           -2.0
                                          1.8                 2.6                      4.096                4.3
                                                                      Vref [V]
5.6   AC Characteristics
      Figure 5-62. Hysteresis vs. VCM - 10 mV (VDD=5V)
                           20                                                                                         Temperature [°C]
                                                                                                                            -40
                           18                                                                                               -20
                                                                                                                            0
                           16                                                                                               25
                                                                                                                            55
                           14
                                                                                                                            85
                                                                                                                            105
         Hysteresis [mV]
                           12
                                                                                                                            125
                           10
                            0
                             -0.5   0.0     0.5   1.0   1.5     2.0    2.5       3.0      3.5   4.0   4.5     5.0   5.5
                                                               Vcommon mode [V]
                     56
   Hysteresis [mV]
48
40
32
24
16
                      0
                       -0.5     0.0    0.5    1.0    1.5    2.0    2.5     3.0    3.5    4.0    4.5    5.0    5.5
                                                            Vcommon mode [V]
                                                                                                                        125
                      5.0
4.0
3.0
2.0
1.0
                      0.0
                         -0.5    0.0    0.5    1.0    1.5    2.0    2.5     3.0    3.5    4.0    4.5    5.0    5.5
                                                             Vcommon mode [V]
                       6
         Offset [mV]
                       0
                        -0.5     0.0        0.5   1.0   1.5        2.0      2.5     3.0        3.5   4.0   4.5     5.0   5.5
                                                               Vcommon mode [V]
0.6
0.4
0.2
                       0.0
                             0         16          32         48             64           80          96         112     128
                                                                         OSCCAL [x1]
20
18
16
14
12
       10
            0      16        32    48         64           80   96    112    128
                                         OSCCAL [x1]
20.0
19.9
19.8
19.7
19.6
       19.5
           -40      -20       0    20        40            60   80   100    120
                                        Temperature [°C]
20.0
19.9
19.8
19.7
19.6
                           19.5
                                  1.5   2.0   2.5   3.0         3.5          4.0    4.5     5.0     5.5
                                                              Vdd [V]
36.0 5.5
35.0
34.0
33.0
32.0
31.0
                           30.0
                               -40      -20   0     20         40            60    80     100     120
                                                          Temperature [°C]
                     36.0
                                                                                         125
                     35.0
34.0
33.0
32.0
31.0
                     30.0
                         1.5   2.0   2.5   3.0     3.5     4.0    4.5        5.0   5.5
                                                 Vdd [V]
6.   Ordering Information
       • Available ordering options can be found by:
          – Clicking on one of the following product page links:
               • ATmega809 Product Page
               • ATmega1609 Product Page
               • ATmega3209 Product Page
               • ATmega4809 Product Page
          – Searching by product name at microchipdirect.com
          – Contacting your local sales representative
     Note:  Tape and Reel identifier only appears in the catalog part number description. This identifier is
     used for ordering purposes. Check with your Microchip Sales Office for package availability with the Tape
     and Reel option.
8. Package Drawings
             Note:    For the most current package drawings, please see the Microchip Packaging Specification located at
                      http://www.microchip.com/packaging
                       48X TIPS
                            0.20 C A-B D
                                                                     D
                                                                    D1
                                                           D1
                                                           2
A B
E1 E
                                                                                                       E1
                                                                                 A               A     2
                                         E1
                                         4    N
                           NOTE 1                    1 2                                 4X
                                                      D1                                      0.20 H A-B D
                                                      4
                                                                                        48x b
                                                                e                           0.08       C A-B D
TOP VIEW
                                                                                                       0.10 C          H
                       C          A2
                           A
             SEATING
              PLANE                                                                                         0.08 C
A1 SIDE VIEW
       Note:    For the most current package drawings, please see the Microchip Packaging Specification located at
                http://www.microchip.com/packaging
                                                        
                                           L
                                    (L1)
SECTION A-A
                                                              Units             MILLIMETERS
                                                   Dimension Limits      MIN        NOM           MAX
                             Number of Leads                   N                      48
                             Lead Pitch                         e                  0.50 BSC
                             Overall Height                    A           -           -          1.20
                             Standoff                          A1        0.05          -          0.15
                             Molded Package Thickness          A2        0.95        1.00         1.05
                             Foot Length                        L        0.45        0.60         0.75
                             Footprint                         L1                  1.00 REF
                             Foot Angle                                  0°         3.5°          7°
                             Overall Width                     E                   9.00 BSC
                             Overall Length                    D                   9.00 BSC
                             Molded Package Width              E1                  7.00 BSC
                             Molded Package Length             D1                  7.00 BSC
                             Lead Thickness                     c        0.09          -          0.16
                             Lead Width                         b        0.17        0.22         0.27
                             Mold Draft Angle Top                       11°         12°          13°
                             Mold Draft Angle Bottom                    11°         12°          13°
           Notes:
           1. Pin 1 visual index feature may vary, but must be located within the hatched area.
           2. Chamfers at corners are optional; size may vary.
           3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
              protrusions shall not exceed 0.25mm per side.
           4. Dimensioning and tolerancing per ASME Y14.5M
                  BSC: Basic Dimension. Theoretically exact value shown without tolerances.
                  REF: Reference Dimension, usually without tolerance, for information purposes only.
           5. Datums A-B and D to be determined at center line between leads where leads exit
              plastic body at datum plane H
                                                                 Microchip Technology Drawing C04-300-PT Rev A Sheet 2 of 2
       Note:      For the most current package drawings, please see the Microchip Packaging Specification located at
                  http://www.microchip.com/packaging
C1
C2 G
                                                               SILK SCREEN
                                        48
Y1
                                                        1 2
                                                                                                X1
                                                                E
                                                               Units                 MILLIMETERS
                                                    Dimension Limits          MIN        NOM            MAX
                            Contact Pitch                       E                      0.50 BSC
                            Contact Pad Spacing                 C1                        8.40
                            Contact Pad Spacing                 C2                        8.40
                            Contact Pad Width (X48)             X1                                      0.30
                            Contact Pad Length (X48)            Y1                                      1.50
                            Distance Between Pads               G             0.20
         Notes:
         1. Dimensioning and tolerancing per ASME Y14.5M
                 BSC: Basic Dimension. Theoretically exact value shown without tolerances.
         2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
            reflow process
140 mg
Y8X
             Note:    For the most current package drawings, please see the Microchip Packaging Specification located at
                      http://www.microchip.com/packaging
       Note:    For the most current package drawings, please see the Microchip Packaging Specification located at
                http://www.microchip.com/packaging
TBD mg
R7X
9. Conventions
       Symbol                     Description
       KB                         kilobyte (210 = 1024)
       MB                         megabyte (220 = 1024*1024)
       GB                         gigabyte (230 = 1024*1024*1024)
       b                          bit (binary ‘0’ or ‘1’)
       B                          byte (8 bits)
       1 kbit/s                   1,000 bit/s rate (not 1,024 bit/s)
       1 Mbit/s                   1,000,000 bit/s rate
       1 Gbit/s                   1,000,000,000 bit/s rate
       word                       16-bit
       Symbol                  Description
       kHz                     1 kHz = 103 Hz = 1,000 Hz
       KHz                     1 KHz = 1,024 Hz, 32 KHz = 32,768 Hz
       MHz                     1 MHz = 106 Hz = 1,000,000 Hz
       GHz                     1 GHz = 109 Hz = 1,000,000,000 Hz
       ms                      1 ms = 10-3s = 0.001s
       µs                      1 µs = 10-6s = 0.000001s
       ns                      1 ns = 10-9s = 0.000000001s
Customer Support
Users of Microchip products can receive assistance through several channels:
  •   Distributor or Representative
  •   Local Sales Office
  •   Field Application Engineer (FAE)
  •   Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
Note:  Tape and Reel identifier only appears in the catalog part number description. This identifier is
used for ordering purposes. Check with your Microchip Sales Office for package availability with the Tape
and Reel option.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,
chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,
SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,
ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©   2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-4321-6
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
                                                                                   ®                 ®
and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC
                   ®
DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.