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Internal Chip Organization 1.3.4

This document discusses the internal organization of memory chips. It begins with a basic block diagram of a memory chip that shows address connections, chip select input, output enable lines, and output connections. It notes that the chip is active low and that write and read lines are also active low. The next section discusses how memory is organized into an array of cells that can each store one bit. Words are formed from rows of these cells. A 2D organization is described where cells are arranged in rows and columns addressed by a memory address register. The final section introduces a 2.5D organization that breaks the address register into two parts to address rows and columns with smaller decoders in order to avoid an exponential increase in decoder and select lines

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173 views3 pages

Internal Chip Organization 1.3.4

This document discusses the internal organization of memory chips. It begins with a basic block diagram of a memory chip that shows address connections, chip select input, output enable lines, and output connections. It notes that the chip is active low and that write and read lines are also active low. The next section discusses how memory is organized into an array of cells that can each store one bit. Words are formed from rows of these cells. A 2D organization is described where cells are arranged in rows and columns addressed by a memory address register. The final section introduces a 2.5D organization that breaks the address register into two parts to address rows and columns with smaller decoders in order to avoid an exponential increase in decoder and select lines

Uploaded by

Rishi Kasrija
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Internal Chip Organization 1.3.

INTERNAL CHIP ORGANIZATION


This is the basic block diagram for understanding the working of basic chip.

Fig.3.5.1 Memory Chip

 This is the memory component which shows basic chip organization.


 There are some address connections, chip select input, output enable, output
connections.
 Chip is active low i.e it will be enabled if low input (0) is given.
 Write an read lines are also active low.
 OE stands for Output Enable, WE stands for Write Enable.
 For chip to be in working condition, Chip must be given active low input.

INTERNAL ORGANIZATION OF MEMORY CHIPS: 


A memory consists of cells in the form of an array, in which each cell is capable of storing
one bit of information. Each row of the cells constitutes a memory words and all cells of a
row are connected to a common line referred to as a word line. Thus W×b memory has w
words, each word having ‘b’ number of bits. 
2D MEMORY ORGANIZATION: This is the simplest type of organization. The cells are
organized in the form of a two dimensional array with rows and columns. Each row refers to
a word line. The Memory address register (MAR) holds the address of the location where the
read /write operation is executed.
 For a W×b memory, MAR has log2w=n bits. The content of MAR is decoded by an address
decoder on the chip to activate each word line. The 2D memory organization for RAMs and
ROMs mostly suffers from a problem of scale: it works fine when the number of words in the
memory is relatively small but quickly mushrooms as the memory is scaled up or increased in
size. This happens because the number of word select wires is an exponential function of the
size of the address. As the number of address increases, number of selection wires also
increases. This happens because the number of word select wires is an exponential function
of the size of the address. Suppose that the MAR is 10 bits wide, which means there are 1024
words in the memory. The decoder will need to output 1024 separate lines. 1024 is not much
larger but image 20 bits wide address; it will be 1024×1024 words.

Fig 3.5.2
2.5D MEMORY ORGANIZATION: One way to tackle the exponential explosion of
growth in the decoder and word select wires is to organize memory cells into a two-
dimension grid of words instead of a one-dimensional arrangement. Then the MAR is broken
into two halves, which are fed separately into smaller decoders. One decoder addresses the
rows of the grid while the other decoder addresses the columns.

HOMEWORK (ASSESMENT)
Q1. The parallel mode of communication is not suitable for long devices because of ______
A. Timing skew
B. Memory access delay
C. Latency
D. None of the mentioned
Answer:A
 Q2. User programmable terminals that combine VDT hardware with built-in microprocessor
is _____
A. KIPs
B. Pc
C. Mainframe
D. Intelligent terminals
Answer:D
Q3. The use of spooler programs or _______ Hardware allows PC operators to do the
processing work at the same time a printing operation is in progress.
A. Registers
B. Memory
C. Buffer
D.CPU
Answer:C

References
Reference Books:

 J.P. Hayes, “Computer Architecture and Organization”, Third Edition.

 Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.

 Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson Education.
Text Books:

 Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition, Addison


Wesley.

 Patterson and Hennessy, “Computer Architecture”, Fifth Edition Morgaon Kauffman.


Other References

 http://www.sgrrits.org/pdf/e-content/IT/Internal-organization-of-Memory-chips.pdf
 https://www.ics.p.lodz.pl/~dpuchala/CompArch/Lecture_6.pdf

Video References

 https://www.youtube.com/watch?v=LetdmZ3V-dk
 https://www.youtube.com/watch?v=3x9OMMwU7dQ

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