LinkSwitch-TN2 Family

Highly Energy Efficient Off-line Switcher IC with Integrated System Level

Protection for Low Component-Count Power Supplies

Product Highlights
Highest Performance and Design Flexibility
• Supports buck, buck-boost and flyback topologies
• Excellent load and line regulation FB BP/M
• Selectable device current limit
• 66 kHz operation with accurate current limit + D S +
• Allows the use of low-cost off-the-shelf inductors Wide Range LinkSwitch-TN2
DC
High-Voltage Output
• Reduces size and cost of magnetics and output capacitor DC Input
• Frequency jittering reduces EMI filter complexity
• Pin-out simplifies PCB heat sinking
PI-7841-041816
Enhanced Safety and Reliability Features Figure 1. Typical Buck Converter Application (See Application Examples
Section for Other Circuit Configurations).
• Auto-restart for short-circuit and open loop faults
• Output overvoltage protection (OVP)
• Line input overvoltage protection (OVL)
• Hysteretic over-temperature protection (OTP)
• Extended creepage between DRAIN pin and all other pins improves
field reliability
• 725 V MOSFET rating for excellent surge withstand
• 900 V MOSFET rating series for industrial or extra safety margin
Figure 2. Package Options. P: PDIP-8C, G: SMD-8C, D: SO-8C.
EcoSmart™– Extremely Energy Efficient
• Standby supply current <100 μA
• On/Off control provides constant efficiency over a wide load range Output Current Table1
• Easily meets all global energy efficiency regulations 725 V MOSFET
• No-load consumption <30 mW with external bias
230 VAC ±15% 85-265 VAC
Applications Product4
MDCM2 CCM3 MDCM2 CCM3
• Appliances
• Metering LNK3202P/G/D 63 mA 80 mA 63 mA 80 mA
• Smart LED drivers and industrial controls LNK3204P/G/D 120 mA 170 mA 120 mA 170 mA
• IOT, home and building automation LNK3205P/G/D 175 mA 270 mA 175 mA 270 mA
Description LNK3206P/G/D 225 mA 360 mA 225 mA 360 mA
The LinkSwitch™-TN2 family of ICs for non-isolated off-line power LNK3207P/G/D 360 mA 575 mA 360 mA 575 mA
supplies provides dramatically improved performance compared to LNK3208P/G/D 485 mA 775 mA 485 mA 775 mA
traditional linear or cap-dropper solutions. Designs using the highly
LNK3209P/G/D 600 mA 1000 mA 600 mA 1000 mA
integrated LinkSwitch-TN2 ICs are more flexible and feature increased
efficiency, comprehensive system level protection and higher reliability. 900 V MOSFET
The device family supports buck, buck-boost and flyback converter Product4 230 VAC ±15% 85-265 VAC
topologies. Each device incorporates a 725 V / 900 V power MOSFET,
MDCM 2
CCM 3
MDCM2 CCM3
oscillator, On/Off control for highest efficiency at light load, a high-
voltage switched current source for self-biasing, frequency jittering, LNK3294P/G 120 mA 170 mA 120 mA 170 mA
fast (cycle-by-cycle) current limit, hysteretic thermal shutdown, and LNK3296P/G 225 mA 360 mA 225 mA 360 mA
output and input overvoltage protection circuitry onto a monolithic IC.
Table 1. Output Current Table.
LinkSwitch-TN2 ICs consume very little current in standby resulting in Notes:
power supply designs that meet all no-load and standby specifications 1. Typical output current in a non-isolated buck converter with devices operating
worldwide. MOSFET current limit modes can be selected through the at default current limit and adequate heat sinking. Output power capability
BYPASS pin capacitor value. The high current limit level provides depends on respective output voltage and thermal requirements. See Key
maximum continuous output current while the low level permits using Applications Considerations Section for complete description of assumptions,
including fully discontinuous conduction mode (DCM) operation.
very low cost and small surface mount inductors. A full suite of
2. Mostly discontinuous conduction mode.
protection features enables safe and reliable power supplies protecting 3. Continuous conduction mode.
the device and the system against input and output overvoltage faults, 4. Packages: P: PDIP-8C, G: SMD-8C, D: SO-8C.
device over-temperature faults, lost regulation, and power supply output
overload or short-circuit faults. The device family is available in three different packages: PDIP-8C,
SO-8C, and SMD-8C (725 V PNs only).

www.power.com June 2022

This Product is Covered by Patents and/or Pending Patent Applications.
 LinkSwitch-TN2

BYPASS DRAIN
(BP/M) (D)
REGULATOR
5.0 V

IFBSD IFB FAULT

PRESENT BYPASS PIN
5.2 V CAPACITOR
DETECT
AUTO-RESTART BYPASS PIN
COUNTER UNDERVOLTAGE
OVL + CURRENT LIMIT
CLOCK
5.0 V -
COMPARATOR
RESET 4.5 V
+

-
VI
LIMIT

JITTER
CLOCK THERMAL
SHUTDOWN
DCMAX

OSCILLATOR

S Q
FEEDBACK
(FB) R Q

2.0 V -VT
LEADING
EDGE
BLANKING
OVP
DETECT

GROUND SOURCE
(G)* (S)

PI-7879b-030822

Figure 3. Functional Block Diagram. (*Only size 8 P/G Package)

Pin Functional Description SOURCE (S) Pin:

This pin is the power MOSFET source connection. It is also the
DRAIN (D) Pin:
ground reference for the BYPASS and FEEDBACK pins.
Power MOSFET drain connection. Provides internal operating current
for both start-up and steady-state operation. GROUND (G) Pin:
Size LNK3208/9 P/G package only.
BYPASS (BP/M) Pin:
Ground reference for the BYPASS and FEEDBACK.
This pin has multiple functions:
• It is the connection point for an external bypass capacitor for the
internally generated 5.0 V supply.
• It is a mode selector for the current limit value, depending on the
value of the capacitance added. Use of a 0.1 μF capacitor results P Package (DIP-8C)
in the standard current limit value. Use of a 1 μF capacitor results
G Package (SMD-8C) D Package (SO-8C)
in the current limit being reduced, allowing design with lowest cost
surface mount buck chokes.
• It provides a shutdown function. When the current into the BYPASS
BP/M 1 8 S/G* BP/M 1 8
pin exceeds IBPSD for a time equal to 2 to 3 cycles of the internal S
oscillator (fOSC), the device enters auto-restart. This can be used to 2 7
FB 2 7 S FB S
provide an output overvoltage protection function with external
6
circuitry. 6 S S
4 5
FEEDBACK (FB) Pin: D S
D 4 5 S
During normal operation, switching of the power MOSFET is con-
trolled by the FEEDBACK pin. MOSFET switching is terminated when
a current greater than IFB (49 µA) is delivered into this pin. Line
overvoltage protection is detected when a current greater than IFBSD
(670 µA) is delivered into this pin for 2 consecutive switching cycles. PI-7842e-030822

Figure 4. Pin Configuration. (*G for size LNK3208/9)

2
www.power.com Rev. P 06/22
 LinkSwitch-TN2

LinkSwitch-TN2 Functional Description 600

PI-3660-081303
LinkSwitch-TN2 combines a high-voltage power MOSFET switch with 500
a power supply controller in one device. Unlike conventional PWM VDRAIN
(pulse width modulator) controllers, LinkSwitch-TN2 uses a simple 400
ON/OFF control to regulate the output voltage. The LinkSwitch-TN2
controller consists of an oscillator, feedback (sense and logic) circuit, 300
5.0 V regulator, BYPASS pin undervoltage circuit, over-temperature
protection, line and output overvoltage protection, frequency jittering,
200
current limit circuit, leading edge blanking and a 725 V or 900 V
power MOSFET. The LinkSwitch-TN2 incorporates additional circuitry
100
for auto-restart.

Oscillator 0
The typical oscillator frequency is internally set to an average of fOSC 68 kHz
(66 kHz). Two signals are generated from the oscillator: the maximum 64 kHz
duty cycle signal (DC(MAX)) and the clock signal that indicates the
beginning of each cycle.

The LinkSwitch-TN2 oscillator incorporates circuitry that introduces a 0 20

small amount of frequency jitter, typically 4 kHz peak-to-peak, to Time (µs)
minimize EMI emission. The modulation rate of the frequency jitter is Figure 5. Frequency Jitter.
set to 1 kHz to optimize EMI reduction for both average and quasi-
peak emissions. The frequency jitter should be measured with the In addition, there is a shunt regulator clamping the BYPASS pin at
oscilloscope triggered at the falling edge of the DRAIN waveform. VBP(SHUNT) (5.2 V) when current is provided to the BYPASS pin through
The waveform in Figure 5 illustrates the frequency jitter of the an external resistor. This facilitates powering of LinkSwitch-TN2
LinkSwitch-TN2. externally through a bias winding to decrease the no-load consump-
tion to about 10 mW (flyback). The device stops switching instantly
Soft-Start
and enters auto-restart when a current ≥IBPSD is delivered into the
At power-up or during a restart attempt in auto-restart, the device
BYPASS pin. Adding an external Zener diode from the output voltage
applies a soft-start by temporarily reducing the oscillator frequency.
to the BYPASS pin allows implementing an hysteretic OVP function in
LNK3202-07 and LNK329x reduce the frequency to fOSC(SS) (typically
a flyback converter (see Figure 6). The current into the BYPASS pin
33 kHz. LNK3208 and LNK3209 reduce the oscillator frequency to
should be limited to less than 16 mA.
initially 16.5 kHz followed by a stepwise increase to 22 kHz and
33 kHz over a period of 256 switching cycles. Soft-start terminates BYPASS Pin Undervoltage
and the device continues operating at the nominal oscillator The BYPASS pin undervoltage circuitry disables the power MOSFET
frequency fOSC either after 256 switching cycles or if the output when the BYPASS pin voltage drops below VBP–VBPH (approximately 4.5 V).
voltage reaches regulation. Once the BYPASS pin voltage drops below this threshold, it must rise
Feedback Input Circuit back to VBP to enable (turn-on) the power MOSFET.
The feedback input circuit at the FEEDBACK pin consists of a low Over-Temperature Protection
impedance source follower output set at VFB (2.0 V). When the The thermal shutdown circuitry senses the die temperature. The
current delivered into this pin exceeds IFB (49 µA), a low logic level threshold is set at TSD (142 °C typical) with a 75 °C (TSDH) hysteresis.
(disable) is generated at the output of the feedback circuit. This When the die temperature rises above TSD the power MOSFET is
output is sampled at the beginning of each cycle on the rising edge disabled and remains disabled until the die temperature falls to
of the clock signal. If high, the power MOSFET is turned on for that TSD –TSDH, at which point it is re-enabled.
cycle (enabled), otherwise the power MOSFET remains off (disabled).
The sampling is done only at the beginning of each cycle. Subse- Current Limit
quent changes in the FEEDBACK pin voltage or current during the The current limit circuit senses the current in the power MOSFET.
remainder of the cycle do not impact the MOSFET enable/disable When this current exceeds the internal threshold (ILIMIT), the power
status. If a current greater than IFBSD is injected into the feedback pin MOSFET is turned off for the remainder of that cycle. The leading
while the MOSFET is enabled for at least two consecutive cycles the edge blanking circuit inhibits the current limit comparator for a short
part will stop switching and enter auto-restart off-time. Normal time (tLEB) after the power MOSFET is turned on. This leading edge
switching resumes after the auto-restart off-time expires. This blanking time has been set so that current spikes caused by capaci-
shutdown function allows implementing line overvoltage protection in tance and rectifier reverse recovery time will not cause premature
flyback converters (see Figure 6). The current into the FEEDBACK pin termination of the switching pulse. Current limit can be selected using
should be limited to less than 1.2 mA. the BYPASS pin capacitor (0.1 µF for normal current limit / 1 µF for
reduced current limit). LinkSwitch-TN2 selects between normal and
5.0 V Regulator and 5.2 V Shunt Voltage Clamp reduced current limit at power-up prior to switching.
The 5.0 V regulator charges the bypass capacitor connected to the
BYPASS pin to VBP by drawing a current from the voltage on the Auto-Restart
DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal In the event of a fault condition such as output overload, output
supply voltage node for the LinkSwitch-TN2. When the MOSFET is short, or an open-loop condition, LinkSwitch-TN2 enters into
on, the LinkSwitch-TN2 runs off of the energy stored in the bypass auto-restart operation. An internal counter clocked by the oscillator
capacitor. Extremely low power consumption of the internal circuitry gets reset every time the FEEDBACK pin is pulled high. If the
allows the LinkSwitch-TN2 to operate continuously from the current FEEDBACK pin is not pulled high for t AR(ON) (50 ms), the power
drawn from the DRAIN pin. A bypass capacitor value of 0.1 µF is MOSFET switching is disabled for a time equal to the auto-restart
sufficient for both high frequency decoupling and energy storage. off-time. The first time a fault is asserted the off-time is 150 ms

3
www.power.com Rev. P 06/22
 LinkSwitch-TN2

(t AR(OFF) First Off Period). If the fault condition persists, subsequent connected from the output to the BYPASS pin and bypass voltage, will
off-times are 1500 ms long (t AR(OFF) Subsequent Periods). The cause a current in excess of IBPSD injected into the BYPASS pin, which
auto-restart alternately enables and disables the switching of the will trigger the auto-restart and protect the power supply from
power MOSFET until the fault condition is removed. The auto-restart overvoltage.
counter is gated by the switch oscillator.
Line Overvoltage Protection
Hysteretic Output Overvoltage Protection
In a flyback converter LinkSwitch-TN2 can sense indirectly the DC bus
The output overvoltage protection provided by the LinkSwitch-TN2 IC
overvoltage condition during the power MOSFET on-time by monitor­
uses auto-restart that is triggered by a current >IBPSD into the BYPASS
ing the current flowing into the FEEDBACK pin depending on circuit
pin. In addition to an internal filter, the BYPASS pin capacitor forms
configuration. Figure 7 shows one possible circuit implementation.
an external filter providing noise immunity from inadvertent triggering.
During the MOSFET on-time, the voltage across the secondary
For the bypass capacitor to be effective as a high frequency filter, the
winding is proportional to the voltage across the primary winding.
capacitor should be located as close as possible to the SOURCE and
The current flowing through emitter and base of transistor Q3 is
BYPASS pins of the device.
therefore representing VBUS. Indirect line sensing minimizes power
The OVP function can be realized in a flyback converter by connect- dissipation and is used for line OV protection. The LinkSwitch-TN2
ing a Zener diode from the output supply to the BYPASS pin. The will go into auto- auto-restart mode if the FEEDBACK pin current
circuit example shown in Figure 6 describes a simple method for exceeds the line overvoltage threshold current IFBSD for at least 2
implementing the output overvoltage protection. Adding additional consecutive switching cycles.
filtering can be achieved by inserting a low value (10 Ω to 47 Ω)
In order to have accurate line OV threshold voltage and also for good
resistor in series with the OVP Zener diode. The resistor in series
efficiency, regulation performance and stability, the transformer
with the OVP Zener diode also limits the maximum current into the
leakage inductance should be minimized. Low leakage will minimize
BYPASS pin. The current should be limited to less than 16 mA.
ringing on the secondary winding and provide accurate line OVP
During a fault condition resulting from loss of feedback, the output sampling. In some designs, a RC snubber across the rectifier diode
voltage will rapidly rise above the nominal voltage. A voltage at the may be needed to damp the ringing at the secondary winding when
output that exceeds the sum of the voltage rating of the Zener diode line voltage is sampled.

T1
+
VO

+
VBUS
D VOV = VBP + VDOVP
FB
LinkSwitch-TN2 BP
RBP

S CBP
DOVP

PI-8024-092916

Figure 6. Non-Isolated Flyback Converter with Output Overvoltage Protection.

T1
n:1
+
R3* VO

n:1 VR3

+ D3 VOV = (VVR3 + VD3 + VBE(Q3) – VBP + VR3 ) × n + VDS(ON)

VBUS
*R3 limits the current into the FEEDBACK pin.
R4** A maximum current of 120% of IFBSD is
Q3
D recommended.
FB
LinkSwitch-TN2 **R4 is a pull-down resistor for Q3 to avoid
BP
inadvertant triggering. 2 kΩ is a typical starting point
S cBP

PI-8025-092616

Figure 7. Line-Sensing for Overvoltage Protection by using FEEDBACK Pin.

4
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Applications Example

R5
26.7 kΩ

R1
11.8 kΩ
1%

R3 C3 D2
RF1 2.49 kΩ 10 µF
8.2 Ω L2 C1 1N4005GP 12 V,
1% 25 V
2W 1 mH FB BP/M 100 nF 120 mA
D S L1
D3 1 mH
85-265
1N4007 C4 C5 LinkSwitch-TN2 280 mA C2 R4
4.7 µF 4.7 µF LNK3204 D1 100 µF 3.3 kΩ
VAC UF4005
D4 400 V 400 V 16 V 1%
1N4007 RTN

PI-7857-092616

Figure 8. Universal Input, 12 V, 120 mA Constant Voltage Power Supply using LinkSwitch-TN2.

A 1.44 W Universal Input Buck Converter Regulation is maintained by skipping switching cycles. As the output
The circuit shown in Figure 8 is a typical implementation of a 12 V, voltage rises, the current into the FEEDBACK pin will rise. If this
120 mA non-isolated power supply used in appliance control such as exceeds IFB then subsequent cycles will be skipped until the current
rice cookers, dishwashers or other white goods. This circuit may also reduces below IFB. Thus, as the output load is reduced, more cycles
be applicable to other applications such as night-lights, LED drivers, will be skipped and if the load increases, fewer cycles are skipped.
electricity meters, and residential heating controllers, where a To provide overload protection if no cycles are skipped during a
non-isolated supply is acceptable. 50 ms period, LinkSwitch-TN2 will enter auto-restart, limiting the
average output power to approximately 3% of the maximum overload
The input stage comprises fusible resistor RF1, diodes D3 and D4,
power. Due to tracking errors between the output voltage and the
capacitors C4 and C5, and inductor L2. Resistor RF1 is a flame proof,
voltage across C3 at light load or no-load, a small pre-load may be
fusible, wire wound resistor. It accomplishes several functions:
required (R4). For the design in Figure 8, if regulation to zero load is
A. Inrush current limitation to safe levels for rectifiers D3 and D4; required, then this value should be reduced to 2.4 kΩ.
B. Differential mode noise attenuation;
Key Application Considerations
C. Acts as an input fuse in the event any other component fails
short-circuit (component fails safely open-circuit without emitting LinkSwitch-TN2 Design Considerations
smoke, fire or incandescent material).
Output Current Table
The power processing stage is formed by the LinkSwitch-TN2, Data sheet maximum output current table (Table 1) represents the
freewheeling diode D1, output choke L1, and the output capacitor C2. typical practical continuous output current for both mostly discontinu-
The LNK3204 was selected such that the power supply operates in ous conduction mode (MDCM) and continuous conduction mode (CCM)
the mostly discontinuous-mode (MDCM). Diode D1 is an ultrafast of operation that can be delivered from a given LinkSwitch-TN2
diode with a reverse recovery time (tRR) of approximately 75 ns, device under the following assumed conditions:
acceptable for MDCM operation. For continuous conduction mode
(CCM) designs, a diode with a tRR of ≤35 ns is recommended. 1. Buck converter topology.
Inductor L1 is a standard off-the-shelf inductor with appropriate RMS 2. The minimum DC input voltage is ≥70 V. The value of input
current rating (and acceptable temperature rise). Capacitor C2 is the capacitance should be large enough to meet this criterion.
output filter capacitor; its primary function is to limit the output 3. For CCM operation a KRP* of 0.4.
voltage ripple. The output voltage ripple is a stronger function of the 4. Output voltage of 12 VDC.
ESR of the output capacitor than the value of the capacitor itself. 5. Efficiency of 75%.
Optional resistor R5 supplies the BYPASS pin externally for signifi- 6. A catch/freewheeling diode with tRR ≤75 ns is used for MDCM
cantly lower no-load input power and increased efficiency over all operation and for CCM operation, a diode with tRR ≤35 ns is used.
load conditions. 7. The part is board mounted with SOURCE pins soldered to a
sufficient area of copper to keep the SOURCE pin temperature at
To a first order, the forward voltage drops of D1 and D2 are identical. or below 100 °C.
Therefore, the voltage across C3 tracks the output voltage. The
voltage developed across C3 is sensed and regulated via the resistor *KRP is the ratio of ripple to peak inductor current.
divider R1 and R3 connected to U1’s FEEDBACK pin. The values of R1
and R3 are selected such that, at the desired output voltage, the
voltage at the FEEDBACK pin is 2.00 V.

5
www.power.com Rev. P 06/22
 LinkSwitch-TN2

LinkSwitch-TN2 Selection and Selection Between guarantee a specified reverse recovery time. To a first order, the
MDCM and CCM Operation forward drops of D1 and D2 should match.

Select the LinkSwitch-TN2 device, freewheeling diode and output Inductor L1

inductor that gives the lowest overall cost. In general, MDCM Choose any standard off-the-shelf inductor that meets the design
provides the lowest cost and highest efficiency converter. CCM requirements. A “drum” or “dog bone” “I” core inductor is recom­
designs require a larger inductor and ultrafast (tRR ≤35 ns) freewheel- mended with a single ferrite element due to its low-cost and very low
ing diode in all cases. It is lower cost to use a larger LinkSwitch-TN2 audible noise properties. However, the inductor should be selected
in MDCM than a smaller LinkSwitch-TN2 in CCM because of the as varnished type in order to get low audible noise. The typical
additional external component costs of a CCM design. However, if inductance value and RMS current rating can be obtained from the
the highest output current is required, CCM should be employed LinkSwitch-TN2 design spreadsheet available within the PI Expert
following the guidelines below. design suite from Power Integrations. Choose L1 greater than or
equal to the typical calculated inductance with RMS current rating
Topology Options greater than or equal to calculated RMS inductor current. Care
LinkSwitch-TN2 can be used in all common topologies, with or without should be taken to ensure that the inductor has sufficient voltage
an optocoupler and reference to improve output voltage tolerance rating as this is a high-voltage application.
and regulation. Table 2 provides a summary of these configurations. Capacitor C2
For more information see the Application Note – LinkSwitch-TN2 The primary function of capacitor C2 is to smooth the inductor current.
Design Guide. The actual output ripple voltage is a function of this capacitor’s ESR.
Component Selection To a first order, the ESR of this capacitor should not exceed the rated
ripple voltage divided by the typical current limit of the chosen
Referring to Figure 8, the following considerations may be helpful in LinkSwitch-TN2.
selecting components for a LinkSwitch-TN2 design.
Feedback Resistors R1 and R3
BYPASS Pin Capacitor C1 The values of the resistors in the resistor divider formed by R1 and
Capacitor connected from the BYAPSS pin provides decoupling for the R3 are selected to maintain 2.00 V at the FEEDBACK pin. It is
controller and also selects current limit. A 0.1 mF or 1 mF capacitor may recommended that R3 be chosen as a standard 1% resistor of 2.49 kΩ.
be used as indicated in the data sheet. Though electrolytic capaci- This ensures good noise immunity by biasing the feedback network
tors can be used, often surface mount multi-layer ceramic capacitors with a current of approximately 0.8 mA.
are preferred for use as they enable placement of capacitors close to
the IC and design of compact switching power supplies. 16 V, 25 V or External Bias Resistor R5
higher X7R dielectric capacitors are recommended to ensure To reduce the no-load input power of the power supply, resistor R5,
minimum capacitance change under DC bias and temperature. connected from the feedback capacitor C3 to the BYPASS pin, is
recommended. This is applicable to the power supply whose output
Freewheeling Diode D1 voltage is higher than VBP(SHUNT). To achieve lowest no-load power
Diode D1 should be an ultrafast type. For MDCM, reverse recovery consumption, the current fed into the BYPASS pin should be slightly
time tRR ≤75 ns should be used at a temperature of 70 °C or below. higher than 120 mA. For the best full load efficiency and thermal
Slower diodes are not acceptable, as continuous mode operation will performance, the current fed into the BYPASS pin should be slightly
always occur during startup, causing high leading edge current higher than the IS2 Max value.
spikes, terminating the switching cycle prematurely, and preventing
the output from reaching regulation. If the ambient temperature is Feedback Capacitor C3
above 70 °C then a diode with tRR ≤35 ns should be used. Capacitor C3 can be a low cost general purpose capacitor. It provides
a “sample and hold” function, charging to the output voltage during
For CCM an ultrafast diode with reverse recovery time tRR ≤35 ns the off time of LinkSwitch-TN2. Its value should be 10 µF to 22 µF;
should be used. A slower diode may cause excessive leading edge smaller values cause poorer regulation at light load conditions.
current spikes, terminating the switching cycle prematurely and
preventing full power delivery. Pre-Load Resistor R4
In high-side, direct feedback designs where the minimum load is
Fast recovery and slow recovery diodes should never be used as the <3 mA, a pre-load resistor is required to maintain output regulation.
large reverse recovery currents can cause excessive power dissipa- This ensures sufficient inductor energy to pull the inductor side of the
tion in the diode and/or exceed the maximum drain current specifica- feedback capacitor C3 to input return via D2. The value of R4 should
tion of LinkSwitch-TN2. be selected to provide a minimum output load of 3 mA.
Feedback Diode D2 In designs with an optocoupler a Zener diode or reference bias
Diode D2 can be a low-cost slow diode such as the 1N400X series, current provides a 1 mA to 2 mA minimum load, preventing “pulse
however it should be specified as a glass passivated type to bunching” and increased output ripple at zero load.

6
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Topology Basic Circuit Schematic Key Features

1. Output referenced to input

High-Side 2. Positive output (VO) with respect to -VIN
FB BP/M
Buck – 3. Step down – VO < VIN
Direct + D S + 4. Low cost direct feedback (±10% typ.)
Feedback VIN LinkSwitch-TN2 VO 5. Requires an output load to maintain regulation

PI-7843-031616

1. Output referenced to input

FB BP/M
2. Positive output (VO) with respect to -VIN
High-Side + D S + 3. Step down – VO < VIN
Buck – LinkSwitch-TN2 4. Optocoupler feedback
Optocoupler - Accuracy only limited by reference choice
VIN VO
Feedback - Low cost non-safety rated optocoupler
- No pre-load required
5. Minimum no-load consumption
PI-7844-031616

+ +

Low-Side
LinkSwitch-TN2
Buck – VIN VO
Optocoupler
Feedback
BP/M FB
1. Output referenced to input
S D
PI-7845-031616 2. Negative output (VO) with respect to +VIN
3. Step down – VO < VIN
+ 4. Optocoupler feedback
IO - Accuracy only limited by reference choice
- Low cost non-safety rated optocoupler
Low-Side LinkSwitch-TN2 - No pre-load required
Buck – VIN VF +
- Ideal for driving LEDs
Constant
Current LED
Driver BP/M FB

S D
VF PI-7846-031616
R=
IO

High-Side
Buck-Boost – FB BP/M
Direct D S
+ 1. Output referenced to input
Feedback LinkSwitch-TN2
VIN VO 2. Negative output (VO) with respect to +VIN
3. Step up/down – VO > VIN or VO < VIN
+
4. Low cost direct feedback (±10% typ.)
PI-7847-031616
5. Fail-safe – output is not subjected to input
2V voltage if the internal power MOSFET fails
300 Ω RSENSE = 6. Ideal for driving LEDs – better accuracy and
IO
2 kΩ temperature stability than low-side buck
High-Side FB BP/M RSENSE IO
Buck-Boost – constant current LED driver
+ D S 7. Requires an output load to maintain regulation
Constant
LinkSwitch-TN2
Current LED VIN 10 µF 100 nF
Driver 50 V

PI-7849-031616

Table 2. Common Circuit Configurations using LinkSwitch-TN2. (continued on next page)

7
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Topology Basic Circuit Schematic Key Features

1. Output referenced to input
+ 2. Positive output (VO) with respect to +VIN
3. Step up/down – VO > VIN or VO < VIN
Low-Side LinkSwitch-TN2 4. Optocoupler feedback
Buck-Boost – VIN VO - Accuracy only limited by reference choice
Optocoupler - Low cost non-safety rated optocoupler
Feedback - No pre-load required
BP/M FB + 5. Fail-safe – output is not subjected to input
S D voltage if the internal power MOSFET fails
PI-7848-031616
6. Minimum no-load consumption

Table 2 (cont). Common Circuit Configurations using LinkSwitch-TN2.

LinkSwitch-TN2 Layout Considerations Figures 9a, 9b and 9c are printed circuit board layout design
examples for the circuit schematic shown in Figure 8. The loop
In the buck or buck-boost converter configuration, since the SOURCE formed between the LinkSwitch-TN2, inductor (L1), freewheeling
pins in LinkSwitch-TN2 are switching nodes, the copper area diode (D1), and output capacitor (C2) should be kept as small as
connected to SOURCE should be minimized to minimize EMI within possible. The BYPASS pin capacitor C1 should be located physically
the thermal constraints of the design. close to the SOURCE (S) and BYPASS (BP) pins. To minimize direct
In the boost configuration, since the SOURCE pins are tied to DC coupling from switching nodes, the LinkSwitch-TN2 should be placed
return, the copper area connected to SOURCE can be maximized to away from AC input lines. It may be advantageous to place capacitors
improve heat sinking. C4 and C5 in-between LinkSwitch-TN2 and the AC input. The second
rectifier diode D4 is optional, but may be included for better EMI
performance and higher line surge withstand capability.

Figure 9a. Recommended Printed Circuit Layout for LinkSwitch-TN2 using P Package.

8
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Figure 9b. Recommended Printed Circuit Layout for LinkSwitch-TN2 using G Package.

Figure 9c. Recommended Printed Circuit Layout for LinkSwitch-TN2 using D Package.

9
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Quick Design Checklist 4. Thermal Check – At maximum output power, minimum input
voltage and maximum ambient temperature, verify that the
As with any power supply design, all LinkSwitch-TN2 designs should LinkSwitch-TN2 SOURCE pin temperature is 100 °C or below.
be verified for proper functionality on the bench. The following This ensures adequate margin due to variations in RDS(ON) from
minimum tests are recommended: part to part. If the device temperature of the IC exceeds 85 °C
1. Adequate DC Rail Voltage – Check that the minimum DC input with ambient temperature of 25 °C, it is recommended the next
voltage does not fall below 70 VDC at maximum load, minimum bigger device in the family should be selected for the application.
input voltage. A battery powered thermocouple meter is recommended to make
2. Correct Diode Selection – UF400x series diodes with reverse measurements when the SOURCE pins are a switching node.
recovery time of 75 ns or better are recommended only for Alternatively, the ambient temperature may be raised to indicate
designs that operate in MDCM at an ambient of 70 °C or below. margin to thermal shutdown.
For designs operating in continuous conduction mode (CCM) and/ In a LinkSwitch-TN2 design using a buck or buck-boost converter
or higher ambients, then a diode with a reverse recovery time of topology, the SOURCE pin is a switching node. Oscilloscope measure-
35 ns or better, such as the BYV26C, is recommended. ments should therefore be made with probe grounded to a DC voltage,
3. Maximum Drain Current – Verify that the peak drain current is such as primary return or DC input rail, and not to the SOURCE pins.
below the data sheet peak drain specification under worst-case The power supply input must always be supplied from an isolated
conditions of highest line voltage, maximum overload (just prior source when doing measurements (e.g. via an isolation transformer).
to auto-restart) and highest ambient temperature.

10
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Absolute Maximum Ratings(1,5)

DRAIN Pin Voltage: LNK320x.........................................-0.3 to 725 V Storage Temperature ..............................................-65 °C to 150 °C
LNK329x..........................................-0.3 to 900 V Operating Junction Temperature3 .............................-40 °C to 150 °C
DRAIN Pin Peak Current: LNK3202........................................600 mA2 Lead Temperature4 ................................................................ 260 °C
LNK3204......................................1230 mA2
LNK3205......................................2460 mA2 Notes:
LNK3206......................................3750 mA2 1. All voltages referenced to SOURCE, TA = 25 °C.
LNK3207......................................3750 mA2 2. See Figure 15 and Figure 23, for VDS > 400 V.
LNK3208......................................6300 mA2 3. Normally limited by internal circuitry.
LNK3209.................................... 10200 mA2 4. 1/16 in. from case for 5 seconds.
LNK3294........................................968 mA2 5. Maximum ratings specified may be applied, one at a time,
LNK3296......................................3194 mA2 without causing permanent damage to the product.
FEEDBACK Pin Voltage................................................... -0.3 V to 7 V Exposure to Absolute Maximum Rating conditions for
FEEDBACK Pin Current...........................................................100 mA extended periods of time may affect product reliability.
BYPASS Pin Voltage.........................................................0.3 V to 7 V

Thermal Resistance
Thermal Resistance: P or G Package: Notes:
(qJA) ........................................ 70 °C/W2; 60 °C/W3 1. Measured on pin 8 (SOURCE) close to plastic interface.

(qJC)1 ........................................................ 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
D Package: 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJA) ......................................100 °C/W(2; 80 °C/W3

(qJC)1 ........................................................ 30 °C/W

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 10
(Unless Otherwise Specified)
Control Functions

Output Average 62 66 70
fOSC TJ = 25 °C kHz
Frequency Peak-Peak Jitter 4

LNK320x 66 69 73
Maximum Duty Cycle DCMAX S2 Open %
LNK329x 65 68 72
FEEDBACK Pin Turnoff VBP = 5.0 V to 5.5 V
IFB 44 49 54 mA
Threshold Current TJ = 25 °C
FEEDBACK Pin Voltage VBP = 5.0 V to 5.5 V
VFB 1.97 2.00 2.03 V
at Turnoff Threshold TJ = 25 °C
FEEDBACK Pin Instant
IFB(SD) TJ = 25 °C 520 675 800 mA
Shutdown Current
FEEDBACK Pin Instant Switch
TJ = 25 °C 2
Shutdown Delay Cycles
FEEDBACK Pin Voltage VBP = 5.0 V to 5.5 V
VFB(SD) 3.3 V
at Shutdown Current TJ = 25 °C
VFB = 2.1 V LNK32xx 75
IS1 (MOSFET Not Switching) mA
See Note A LNK3208/9 95

LNK3202 98 160
LNK3204 113 180
LNK3205 141 220
DRAIN Pin
Supply Current LNK3206 165 250
FEEDBACK Open
IS2 (MOSFET Switching) LNK3207 190 290 mA
See Notes A, B
LNK3208 275 405
LNK3209 300 460
LNK3294 120 170
LNK3296 225 320

11
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 10 Min Typ Max Units
(Unless Otherwise Specified)

Control Functions (cont.)

VBP = 0 V
ICH1 -11 -7 -3
BYPASS Pin TJ = 25 °C
mA
Charge Current VBP = 4 V
ICH2 -7.5 -5 -2.5
TJ = 25 °C
BYPASS Pin Voltage VBP 4.7 5.0 5.2 V
BYPASS Pin Shutdown
IBP(SD) TJ = 25 °C 6 8 mA
Threshold Current
BYPASS Pin
VBP(SHUNT) IBP = 2 mA 4.9 5.2 5.5 V
Shunt Voltage

BYPASS Pin LNK32xx 0.37 0.47 0.57

VBP(H) V
Voltage Hysteresis
LNK3208/9 0.35 0.47 0.60
BYPASS Pin
IBP(SC) See Note C 55 mA
Supply Current
Circuit Protection
di/dt = 55 mA/ms
126 136 146
TJ = 25 °C
LNK3202
di/dt = 250 mA/ms
149 170 191
TJ = 25 °C
di/dt = 65 mA/ms
240 257 275
TJ = 25 °C
LNK3204
di/dt = 415 mA/ms
278 317 356
TJ = 25 °C
di/dt = 75 mA/ms
350 375 401
TJ = 25 °C
LNK3205
di/dt = 500 mA/ms
394 448 502
TJ = 25 °C
di/dt = 95 mA/ms
450 482 515
TJ = 25 °C
LNK3206
di/dt = 610 mA/ms
510 580 650
TJ = 25 °C
di/dt = 95 mA/ms
Standard Current Limit 725 780 835
TJ = 25 °C
(CBP = 0.1 mF, ILIMIT LNK3207 mA
See Note D, H) di/dt = 610 mA/ms
893 1015 1137
TJ = 25 °C
di/dt = 165 mA/ms
970 1040 1110
TJ = 25 °C
LNK3208
di/dt = 1000 mA/ms
1131 1285 1440
TJ = 25 °C
di/dt = 165 mA/ms
1200 1300 1400
TJ = 25 °C
LNK3209
di/dt = 1000 mA/ms
1413 1600 1787
TJ = 25 °C
di/dt = 65 mA/ms
240 257 275
TJ = 25 °C
LNK3294
di/dt = 415 mA/ms
278 317 356
TJ = 25 °C
di/dt = 95 mA/ms
450 482 515
TJ = 25 °C
LNK3296
di/dt = 610 mA/ms
510 580 650
TJ = 25 °C

12
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 10 Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection (cont.)
di/dt = 28 mA/ms
70 80 90
TJ = 25 °C
LNK3202
di/dt = 170 mA/ms
104 119 134
TJ = 25 °C
di/dt = 65 mA/ms
180 205 230
TJ = 25 °C
LNK3204
di/dt = 415 mA/ms
227 258 289
TJ = 25 °C
di/dt = 75 mA/ms
227 259 291
TJ = 25 °C
LNK3205
di/dt = 500 mA/ms
292 332 372
TJ = 25 °C
di/dt = 95 mA/ms
325 370 415
TJ = 25 °C
LNK3206
di/dt = 610 mA/ms
408 464 520
TJ = 25 °C
di/dt = 95 mA/ms
Reduced Current Limit 545 620 695
TJ = 25 °C
(CBP = 1 mF, ILIMIT(RED) LNK3207 mA
See Note D, H) di/dt = 610 mA/ms
730 830 930
TJ = 25 °C
di/dt = 165 mA/ms
739 840 941
TJ = 25 °C
LNK3208
di/dt = 1000 mA/ms
941 1070 1199
TJ = 25 °C
di/dt = 165 mA/ms
925 1050 1175
TJ = 25 °C
LNK3209
di/dt = 1000 mA/ms
1194 1350 1506
TJ = 25 °C
di/dt = 65 mA/ms
180 205 230
TJ = 25 °C
LNK3294
di/dt = 415 mA/ms
227 258 289
TJ = 25 °C
di/dt = 95 mA/ms
325 370 415
TJ = 25 °C
LNK3296
di/dt = 610 mA/ms
408 464 520
TJ = 25 °C
LNK3202
373 534 687
See Note I
LNK3204
356 475 594
See Note I
LNK3205
412 531 650
See Note I
LNK3206
Minimum On-Time tON(MIN) 442 591 734 ns
See Note I
LNK3207
656 875 1094
See Note I
LNK3208
435 580 725
See Note I
LNK3209
442 591 734
See Note I

13
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 10 Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection (cont.)
LNK3294
356 480 599
See Note I
Minimum On-Time tON(MIN) ns
LNK3296
350 550 760
See Note I

Leading Edge TJ = 25 °C
tLEB 300 450 ns
Blanking Time See Note E

Thermal Shutdown
TSD See Note F 135 142 150 °C
Temperature

Thermal Shutdown
TSDH See Note F 75 °C
Hysteresis

Soft-Start Period
256 Cycles
LNK32xx See Note E

Soft-Start Frequency 33 kHz

Soft-Start Period 1 64 Cycles

Internal Soft-Start fOSC(SS) Soft-Start Frequency 1 16.5 kHz

Soft-Start Period 2 64 Cycles

LNK3208/9
Soft-Start Frequency 2 22 kHz

Soft-Start Period 3 128 Cycles

Soft-Start Frequency 3 33 kHz

Output

LNK3202 TJ = 25 °C 48 55.2
ID = 13 mA TJ = 100 °C 76 88.4

LNK3204 TJ = 25 °C 24 27.6
ID = 25 mA TJ = 100 °C 38 44.2

LNK3205 TJ = 25 °C 12 13.8
ID = 35 mA TJ = 100 °C 19 22.1

LNK3206 TJ = 25 °C 7 8.1
ID = 45 mA TJ = 100 °C 11 12.9

ON-State LNK3207 TJ = 25 °C 7 8.1

RDS(ON) W
Resistance ID = 45 mA TJ = 100 °C 11 12.9

LNK3208 TJ = 25 °C 4.25 4.85

ID = 45 mA TJ = 100 °C 5.78 6.60

LNK3209 TJ = 25 °C 2.70 3.20

ID = 45 mA TJ = 100 °C 3.80 4.37

LNK3294 TJ = 25 °C 17 19.6
ID = 83 mA TJ = 100 °C 27 31

LNK3296 TJ = 25 °C 5.3 6.1

ID = 163 mA TJ = 100 °C 8.4 9.7

14
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 10 Min Typ Max Units
(Unless Otherwise Specified)
Output (cont.)
VBP = 5.4 V
VFB ≥2.1 V
IDSS1 200
VDS = 80% BVDSS
OFF-State Drain TJ = 125 °C mA
Leakage Current
VBPP = 5.4 V
IDSS2 VDSS = 325 V 15
TJ = 25 °C

VBP = 5.4 V LNK320X 725

Breakdown Voltage BVDSS VFB ≥2.1 V V
TJ = 25 °C LNK329X 900

LNK3202 to LNK3207 18
DRAIN Pin
TJ = 25 °C V
Supply Voltage LNK3208 to LNK3209 25

Auto-Restart TJ = 25 °C
t AR(ON) 50 ms
ON-Time See Note G

First Off Period 150

Auto-Restart TJ = 25 °C
t AR(OFF) ms
OFF-Time See Note G Subsequent Periods 1500

Auto-Restart
DC AR Subsequent Periods 3 %
Duty Cycle

NOTES:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is = 2.1 V (MOSFET not switching) and the sum of IS2 and
IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is
to measure the BYPASS pin current at 5.1 V.
C. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK pins and not any other
external circuitry.
D. For current limit at other di/dt values, refer to Figures 21 and 22.
E. This parameter is guaranteed by design.
F. This parameter is derived from characterization.
G. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
H. The BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target
application.
I. Measured using circuit in Figure 12 with 50 W drain pull-up. The width of the drain pulse is measured as the time from VFALL = 42 V to
VRISE = 40 V (VDR = 50 V), for LNK32x6/x5/x4 and as the time from VFALL = 32 V to VRISE = 30 V on rising edge (VDR = 35 V), for LNK3202.

Tolerance Relative to
Nominal BP/M Pin Minimal Capacitor Value
Capacitor Value
Min Max
0.1 mF -60% +100%
1 mF -50% +100%

15
www.power.com Rev. P 06/22
 LinkSwitch-TN2

470 kΩ
470 Ω
5W
S2
S1

FB
BP/M
50 V 0.1 µF 50 V

S
S
PI-7850-033016

Figure 10. LinkSwitch-TN2 General Test Circuit.

50 Ω FB BP/M

D S
0.1 µF
VDR

PI-7899-031816

Figure 11. LinkSwitch-TN2 Duty Cycle Measurement. Figure 12. LinkSwitch-TN2 Minimum On-Time Test Circuit.

T1 T2

VDR
VFALL VRISE

TON_MIN = T2 - T1

0V

PI-7898-031716

Figure 13. LinkSwitch-TN2 Minimum On-Time Measurement.

16
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Typical Performance Characteristics

1.1 0.7

PI-2213-012301

PI-7932i-050922
Scaling Factors:
0.6 LNK3202 1.00
LNK3204 2.05

Drain Current IDS (A)

(Normalized to 25 °C)

LNK3205 4.10
Breakdown Voltage

0.5 LNK3206 6.25

LNK3207 6.25
LNK3208 10.5
0.4 LNK3209 17.0
1.0
0.3

0.2

0.1

0.9 0
-50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800
Junction Temperature (°C) Drain Voltage VDS (V)
Figure 14. Breakdown vs. Temperature. Figure 15. Maximum Allowable Drain Current vs. Drain Voltage.

0.30 1000

PI-7853j-050922
PI-7851j-050922

Scaling Factors:
LNK3202 1.00
0.25 Drain Capacitance (pF) LNK3204 2.05
Drain Current IDS (A)

25 °C
LNK3205 4.10
LNK3206 6.25
0.20 100 LNK3207 6.25
100 °C LNK3208 10.5
LNK3209 17.0
0.15
Scaling Factors:
LNK3202 1.00
0.10 LNK3204 2.05 10
LNK3205 4.10
LNK3206 6.25
0.05 LNK3207 6.25
LNK3208 10.5
LNK3209 17.0
0 1
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450
Drain Voltage VDS (V) Drain Voltage (V)

Figure 16. Output Characteristics. Figure 17. COSS vs. Drain Voltage.
Default Current Limit at High di/dt

1.2 1.2
Default Current Limit at Low di/dt

PI-8112b-051022

PI-8111b-051022

1.0 1.0
(Normalized to 25 ˚C)

(Normalized to 25 ˚C)

0.8 0.8

0.6 Normalized ILIM = 1 Normalized ILIM = 1

0.6
Scaling Factors: Scaling Factors:
LNK3202 55 mA/µs 136 mA LNK3202 250 mA/µs 170 mA
0.4 LNK3204 65 mA/µs 257 mA 0.4 LNK3204 415 mA/µs 317 mA
LNK3205 75 mA/µs 375 mA LNK3205 500 mA/µs 448 mA
LNK3206 95 mA/µs 482 mA LNK3206 580 mA/µs 580 mA
0.2 LNK3207 95 mA/µs 780 mA 0.2 LNK3207 610 mA/µs 1015 mA
LNK3208 165 mA/µs 1040 mA LNK3208 1000 mA/µs 1285 mA
LNK3209 165 mA/µs 1300 mA LNK3209 1000 mA/µs 1600 mA
0.0 0.0
-50 0 50 100 150 -50 0 50 100 150
Junction Temperature (˚C) Junction Temperature (˚C)
Figure 18. Current Limit vs. Temperature. Figure 19. Current Limit vs. Temperature.

17
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Typical Performance Characteristics

1.2 1.4

Normalized Default Current Limit

PI-8114b-051022
PI-8113-092716
1.2
1.0
(Normalized to 25 ˚C)
Output Frequency

1.0
0.8
0.8 Scaling Normalized Normalized
0.6 Factors: di/dt = 1 ILIM = 1
0.6 LNK3202 55 mA/µs 136 mA
LNK3204 65 mA/µs 257 mA
0.4
0.4 LNK3205 75 mA/µs 375 mA
LNK3206 95 mA/µs 482 mA
0.2 LNK3207 95 mA/µs 780 mA
0.2 LNK3208 165 mA/µs 1040 mA
LNK3209 165 mA/µs 1300 mA
0.0 0.0
-50 0 50 100 150 1 2 3 4 5 6 7
Junction Temperature (˚C) Normalized di/dt
Figure 20. Output Frequency vs. Junction Temperature. Figure 21. Default Current Limit vs. di/dt.
Normalized Reduced Current Limit

1.4

PI-8115b-0512022
1.2

1.0

0.8 Scaling Normalized Normalized

Factors: di/dt = 1 ILIM = 1
0.6 LNK3202 28 mA/µs 80 mA
LNK3204 65 mA/µs 205 mA
0.4 LNK3205 75 mA/µs 259 mA
LNK3206 95 mA/µs 370 mA
LNK3207 95 mA/µs 620 mA
0.2 LNK3208 165 mA/µs 840 mA
LNK3209 165 mA/µs 1050 mA
0.0
1 2 3 4 5 6 7
Normalized di/dt
Figure 22. Reduced Current Limit vs. di/dt.

18
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Typical Performance Characteristics 900 V

2.5 0.6

PI-8957-040319

PI-8831-092618
Scaling Factors: Scaling Factors:
LNK3x94 1.0 LNK3294 1.0
LNK3x96 3.0 0.5 LNK3296 3.3
2

Drain Current IDS (A)

25 °C
Drain Current (A)

0.4
1.5
100 °C
0.3
1
0.2

0.5
0.1

Current Pulse Width ≤ 500 ns

0 0
0 125 250 375 500 625 750 875 1000 0 5 10 15 20
Drain Voltage (V) Drain Voltage VDS (V)
Figure 23. Maximum Allowable Drain Current vs. Drain Voltage. Figure 24. Output Characteristics.

10000

PI-8832-021419
Scaling Factors:
LNK3294 1.0
LNK3296 3.3
Drain Capacitance (pF)

1000

100

10

1
0 100 200 300 400 500
Drain Voltage (V)
Figure 25. COSS vs. Drain Voltage.

19
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Typical Performance Characteristics 900 V

Normalized Standard Current Limit

Normalized Standard Current Limit

1.4 1.4

PI-8914-020719
PI-8913-020719
1.2 1.2

1.0 1.0

0.8 0.8

Scaling Normalized Normalized Scaling Normalized Normalized

0.6 0.6
Factors: di/dt = 1 ILIM = 1 Factors: di/dt = 1 ILIM = 1
LNK3294 65 mA/µs 250 mA LNK3294 65 mA/µs 197 mA
0.4 LNK3296 95 mA/µs 480 mA 0.4 LNK3296 95 mA/µs 368 mA

0.2 0.2

0.0 0.0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
Normalized di/dt Normalized di/dt
Figure 26. Normalized Current Limit vs. di/dt. Figure 27. Normalized Current Limit vs. di/dt.

Default Current Limit at High di/dt

1.2 1.2
Default Current Limit at Low di/dt

PI-8915-020719

PI-8916-020719
1.0 1.0
(Normalized to 25 °C)

(Normalized to 25 °C)
0.8 0.8

0.6 0.6
Scaling Scaling
Factors: Normalized ILIM = 1 Factors: Normalized ILIM = 1
0.4 LNK3294 65 mA/µs 250 mA 0.4 LNK3294 415 mA/µs 283 mA
LNK3296 95 mA/µs 480 mA LNK3296 610 mA/µs 577 mA

0.2 0.2

0.0 0.0
-50 -30 -10 10 30 50 70 90 110 130 150 -50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 28. Standard Current Limit at Low Ramp Rate. Figure 29. Standard Current Limit at High Ramp Rate.
Reduced Current Limit at High di/dt
Reduced Current Limit at Low di/dt

1.2 1.2
PI-8918-020719
PI-8917-020719

1.0 1.0
(Normalized to 25 °C)
(Normalized to 25 °C)

0.8 0.8

0.6 0.6
Scaling Scaling
Factors: Normalized ILIM = 1 Factors: Normalized ILIM = 1
0.4 LNK3294 65 mA/µs 197 mA 0.4 LNK3294 415 mA/µs 225 mA
LNK3296 95 mA/µs 368 mA LNK3296 610 mA/µs 460 mA

0.2 0.2

0.0 0.0
-50 -30 -10 10 30 50 70 90 110 130 150 -50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 30. Reduced Current Limit at Low Ramp Rate. Figure 31. Reduced Current Limit at High Ramp Rate.

20
www.power.com Rev. P 06/22
 LinkSwitch-TN2

PDIP-8C (P Package)
.06 in
⊕ D S .004 (.10) [1.41 mm]
-E- ∅.03 in
[0.86 mm]

.10 in
[2.54 mm] Typ
.240 (6.10)
.260 (6.60)
.30 in
∅.06 in [7.62 mm]
0.200 in [1.41 mm]
[5.08 mm]

Pin 1

.356 (9.05)
-D-
.387 (9.83) .30 in
[7.62 mm]
.057 (1.45)
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM

-T-
SEATING .008 (.20)
PLANE .118 (3.00) .015 (.38)
.140 (3.56)

.300 (7.62) BSC

.100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7)
.068 (1.73) MINIMUM .300 (7.62)
.014 (.36)
.022 (.56) ⊕T E D S .010 (.25) M .390 (9.91)

Notes:
1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses.
3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1.
Pin 3 is omitted.
5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm).
6. Lead width measured at package body. P08C
7. Lead spacing measured with the leads constrained to be perpendicular to plane T.
PI-3933b-092920

21
www.power.com Rev. P 06/22
 LinkSwitch-TN2

SMD-8C (G Package)
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
.086 protrusions shall not exceed
.186 .006 (.15) on any side.
.372 (9.45) 3. Pin locations start with Pin 1,
.240 (6.10)
.388 (9.86) .286 .420 and continue counter-clock-
.260 (6.60)
⊕ E S .010 (.25) wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
Pin 1 Pin 1 5. Lead width measured at
.137 (3.48) package body.
MINIMUM Solder Pad Dimensions 6. D and E are referenced
.100 (2.54) (BSC) datums on the package
body.
.356 (9.05)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)

.004 (.10)
.032 (.81) .048 (1.22)
.068 (1.73)
.009 (.23) .004 (.10) .036 (0.91) 0 °- 8°
.043 (1.09)
.012 (.30) .044 (1.12) G08C
PI-4015b-072320

22
www.power.com Rev. P 06/22
 LinkSwitch-TN2

SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315

23
www.power.com Rev. P 06/22
 LinkSwitch-TN2

PDIP-8C (P) and SMD-8C (G) PACKAGE MARKING

A
1630
LNK3204P C
3Z380J D

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code

PI-8117-093016

SO-8C (D) PACKAGE MARKING

A
1630
LNK3202D C
4D426E D

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code

PI-8116-092816

24
www.power.com Rev. P 06/22
 LinkSwitch-TN2

MSL Table

Part Number MSL Rating

LNK3202P
LNK3204P
LNK3294P
LNK3205P
LNK3206P
N/A
LNK3207P
LNK3208P
LNK3209P
LNK3294P
LNK3296P

LNK3202G
LNK3204G
LNK3294G
LNK3205G
LNK3206G
3
LNK3207G
LNK3208G
LNK3209G
LNK3294G
LNK3296G

LNK3202D
LNK3204D
LNK3205D
LNK3206D 1
LNK3207D
LNK3208D
LNK3209D

ESD and Latch-Up

Test Conditions Results

Latch-up at 125 °C EIA/JESD78 > ±100 mA or > 1.5 × VMAX on all pins

> ±2 kV on all pins, except DRAIN Pin for

Human Body Model ESD EIA/JESD22-A114-A
LNK3202 ±1.5 kV

Machine Model ESD EIA/JESD22-A115-A > ±200 V on all pins

Part Ordering Information

• LinkSwitch Product Family
• TN2 Series Number
• MOSFET Rating
0 725 V
9 900 V
• Package Identifier (All RoHS Compliant and Halogen Free)
G Plastic Surface Mount SMD-8C
P Plastic PDIP-8C
D Plastic SO-8C (725 V Family only)
• Tape & Reel and Other Options
Tape and Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D Package.
LNK 3204 G - TL TL
Not available for P Package.

25
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Revision Notes Date

A Preliminary release of 725 V parts. 04/16
B Introduction release of 725 V parts. 07/16
C Production release of 725 V parts. 10/16
D Added IC images on page 1. 10/14/16
E Updated Note D, Figure 16, VFB parameter. 11/8/16
Updated Figures 12 and 13 Captions. Corrected DRAIN Pin Peak Current to match Figure 15 and Corrected Note 2 in
F 01/06/17
Absolute Maximum Ratings Section.
G Production release of LNK3294 and LNK3296 parts. 02/19
H Updated Figure 23. 04/19
I Added Max values for IS2 and added IDSS2 at TJ - 125 °C. 08/19
J Updated ESD and Latch-Up table. 01/20
K Updated per PCN-20321. 08/20
L Updated per PCN-20331 and added size 7. 10/20
M Updated VBP(SHUNT) Min and Max values. 10/21/20
N Introduction release of LNK3208 part. 04/22
O Introduction release of LNK3209 part. 05/22
P Production release of LNK3208 and LNK3209 parts. 06/22

26
www.power.com Rev. P 06/22
 LinkSwitch-TN2

Notes

27
www.power.com Rev. P 06/22
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC,
HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI,
PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are
property of their respective companies. ©2022, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters Germany Italy Singapore

5245 Hellyer Avenue (AC-DC/LED/Motor Control Sales) Via Milanese 20, 3rd. Fl. 51 Newton Road
San Jose, CA 95138, USA Einsteinring 24 20099 Sesto San Giovanni (MI) Italy #19-01/05 Goldhill Plaza
Main: +1-408-414-9200 85609 Dornach/Aschheim Phone: +39-024-550-8701 Singapore, 308900
Customer Service: Germany e-mail: eurosales@power.com Phone: +65-6358-2160
Worldwide: +1-65-635-64480 Tel: +49-89-5527-39100 e-mail: singaporesales@power.com
Japan
Americas: +1-408-414-9621 e-mail: eurosales@power.com
Yusen Shin-Yokohama 1-chome Bldg. Taiwan
e-mail: usasales@power.com
Germany (Gate Driver Sales) 1-7-9, Shin-Yokohama, Kohoku-ku 5F, No. 318, Nei Hu Rd., Sec. 1
China (Shanghai) HellwegForum 3 Yokohama-shi, Nei Hu Dist.
Rm 2410, Charity Plaza, No. 88 59469 Ense Kanagawa 222-0033 Japan Taipei 11493, Taiwan R.O.C.
North Caoxi Road Germany Phone: +81-45-471-1021 Phone: +886-2-2659-4570
Shanghai, PRC 200030 Tel: +49-2938-64-39990 e-mail: japansales@power.com e-mail: taiwansales@power.com
Phone: +86-21-6354-6323 e-mail: igbt-driver.sales@power.com
Korea UK
e-mail: chinasales@power.com
India RM 602, 6FL Building 5, Suite 21
China (Shenzhen) #1, 14th Main Road Korea City Air Terminal B/D, 159-6 The Westbrook Centre
17/F, Hivac Building, No. 2, Keji Nan Vasanthanagar Samsung-Dong, Kangnam-Gu, Milton Road
8th Road, Nanshan District, Bangalore-560052 India Seoul, 135-728, Korea Cambridge
Shenzhen, China, 518057 Phone: +91-80-4113-8020 Phone: +82-2-2016-6610 CB4 1YG
Phone: +86-755-8672-8689 e-mail: indiasales@power.com e-mail: koreasales@power.com Phone: +44 (0) 7823-557484
e-mail: chinasales@power.com e-mail: eurosales@power.com