1 Architecture of 8255

 The parallel input-output port chip 8255 is also called as programmable

peripheral input- output port. The Intel’s 8255 is designed for use with
Intel’s 8-bit, 16-bit and higher capability microprocessors.
 It has 24 input/output lines which may be individually programmed in
two groups of twelve lines each, or three groups of eight lines. The two
groups of I/O pins are named as Group A and Group B. Each of these two
groups contains a subgroup of eight I/O lines called as 8-bit port and
another subgroup of four lines or a 4-bit port. 
Thus Group A contains an 8-bit port A along with a 4-bit port. C upper.
The port A lines are identified by symbols PA0-PA7 while the port C
lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit port
B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3.
The port C upper and port C lower can be used in combination as an 8-bit
port C. Both the port C are assigned the same address. Thus one may
have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from
8255. All of these ports can function independently either as input or as
output ports. This can be achieved by programming the bits of an internal
register of 8255 called as control word register (CWR). This buffer
receives or transmits data upon the execution of input or output
instructions by the microprocessor. The control words or status
information is also transferred through the buffer.
 

 
.
 Flags register in 8085 Microprocessor
MicrocontrollerMicroprocessor8085
In 8085 microprocessor, the flags register can have a total of eight flags. Thus
a flag can be represented by 1 bit of information. But only five flags are
implemented in 8085. And they are:
Carry flag (Cy),
Auxiliary carry flag (AC),
Sign flag (S),
Parity flag (P), and
Zero flag (Z).
The respective position of these flag bits in flag register has been show the
below figure. The positions marked by “x” are to be considered as don't care
bits in the flags register. The user is not required to memorize the positions of
these flags in the flags register.

Fig. Flags register

Now consider the programmer's view of 8085 contains the flags register has
been depicted in the following figure -

Carry flag (Cy): after performing the addition of any two 8-bit numbers, the
carry generated can be either 0 or 1. That is only 1-bit. Thus to store the carry
information 1-bit storage is enough. The Cy flag is stored in the LS bit position
in the flags register. Instructions that use the Cy flag are widely used in the
user programs.
Example 1: In the addition of 45H and F3H, the result thus produced will be
38H and with Cy flag = 1, as shown below.
Auxiliary carry flag (Ac): Now let us consider the addition of any two 8-bit (2-
hex digit) numbers, a carry may be generated when we add the LS hex digits
of the two numbers. Such a carry is called intermediate carry also known as
half carry, or auxiliary carry (AC). Intel prefers to call it AC. In the above
Example 1, AC was not generated but in Example 2, AC is generated.
As this is only an intermediate carry, we may not be interested in storing this
bit information. But 8085 microprocessor still stores this AC information in bit
position 4 of the flags register. The result of execution of DAA instruction, is
affected by the status of this flag. However, in our 8085 instruction set does
not provide any instruction, which explicitly uses the AC flag.
Sign flag (S): The S flag is set to 1, when the result thus produced against
any logical or arithmetic operations is negative, indicated by MS bit of 8-bit
result being 1. It is reset to 0 otherwise if the result is positive, indicated by
MS bit of 8-bit result being 0.
Thus, the value of S flag is essentially the value of the MS bit of the 8-bit
result. In the above Example 1, as the 8-bit result is 38H = 0 011 1000, 0 in
MSB indicates result is positive and the sign flag is reset to 0. Note that we
are not considering here the 9-bit result including the carry, to decide the S
flag value. In Example 2, as the 8-bit result is A3H = 1 010 0011, the MSB has
become 1 that means negative and the sign flag is set to 1.
But when we shall work with unsigned numbers, then we shall simply ignore
the S flag. For example, if we are treating 85H and 1EH as unsigned
numbers, their sum will be the unsigned number A3H. In this case, S flag
becomes 1, but we do not care for the value of the S flag. And we shall ignore
it as well.
Instructions that use the S flag are quite often used in the user programs.
Parity flag (P): The P flag is set to 1, if the 8-bit result thus produced against
any logical and arithmetic operation has an even number of 1's in it. If there
are odd number of 1's in the 8-bit result, the P flag is reset to 0.
In our previous Example 1, as the 8-bit result 38H = 0011 1000 has three
numbers of 1's, so having odd number of 1’s, the parity flag is reset to 0. On
the other hand, in Example 2, as the 8-bit result A3H = 1010 0011 has four
numbers of 1's (so an even number of 1’s), the parity flag is set to 1.
As the user does not really care for the number of 1's present in the result
after an arithmetic operation, this flag is not of much use practically.
Zero flag (Z): The Z flag is set to 1, if after arithmetic and logical operations,
the 8-bit result thus produced, is 00H. If the 8-bit result is not equal to 00H,
the Z flag is reset to 0. Thus the Z flag is hoisted to indicate that the result is
0.
ADDRESSING MODES:-- The different ways in which a source operand is denoted in an
instruction is known as addressing modes. There are 8 different addressing modes in 8086
programming –

>>immediate addressing mode. The addressing mode in which the data operand is a part
of the instruction itself is known as immediate addressing mode. Example MOV CX, 4929
H, ADD AX, 2387 H, MOV AL, FFH

>>Register addressing mode It means that the register is the source of an operand for an
instruction. Example MOV CX, AX ; copies the contents of the 16-bit AX register into ADD
BX, AX ; the 16-bit CX register), ADD BX, AX

>>Direct addressing mode The addressing mode in which the effective address of the
memory location is written directly in the instruction. Example MOV AX, [1592H], MOV AL,
[0300H]

>>Register indirect addressing mode This addressing mode allows data to be addressed at
any memory location through an offset address held in any of the following registers: BP,
BX, DI & SI. Example MOV AX, [BX] ; Suppose the register BX contains 4895H, then the
contents ADD CX, {BX} ; 4895H are moved to AX

>>Based addressing mode In this addressing mode, the offset address of the operand is
given by the sum of contents of the BX/BP registers and 8-bit/16-bit displacement.
Example MOV DX, [BX+04], ADD CL, [BX+08]

>>Indexed addressing mode In this addressing mode, the operands offset address is found
by adding the contents of SI or DI register and 8-bit/16-bit displacements. Example MOV
BX, [SI+16], ADD AL, [DI+16]

>>Based-index addressing mode In this addressing mode, the offset address of the
operand is computed by summing the base register to the contents of an Index register.
Example ADD CX, [AX+SI], MOV AX, [AX+DI]

>>Based indexed with displacement mode In this addressing mode, the operands offset is
computed by adding the base register contents. An Index registers contents and 8 or 16-bit
displacement. Example MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]