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Resume SH

This document contains contact information and a resume for Shoaib Shahzad. It lists an objective of applying research and development skills to obtain profits for organizations, with an interest in teaching. It details technical skills in programming, tools, and hardware. It provides experience in design engineering including FPGA implementation and verification. It lists academic projects in H.264, JPEG, equalization, and more. It provides education history from Lund University and University of Lahore.

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Ayaz Butt Azz
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142 views2 pages

Resume SH

This document contains contact information and a resume for Shoaib Shahzad. It lists an objective of applying research and development skills to obtain profits for organizations, with an interest in teaching. It details technical skills in programming, tools, and hardware. It provides experience in design engineering including FPGA implementation and verification. It lists academic projects in H.264, JPEG, equalization, and more. It provides education history from Lund University and University of Lahore.

Uploaded by

Ayaz Butt Azz
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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House 102, Street 3 Tehmasipabad, Rawalpindi, Pakistan

+92-3320626666

shoaib.shaby@gmail.com

Shoaib Shahzad
Objective
To apply research and development capabilities of design engineering to obtain maximum profits for a well reputed organization engaged in growing technologies. Also interested in teaching to deliver my skills for bright future of the students.

Technical Skills
Programming: VHDL, C/C++, Assembly, TCL scripting, System C Tools: Cadence, Xilinx ISE-EDK, ModelSim, Synopsys Design Vision, MatLab, Labview Hardware tools: FPGA, Logic Analyzer, Oscilloscope, Micro-controllers(Atmel, PIC) Courses of interest: Digital Logic Design, Algorithms, Data structures, Programing, Mathematics (All level), Probability Socware Technologies Islamabad, Pakistan

Experience
[Sep 2007]-[June 2009] Design Engineer

Major duties include RTL coding, FPGA implementation and verification Dealing with synthesis and timing issues during implementation like static timing analysis, clock improvements, RTL optimization, Xilinx IP cores. Handling multiple clock domains Co-coordinating and reporting to project manager for on current projects Also worked as team leader for couple of projects Documentation and presentations

Academic Projects
ASIC Implementation of H.264 Intra-prediction Module Tasks includes: VHDL programming Synthesis using Synopsys Design Vision Place and route using SOC-Encounter ( Cadence) Verification using FPGA(Virtex II Pro and logic analyzer) JPEG encoder/decoder Tasks includes: Matlab Model VHDL programming Synthesis and Place and route Verfication FPGA based Equalizer Tasks includes: VHDL and Matlab Programming

FPGA implementation using Virtex II Pro ASIC implementation of SRAM cells Main tasks: Cadence implementation using cadence virtousu LVS vs DRC Two stage amplifier design using Cadence Viterbi Decoder Tasks includes: Matlab mode and VHDL programming Signal processing based projects Real time Reverberation using TMS320DM6437 in C and Matlab Virtual Reality Environment using Matlab

Education Lund University Specialized in System on Chip Lund Masters Eng.

Majors: VLSI, ASIC projects, Image processing, DSP design, Digital IC design, Embedded systems The University of Lahore Lahore BS Eng. Specialized in Electronics and Communication Majors: Microelectronics, Digital Design, Signal processing, Wireless Communication

Research/Master Thesis Proposed a novel algorithm of Intra-prediction in H.264 with ASIC implementation The proposed areas: Fast algorithm for intra-prediction mode selection Enhanced version of CABAC ASIC implementation in VHDL and cadence Verification of project using FPGA and Logic analyzer Computer Skills References Will be provided on demand MS Office and Windows Linux and Unix (Basics) LaTex MS Project

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