Preliminary

X24C16 Information

16K X24C16 2048 x 8 Bit

Serial E2PROM

FEATURES DESCRIPTION
• 2.7V to 5.5V Power Supply The X24C16 is a CMOS 16,384 bit serial E2PROM,
• Low Power CMOS internally organized 2048 X 8. The X24C16 features a
—Active Read Current Less Than 1 mA serial interface and software protocol allowing operation
—Active Write Current Less Than 3 mA on a simple two wire bus.
—Standby Current Less Than 50 µA
• Internally Organized 2048 x 8 The X24C16 is fabricated with Xicor’s advanced CMOS
• 2 Wire Serial Interface Textured Poly Floating Gate Technology.
—Bidirectional Data Transfer Protocol The X24C16 utilizes Xicor’s proprietary Direct WriteTM
• Sixteen Byte Page Write Mode cell providing a minimum endurance of 100,000 cycles
—Minimizes Total Write Time Per Byte and a minimum data retention of 100 years.
• Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC
Packages

FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(7) TEST H.V. GENERATION
START CYCLE
TIMING
& CONTROL
(5) SDA START
STOP
LOGIC

CONTROL
LOGIC
SLAVE ADDRESS
E2PROM
REGISTER XDEC
(6) SCL LOAD INC 128 X 128
+COMPARATOR

(3) A2 WORD
(2) A1 ADDRESS
COUNTER
(1) A0

R/W YDEC

8
CK DOUT
PIN DATA REGISTER

DOUT
ACK
3840 FHD F01

© Xicor, 1991 Patents Pending Characteristics subject to change without notice

1
3840-1.1 7/29/96 T1/C0/D0 SH
X24C16

PIN DESCRIPTIONS PIN CONFIGURATION

Serial Clock (SCL)
The SCL input is used to clock all data into and out of the DIP/SOIC
device.
A0 1 8 VCC
Serial Data (SDA)
A1 2 7 TEST
SDA is a bidirectional pin used to transfer data into and X24C16
A2 3 6 SCL
out of the device. It is an open drain output and may be
VSS 4 5 SDA
wire-ORed with any number of open drain or open
collector outputs. 3840 FHD F02

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the Pull-Up SOIC
Resistor selection graph at the end of this data sheet.
Address (A0, A1, A2) NC 1 14 NC
A0 2 13 VCC
The A0, A1 and A2 inputs are unused by the X24C16,
A1 3 12 TEST
however, they must be tied to VSS to insure proper
device operation. NC 4 X24C16 11 NC
A2 5 10 SCL
PIN NAMES VSS 6 9 SDA
Symbol Description NC 7 8 NC

A0–A2 Address Inputs 3840 FHD F03

SDA Serial Data

SCL Serial Clock
TEST Hold at VSS
VSS Ground
VCC Supply Voltage
NC No Connect
3840 PGM T01

2
X24C16

DEVICE OPERATION Clock and Data Conventions

The X24C16 supports a bidirectional bus oriented pro- Data states on the SDA line can change only during SCL
tocol. The protocol defines any device that sends data LOW. SDA state changes during SCL HIGH are re-
onto the bus as a transmitter, and the receiving device served for indicating start and stop conditions. Refer to
as the receiver. The device controlling the transfer is a Figures 1 and 2.
master and the device being controlled is the slave. The
Start Condition
master will always initiate data transfers, and provide
the clock for both transmit and receive operations. All commands are preceded by the start condition,
Therefore, the X24C16 will be considered a slave in all which is a HIGH to LOW transition of SDA when SCL is
applications. HIGH. The X24C16 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE
3840 FHD F06

3
X24C16

Stop Condition The X24C16 will respond with an acknowledge after

All communications must be terminated by a stop con- recognition of a start condition and its slave address. If
dition, which is a LOW to HIGH transition of SDA when both the device and a write operation have been se-
SCL is HIGH. The stop condition is also used by the lected, the X24C16 will respond with an acknowledge
X24C16 to place the device into the standby power after the receipt of each subsequent eight bit word.
mode after a read sequence. A stop condition can only In the read mode the X24C16 will transmit eight bits of
be issued after the transmitting device has released the data, release the SDA line and monitor the line for an
bus. acknowledge. If an acknowledge is detected and no
Acknowledge stop condition is generated by the master, the X24C16
will continue to transmit data. If an acknowledge is not
Acknowledge is a software convention used to indicate detected, the X24C16 will terminate further data trans-
successful data transfer. The transmitting device, either missions. The master must then issue a stop condition
master or slave, will release the bus after transmitting to return the X24C16 to the standby power mode and
eight bits. During the ninth clock cycle the receiver will place the device into a known state.
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT STOP BIT

3840 FHD F07

Figure 3. Acknowledge Response From Receiver

SCL FROM
MASTER 1 8 9

DATA
OUTPUT
FROM
TRANSMITTER

DATA
OUTPUT
FROM
RECEIVER
START ACKNOWLEDGE
3840 FHD F08

4
X24C16

DEVICE ADDRESSING eight bits of address in the word address field, providing
direct access to the whole 2048 x 8 array.
Following a start condition the master must output the
address of the slave it is accessing. The most significant Following the start condition, the X24C16 monitors the
four bits of the slave address are the device type identifier SDA bus comparing the slave address being transmit-
(see Figure 4). For the X24C16 this is fixed as 1010[B]. ted with its slave address (device type). Upon a correct
compare the X24C16 outputs an acknowledge on the
Figure 4. Slave Address
SDA line. Depending on the state of the R/W bit, the
X24C16 will execute a read or write operation.
HIGH
ORDER
DEVICE TYPE WORD WRITE OPERATIONS
IDENTIFIER ADDRESS
Byte Write
For a write operation, the X24C16 requires a second
1 0 1 0 A2 A1 A0 R/W
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
3840 FHD F09 2048 words in the array. Upon receipt of the word address
the X24C16 responds with an acknowledge, and awaits
The next three bits of the slave address field are the bank the next eight bits of data, again responding with an
select bits. They are used by the host to toggle between acknowledge. The master then terminates the transfer by
the eight 256 x 8 banks of memory. These are, in effect, generating a stop condition, at which time the X24C16
the most significant bits for the word address. begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C16
The next three bits of the slave address are an extension inputs are disabled, and the device will not respond to any
of the array’s address and are concatenated with the requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.

Figure 5. Byte Write

S
T SLAVE WORD S
BUS ACTIVITY: A ADDRESS ADDRESS DATA T
MASTER R O
T P
SDA LINE S P
A A A
BUS ACTIVITY: C C C
X24C16 K K K
3840 FHD F10

5
X24C16

Page Write Flow 1. ACK Polling Sequence

The X24C16 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte WRITE OPERATION
write operation, but instead of terminating the write cycle COMPLETED
after the first data word is transferred, the master can ENTER ACK POLLING
transmit up to fifteen more words. After the receipt of
each word, the X24C16 will respond with an acknowl-
edge. ISSUE
START
After the receipt of each word, the four low order address
bits are internally incremented by one. The high order
seven bits of the address remain constant. If the master
should transmit more than sixteen words prior to gener- ISSUE SLAVE
ISSUE STOP
ating the stop condition, the address counter will “roll ADDRESS AND R/W = 0
over” and the previously written data will be overwritten.
As with the byte write operation, all inputs are disabled
until completion of the internal write cycle. Refer to ACK NO
Figure 6 for the address, acknowledge and data transfer RETURNED?
sequence.
YES
Acknowledge Polling
The disabling of the inputs can be used to take advan- NEXT
NO
tage of the typical 5 ms write cycle time. Once the stop OPERATION
A WRITE?
condition is issued to indicate the end of the host’s write
operation the X24C16 initiates the internal write cycle.
YES
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the X24C16 is still busy with the ISSUE BYTE
ISSUE STOP
ADDRESS
write operation no ACK will be returned. If the X24C16
has completed the write operation an ACK will be
returned and the host can then proceed with the next
read or write operation. Refer to Flow 1.
PROCEED PROCEED

3840 FHD F11

Figure 6. Page Write

S
T SLAVE WORD S
BUS ACTIVITY: A ADDRESS ADDRESS (n) DATA n DATA n+1 DATA n+15 T
MASTER R O
T P
SDA LINE S P
A A A A A
BUS ACTIVITY: C C C C C
X24C16 K K K K K

NOTE: In this example n = xxxx 000 (B); x = 1 or 0

3840 FHD F12

6
X24C16

READ OPERATIONS bit word. The read operation is terminated by the master;
by not responding with an acknowledge and by issuing
Read operations are initiated in the same manner as
a stop condition. Refer to Figure 7 for the sequence of
write operations with the exception that the R/W bit of the
address, acknowledge and data transfer.
slave address is set to a one. There are three basic read
operations: current address read, random read and Random Read
sequential read.
Random read operations allow the master to access any
It should be noted that the ninth clock cycle of the read memory location in a random manner. Prior to issuing
operation is not a “don’t care.” To terminate a read the slave address with the R/W bit set to one, the master
operation, the master must either issue a stop condition must first perform a “dummy” write operation. The mas-
during the ninth cycle or hold SDA HIGH during the ninth ter issues the start condition, and the slave address
clock cycle and then issue a stop condition. followed by the word address it is to read. After the word
address acknowledge, the master immediately reissues
Current Address Read the start condition and the slave address with the R/W bit
Internally the X24C16 contains an address counter that set to one. This will be followed by an acknowledge from
maintains the address of the last word accessed, the X24C16 and then by the eight bit word. The read
incremented by one. Therefore, if the last access (either operation is terminated by the master; by not responding
a read or write) was to address n, the next read operation with an acknowledge and by issuing a stop condition.
would access data from address n + 1. Upon receipt of Refer to Figure 8 for the address, acknowledge and data
the slave address with the R/W bit set to one, the transfer sequence.
X24C16 issues an acknowledge and transmits the eight

Figure 7. Current Address Read

S
T SLAVE S
BUS ACTIVITY: A ADDRESS DATA T
MASTER R O
T P
SDA LINE S P
A
BUS ACTIVITY: C
X24C16 K
3840 FHD F13

Figure 8. Random Read

S S
T SLAVE WORD T SLAVE S
BUS ACTIVITY: A ADDRESS ADDRESS n A ADDRESS DATA n T
MASTER R R O
T T P
SDA LINE S S P
A A A
BUS ACTIVITY: C C C
X24C16 K K K
3840 FHD F14

7
X24C16

Sequential Read The data output is sequential, with the data from address
Sequential reads can be initiated as either a current n followed by the data from n + 1. The address counter
address read or random access read. The first word is for read operations increments all address bits, allowing
transmitted as with the other read modes, however, the the entire memory contents to be serially read during
master now responds with an acknowledge, indicating it one operation. At the end of the address space (address
requires additional data. The X24C16 continues to out- 2047), the counter “rolls over” to 0 and the X24C16
put data for each acknowledge received. The read continues to output data for each acknowledge re-
operation is terminated by the master; by not responding ceived. Refer to Figure 9 for the address, acknowledge
with an acknowledge and by issuing a stop condition. and data transfer sequence.

Figure 9. Sequential Read

SLAVE S
BUS ACTIVITY: ADDRESS A A A T
MASTER C C C O
K K K P
SDA LINE P
A
BUS ACTIVITY: C
X24C16 K DATA n DATA n+1 DATA n+2 DATA n+x
3840 FHD F15

Figure 10. Typical System Configuration

VCC
PULL-UP
RESISTORS

SDA
SCL

MASTER SLAVE MASTER

SLAVE MASTER
TRANSMITTER/ TRANSMITTER/ TRANSMITTER/
RECEIVER TRANSMITTER
RECEIVER RECEIVER RECEIVER
3840 FHD F16

8
X24C16

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias .................. –65°C to +135°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
Voltage on any Pin with This is a stress rating only and the functional operation of
Respect to VSS ................................ –1.0V to +7.0V the device at these or any other conditions above those
D.C. Output Current ............................................ 5 mA indicated in the operational sections of this specification is
Lead Temperature not implied. Exposure to absolute maximum rating condi-
(Soldering, 10 Seconds) ............................. 300°C tions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max. Supply Voltage Limits
Commercial 0°C 70°C X24C16 4.5V to 5.5V
Industrial –40°C +85°C X24C16–3.5 3.5V to 5.5V
Military –55°C +125°C X24C16–3 3V to 5.5V
3840 PGM T09
X24C16–2.7 2.7V to 5.5V
3840 PGM T10

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified)
Limits
Symbol Parameter Min. Max. Units Test Conditions
lCC1 VCC Supply Current (read) 1 SCL = VCC x 0.1/VCC x 0.9 Levels
lCC2 VCC Supply Current (write) 3 mA @ 100 KHz, SDA = Open, All Other
Inputs = GND or VCC – 0.3V
ISB1(1) VCC Standby Current 150 µA SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 5.5V
ISB2(1) VCC Standby Current 50 µA SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 3.3V +10%
ILI Input Leakage Current 10 µA VIN = GND to VCC
ILO Output Leakage Current 10 µA VOUT = GND to VCC
VlL(2) Input Low Voltage –1.0 VCC x 0.3 V
VIH(2) Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL Output Low Voltage 0.4 V IOL = 3 mA
3840 PGM T03
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(3) Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
3840 PGM T05
Notes: (1) Must perform a stop command prior to measurement.
(2) VIL min. and VIH max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.

9
X24C16

A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT

5.0V
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and 1533Ω
Fall Times 10 ns
Output
Input and Output
Timing Levels VCC x 0.5 100pF
3840 PGM T02

3840 FHD F18

A.C. CHARACTERISTICS LIMITS (Over the recommended operating conditions unless otherwise specified.)
Read & Write Cycle Limits
Symbol Parameter Min. Max. Units
fSCL SCL Clock Frequency 0 100 KHz
TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns
tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs
tBUF Time the Bus Must Be Free Before a 4.7 µs
New Transmission Can Start
tHD:STA Start Condition Hold Time 4.0 µs
tLOW Clock Low Period 4.7 µs
tHIGH Clock High Period 4.0 µs
tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs
tHD:DAT Data In Hold Time 0 µs
tSU:DAT Data In Setup Time 250 ns
tR SDA and SCL Rise Time 1 µs
tF SDA and SCL Fall Time 300 ns
tSU:STO Stop Condition Setup Time 4.7 µs
tDH Data Out Hold Time 300 ns
3840 PGM T06
POWER-UP TIMING
Symbol Parameter Max. Units
tPUR(4) Power-up to Read Operation 1 ms
tPUW(4) Power-up to Write Operation 5 ms
3840 PGM T07
Bus Timing
tF tHIGH tLOW tR

SCL

tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO

SDA IN

tAA tDH tBUF

SDA OUT
3840 FHD F04

Notes: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.

10
X24C16

WRITE CYCLE LIMITS

Symbol Parameter Min. Typ.(5) Max. Units
tWR(6) Write Cycle Time 5 10 ms
3840 PGM T08

The write cycle time is the time from a valid stop bus interface circuits are disabled, SDA is allowed to
condition of a write sequence to the end of the internal remain high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24C16 address.

Write Cycle Timing

SCL

SDA 8th BIT ACK

WORD n
tWR
STOP START X24C16
CONDITION CONDITION ADDRESS
3840 FHD F05

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.

Guidelines for Calculating Typical Values of SYMBOL TABLE

Bus Pull-Up Resistors
WAVEFORM INPUTS OUTPUTS

Must be Will be
120 steady steady
V
RMIN = CC MAX =1.8KΩ
100 IOL MIN
May change Will change
RESISTANCE (KΩ)

tR from Low to from Low to

80 RMAX = High High
CBUS
60 MAX. May change Will change
RESISTANCE from High to from High to
40 Low Low
Don’t Care: Changing:
20 MIN. Changes State Not
RESISTANCE Allowed Known
0
0 20 40 60 80 100 120 Center Line
N/A is High
BUS CAPACITANCE (pF) Impedance
3840 FHD F17

11
X24C16

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)
0.360 (9.14)

0.260 (6.60)
0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300 0.060 (1.52)

(7.62) REF. 0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL 0.145 (3.68)
SEATING 0.128 (3.25)
PLANE

0.150 (3.81) 0.025 (0.64)

0.125 (3.18) 0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79) 0.020 (0.51)
0.090 (2.29) 0.016 (0.41)

0.325 (8.25)
0.015 (0.38)
0.300 (7.62)
MAX.

0°
TYP. 0.010 (0.25) 15°

NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

3926 FHD F01

12
X24C16

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.019 (0.49)

0.188 (4.78)
0.197 (5.00)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.19)
0.050 (1.27)
0.010 (0.25)

0.010 (0.25) 0.050" TYPICAL

X 45°
0.020 (0.50)

0.050"
0° – 8° TYPICAL
0.0075 (0.19)
0.010 (0.25) 0.250"

0.016 (0.410)
0.037 (0.937)

0.030"
TYPICAL
FOOTPRINT 8 PLACES

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)

3926 FHD F22

13
X24C16

14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.020 (0.51)

0.336 (8.55)
0.345 (8.75)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.10)
0.050 (1.27)
0.010 (0.25)

0.010 (0.25) 0.050" Typical

X 45°
0.020 (0.50)

0° – 8° 0.050" Typical
0.0075 (0.19)
0.010 (0.25) 0.250"

0.016 (0.41)
0.037 (0.937)

0.030" Typical
FOOTPRINT 14 Places

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F10

14
X24C16

ORDERING INFORMATION
X24C16 X X -X

Device VCC Range

Blank = 4.5V to 5.5V
3.5 = 3.5V to 5.5V
3 = 3V to 5.5V
2.7 = 2.7V to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883

Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC

Part Mark Convention X24C16 X P = 8-Lead Plastic DIP

S8 = 8-Lead SOIC
X S14 = 14-Lead SOIC

Blank = 4.5V to 5.5V, 0°C to +70°C

I = 4.5V to 5.5V, –40°C to +85°C
B = 3.5V to 5.5V, 0°C to +70°C
C = 3.5V to 5.5V, –40°C to +85°C
D = 3.0V to 5.5V, 0°C to +70°C
E = 3.0V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
M = 4.5V to 5.5V, –55°C to +125°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.

US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.

15