Modern Semiconductor Devices for Integrated Circuits Chapter 5.

MOS Capacitor

Chapter 5

MOS Capacitor
OBJECTIVES

1. Understand the modern MOS structures.

2. Understand the concepts of surface depletion,
threshold, and inversion.
3. Understand the MOS capacitor C-V
4. Build the foundation for understanding the
MOSFETs.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

MOS (Metal-Oxide-Semiconductor) Capacitor

Al (before 1970),
Heavily doped polycrystalline silicon (after 1970)
; withstanding high T without reacting with SiO2
Various metals (after 2008)

Thickness: as thin as ~ 1.5 nm

Silicon dioxide (almost perfect insulator)
Advanced dielectrics (after 2008)

The MOS capacitor

The MOS capacitor: the simplest of

MOS devices and the structural
heart of all MOS devices including
MOSFETs.

An MOS transistor is an MOS capacitor with PN junctions at two ends.

Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Revisiting Chapter 4

Metal-Semiconductor Contact
 Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

Part III: Metal-Semiconductor Junction

Two different types of MS contacts:

(1) Rectifying contacts (Schottky contact)

- Similar I-V characteristics to those of P-N junctions
- Operates with single type of carrier (majority carrier)
à Simple to fabricate
à Nostored- chargeef f
ect
à Switching speed is much higher
than that of p-n junction diodes

(2) Ohmic contacts

- Linear I-V characteristics
- To carry current into and out of the semiconductor device
I

VA
 Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

q Metal-Semiconductor Junctions (n-type S)

Rectifying contacts (Schottky contact) :
Vacuum level, E0
- the minimum energy for electrons to E0
be completely free itself from the
material.
Workfunction, qF [eV]
- The difference between vacuum level
and Fermi-level of materials.
qF m is an invariant property of metal.
It is the minimum energy required to
free up electrons from metal.
(Mg:3.66 eV, Al:4.3eV, Au:4.8eV, Ni:5.15eV)
qF s depends on the doping.

Flat band=zero field condition

Fixed material
Variable by doping concentration
constant
where c = (E0 – EC)|SURFACE is a fundamental property of the semiconductor,
so-called electron affinity.
(Example: c = 4.0 eV, 4.05 eV and 4.07 eV for Ge, Si and GaAs, respectively)
 Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

E0

E0
EC
EF
e-
EFm Ei EFm EF
EV E
e- : very small

Under equilibrium, the Fermi level should be invariant with position.

W
Electrons in S should move to M.
Net loss of electrons from S creates a surface depletion region and growing barrier to
electron transfer from the S to M until the Fermi level become flat.
(To align two EF, the electrostatic potential of S must be raised (i.e. the electron energies must
be lowered) relative to that of the metal.)

; Invariant !

; prevents further net electron diffusion from S to M.

; can be decreased or increased by the application of either forward- or reverse-bias voltage.
Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions
 Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

q Metal-Semiconductor Junctions (n-type S)

Rectifying contacts (Schottky contact) :
The barrier height from M to S remains the same! à Rectifying
Majority carriers (electrons)
contribute to the current for
both cases.

à Absence of minority
carriers
à Short delay time
E à
High-frequency properties and
switching speed are therefore
generally better than
typical p-n junctions.
V (forward bias) +
à contact potential is reduced from V0 to V0 –V Simple fabrication steps
à electrons in S CB can diffuse across the depletion +
region to M Dense integration
à forward current increasing
Vr (reverse bias)
à contact potential is increased from V0 to V0 +Vr
à electrons in S CB canNOT diffuse across the
depletion region to M
à negligible constant reverse current
 Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

q Metal-Semiconductor Junctions
I
q Ohmic contacts
ü Linear I-V characteristic in both biasing directions
VA
ü Minimal resistance and no tendency to rectify signals
ü For example: F m < F s (n-type),
The barrier to electron flow between the metal and the semiconductor is
small and easily overcome by a small voltage
; Even a small VA>0 gives rise to a large forward bias current
; Under reverse biasing, there is a small barrier for electron flow from
metal to the semiconductor
Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

q Metal-Semiconductor Junctions I
q Ohmic contacts
VA
ü Next example of Ohmic contact: F m > F s (p-type)
Easy hole flow across the junction

ü No depletion region occurs in the semiconductor unlikely the rectifying contact

( the electrostatic potential difference required to align the Fermi levels at
equilibrium calls for accumulation of majority carriers in S)
Modern Semiconductor Devices for Integrated Circuits Chapter 4. PN and Metal-Semiconductor Junctions

q Metal-Semiconductor Junctions
q Ohmic contacts : practical method

ü A practical method for forming Ohmic contacts regardless of the biasing

polarity and relative work functions between S & M is by doping the
semiconductor heavily (1017/cm3~1019/cm3) in the contact (surface) region.
ü Barrier height is not affected by an increase in the semiconductor doping. Thus
if a barrier exists at the interface, the depletion width is small enough to allow
carriers to tunnel through the barrier.

SiO2 metal SiO2

n+
n-Si

Electrical nature of Ideal MS contacts

n-type p-type
Semiconductor Semiconductor
Rectifying Ohmic
Ohmic Rectifying
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

• The Ideal MOS Capacitor

ü Modified work function qFm :

measured from the metal Fermi level
to the conduction band of the oxide
ü Assumption: F m = F S
ü A negative gate bias
à the electron energies are raised in metal
relative to the semiconductor by qV (V: applied bias)
ü A negative gate bias
à a negative charge on the metal
à an equal net positive charge to accumulate
at the surface of the semiconductor
ü Fm and FS do not change with applied voltage,
moving EFm up in energy relative to EFs causes
a tilt in the oxide conduction band hole accumulation
ü An electric field causes a gradient in Ei
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

ü Theaccumulation of holes near the interface à hole increase

ü Since no current passes through the MOS structure,

there can be no variation in the Fermi level within
the semiconductor
Ei-EF ­ à Ei moving up (band bending)
à EF lies closer to the EV à a larger hole concentration

ü A positive gate bias à lowering the metal Fermi level

by qV in metal
A positive gate voltage à positive charge on the metal
à a corresponding net negative charge at the surface
of the semiconductor (depletion of holes from the
region near the surface, leaving behind uncompensated
ionized acceptors) hole depletion
ü For a positive gate bias, moving Ei closer to EF, and bending the bands
down near the semiconductor surface
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

üFor a higher positive gate bias, the bands at the

semiconductor surface bend down more strongly
à Ei below EF (Ei < EF ) à al arg erelectr on concentr
a ti
on
à The n-type surface layer is formed not by doping,
but instead by inversion of the originally p-type
semiconductor
à it becomes the channel in the FET

ü qf: the extent of band bending at x

ü qfs: the band bending at the surface
ü fs =0: flat band
ü fs < 0: bend up, accumulation
ü fs > 0: bend down, depletion
ü fs > fF: Ei < EF, inversion
ü EF-Ei @ surface =qfF à strong inversion
Thickness of inversion layer
~ 5 nm, typically true n-type conduction channel
Thickness of depletion layer
~ hundreds of nm
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

q Effects of Real Surfaces

• Effect of Surfaces: Work function potential difference
ü Fs depends on the doping of the semiconductor since the Fermi level
changes with the doping

n+ poly n Si
EF EC EC
EF

EV EV

; always negative n+ poly p Si

EF EC EC
EF
EV EV
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

ü The bands bend down near the semiconductor surface

ü If Fms is sufficiently negative, an inversion region can exist with no
external voltage applied
üI na li
g ningEF we must include a tilt in the oxide conduction band
(implying an electric field)

To obtain the flat band

condition, we must apply
a negative voltage to the
metal (VFB= Fms)
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Flat-Band Condition and Flat-Band Voltage

For Vg = 0 Flat-Band Condition (for Vg = Vfb)

Electron energy barrier

Flat-band
Applying a negative
Band is not flat. voltage equal to flat-
band voltage (Vfb) to the
gate.

Flat-Band Voltage (<0)

Hole energy barrier

In SiO2, the exact position of EF has no significance.

,assuming EF is around in the middle of the SiO2 band gap.

Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Surface Accumulation
For Vg < Vfb

hole accumulation
(ps > p0 = Na)

At flat-band,
Potential reference

Accumulation
layer
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

In the case of surface accumulation, is small in a first-order model.

Using Gauss’s Law at the surface,

oxide
surface

(deep into semiconductor)

semiconductor

In general,

All the charge that may be present in

the substrate, including Qacc.

The MOS capacitor in accumulation behaves

like a capacitor but with a shift in V by Vfb.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Surface Depletion Negative due to acceptor ions

For Vg > Vfb

The MOS capacitor is biased into

surface depletion.
(a) Types of charge present;
(b) energy band diagram.

Depletion layer
charge
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Threshold Condition and Threshold Voltage

For more positive (Vg = Vt > Vfb)
Fermi potential energy

Threshold condition

Depletion layer
charge
Surface electron
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Fermi potential energy

Theoretical threshold voltage vs. body doping concentration.

At threshold,

Threshold Voltage, Vt
(Vg at the threshold condition)

For N-Type Body

For P-Type Body

 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Strong Inversion beyond Threshold

For Vg > Vt
WithVg > Vt , does not increase much
further beyond since even small
increase in would induce a much
larger surface electron density and
therefore a larger Vox that would soak
up the Vg .

An MOS capacitor is biased into

inversion.

Depletion layer
charge

Inversion layer charge density Inversion layer

(thickness: ~5 nm)

Surface becomes N-type.

 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

; Depletion width is pinched

The MOS capacitor in strong

inversion behaves like a
capacitor except for a voltage
There are few electrons in the P-type body, and it offset of Vt.
can take minutes for thermal generation to
generate the necessary electrons to form the
inversion layer.

How to solve this problem?

(a) The surface inversion behavior is best studied with a PN junction

butting the MOS capacitor to supply the inversion charge. (b) The
inversion layer may be thought of as a thin N-type layer.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Review: Basic MOS Capacitor Theory

Surface potential saturates at 2ϕB

in inversion when Vg is larger than
Vt and saturates at Vfb in
accumulation.

Depletion-region width in the

body of an MOS capacitor.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Components of charge (C/cm2) in the MOS

capacitor substrate: (a) depletion-layer charge; (b)
inversion-layer charge; and (c) accumulation-layer
charge.

The total substrate charge, Qsub (C/cm2),

is the sum of Qacc, Qdep, and Qinv.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Qsub Vs. Surface Potential

Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

q The Metal-Insulator-Semiconductor FET

Types of MOSFETs

Normally-off MOSFETs
(Enhancement type)

The main MOSFET type is the N-channel

enhancement type. The P-channel
enhancement type is used as a
complementary transistor in circuits known
as CMOS (Complementary MOS)
technology.
Normally-on MOSFETs
(Depletion type)

To turn them off, the channels have to be

depleted of electrons or holes
depletion type
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

q The Metal-Insulator-Semiconductor FET

• Basic Operation and Fabrication

ü Basic MOS transistor: enhancement-mode n-channel device

ü No current flows from drain to source without a conducting n channel
between them. The Fermi level is flat in equilibrium.
ü There is a potential barrier for an electron to go from the source to the
drain, corresponding to the built-in potential of the back-to-back p-n
junctions between the source and drain.
ü When a positive voltage is applied to the gate relative to the substrate,
negative charges are induced in the underlying Si, by the formation of a
depletion region and a thin surface region containing mobile electrons.
induced electron à cur r entf l
ow
ü Th eef fectoftheg atevol ta gei s tova r
yth econducta nceofth isinduced
channel for low drain-to-source voltage
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

ü If the barrier is reduced sufficiently by applying a gate voltage

in excess of what is known as the threshold voltage, VT,
there is significant current flow from the source to the drain.
The threshold voltage VT is the minimum gate voltage required to
induce the channel.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

ü Similarly, a p-channel device (made on an n-type substrate with p-

type source and drain implants or diffusions) requires a gate voltage
more negative than some threshold value to induce the required
positive charge (mobile holes) in the channel.
ü A normally on device is called a depletion-mode transistor, since
gate voltage is used to deplete a channel which exists at equilibrium.
ü The more common MOS transistor is normally off with zero gate
voltage, and operates in the enhancement mode

ü If the gate voltage exceeds VT in an n-channel device, electrons are

induced in the p-type substrate à like an induced n-type resistor
ü As th eVG increases, more electron charge is induced in the channel
and the channel becomes more conducting.
ü Thedr ai
n cur rentini
ti
a l
lyi
ncrea ses li
nea r
lyw iththedr ain bias
à the linear regime

Gate-controlled potential barrier device

or Gate-controlled resistor
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Choice of Vt and Gate Doping Type

To make circuit design easier, it is routine to set Vt at a small positive value, e.g., 0.4 V, so that, at Vg = 0,
the transistor does not have an inversion layer and current does not flow between the two N+ regions.

Enhancement-Type Device

N-channel
enhancement-
type

P-channel
enhancement-
type

P-type body is almost always paired with N+ gate to achieve a small positive threshold voltage,
and N-type body is normally paired with P+ gate to achieve a small negative threshold voltage.

For the case of P-type body paired with P+ gate, Vt would be too large (over 1 V) and necessitate a
larger power supply voltage. This would lead to larger power consumption and heat generation.
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

MOS C-V Characteristics for measuring Tox, Na or Nd, VTh, or VFB

Setup for the C–V measurement. The capacitance is calculated
from, Vg D.C ramping + a.c small
signal

Cox t
Cdep

The quasi-static MOS C–V characteristics.

The capacitance in the MOS theory is
always the small-signal capacitance. accumulation depletion inversion
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Majority carrier Majority carrier

charge oscillation charge oscillation

accumulation region depletion region

Minority carrier
charge oscillation

No minority carrier
charge oscillation

No need for majority Majority carrier

carrier charge oscillation charge oscillation

inversion region with efficient supply of inversion inversion region with no supply of inversion electrons (or
electrons from the N region (corresponding to the weak supply by thermal generation) corresponding to the
transistor C–V or the quasi-static C–V) high-frequency capacitor C–V case.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Oxide Charge-A Modification to Vfb and Vt

- Qm(mobile ionic charge);

cause instabilities in Vfb and Vt.
- Qot (oxide trapped charge)
- Qf (fixed oxide charge)
- Qit (interface trapped charge);
degrade the substrate current of
MOSFET.

More Qit and Qf appear after the oxide is

subjected to high field some time due to the
breaking or rearrangement of chemical bonds
Reliability
This raises a reliability concern because the Vt.
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Oxide Charge-A Modification to Vfb and Vt

Flat-band condition (no band bending at body surface)

(a) without any oxide charge; (b) with Qox at the oxide–substrate interface.
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Poly-Si Gate Depletion-Effective Increase in Tox

1 – 2 nm

Poly-gate depletion effect illustrated with

(a) the band diagram and
(b) series capacitors representation.
An N+ poly-Si gate can also be depleted.
P+ poly-Si gate
According to Gauss’s Law,

Wdpoly qNpolyWdpoly

oxide
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Poly-Si Gate Depletion-Effective Increase in Tox

The MOS capacitance in the inversion region becomes

Poly-depletion effect effectively

increases Tox by Wdpoly/3, and
can have a significant impact
on the C-V curve if Tox is thin.

Solutions; 1) dope the poly-Si heavily (can cause dopant penetration from the gate
through the oxide into the substrate).
2) use poly-SiGe gate to be doped to a higher concentration.
3) substitute the poly-Si gate with a metal gate.

Poly-depletion effect is undesirable because a reduced C means

reduced Qinv and reduced transistor current.
Poly-gate depletion effectively
reduces Vg by .

Even 0.1 V would be highly undesirable when

the power-supply voltage is only around 1 V.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Inversion and Accumulation Charge-Layer

Thicknesses and Quantum Mechanical Effect

Physical Tox Tinv

Effective gate dielectric
Effective bottom electrode of Tinv,electron < Tinv,hole
the MOS capacitor
(because mn < mp)

Average inversion-layer thickness (centroid) for

electrons (in P body) and holes (in N body).
(From [3]. © 1999 IEEE.)
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Cox
Cacc

With accumulation
charge-layer thickness

The effects of poly-depletion and charge-layer thickness on the C–V curve of an N+

poly-gate, P-substrate device.
Increasing Vg.

Equivalent circuit for understanding the C–V curve in the depletion region and the inversion region.
(a) General case for both depletion and inversion regions; (b) in the depletion regions; (c) Vg ≈ Vt ;
and (d) strong inversion.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Effective Oxide Thickness

• Tinv and Wpoly: not negligible for thinner Tox with thickness of < 10 nm

• Because it is difficult to separate Tox from Tinv and Wpoly by measurement, an electrical oxide
thickness, Toxe, is often used to characterize the total effective oxide thickness.
(Toxe is deduced from the inversion-region capacitance measured at Vg = Vdd.)

• Toxe : an effective oxide thickness corresponding to an effective gate capacitance, Coxe.

Total inversion charge per area, Qinv, is

Typically, Toxe is larger than Tox by 0.6-1.0 nm .

Quantum Effect on Threshold Voltage

At high substrate doping concentration, the high electric field in the substrate at the
oxide interface causes energy levels to be quantized and effectively increases Eg and
decreases ni. This requires the band to bend down more before reaching threshold, i.e.,
causes to increase.

The net effect is that the threshold voltage is increased by 100 mV or so depending on
the doping concentration
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Quantum well effect → the lowest energy level is not Ec

: the lowest energy level exists
at E1 (quantized energy level) over Ec
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

CCD Imager and CMOS Imager

used in digital cameras and camcorders
• CCD (Charge-Coupled Device) Imager:
1) high performance( good uniformity and contrast ratio)
2) small number of sophisticated sensing circuits
3) expensive.
• CMOS Imager:
1) small area and less expensive
2) compatible with CMOS IC technology
3) easily integrated with signal processing and control circuits
4) less power.

CCD Imager
The heart of a CCD imager is a large number of MOS capacitor densely packed in a
two-dimensional array.

Deep Depletion
When a voltage, Vg > Vt, has been suddenly applied to the gate, an MOS capacitor is
driven into nonequlibrium where there are no electrons (no inversion layer) at the surface,
because thermal generation is a slow process and, in balancing the charge added to the
gate, the depletion width becomes greater than Wdmax to offset the missing minority
carriers. This called “deep-depletion”.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

EFp

EFn

Depletion layer charge

Depletion layer
charge

Wdmax
No inversion layer
Inversion layer Wdmax
(thickness: ~5 nm)

Deep-depletion C–V
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

light

After exposure to light, photo-generated

electrons have been collected at the
surface. The number of electrons is
proportional to the light intensity.

The first function of CCD array:

To convert an image( two-dimensional pattern of
light intensity) into packets of electrons stored in
a two-dimensional array of MOS capacitor

The second function of CCD array:

To transfer the collected charge packets to the
edge of the array, where they can be read by a
charge sensing circuit in a serial manner.
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

How does CCD shift the charge packets?

• V1 creates the deepest depletion.

• Exposure to a lens-projected image has produced some electrons in

the element on the right, even more in the element on the left and yet
more in the middle element in proportion to the image light intensity
around those three locations.

• V2 creates the deepest depletion.

• The charge packets will move to the elements connected to V2 (i.e.,

shifted to the right by one element. The choice of V1>V3 ensures that
no electrons are transferred to the left.

• V1 is reduced to the same values as V3.

• The drawing in (c) is identical to (a) but with all the charge packets
shifted to the right by one capacitor element.

The array is biased in the sequence (a), (b), (c), (a), (b), (c), (a) ... .
In this manner the electron packets are shifted to the right element by element.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Waiting at the right edge of the array is a charge-sensing circuit that generates
a serial voltage signal that faithfully represents the image light pattern.

[Architecture of a two-dimensional CCD imager]

The arrows show the path of the charge-packet movement.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

CMOS Imager
• Electrons generated by light near the PN junction diffuse to junction and get collected and
stored in the thin N+-region. Since the PN junction is a capacitor, the stored electrons change
the capacitor voltage, i.e., the N+-region voltage. This voltage is amplified in the pixel as
shown in the figure below.

• Each pixel also contains a switch made of an MOS transistor and controlled by the voltage
Vr1, Vr2, or Vr3. In order to read the top row of pixels, Vr1 is raised to turn on (close) all the
switches in the top row. This brings the signals from all the top-row pixels to the shifter circuit.

Amplifier circuit

PN junction switch
charge collector

[Architecture of a CMOS imager]

Each array element has its own charge-to-voltage converter represented by the
triangle. Actual imagers may support hundreds to over a thousand rows and
columns of pixels.
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor
 Modern Semiconductor Devices for Integrated Circuits Chapter 5. MOS Capacitor

Flat-band voltage
Chapter Summary

Gate voltage

Threshold voltage

At threshold,
Electrical oxide thickness