An Efficient Approach to Improve PSRR Performance of

Kuijk BGR Topology

Hui Nie1, 2, Wengao Lu1*, Ran Fang1, Guannan Wang1, Yacong Zhang1, Zhongjian Chen1, Lijiu Ji1
1
Key Laboratory of Microelectronic Devices and Circuit,
Department of Microelectronics, Peking University, Beijing 100871, China
2
School of software and Microelectronics, Peking University, Beijing 102600, China
* Email: wglu@pku.edu.cn

Abstract specification to describe how BGR output could immune

A highly efficient approach to improve PSRR behavior from that disturbance. Many ways have been found to
of Kuijk BGR topology is derived though small signal improve PSRR performance of BGR circuit, such like
transfer function analysis and, a BGR circuit has been Pseudo-Power Supply approach [4], which is not fit for
designed and fabricated on standard 0.5m CMOS low voltage, low power application.
technology to verify this method. This thought greatly
relieves the trade-offs of BGR circuit design among In this paper, we will focus our attention on a practical
power consumption, PSRR performance, area and etc.. method to improve PSRR performance of Kuijk BGR
This BGR circuit consumes 3A current at 5V single structure, which trades little design effort for high
power supply, with >130 dB DC PSRR performance, performance improvement. In Section 2, we will do
occupies an area of 350m×100m, and is of self-biased some abstraction and PSRR analysis of this classic
characteristic with 2~6 V work supply voltage range. topology; meanwhile, a novel approach to enhance
PSRR performance will be introduced. Based on that
1. Introduction method, an implementation will be provided in Section 3.
Nowadays, BGR (bandgap reference) circuit is widely Finally, in Section 4, some conclusions are reported.
embedded in modern SoC systems as a fundamental
building block. Basic Kuijk BGR circuit [1] shown in 2. Analysis of Kuijk BGR Topology
Fig. 1 and its derivations are composed of a most Kuijk BGR employs Op-Amp for regulation and
popular BGR architecture [2].Since it can be designed by providing current to bias bipolar transistors. To proceed
replacing NPN transistors with diode-connected PNP the following analysis compact, it has been considered
counterparties, this topology is fully compatible with the that the Op-Amp in Fig. 1 has been realized by an OTA,
mainstream CMOS technology, on which parasitic driving one or more pass PMOS transistors [3].
vertical PNP transistors are available.
2.1 Behavioral modeling of Kuijk BGR topology
VREF
R2 R1

VDD

R3

Q2 Q1

Figure 2. An abstraction of Kuijk BGR topology

Figure 1. Basic Kuijk BGR circuit
Taking circuit in Fig.1 for example, we can gain three
Ideally, BGR circuit provides a DC voltage independent main function blocks in the light of function division
of all external environmental factors; while, noisy digital (These blocks may have some elements in common):
and switch-capacitor networks integrated on the same Current Distribute Network for current distribution,
die with sensitive analog blocks introduce severe which include R1, R2 and pass devices; Bandgap Core
glitches to analog power supply line, and PSRR (Power for reference voltage generation, which is composed by
Supply Rejection Ratio) is an utmost important design R1 ~ R3, Q1 and Q3; OTA, providing loop regulation, is

978-1-4244-5798-4/10/$26.00 ©2010 IEEE

the key factor for performance enhancement. We can consideration, and we can get
draw functionality representation in Fig. 2 (Adding Vdd sCload  1 RA  E ˜ Aota (0) ˜ gm3  1 rds 3 (5)
PSRRref (0)
Start-up Circuit for completeness). Vref 1  1 PSRRota (0)  ˜ gm3  1 rds3
OTA of high PSRR is adopted in most design of this
Based on this abstraction, we can have many
circuit. In this situation, 1/PSRRota(0) << 1, and then
transformations of the basic Kuijk BGR circuit. For
example, we can use current mirrors driven directly by PSRRref (0) | E ˜ Aota (0) (6)
OTA to implement Current Distribute Network; we can Based on Eq. (5), in the case that 1/PSRRota(0)  1, we
make alternatives to design Bandgap Core… can get expression 1  1 PSRRota (0)  ˜ gm3rds 3  1 , and
the PSRR of the BGR output
In this work, we will focus our PSRR analysis on the
PSRRref (0)  E ˜ Aota (0) ˜ g m3 ˜ rds 3 (7)
specific circuit in Fig. 3, and the method to improve
PSRR performance is also available for other This result is 10× to 100× order of magnitude higher
alternatives of the Kuijk BGR topology. than the former in Eq. (6). And the method we propose
in this paper is to optimize BGR PSRR performance by
Vdd modifying the design of OTA in Kuijk BGR topology.
M3
The OTA of 1/PSRRota(0)  1 can be realized by a simple
Vref
structure as shown in Fig. 4: A sub-OTA (mostly
one-stage OTA) cascade with a CS (Common Source)
Vdd
R1 R2 stage, which take dioded-connected MOSFET (PMOS in
Fig.4) as its load. This CS stage mainly provides the
OTA output with unity PSRR response, needs little
Cload
current consumption to realize, and offers designers a
R3
low power option.

Q1 Q2
Vdd

Figure 3. A representative of Kuijk BGR topology VN

2.2 Small signal transfer function analysis VP

Supposing there is a small signal fluctuation on the
power supply line, small signal current equation of node
A in Fig. 3 can be derived based on KCL discipline:
Vdd  Vref
 ª¬ E ˜ Aota ( s) ˜Vref  Vdd PSRRota (s)  Vdd º¼ u gm3  Figure 4. OTA with unity PSRR performance
r ds 3

Vref §¨ sCload  1 ·¸ (1) Next, assuming that the internal OTA of BGR is
© RA ¹ implemented as shown in Fig. 4, we move forward to
where discuss the high frequency PSRR behavior. Obviously,
R3  1 gQ 2 1 gQ1 (2)
the OTA in Fig. 4 would exhibit a stable PSRR response
E  over a relatively wide frequency range, and it is safe to
R3  R2  1 gQ 2 R1  1 gQ1
say 1/PSRRota(s)  1, and Eq. (4) can be rewritten as
PSRRref ( s)  E ˜ Aota ( s) ˜ g m3 ˜ rds 3 (8)
RA  R 1 g  &  R
1 Q1 2  R3  1 gQ 2  (3)
Take the case that Aota ( s ) shows a two-pole frequency
and hence, the PSRR of the circuit in Fig. 3 can be response, i.e.
estimated by Eq. (4): Aota (0) (9)
Aota ( s)
1  s p1 1  s p2 
Vdd sCload  1 RA  E ˜ Aota ˜ gm3  1 rds 3 (4) then
PSRRref (s)
Vref 1 1 PSRRota (s)  ˜ gm3  1 rds3 ª B º
Aota (0) «1  1  s p1 1  s p2 1  s p0  »
¬ Aota (0) ¼ (10)
PSRRref ( s)
Firstly, let’s take low frequency PSRR response into 1  s p1 1  s p2 
where the proposed method to improve PSRR performance of
rds 3 1 Kuijk BGR topology. M5 ~ M16 forms the OTA of this
B  1 , p0 (11)
BGR. The existence of the branch containing M12
RA RACload
improves the OTA’s loop gain, and meanwhile, helps
Eq. (10) shows that this transfer function contains two
loop stability of the whole circuit.
poles and three zeros. Zeros can delay the deterioration
of PSRR performance as frequency grows, and it is the
This BRG has been designed and taped out as a building
first zero that we concern most. Assuming the first zero
block in several system chips on 0.5m standard CMOS
is much lower than the others [5], we can say the
process, and has passed functionality test. Fig. 6 shows a
dominate zero
segment of the microphotograph of an ADC chip, in
1 B §1 1 1 · which this implementation is embedded, and occupies an
| ¨   ¸ (12)
z1 Aota (0) © p1 p2 p0 ¹ area of 350m×100m as shown within the white frame
Since the poles of OTA has been limited by power of the figure.
consumption and loop stability constraints, this structure
need large bypass capacitance on the output for the sake The overall current consumption of this self-biased
of PSRR performance. Kuijk BGR is about 3uA over a work supply voltage
range of 2~6V, and the PSRR performance is given by
Based on the analysis above, the proposed way to simulation results in Fig.7 (shown as 1/PSRRota(s) in 5V
improve PSRR is suitable for circuits of Kuijk BGR single supply voltage), in which we can see that the DC
topology, which employ the regulation of OTA PSRR of this proposed BGR is more than 130dB.
embedded to generate their BGR outputs directly.

3. Implementation

Vdd

M 11 M 13
M5 M3
M 16
M 12 M4

Vref

M6 M7
R1 R2

Figure 7. PSRR simulation result of the proposed BGR

R3

M8 M9 M 10 M 14 M 15
Q1 Q2 4. Summary
The method presented in this paper provides an effective
solution for PSRR improvement of Kuijk BGR topology,
and meanwhile, offers designers self-biased, low power
Figure 5. BGR circuit with PSRR performance and wide work supply voltage range options. A BGR
enhancement (without start-up circuit) circuit to implement this approach, which has been taped
out and has passed functionality test, is also provided.
Finally, some valuable simulation results are given.

References
[1] K. E. Kuijk, IEEE J. Solid-State circuit, sc-8(1),
p.222-226 (1973)
[2] G. Giustolisi and G. Palumbo, IEEE Trans. Circuits
Syst. I, 50(2), p185-197 (2003)
[3] J. Redoutl and M. Steyaert, IEEE Trans. Circuits
Syst. II, 57(2), p75-79 (2010)
[4] K. Tham and K. Nagaraj, IEEE J. Solid-State circuit,
Figure 6. A microphotograph of proposed BGR circuit 30(5), p.586-590 (1995)
embedded in an ADC chip [5] B. Razavi, Design of Analog CMOS Integrated
Circuits, McGraw Hill (2003)
BGR circuit (without start-up circuit) in Fig. 5 follows