FLIP FLOP

A flip
lip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip Flip-flops
flops and latches are fundamental
building blocks of digital electronics systems used in computecomputers,
rs, communications, and many
other types of systems. Both are used as data storage elements. It is the basic storage element in
sequential logic. But first, let’s clarify the difference between a latch and a flip
flip-flop.
flop.

Flip flop v/s Latch

The basic difference

nce between a latch and a flip
flip-flop
flop is a gating or clocking mechanism.

In simple words, Flip Flop is edge

edge-triggered and a latch is level triggered.

For example, let us talk about SR latch and SR flip

flip-flops.
flops. In this circuit when you Set S as active
the output
tput Q would be high and Q’ will be Low. This is irrespective of anything else. (This is an
active-low
low circuit so active here means low, but for an active high circuit active would mean
high)
 SR Latch

A flip-flop, on the other hand, is synchronous and is also known as a gated or clocked SR latch.

SR Flip-Flop

In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you give
an active clock signal. Otherwise, even if the S or R is active the data will not change. Let’s look
at the types of flip-flops to understand better.

SR Flip Flop

There are majorly 4 types of flip-flops, with the most common one being SR flip-flop. This
simple flip-flop circuit has a set input (S) and a reset input (R). In this system, when you Set “S”
as active the output “Q” would be high and “Q‘” will be low. Once the outputs are established,
the wiring of the circuit is maintained until “S” or “R” go high, or power is turned off. As shown
above, it is the simplest and easiest to understand. The two outputs, as shown above, are the

inverse of each other. The truth table of SR Flip-Flop is highlighted below.

The Set State

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at
logic level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its
output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input
“A” and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be
at logic level “0”.
 Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1”
with S remaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B =
“0”. Since one of its inputs is still at logic level “0” the output at Q still remains HIGH at logic
level “1” and there is no change of state. Therefore, the flip-flop circuit is said to be “Latched” or
“Set” with Q = “1” and Q = “0”.

Reset State

In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic
level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic
“0” its output Q must equal logic level “1” (again NAND gate principles). Output Q is fed back
to input “B”, so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.

If the set input, S now changes state to logic “1” with input R remaining at logic “1”,
output Q still remains LOW at logic level “0” and there is no change of state. Therefore, the flip-
flop circuits “Reset” state has also been latched and we can define this “set/reset” action in the
following truth table.

JK Flip Flop

The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:

 When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.

 When the Set or Reset input changes their state while the enable input is 1, the incorrect latching
action occurs.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the shortened
abbreviated letters for Set and Reset, but J and K are not. The J and K are themselves
autonomous letters which are chosen to distinguish the flip flop design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and 'K'
flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop is that
when both inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but
in case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are prevented
by the addition of a clock input circuit. So, the JK flip-flop has four possible input combinations,
i.e., 1, 0, "no change" and "toggle". The symbol of JK flip flop is the same as SR Bistable
Latch except for the addition of a clock input.

Block Diagram:
Circuit Diagram:

In SR flip flop, both the

he inputs 'S' and 'R' are replaced by two inputs J and K. It means the J and
K input equates to S and R, respectively.

The two 2-input

input AND gates are replaced by two 33-input NAND gates.. The third input of each
gate is connected to the outputs at Q and Q'. The cross
cross-coupling
coupling of the SR flip-flop
flip permits the
previous invalid condition of (S = "1", R = "1") to be used to produce the "toggle action" as the
two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the lower
NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q through the
upper NAND gate. Since Q and Q' are always different, we can use them to control the input.
When both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as per the given truth table.

Truth Table:

When both of the inputs of JK flip flop are set to 1 and clock input is also pulse "High" then
from the SET state to a RESET state, the circuit will be toggled. The JK flip flop work as a T-
type toggle flip flop when both of its inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed before the
clock input's timing pulse has time to go "Off". We have to keep short timing plus period (T) for
avoiding this period.

Master-Slave JK Flip Flop

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long
period of time, then Q output will toggle as long as CLK is high, which makes the output of the
flip-flop unstable or uncertain. This problem is called race around condition in J-K flip-flop. This
problem (Race Around Condition) can be avoided by ensuring that the clock input is at logic “1”
only for a very short time. This introduced the concept of Master Slave JK flip flop.

Master Slave JK flip flop –

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in

a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The
output from the master flip flop is connected to the two inputs of the slave flip flop whose output
is fed back to inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected
to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other
words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip
flop then it becomes 0 for slave flip flop.
 Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the
system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.

2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.

3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock
forces the slave to reset, thus the slave copies the master.

4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative
transition of the clock sets the slave, copying the master.

5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the
negative transition of the clock.

6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

1. When the Clock pulse is high the output of master is high and remains high till the clock is low
because the state is stored.

2. Now the output of master becomes low when the clock pulse becomes high again and remains
low until the clock becomes high again.

3. Thus toggling takes place for a clock cycle.

4. When the clock pulse is high, the master is operational but not the slave thus the output of the
slave remains low till the clock remains high.

5. When the clock is low, the slave becomes operational and remains high until the clock again
becomes low.

6. Toggling takes place during the whole process since the output is changing once in a cycle.

This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the
timing of the clock signal.

T Flip Flop

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-flop
work as a Toggle switch. The next output state is changed with the complement of the present
state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip Flop"
has only one input, which is constructed by connecting the input of JK flip flop. This single input
is called T. In simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop".
Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".
 Block diagram of the "T-FlipFlip Flop" is given where T defines the "Toggle input", and CLK
defines the clock signal input.

T Flip Flop Circuit

There are the following two methods which are used to form the "T Flip Flop":

 By connecting the output feedback to the input in "SR Flips Flop".

 We pass the output that we get after performing the XOR operation of T and Q PREV output as the
D input in D Flip Flop.

Construction

The "T Flip Flop" is designed by passing the AND gate's output as input to the NOR gate of the
"SR Flip Flop". The inputs of the "AND" gates, the present output state Q, and its complement
Q' are sent back to each AND gate. The toggle input is passed to the AND gates as input. These
gates are connected to the Clock (CLK) signal. In the "T Flip Flop", a pulse train of narrow
na
triggers are passed as the toggle input, which changes the flip flop's output state. The circuit
diagram of the "T Flip Flop" using "SR Flip Flop" is given below:
The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output after
afte performing
the XOR operation of the T input with the output "Q PREV" is passed as the D input. The logical
circuit of the "T-Flip
Flip Flop" using the "D Flip Flop" is given bbelow:

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the "JK Flip
Flop" are connected as a single input T. Below is the logical circuit of the T Flip Flop" which is
formed from the "JK Flip Flop":

Truth Table of T Flip Flop

 The upper NAND gate is enabled, and the lower NAND gate is disabled when the output Q To is
set to 0. make the flip flop in "set state(Q=1)", the trigger pass
passes
es the S input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the output Q is set
to 1. The trigger passes the R input in the flip flop to make the flip flop in the reset state (Q=0).

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is set to false or 0.

 If toggle input is set to 0 and the present state is also 0, the next state will be 0.

 If toggle input is set to 0 and the present state is 1, the next state will be 1.

The next state of the flip flop is opposite to the current state when the toggle input is set to 1.

 If toggle input is set to 1 and the present state is 0, the next state will be 1.

 If toggle input is set to 1 and the present state is 1, tthe next state will be 0.

The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by the incoming
trigger. The "T Flip Flop" requires two triggers to complete a full cycle of the output waveform.
The frequency of the output produced by the "T Flip Flop" is half of the input frequency. The "T
Flip Flop" works as the "Frequency Divider Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the previous state is
defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop"
because the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop" using "JK
Flip Flop" is given below:
 D Flip Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET =
"0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.

3. Lose the control by the input, which first goes to 1, and the other input remains "0" by which the
resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter between the Set
and Reset inputs for producing another type of flip flop circuit called D flip flop,
flop Delay flip flop,
D-type Bistable, D-type
type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures that at the
th
same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop
flip is designed
using a gated SR flip-flop with an inverter connected between the ininputs
puts allowing for a single
input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level
level-sensitive D-type
type or D flip flop
is constructed from a level-sensitive
sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Circuit Diagram
We know that the SR flip-flop
flop requires two inputs, i.e., one to "SET" the output and another to
"RESET" the output. By using an inverter, we can set and reset the out outputs
puts with only one input
as now the two input signals complement each other. In SR flip flop, when both the inputs are 0,
that state is no longer possible. It is an ambiguity that is removed by the complement in D-flip
D
flop.

In D flip flop, the single inputt "D" is referred to as the "Data" input. When the data input is set to
1, the flip flop would be set, and when it is set to 0, the flip flop would change and become reset.
However, this would be pointless since the output of the flip flop would always change
cha on every
pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip
flop's latching circuitry. When the clock input is set to true, the D input condition is only copied
to the output Q. This forms the basis of another sequential device referred to as D Flip Flop.
Flop

When the clock input is set to 1, the "set" and "reset" inputs of the flip
flip-flop
flop are both set to 1. So
it will not change the state and store the data present on its output be before
fore the clock transition
occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type

type Flip Flop

FLIP FLOP CONVERSIONS

One flip-flop
flop can be converted into the remaining three flip
flip-flops
flops by including some additional
logic.
c. So, there will be total of twelve flip-flop conversions.
 Follow these steps for converting one flip-flop to the other.

 Consider the characteristic table of desired flip-flop.

 Fill the excitation values undefined inputs of given flip-flop for each combination of present state
and next state. The excitation table for all flip-flops is shown below.

 Get the simplified expressions for each excitation input. If necessary, use K maps for
simplifying.

 Draw the circuit diagram of desired flip-flop according to the simplified expressions using given
flip-flop and necessary logic gates.

Now, let us convert few flip-flops into other. Follow the same process for remaining flipflop
conversions.

SR Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of SR flip-flop to other flip-flops.

 SR flip-flop to D flip-flop

 SR flip-flop to JK flip-flop

 SR flip-flop to T flip-flop

SR flip-flop to D flip-flop conversion

Here, the given flip-flop is SR flip-flop and the desired flip-flop is D flip-flop. Therefore,
consider the following characteristic table of D flip-flop.
We know that SR flip-flop flop has two inputs S & R. So, write down the excitation values of SR
flip-flop
flop for each combination of present state and next state values. The following
follow table shows
the characteristic table of D flip-flop
flop along with the excitation inputs of SR flip-flop.
flop.

From the above table, we can write the Boolean functions for each input as below.

Undefined S=m2+d3

Undefined R=m1+d0

We can use 2 variable K-Maps

Maps ffor
or getting simplified expressions for these inputs. The k-
Maps for S & R are shown below.
So, we got S = D & R = D' after simplifying. The circuit diagram of D flip-flop is shown in the
following figure.