EN25P32

EN25P32
32 Mbit Uniform Sector, Serial Flash Memory

FEATURES

• Single power supply operation • High performance program/erase speed

- Full voltage range: 2.7-3.6 volt - Byte program time: 7µs typical
- Page program time: 1.5ms typical
• 32 M-bit Serial Flash
- Sector erase time: 800ms typical
- 32 M-bit/4096 K-byte/16384 pages
- Chip erase time: 25 Seconds typical
- 256 bytes per programmable page
• Lockable 512byte OTP security sector
• High performance
• Minimum 100K endurance cycle
- 100MHz clock rate
• Package Options
• Low power consumption - 16 pins SOP 300mil body width
- 5 mA typical active current - 8 pins SOP 200mil body width
- 1 μA typical power down current - 8 contact VDFN
- All Pb-free packages are RoHS compliant
• Uniform Sector Architecture:
• Commercial and industrial temperature
- Sixty four 64-Kbyte sectors
Range
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin

GENERAL DESCRIPTION

The EN25P32 is a 32M-bit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P32 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P32 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.

This Data Sheet may be revised by subsequent versions 1 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18

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 EN25P32
Figure.1 CONNECTION DIAGRAMS

8 - LEAD SOP 8 - CONTACT VDFN

16 - LEAD SOP

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 EN25P32
Figure 2. BLOCK DIAGRAM

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 EN25P32
SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted
out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS# must
transition from high to low before a new instruction will be accepted.

Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect
(SRP) bits, a portion or the entire memory array can be hardware protected.

Table 1. PIN Names

Symbol Pin Name

CLK Serial Clock Input

DI Serial Data Input

DO Serial Data Output

CS# Chip Enable

WP# Write Protect

HOLD# Hold Input

Vcc Supply Voltage (2.7-3.6V)

Vss Ground

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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18

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 EN25P32

MEMORY ORGANIZATION
The memory is organized as:
z 4,194,304 bytes
z Uniform Sector Architecture
Sixty four 64-Kbyte sectors
z 16384 pages (256 bytes each)

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or
Bulk Erasable but not Page Erasable.

Table 2 Block Sector Architecture

Sector SECTOR SIZE (KByte) Address range
63 64 3F0000h – 3FFFFFh
62 64 3E0000h – 3EFFFFh
61 64 3D0000h – 3DFFFFh
60 64 3C0000h – 3CFFFFh
59 64 3B0000h – 3BFFFFh
58 64 3A0000h – 3AFFFFh
57 64 390000h – 39FFFFh
56 64 380000h – 38FFFFh
55 64 370000h – 37FFFFh
54 64 360000h – 36FFFFh
53 64 350000h – 35FFFFh
52 64 340000h – 34FFFFh
51 64 330000h – 33FFFFh
50 64 320000h – 32FFFFh
49 64 310000h – 31FFFFh
48 64 300000h – 30FFFFh
47 64 2F0000h – 2FFFFFh
46 64 2E0000h – 2EFFFFh
45 64 2D0000h – 2DFFFFh
44 64 2C0000h – 2CFFFFh
43 64 2B0000h – 2BFFFFh
42 64 2A0000h – 2AFFFFh
41 64 290000h – 29FFFFh
40 64 280000h – 28FFFFh
39 64 270000h – 27FFFFh
38 64 260000h – 26FFFFh
37 64 250000h – 25FFFFh
36 64 240000h – 24FFFFh
35 64 230000h – 23FFFFh
34 64 220000h – 22FFFFh
33 64 210000h – 21FFFFh
32 64 200000h – 20FFFFh
31 64 1F0000h – 1FFFFFh
30 64 1E0000h – 1EFFFFh
29 64 1D0000h – 1DFFFFh
28 64 1C0000h – 1CFFFFh
27 64 1B0000h – 1BFFFFh

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 EN25P32
26 64 1A0000h – 1AFFFFh
25 64 190000h – 19FFFFh
24 64 180000h – 18FFFFh
23 64 170000h – 17FFFFh
22 64 160000h – 16FFFFh
21 64 150000h – 15FFFFh
20 64 140000h – 14FFFFh
19 64 130000h – 13FFFFh
18 64 120000h – 12FFFFh
17 64 110000h – 11FFFFh
16 64 100000h – 10FFFFh
15 64 0F0000h – 0FFFFFh
14 64 0E0000h – 0EFFFFh
13 64 0D0000h – 0DFFFFh
12 64 0C0000h – 0CFFFFh
11 64 0B0000h – 0BFFFFh
10 64 0A0000h – 0AFFFFh
9 64 090000h – 09FFFFh
8 64 080000h – 08FFFFh
7 64 070000h – 07FFFFh
6 64 060000h – 06FFFFh
5 64 050000h – 05FFFFh
4 64 040000h – 04FFFFh
3 64 030000h – 03FFFFh
2 64 020000h – 02FFFFh
1 64 010000h – 01FFFFh
0 64 000000h – 00FFFFh

OPERATING FEATURES
SPI Modes

The EN25P32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.

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 EN25P32

Figure 3. SPI Modes

Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of
memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,
using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)
instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be
preceded by a Write Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it
to establish when the previous Write cycle, Program cycle or Erase cycle is complete.

Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power
mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID
(RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
Status Register.The Status Register contains a number of status and control bits that can be read or set
(as appropriate) by specific instructions.

BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions.

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 EN25P32
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register
(SRP, BP2, BP1, BP0) become read-only bits.

In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected form program and erase operation. The OTP_LOCK bit can only be
programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR
command to lock the OTP sector before leaving OTP mode.

Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25P32
provides the following data protection mechanisms:

z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction
completion or Bulk Erase (BE) instruction completion or
z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register
Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra software
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored
except one particular instruction (the Release from Deep Power-down instruction).

Table 3 Protected Area Sizes Sector Organization

Status Register Memory Content

Content
BP2 BP1 BP0 Addresses Density(KB) Portion
Protect Sectors
Bit Bit Bit
1 1 1 All 000000h-3FFFFFh 4096KB All
1 1 0 Sector 32 to 63 200000h-3FFFFFh 2048KB Upper 1/2
1 0 1 Sector 48 to 63 300000h-3FFFFFh 1024KB Upper 1/4
1 0 0 Sector 56 to 63 380000h-3FFFFFh 512KB Upper 1/8
0 1 1 Sector 60 to 63 3C0000h-3FFFFFh 256KB Upper 1/16
0 1 0 Sector 62 to 63 3E0000h-3FFFFFh 128KB Upper 1/32
0 0 1 Sector 63 3F0000h-3FFFFFh 64KB Upper 1/64
0 0 0 None None None None

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 EN25P32
Hold Function

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition
starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)
being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with
Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and
Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment
of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the
internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)
High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold
condition.

Figure 4. Hold Condition Waveform

INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven
Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on
Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code.
Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or
none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted
in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High
after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR),
Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#)
must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.
That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#)

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 EN25P32
being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full
byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data
byte), it will be ignored too. In the case of SE, exact 24-bit address is a must, any less or more will
cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.

Table 4. Instruction Set

Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

Code
Write Enable 06h
Write Disable 04h
Read Status continuous
Register
05h (S7-S0)(1) (2)
Write Status
01h S7-S0
Register
Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuous
(Next Byte)
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0)
continuous
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 (Next byte) continuous
Sector Erase D8h A23-A16 A15-A8 A7-A0
Bulk Erase C7h
Deep Power-down B9h
Release from Deep (4)
Power-down, and dummy dummy dummy (ID7-ID0)
read Device ID ABh
Release from Deep
Power-down
Manufacturer/ 90h
Device ID
dummy dummy 00h(5) (M7-M0) (ID7-ID0)
Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0)
Enter OTP mode 3Ah

Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. All sectors may use any address within the sector.
4. The Device ID will repeat continuously until CS# terminate the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.

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 EN25P32

Table 5. Manufacturer and Device Identification

OP Code (M7-M0) (ID15-ID0) (ID7-ID0)

ABh 15h

90h 1Ch 15h

9Fh 1Ch 2016h

Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction
code, and then driving Chip Select (CS#) High.

Write Disable (WRDI) (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, and Bulk Erase instructions.

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 EN25P32

Read Status Register (RDSR) (05h)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register
may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is also possible to read the Status Register continuously,
as shown in Figure 7.

Table 6. Status Register Bit Locations

Note : In OTP mode, SRP bit is served as OTP_LOCK bit,

The status and control bits of the Status Register are as follows:
BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is

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 EN25P32
set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if,
both Block Protect (BP2, BP1, BP0) bits are 0.

Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for
these bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing this
will ensure compatibility with future devices.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to
1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP,
BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.

In OTP mode this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected form program and erase operation. The OTP_LOCK bit can only be
programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR
command to lock the OTP sector before leaving OTP mode.

Write Status Register (WRSR) (01h)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 8.. The Write Status Register (WRSR) instruction has no
effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#)
must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed
Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is
completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table
3.. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register
Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP)
bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The
Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is
entered.

NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.

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 EN25P32

Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data
Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock
(CLK).
The instruction sequence is shown in Figure 9.. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the
highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be
continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while
an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is
in progress.

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 EN25P32
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy
byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at
that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum
frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 10.. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the
read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at
Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

Page Program (PP) (02h)

The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.

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 EN25P32
The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other bytes of the same page.

Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP) is
initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 3.a and Table 3.b) is not executed.

Sector Erase (SE) (D8h)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2.a and Table 2.b) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 12.. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not

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 EN25P32
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration
is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0)
bits (see Table 3.a and Table 3.b) is not executed.

Bulk Erase (BE) (C7h)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 13.. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is
initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more, sectors are protected.

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 EN25P32

Deep Power-down (DP) (B9h)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 8.).
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from
this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the
Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 14..Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

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 EN25P32

Release from Deep Power-down and Read Device ID (RDI)

Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that
is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.

When used only to release the device from the power-down state, the instruction is issued by driving the
CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 15. After the
time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 16. The Device ID value for the EN25P32 are listed in Table 5. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate.
If the device was previously in the Deep Pow-er-down mode, though, the transition to the Standby Power
mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2 (max), as
specified in Table 10. Once in the Stand-by Power mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.

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 EN25P32

Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Eon (1Ch)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 17. The Device ID values for the EN25P32 are listed in Table 5. If the 24-bit address is
initially set to 000001h the Device ID will be read first

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 EN25P32

Read Identification (RDID)(9Fh)

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction
is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out
on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock . The instruction
sequence is shown in Figure 18. The Read Identification (RDID) instruction is terminated by driving Chip
Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

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 EN25P32

Figure 18. Read Identification (RDID)

Enter OTP Mode (3Ah)

This Flash has a extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to enter
OTP mode before reading / programming or erasing OTP sector. After entering OTP mode, the OTP
sector is mapping to sector 63 respectively, SRP bit becomes OTP_LOCK bit and can be reading by
RDSR command. Program / Erase command will be disabled when OTP_LOCK is ‘1’

WRSR command will ignore the input data and program LOCK_BIT to 1.
User must clear the protect bits before enter OTP mode.
OTP sector can only be program and erase when LOCK_BIT equal ‘0’ and sector 63 not protected. In
OTP mode, user can read other sectors, but program/erase other sectors only allowed when
OTP_LOCK equal ‘0’.
User can use WRDI (04H) command to exit OTP mode.

Figure 19. Enter OTP Mode

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 EN25P32
Table 7 Security Sector Address

Sector Size Address Range

(bytes) Byte mode (x8)
512 3FFE00h – 3FFFFFh

Power-up Timing

Figure 20. Power-up Timing

Table 8. Power-Up Timing and Write Inhibit Threshold

Symbol Parameter Min. Max. Unit

tVSL(1) VCC(min) to CS# low 10 µs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write Inhibit Voltage 1 2.5 V

Note:
1.The parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).

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 EN25P32
Table 9. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)

Symbol Parameter Test Conditions Min. Max. Unit

ILI Input Leakage Current ±2 µA

ILO Output Leakage Current ±2 µA
ICC1 Standby Current CS# = VCC, VIN = VSS or VCC 5 µA
ICC2 Deep Power-down Current CS# = VCC, VIN = VSS or VCC 5 µA
CLK = 0.1 VCC / 0.9 VCC at
20 mA
100MHz, Q = open
ICC3 CLK = 0.1 VCC / 0.9 VCC at
Operating Current (READ) 15 mA
75MHz, Q = open
CLK = 0.1 VCC / 0.9 VCC at
12 mA
33MHz, Q = open
ICC4 Operating Current (PP) CS# = VCC 15 mA
ICC5 Operating Current (WRSR) CS# = VCC 15 mA
ICC6 Operating Current (SE) CS# = VCC 15 mA
ICC7 Operating Current (BE) CS# = VCC 15 mA
VIL Input Low Voltage – 0.5 0.2 VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µA VCC-0.2 V

Table 10. AC Measurement Conditions

Symbol Parameter Min. Max. Unit
CL Load Capacitance 20/30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Note: 1. CL = 20 pF when CLK=100MHz, CL = 30 pF when CLK=75MHz

Figure 21. AC Measurement I/O Waveform

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 EN25P32
Table 11. 100MHz AC Characteristics
(Ta = 0°C to 70°C or – 40°C to 85°C; VCC = 3.0-3.6V)
Symbol Alt Parameter Min Typ Max Unit
Serial Clock Frequency for:
FR fC FAST_READ, PP, SE, BE, DP, RES, WREN, D.C. 100 MHz
WRDI, RDSR, WRSR
fR Serial Clock Frequency READ instruction D.C. 66 MHz
tCLH 1
Serial Clock High Time 4 ns
tCLL1 Serial Clock Low Time 4 ns
tCLCH 2
Serial Clock Rise Time (Slew Rate) 0.1 V / ns
tCHCL 2 Serial Clock Fall Time (Slew Rate) 0.1 V / ns
tSLCH tCSS CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL tCSH CS# High Time 100 ns
tSHQZ 2 tDIS Output Disable Time 6 ns
tCLQX tHO Output Hold Time 0 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tHLCH HOLD# Low Setup Time ( relative to SCK ) 5 ns
tHHCH HOLD# High Setup Time ( relative to SCK ) 5 ns
tCHHH HOLD# Low Hold Time ( relative to SCK ) 5 ns
tCHHL HOLD# High Hold Time ( relative to SCK ) 5 ns
tHLQZ 2 tHZ HOLD# Low to High-Z Output 6 ns
tHHQZ 2 tLZ HOLD# High to Low-Z Output 6 ns
tCLQV tV Output Valid from SCK 9 ns
tWHSL3 Write Protect Setup Time before CS# Low 20 ns
tSHWL3 Write Protect Hold Time after CS# High 100 ns
tDP 2 CS# High to Deep Power-down Mode 3 µs

tRES1 2 CS# High to Standby Mode without Electronic

3 µs
Signature read
tRES2 2 CS# High to Standby Mode with Electronic
1.8 µs
Signature read
tW Write Status Register Cycle Time 10 15 ms
tPP Page Programming Time 1.5 5 ms
tSE Sector Erase Time 64KB sectors 0.8 2 s
tBE Bulk Erase Time 25 50 s
Note: 1. TSCKH + TSCKL must be greater than or equal to 1/ FCLK
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Sector Protect Bit is set at 1.
4. VCC = 3.0-3.6V for 100MHz operation

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 EN25P32

Table 12. 75MHz AC Characteristics

(Ta = 0°C to 70°C or – 40°C to 85°C; VCC = 2.7-3.6V)
Symbol Alt Parameter Min Typ Max Unit
Serial Clock Frequency for:
FR fC FAST_READ, PP, SE, BE, DP, RES, WREN, D.C. 75 MHz
WRDI, RDSR, WRSR
fR Serial Clock Frequency READ instruction D.C. 66 MHz
tCLH 1
Serial Clock High Time 6 ns
tCLL1 Serial Clock Low Time 6 ns
tCLCH 2
Serial Clock Rise Time (Slew Rate) 0.1 V / ns
tCHCL 2 Serial Clock Fall Time (Slew Rate) 0.1 V / ns
tSLCH tCSS CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL tCSH CS# High Time 100 ns
tSHQZ 2 tDIS Output Disable Time 6 ns
tCLQX tHO Output Hold Time 0 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tHLCH HOLD# Low Setup Time ( relative to SCK ) 5 ns
tHHCH HOLD# High Setup Time ( relative to SCK ) 5 ns
tCHHH HOLD# Low Hold Time ( relative to SCK ) 5 ns
tCHHL HOLD# High Hold Time ( relative to SCK ) 5 ns
tHLQZ 2 tHZ HOLD# Low to High-Z Output 6 ns
tHHQZ 2 tLZ HOLD# High to Low-Z Output 6 ns
tCLQV tV Output Valid from SCK 6 ns
tWHSL3 Write Protect Setup Time before CS# Low 20 ns
tSHWL3 Write Protect Hold Time after CS# High 100 ns
tDP 2 CS# High to Deep Power-down Mode 3 µs

tRES1 2 CS# High to Standby Mode without Electronic

3 µs
Signature read
tRES2 2 CS# High to Standby Mode with Electronic
1.8 µs
Signature read
tW Write Status Register Cycle Time 10 15 ms
tPP Page Programming Time 1.5 5 ms
tSE Sector Erase Time 64KB sectors 0.8 2 s
tBE Bulk Erase Time 25 50 s

Note: 1. TSCKH + TSCKL must be greater than or equal to 1/ FCLK

2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Sector Protect Bit is set at 1.

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 EN25P32

Figure 22. Serial Output Timing

Figure 23. Input Timing

Figure 24. Hold Timing

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 EN25P32

ABSOLUTE MAXIMUM RATINGS

Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up to
or above these values. Exposure of the device to the maximum rating values for extended periods of time
may adversely affect the device reliability.

Parameter Value Unit

Storage Temperature -65 to +125 　C
Plastic Packages -65 to +125 　C

Output Short Circuit Current1 200 mA

Input and Output Voltage (with respect to

-0.5 to +4.0 V
ground) 2

Vcc -0.5 to +4.0 V

Notes:
1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for
periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O
pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure
below.

RECOMMENDED OPERATING RANGES 1

Parameter Value Unit

Ambient Operating Temperature

Commercial Devices 0 to 70 　C
Industrial Devices -40 to 85

Operating Supply Voltage Regulated: 3.0 to 3.6

Vcc V
Full: 2.7 to 3.6
Notes:
16 Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc
+1.5V

Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

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 EN25P32
Table 13. DATA RETENTION and ENDURANCE

Parameter Description Test Conditions Min Unit

150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years

Erase/Program Endurance -40 to 85 °C 100k cycles

Table 14. LATCH UP CHARACTERISTICS

Parameter Description Min Max

Input voltage with respect to Vss on all pins except I/O pins
(including A9, Reset and OE#) -1.0 V 12.0 V

Input voltage with respect to Vss on all I/O Pins -1.0 V Vcc + 1.0 V

Vcc Current -100 mA 100 mA

Note : These are latch up characteristics and the device should never be put under these conditions. Refer to
Absolute Maximum ratings for the actual operating limits.

Table 15. CAPACITANCE

( VCC = 2.7-3.6V)

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 pF
COUT Output Capacitance VOUT = 0 8 pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.

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 EN25P32
PACKAGE MECHANICAL

Figure 25. 8 LEAD SOP 200 mil ( official name = 209 mil )

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 EN25P32
Figure 26. VDFN8( 5x6mm )

DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A 0.76 0.80 0.84
A1 0.00 0.02 0.04
A2 --- 0.20 ---
D 5.90 6.00 6.10
E 4.90 5.00 5.10
D2 4.18 4.23 4.28
E2 3.95 4.00 4.05
e --- 1.27 ---
b 0.35 0.40 0.45
L 0.55 0.60 0.65
Note : 1. Coplanarity: 0.1 mm

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 EN25P32
Figure 27. 16 LEAD SOP 300 mil

DIMENSION IN MM
SYMBOL
MIN. NOR MAX
A --- --- 2.65
A1 0.10 0.20 0.30
A2 2.25 --- 2.40
C 0.20 0.25 0.30
D 10.10 10.30 10.50
E 10.00 --- 10.65
E1 7.40 7.50 7.60
e --- 1.27 ---
b 0.31 --- 0.51
L 0.4 --- 1.27
θ 00 50 80
Note : 1. Coplanarity: 0.1 mm

This Data Sheet may be revised by subsequent versions 32 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18

Free Datasheet http://www.datasheet4u.com/

 EN25P32
ORDERING INFORMATION
EN25P32 - 75 F C P

PACKAGING CONTENT
(Blank) = Conventional
P = Lead-free package can represent and
warrant meeting the requirements of the
current RoHS Directive 2002/95/EC.

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)

PACKAGE
F = 16-pin 300mil SOP
H = 8-pin 200mil SOP
V = 8-pin VDFN

SPEED
100 = 100 Mhz
75 = 75 Mhz

BASE PART NUMBER

EN = Eon Silicon Solution Inc.
25P = 3V Serial FLASH with boot sectors
32 = 32 Megabit (4096K x 8)

This Data Sheet may be revised by subsequent versions 33 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18

Free Datasheet http://www.datasheet4u.com/

 EN25P32
Revisions List

Revision No Description Date

A Initial Release 2007/04/23
B To correct the OTP sector is mapping to sector 63 in page 22 2007/06/05
C To correct the Table 3 Protected Area Sizes Sector 2007/10/18
Organization Portion from Lower to Upper in page 8

This Data Sheet may be revised by subsequent versions 34 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18

Free Datasheet http://www.datasheet4u.com/