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3 FPGA Modules

The document outlines an FPGA training program consisting of 8 modules. Module 1 covers digital logic design concepts. Module 2 covers project management skills. Module 3 focuses on RTL coding using Verilog HDL. Module 4 addresses functional verification using Verilog HDL. Module 5 involves a standard mini project applying Verilog. Modules 6 and 7 cover interface protocols and system on chip architectures. Module 8 discusses advanced FPGA implementation techniques. The modules progress from basic digital design to advanced verification and FPGA implementation strategies.

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57 views2 pages

3 FPGA Modules

The document outlines an FPGA training program consisting of 8 modules. Module 1 covers digital logic design concepts. Module 2 covers project management skills. Module 3 focuses on RTL coding using Verilog HDL. Module 4 addresses functional verification using Verilog HDL. Module 5 involves a standard mini project applying Verilog. Modules 6 and 7 cover interface protocols and system on chip architectures. Module 8 discusses advanced FPGA implementation techniques. The modules progress from basic digital design to advanced verification and FPGA implementation strategies.

Uploaded by

Abhimanyu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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FPGA Modules

Module1 : Digital Logic Design  System tasks


 Compiler Directives
 Introduction to Digital logic  Verification Process
 Number Systems  Test bench structures
 Boolean algebra  Bus function models
 Boolean minimization  Assertion based Verification
 Combinational circuit design  Functional Verification Coverage
 Sequential circuit design o Statement
 Finite state machines
o Branch
o Expression
 Designing complex digital circuits o Path
 Logic families o Toggle
 Miscellaneous concepts
Module 5 : Standard mini project – using Verilog
Module 2: Project Management
Module 6 : Interface Protocols
 GVim Editor
 Linux Environment  UART
 Perl Scripting  I2C
 SPI
Module 3: RTL Coding using Verilog HDL  APB
 AHB
 Introduction to HDLs  AXI
 Basic constructs  Glimpse of USB
 Syntax  Glimpse of PCIe
 Modeling styles
 Combinational circuit design Module 7 : Overview of SoC Architectures
 Sequential circuit design
 Finite state machine design  What is an SoC ?
 Digital system design  Advantages of SoCs over conventional ASICs?
 Simulation & Synthesis issues  Typical components of an SoCs
 Unwanted Latches  Sample SoC Architectures
 Clock-gating
 Clock-domain crossing issues
 Low power techniques
 RTL Design strategies

Module 4 : Functional Verification using Verilog HDL

 Delay Concepts
 Tasks & Functions
 Stimulus generation
 Race conditions
 File IO Operations
 Miscellaneous constructs
Module 8 : Advanced FPGA Implementation

 Evolution of Programmable logic


 FPGAs Vs ASICs
 Xilinx FPGA Architecture
 Essential Building blocks
 LUT, Slices, CLBs, BRAMs
 DSP / Multipliers
 Clock Management components
 Processor
 IO Pins
 FPGA Design flow & Implementation
 Reading reports
 Pin Assignments
 Timing & Area Constraints
 DCMs
 Memories & FIFOs
 Timing closure strategy
 Power estimation
 Floorplanning the design
 Back-annotation simulations
 FPGA Board Overview
 FPGA Configuration
 System Testing
 On-board stimulus generation
 Logic state capturing
 On-board debugging strategy
 Debugging using ChipScope Pro
 Advanced Synthesis & Optimization techniques for
High performance designs

Mock Interviews

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