India’s Best Inetitute for IES, GATE & PSUs Detailed Solutions ESE-2023 E &T Engineering Mains Test Series Test No: 2 QA. (a) Solution: Since X(s) has 4 poles and no zeros in the finite s-plane, we may assume that X(s) is of the form, XO) = Gae-BE-E=d) Since x(t) is real, the poles of X(s) must occur in conjugate reciprocal pairs. Therefore, we may assume that b = a* and d= c*. A X0) = Gae—#E-O6--) Since, x(t) is even, X(s) must also be even, Hence, the poles must be symmetric about the jQ-axis. Therefore, c= -a* A @)(s+a*)(s+a) Therefore, XO) = Gas Itis given that the location of one of the poles is (3) e'4. If we assume that this pole is a, we haveMADE EASY Test No :2 E & T ENGINEERING | 11 Qi Also, we are given that j x(f)dt = X(0)=4 1 Substituting in the above expression for X(s), we have A = q (3) 4 “arlene Therefore, X() (b) Solution: () SBI: Substract Immediate with Borrow. SBI 8-bit data e.g. SBI 45H The 8-bit data and the borrow are substracted from the contents of the accumulator, and the results are placed in the accumulator. All flags are affected to reflect the result of the operation. (ii) SHLD: Store H and L Register Direct SHLD 16-bit (address) e.g. SHLD 3000 H The contents of register L are stored in the memory location specified by the 16-bit address in the operand, and the contents of H register are stored in the next memory location by incrementing the operand. The content of registers HL are not altered. This is a 3-byte instruction. No flags are affected. (iii) RRC: Rotate Accumulator Right Each binary bit of the accumulator is rotated right by one position. Bit D, is placed in the position of D, as well as in the carry flag. CY is modified according to bit D, S, Z, P, AC flags are not affected, (iv) SPHL: Copy H and L Registers to the Stack Pointer, The instruction loads the contents of H and L registers into the stack pointer register; the content of H register provide the high order address, and the content of the L. register provide the low-order address. The contents of the H and L registers are not altered. ot MADE EASY wwwmadeeasy.in42 | ESE 2023: MAINS TEST SERIES MADE EASY (v) DAD: Add Register pair to H and L Registers. DAD Reg. Pair e.g., DAD B, DAD D, DADH. The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected. Q1 (©) Solution: Let a, is the Fourier series coefficeint of the signal x(t). ‘The fundamental frequency of x(f) is @,= 100 rad/sec. We know that, x(t) = YD aes X(jo)= Y 2na,5(@-100k) Let given, gilt) = y(f)*h() where, y(t) = x(#cos(agt) ¥,Ga) = F{X((O- 0) #XG(0+0y)} Y,(jo) = = Y, [48(0 100k ~09)+.4,5(0-100k +09)] ¥ 1 y [2,8(@ + 100k - wp) + a3(w-100k + w9)] i If © = 500, then the term in the above summation with k = 5 becomes na_,8(0) + na,5(0) Since x(f) is real, _, = a,. Therefore, the above expression becomes, 2nRela,}3(o) Which is an impulse at @ = 0. Hence, we get Y, (jn) = 2x Re{a,} 3(«) Taking inverse Fourier transform, y,(0) = Retas} e g(t) = Refas} * h(t) = Rela} [Given] Therefore, n() = 8) => Hijo) =1 wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 13 Qa Qi (d) Solution: 8255 Control Word: Mode of B | Port B | Port C, D; D; Dy 10/1 D; lode | of A | Port A | Port C D, Ds Since we are using I/O mode, D, = be in Mode 0. Hence, D,D; = 00 and D, = 0 For input, the corresponding bit is to be 1, and for output, it is to be 0. Since, both groups (Group A and Group B) are to Since port A is to be an o/p port, D, = Since port Cy is to be an i/p port, D, Since port B is to be an i/p port, D, = 1 Since port C, is to be an o/p port, Dy = 0 Thus, the control word can be written as 1jo ofo}ijojijo (¢) Solution: The given transfer function can also be written as, 0.28271 0.31927 0.540.321 +0172? -0.22° 0.562"! +0.63827? +0.082°° 140.62 '+0.34z 70.42% Realization using direct form-I structure: He x(n) & score MADE EASY wwwmadeeasy.in414 | ESE 2023: MAINS TEST SERIES MADE EASY Realization using direct form-II structure: x(n) @ 2 y(n) Q4 (f) Solution: The program to transfer a string of data in 8085 microprocessor can be written as follows: LXIH, 4000H LXID, 500011 MVIC, 10H AGAIN: MOVA,M STAXD INXH INXD DCRC JNZ AGAIN HLT The program to transfer a string of data in 8086 microprocessor can be written as follows: MOV SI, 4000H MOV DI, 5000H MOV CX, 10H AGAIN MOV AX, [SI] MOV [DI], AX INCSI INCDI DEC CX JNZ AGAIN HLT score MADE EASY wirwmadeeasyinMADE EASY Test No :2 E & TENGINEERING | 15 Q2 (a) Solution: (i) Given, x,(f) = el leos(2t) Let We know that, e'u(t)}< 25. We know that, cos(2t)<—! Ts n[8(w-2)+8(w+2)] x(P)e0s(28) > [X(0-2)+ X(0+2)] Therefore, from the above multiplying property AHeosmiyetty#{ 2, 2 x)=] em cos(2t) 2n| 14(@-2 14042" Te A cos(2tye 2D 1 1 em cos(2t) Ts(o-2)) Ts(@42 — in(2nt) (ii), Given, x) = GE-1) X,(o) 1 sin(2nt) We know that, x() = mt © -2n Qn x(t) = seer), > u(w +2n)-u(w-2n) sin(2n!) _ sin(QQnt-2n) _ sin(2n(t-1)) n(t—1) m(t—1) n(t=1) = x(t-1) We know that, x() #7 x(o) ecovot MADE EASY wirwmadeeasyin16 | ESE 2023: MAINS TEST SERM ES x(t-1) De X(o) sin(2nt) Therefore, H(t 20) — (2) aT £L_, i [u(o+2n)-u(w-2n)] iit) Gi _ [Pp o t 0500S wwwmadeeasy.in48 | ESE 2023: MAINS TEST SERIES MADE EASY wall) vie ° , [r-s(2) aa ea) o 2 2(1-cosw) oF Q2 (b) Solution: () Programmed data transfer schemes: In programmed data transfer schemes, the data transfer is controlled by CPU. Programmed data transfer schemes can be of three types: 1 Synchronous Transfer : In synchronous data transfer, the device which sends the data and device which receives the data are synchronised with same clock. Itis suitable when both microprocessor and I/O device matches in speed. The data transfer takes place through IN and OUT instruction in 1/O mapped I/O devices and with instruction related to memory read/write in case of memory mapped I/O devices. Asynchronous Transfer : This technique of data transfer is used when speed of microprocessor and that of I/O device is not matching. The microprocessor continuously checks the status of I/O device to see whether device is ready to send data or not. When I/O devices becomes ready, it sends signals called handshake signals. READY signal is handshake signal used by 8085 for asynchronous data transfer. Interrupt driven data transfer : In this mode of data transfer, the microprocessor initiates the I/O device to get ready and then it executes its main programmes, instead of remaining in loop to check the status of I/O device. When I/O device is ready to transfer data, it sends a high signal to microprocessor through interrupt line. On receiving an interrupt signal through interrupt line, the microprocessor complete the current instruction being executed and then attend 1/O device. After completing the data transfer, the microprocessor return back to main program. Interrupt data transfer is used for slow 1/O devices. It is efficient than asynchronous data transfer mode because time of microprocessor is not wasted in waiting while I/O device is getting ready. score MADE EASY wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 19 (i) Direct Memory Access (DMA): It is a process of high speed direct data transfer between memory and external peripherals (I/O device) without programming, intervention. DMA involves communication or data transfer controlled by an external peripheral. Wherever the microprocessor-controlled data transfer is too slow, DMA. is generally used; e.g. data transfer between hard disk and read/write memory of the system. 8237/8257 ICs are DMA controllers. DMA controllers takes control of, the buses and transfer data directly between memory and external peripherals. When large amount of data is to be printed out from the memory of a computer, DMA is used because it avoids using MPU, thus, allowing the MPU to attend to another job. DMA transfer is faster than either interrupt initiated I/O or polling based I/O for large data transfer. Q2 (c) Solution: ‘The overall impulse response of the system can be given by, (ni) = h(n) * Drala) ~ thal) * hyo} Iig(rt) * hy(n) = {(1 + 1) u(n)] * [82 -2)] = (2-1) wn = 2) Inn) —Uhg(n) * g(r] = (1) a(n) ~ (= 1) u(r ~ 2) = frru(n) + u(r] = [nu(n ~ 2) - u(n = 2)] = 8(n 1) + un) + u(n 2) = 2u(n) - 3(n) 111)_1 1, 1 h,(t) para} atoning Hence, = [2u(n) - 3(n)]* [480 +tom—+20-2)| = [stor Sutr—1y +r) [S09 +3 00—1 + 5360-2] hn) = 48(0 +5 5(0—1) + 28(n-2)+3 (0-3) Given that, x(n) = 8(142)438(-1) -48(n-3)={1,0,0,3,0,-4} wwwmadeeasy.in20 | ESE 2023: MAINS TEST SERIES MADE EASY .1 8 85 8 5 8 He) 2 4 2 2 2 2 2 2 2 at 0 9 3 0 4 15 5 3 5 3 5 5 5 8 2 4 2 2 2 2 2 2 2 0 0 0 0 0 0 6 0 oO 0 0 0 0 0 6 0 Oo t 305 BB Bb 2 4 © 2 2 22 0 0 0 0 0 Oo 2 5 0-10 1 8 3 1B wig G24 FP s 2 0 0 3 13 So, u(n) apa ® 2 Q3 (a) Solution: LXIH, 6000H_ ; Initialize memory pointer MVIC,00H — ; Initialize number counter MVID,00H — ; Initialize positive number counter MVIB,00H — ; Initialize negative number counter MVIE,00H — ; Initialize zero number counter BEGIN : MOVA,M — ; Get the number CPI00H ; Ifnumber=0 JZ ZERONUM ; Go to ZERONUM ANI80H ; IfMSB of number = 1 JNZNEGNUM ; If number is negative goto NEGNUM INRD ; Otherwise increment positive number counter JMP LAST wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 214 ZERONUM: INRE ; Increment zero number counter JMP LAST NEGNUM: — INRB ; Increment negative number counter LAST: INXH ; Increment memory pointer INRC ; Increment number counter MOV A, C CPI32H ; If number counter = 50,, JNZ BEGIN ; Then store otherwise check next number LXIH, 7000; Initialize memory pointer MOVM,B __ ; Store negative number count INXH MOVM,E _ ; Store zero number count INXH MOVM,D __; Store positive number count HLT Q3 (b) Solution: ay" @) Given, x(n) = (3) {ul[n]-u[n-10]} by the definition of z-transform, X@) wwwmadeeasy.in22 | ESE 2023: MAINS TEST SERIES MADE EASY Pole-zero plot for X(z) zplane ele p \ Pole-zero ; | eancelation (i) by the definition of z-transform, > ane" < 2) [2nn = Y7( 4) cos) 4 x ls Le x2) score MADE EASY wirwmadeeasyinMADE EASY Test No :2 E & TENGINEERING | 23 1 where ROC: |z| > > 3 The pole-zero plot, Q3_ (¢) Solution: () The spectrum of m(t) = cos ust is given by F[cos est] = M( 2) + 08(w + «,) The spectrum of m(t) is shown below Me) a The spectrum of the sampled signal is given as le Mo) = = XY M(@-nw,) Figure below shows the spectrum of M,(«) of the ideal sampled signal m,(t) with nf. ,= 30, o, = 507 ©, wwwmadeeasy.in24 | ESE 2023: MAINS TEST SERIES MADE EASY M(o) Also indicated by a dashed line is the passband of low pass filter with w, = @,/2. It may be seen that aliasing does occur , and the low pass filter output x,(t) is given by 1 4,(0) = cos (0, @,)E = COS Wot # m(t) In the figure given below is depicted m(f), its samples and reconstructed signal x0), m() Samples Fig, Effect of aliasing on a sinusoidal signal (ii) Following are the three instructions, which use stack memory for their execution: 1. PUSH 2. POP 3. XTHL 1. PUSHR, (i) Stores the contents of register pairs R, on Rp > BC, DE, HL and PSW two top locations of stack. (ii) 1-byte instruction (ii) Register indirect addressing mode (iv) 3 machines cycles and 12-T states () No flag is affected. score MADE EASY wirwmadeeasyinTest No :2 E & TENGINEERING | 25 2. POP R, (Receives the contents of two top locations R, > BC, DE, HL and PSW of stack to register pair Rp. (ii) 1-byte instruction. (iii) Register indirect addressing mode (iv) 3 machine cycles and 10-T states (v) No flag is affected. 3. XTHL (i) Exchanges the contents of two top locations R, > BC, DE, HL and PSW of stack with contents of HL pair. Q4 (a) Solution: (@) Algorithm: (ii) 1-byte instruction. (iii) Register indirect addressing mode (iv) 5 machine cycles and 16-T states (v) No flag is affected. 1. Load the BCD number in the accumulator. 2. Unpack the 2 digit BCD number into two separate digits. Let the left digit be BCD2 and the right one BCD1. 3. Multiply BCD2 by 10 and add BCD1 to it. Program: LDA 2200H MOV B, A ANIOFH MOV C, A MOV A,B ANIFOH RRC RRC RRC RRC MOV B,A XRA A MVID,0AH ; Get the BCD number Save it in B register Mask most significant four bits Save unpacked BCD1 in C register Get BCD again Mask least significant four bits Convert most significant four bits into unpacked BCD2 Convert most significant four bits into unpacked BCD2 Convert most significant four bits into unpacked BCD2 Convert most significant four bits into unpacked BCD2 Save unpacked BCD 2 in B register Clear accumulator Set D asa multiplier of 10 wwwmadeeasy.in26 | ESE 2023: MAINS TEST SERIES MADE EASY SUM: ADDD ; Add 10 until (B) = 0 DCRB ; Decrement BCD2 by one JNZSUM —; _Is multiplication complete? If not, go back and add again ADDC ; Add BCD1 STA 2300H ; Store the result HLT ; Terminate program execution (i) Consider an 8-bit binary number 00101101 BQ Q BW QW QD Binary code —+ 0 0 1 0 1 1 o o1 te bob dE EEE Grycode —¥0 0 1 1 1 0 1 1 Program logic: To XOR each bit with it’s adjacent bit, we right shift the contents of original number and then XOR the result with the original number. ie, 00101101 +— Binary number © 90010110 = Right shift binary number 00111011 + Gray code number Program: MOV A,52H_ ; Load binary number MOV RO,A —; Save binary number into register RO CLRC ; Clear carry flag RRCA ; Right shift Accumulator content (The value of carry flag moves into MSB) XRLA,RO —; XOR the shifted content with original number HLT Qa (b) Solution: Given input to an LTI system, ey a xy = Yoel From the definition of Fourier series, 5 2n ) TKO! ; where, Wy = 7 KO = Y Cello" ; where, w= 7, wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 27 where, Ty is the fundamental time period. On comparing, TT =8 Therefore, the given signal x,(f) is periodic with period T = 8 and has Fourier series coefficients C, = alFl. The average energy in the input signal is AfpqnPat = fea? r (oh E (2)! a _lel+a2+1_ lta? "Ina? 1-0? Let the low pass filter passes some number, say nt of the harmonic components of »;(t) so that the average energy in the output signal is 1 2 liver ae = To make the energy in the output at least 90% of that in the input, Led —2oe2m'2 2 +0? ~201 oof Lhe v 1-a 1-02 1+ a2 — 2e2m+2 v 0.941 + 02) 1+a? am +2 oe 2 ” by taking ‘log’ on both sides, ot MADE EASY wwwmadeeasy.in28 | ESE 2023: MAINS TEST SERIES MADE EASY log 22 (2m + 2)log a < !e8| 5 w o ae (m + I)log o2 v1 [elo] <1] 2n Because the harmonics are spaced at = intervals in frequency, Therefore, the minimum value of Wis toe( 1 + -] 20 4|2" We | Togat | 8 log{ 24° | 20 iz Wain = | Togat 7 Qa (c) Solution: () From the given pole-zero plot, we get, where, put, H(e®) = 2 and |Heei™f = EASY wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 29 2 1 ae? - nei +0? Therefore, [HCP = AP Hef = 1a This implies that, |H(e®)| = |A| = constant (ii) BSR is a special mode and is applicable only for the bits at port C. In the control word format, if the MSB is mode 0 (D, = 0), the BSR (bit set/reset) mode takes effect. In this mode, any bit at port C can be set or reset by specifying, the bit which has to be set or reset. However, at a time, only one bit can be addressed and that bit is to be either set or reset. The corresponding control word has to be decided and moved to the control word register (CWR) Control Word Format: DD, Dy Ds DD, DB o [x] x |x| Bitsetec [| s/r —_ ~~ s(Port-c) BSR Not used Mode D, D, D; D, Ds D, D, Dy 1, PC, to be set: 0 x x x oO 0 0 1 = 01H treat ‘X’ as ‘0’ 2. PC, to be reset: 0 0 0 0 1 1 1 0 = OBH 3. PC, to be set: 0 0 0 0 0 0 1 = BH 4. PC, to be set: 0 0 0 0 1 1 1 1 = OFH Here Dy = 1 means set; D, = 0 means reset In the BSR mode, port C should be in 0/p mode. wwwmadeeasy.in30 | ESE 2023: MAINS TEST SERIES MADE EASY Q5 (a) Solution: For calculating Thevenin’s voltage, open the resistor R, The above circuit can be redrawn as: 20V 20 40+10 the voltage drop across 40 & resistor is, Ving = 4X 40=04 x 40=16V The branch current, =04A ry The branch current, 50+10 60 The voltage drop across 50 @ resistor is, score MADE EASY wirwmadeeasyinMADE EASY Test No :2 E & T ENGINEERING | 34 aagny Dig = Vat 20V D 102 102 av by using KVL in the above loop, 15-16 - Vy, = 0 Va = -1V For calculating Thevenin‘s resistance, Ry, deactivate all active sources. 40. 109 102 Ry, = (40110) + 60] 10) = 16.33 @ The Thevenin’s equivalent circuit is ANA ° 267) bow ) . The I —1_ 29.12mA score MADE EASY wwwmadeeasy.in32_| ESE 2023: MAINS TEST SERIES MADE EASY Q5-{by Sotution Convert Y network of 3, 3@, 39 into A RyRy + RoRg + R3Ry R, R 1 R, =99 The circuit is reduced to, 30 2a ea) aa-250 Gas Fd) | JZ 092) 11.69) =225.0 The circuit is reduced to, \ ze ro $5 su” $20 2 oy R, = 3Q,R,=225 Q,R,= 2252 R,Ry + RRs + RgRy Ri Re 6.188 score MADE EASY wirwmadeeasyinMADE EASY Test No :2 E & T ENGINEERING | 33 Similarly, R= 8259 R= 8252 The circuit is reduced to, oi — 3a ——~| - gi $0) (0.9) || 6188.) = 3.6660 O50 #0) (29) || (8.259) =1619 The circuit is reduced to, my easng £ e010 a0-sz760 30 Ry Rog = 3+ [(8.25) || (6.276)] +3 Ry = 34321843 Re = 9.218. 2 Q5 (c) Solution: Gain Margin: It is the reciprocal of the magnitude | G(jw) | at the frequency at which the phase angle is -180°. 1 [CGio.)] For a stable minimum phase system, the gain margin indicates how much the gain can be increased before the sytem become unstable. For an unstable system, gain margin is indicative of how much the gain must be decreased to make the system stable. @, — Phase crossover frequency at which the phase angle of G(j) is -180°. K, (4B) = 20 log K, = -20 log |G, | Phase Margin : The phase margin is that amount of additional phase lag at the gain crossover frequency required to bring the system to the verge of instability. The gain crossover frequency is the frequency at which | G(jw) | = 1. Phase margin, y = 180° + 6 ~ Phase angle of open loop transfer function at gain crossover frequency, ie., 6= ZG(j,). K ot MADE EASY wwwmadeeasy.in34 | ESE 2023: MAINS TEST SERIES MADE EASY Importance of GM and PM in Control System design: + PMand GM of a control system are a measure of closeness of the polar plot to the -1 + j0 point. These margins are used as design criteria + Either GM alone or PM alone does not give sufficient indication of relative stability. Both should be given in the determination of relative stability. + For minimum-phase system, both PM and GM must be positive for the system to be stable. Negative margins indicates instability. + For satisfactory performance, the PM should be between 30°-60° and GM should be greater than 6 dB. With these values, a minimum phase system has guaranteed stability, even if open loop system gain and time constants vary to a certain extent. Q5 (d) Solution: * The Routh table for the given characteristic equation can be formed as follows: st 1 2 10 8 K K+1 0 2 | 2K-(K+1) ( x) | AEF (7 - 10 0 . K K 2 st (K+1)- 10K 0 (K-1) ° 10 o 0 + For the system to be stable, all the elements in the first column of the Routh table should have same sign. For this, the following conditions should be satisfied: From s* row, K>0 (i) From s* row, wt >0 K>1 (ii) 10K ({K-1) K2-1-10K? > 0 -9K2-1 > 0 (iii) + No real value of “K” satisfies all the equations (i), (ii) and (iii) simultaneously. So, the given system is unstable for any real value of “K”. From s! row,(K+1)- wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 35 Q5 (e) Solution: Inany passive linear bilateral network, if the single voltage source V, in branch x produces the current response I, in branch y, then the removal of the voltage source from branch x and its insertion in branch y will produce the current response I, in the branch x. The current I can be calculated with nodal analysis 90.2 sy 2 y, 752 Vit WWF V5 1" 50g 50.2 30V = Ref. Node Nodal equations VV VM VinVs 6 ‘15, 9 ~° Putting V, = 30 V in above equation gives, 0.094, - 0.017V, = 0.33 (ii) At node V,, It reduces to, -0.017V; +0.05V, = 0.4 (iii) Solving (ii) and (iii) gives, 5.28 V; V,=98 5.28 Let us now interchange source V = 30 V and measure current in branch where source is, shorted wwwmadeeasy.in36 | ESE 2023: MAINS TEST SERIES MADE EASY Mesh analy 901, = 75(l, ~ I) - 60 (1, - 1, 225 I, - 601, ~75 1 Mesh equations for loop 2, ~50(I, ~ I,) ~ 60 (I, ~ 1,) - 151, +30 = 0 ~60 1, +125 1, - 501, = 30 Av) Mesh equations for loop 3, -75(Iy - 1,) - 50 (1, - 1, -75 I, - 50 I, +125 I, = 0 (vi) Solving (iv), (v) and (vi) we get I, = 1=0.35 A proved Mesh equations for loop 1, 0 0 iv) Q5 (f) Solution: The given circuit can be broken into two constituent circuits by considering individual source. By considering source, E, where, X, = @L = 2n x 50 x 63.33 x 107 ~ 202 x, = b= 1 ___=1600 © WC” 2nx50% 19.8910" py 02 ja 10020" V impedance seen from source E,, Zin, 4 = 20+ (160 || 720) = 5p) 4 i160 720 _ ~ = 204-7’ = 00 + j22,857 =j40 0 + 22.85; = 30.372 248,81° Q wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 37 , 10040" _ 100.20" Current, I = “7 ~~ 30372248.81° int x— 20 __3.2937-48.81°x—20 — 7160+ 720 —j40 O47 A131.19°A 293 Z-48.81°A, By considering source, E, 92 = joa pp > a8" impedance seen from source E,, Z, j20+{20 || (-j160) | ne yp 4 20 (160) 20-160 j20 + 19.692 ~ j2.462 = 19,692 + j17.538 = 26.37 Z41.69° 0 702-30" __ 702-30" Zing 26.37 Z41.69° = 2.655 2-71.69" A 17x20 _ 53.102~71.69° = 20=j160 161.252-82.87° 1, = 0.329 211.18° A Using superposition theorem, N u ind Current, I” = i the total current, L+l = 0.47 2131.19° + 0,329 211.18° 0.42 288.2°A wwwmadeeasy.in38 | ESE 2023: MAINS TEST SERIES MADE EASY Q.6 (a) Solution: (i) From the given Bode plot, it is clear that, there is one pole at origin, one pole at , and one zero at So, the transfer function can be given as, (as ‘ ) G(s) = S24 (rz) oy Finding the value of K: With starting slope, -20 log,, (w) + 20 logy, K = Atw=1rad/sec, -20 log, (1) + 20 log, K 20 logyy K = 20 logy» (1) So, K=1 q = Finding the value of @,: From the slope between w, and w = 1 rad/sec, -20-0 ————~ = -20 logio(@1)—legi0(1) log; (@,)-0 = 1 10 rad/sec Finding the value of @, : From the slope between @, and (-60)-(-20) oe = 40 108 10(@2) — log 10(@1) g 8s a u , = 10 = w= 100, = 100 rad/sec onl 35o] (s+100) ) 10s(s-+10) So, the transfer function, G(s) ot MADE EASY wwwmadeeasy.inMADE EASY Test No :2 E & TENGINEERING | 39 (i) With X(6) = 0, the given block diagram reduces as, 9 Lt L Jey Cs) ro—fer “~@ a {6s Y cs) al By eliminating feedback loops I, II 4, G& | _Jel “@ Gf Cs) RQ) { Combining the blocks in the loop III, R9—AG, G,G,G, “| m (+ Gja+ GH oo cls) G,G,GG5 Ris) {(1+Gz)(1+G5H5)}+{G2GaGs} With R(s) = 0, G,, Vanishes, but minus sign at summing point must be considered by introducing block of ~1 as shown, XQ G, EHe@-airs By eliminating feedback loops I, Il cls) score MADE EASY wirwmadeeasyin40 | ESE 2023: MAINS TEST SERIES MADE EASY ce) x9—f G Ce) _ G,G5(1+Gp) X(s) (1+ G5Hs)(1+ Gp) + GGyHs Q6 (b) Solution: * The Routh table for the given characteristic equation can be formed as follows: + All the elements in s* row are zeros. If we continue to formulate the Routh table further, then all the elements in the subsequent rows will be infinity. So, this row of zeros causes a difficulty in formulating the complete Routh table. * The existence of the row of zeros in the Routh table indicates that, some roots of the given characteristic equation are symmetrically located with respect to origin. The number of roots that are symmetrical about the origin is equal to the order of the ot MADE EASY wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 44 auxiliary equation, which can be formed by using the coefficients of the row just above the row of zeros in the Routh table as follows: AG) = st-38-4=0 (i) Method-1 to overcome the difficulty: * The row of zeros can be replaced with the coefficients of the first derivative of the auxiliary equation and the Routh table can be formulated as follows: dA 9) 43 6540-0 ds sf 1 2-7-4 & 1 3-40 sf 1 3-400 8 4 6 0 0 s o 0 st o 0 ° en) + There is one sign change in the elements of the first column. So, there will be one root of the characteristic equation which lies in the right-half of s-plane. Hence, the given system is unstable. Method-2 to overcome the difficulty: + The roots of the auxiliary equation also satisfy the characteristic equation. So, the given characteristic equation can be factorized as follows: Stst1 38-4 [49-28-3878 —45—4 fa 3et-4t S48 -39-38 45-4 8-38-45 #384 s-38-4 0 + So, the given characteristic equation can be written as, (s#- 352-4) (2 +541) = 0 (ii) wwwmadeeasy.in42 | ESE 2023: MAINS TEST SERIES MADE EASY + The roots of auxiliary equation are, st-3s%-4 = 0 (2 +1) (2-4) = 0 4=>s -2, +2 So, one root of auxiliary equation lies in the right-half of s-plane. + The nature of the roots of “s? + s + 1 = 0” can be determined as follows: There is no sign change in the elements of the first column of the Routh table of 432.4 §+1=0", So, all the roots of “s? + s +1 = 0” lie in the left-half of s-plane. + From the above two points, itis clear that, one root of the given characteristic equation lies in the right-half of s-plane. So, the given system is unstable. To determine all the roots of given characteristic equation: + The roots of auxiliary equation will also satisfy the given characteristic equation So, the four possible roots of the given characteristic equation are : s = -2, +2, -j1, 41. + Theremaining two roots of the given characteristic equation can be solved as follows 24st1=0 a4 VM? 40) 5 0.5+ jNO75 1, v3 ii * So, all the six roots of the given characteristic equation are 2, +2, -j1, +1, -0.5+ jV075, -0.5- jVO75. Q6 (c) Solution: The open loop transfer function is 10 (6+1410K)s As k is not a multiplying factor, we modify the equation such that k appears as the multiplying factor. Since the characteristic equation is St 45+10ks +10 = 0 G)H() = ot MADE EASY wwwmadeeasy.inMADE EASY Test No :2 E & TENGINEERING | 43 We rewrite this equation as follows:- 10ks P4st10 Let 10k = K The above equation becomes, 14+ Step 1: The system has a open-loop zero at s = 0, and two open loop poles at citvi-40 ae = 0.54 73.1225 Pole-zero plot % —ja.n225 (2k+1)180 Step 2: angle of asymptote , = a ya2 where k= 0,1, 2..... p-2-1 since p=2,z=1,therefore k= 0 180° Real part of pole - ZReal part of zero Centroid = 6 = Step 3: For breakaway point wirwmadeeasyin44 | ESE 2023: MAINS TEST SERIES MADE EASY dK (2s +1)-(s7 ++ 10)( as 2 %-10=0 s= +10 =+3.16 Here, only s = -3.16 is valid breakaway point. Step 4: angle of departure 64 = +[180° + 6] = ¥ angle made by zero at that point ~ ¥ angle made by pole at that point 6, = 90° © = 99.1° - 90° = 9.097° 4[180° + 9.097°] = +189.09° Step 5: Root locus ‘As we require & = 0.7 for the closed loop poles, we find the intersection of the circular root locus and a line having angle cos! § = cos10.7 = 45.57° This angle is with negative real axis as € = 0.7 is an underdamped system. The intersection can be found as: wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 45 jo V0 sin a 10 cosa. cos ot = cos 45.57° = 0.7 o = -V10x0.7 =-2.214 © = Vi0sina = V10-sin 45.57° = 2.258 0.7 with root locus is at The intersection of 2.214 + j2.258 The gain K for this 2.214 + j2.258 _ _('+s+10) s \s = (-2214+ j2.258) K = 3.427 Hence, desired value of velocity feedback gain K k= 7)=0.3427 Q7 (a) Solution: sy . (8+ I(6+2) GO) = Bes 10)(6+20) (1+ jo)(2+ jo) Gio) = (9) = Go) (0s joy20+ fa) ate Magnitude, (100 + )(400 +.) Phase angle, ¢ = -270°+tan“"(w)+tan™ (3) tan (2) tan? (2) Ato=0, M = wand 6 = -270° (or) 90° Atw=e, M = Oand § = -270° (or) 90° So, starting angle and ending angle both are “-270°". wwwmadeeasy.in46 | ESE 2023: MAINS TEST SERIES a afl), afd af) = 1, = -270°+tan*(1) +t (f -ti ‘(a5 ~tan( Ato=1,6 fan” *(1)+ tan’ 2) fan” | 35) tan lao ~207° (or) 153° Finding intersections with 180° line: 30 20 wo? | =-180° 200) (30 (300 tant ‘(ee — ope ae 200-07 “7 30 300 (2-@7) (200-w*) le 90" (2-w*)(200-w") So, (2-@) (200- a) +90 w’ 0 wot - 202 w? + 400 + 90 wo? = 0 wt - 112 @? + 400 = 0 112+ (112)? - 4(400) 56+ ./2736 = 3.7, 108.3 2 0, = J37 = 1.92 rad/sec @, = J108.3 = 10.41 rad/sec So, the polar plot intersects 180° line two times. wirwmadeeasyinMADE EASY Test No :2 E & TENGINEERING | 47 The resultant plot can be given as, Im[G(jo)] 0 Re[G(io)] The value of M, is, (100: a? (400 oF) 1 (1+3.7)(44+37) (1.92)? ¥ (100+3.7)(400+3.7) elllevel) (100+03)(400+03) = 4.15 x 10% The value of M, is, M. 1 (1+ 108.3)(4+108.3) (10.41)? (100 + 108.3)(400+ 108.3) Q7 (b) Solution: (i) To determine V, using superposition theorem : * When 3 A current source is acting alone, Using current division rule, score MADE EASY wirwmadeeasyin48 | ESE 2023: MAINS TEST SERIES MADE EASY 4 __3,4q 9444542 20° «+5 I, = 3Ax [x2@-Sv=12V * When 2 A current source is acting alone, 2a Using current division rule, 9 18 2Ax————_=- 9444245 20 vy = If x2Q=-18V + When 6 A current source is acting alone, a+ ° ie ime Using current division rule, 3 = -6A 5 = Vir = I x2Q=-3V + When 30 V voltage source is acting alone, score MADE EASY wirwmadeeasyinMADE EASY Test No :2 E & T ENGINEERING | 49 + When all the 4 sources are acting simultaneously, using superposition theorem, Vi = Ve4V 44" =12-18-34+3=-06V (ii) To determine V, using source transformation technique: A practical current source can be transformed into a practical voltage source as shown below. 1,x20--5 = ~~ 10 Q7 (c) Solution: To find the current through Z, by Norton’s theorem, let us short the terminals A-B for calculating Norton’s current. The network is redrawn and shown in below figure. Ay, Co | A wwwmadeeasy.in50 | ESE 2023: MAINS TEST SERIES MADE EASY Let the voltage at node be V;. Using nodal analysis, Ve-% 4 43 (1,1 1) Yistat “ NZ" %"Z) or VAY, + Yy+ Vy ‘Vs or Vi = Yt +s N y, = d=. -01-jo30 ow, 17 Zz ip = 0.154 ~ 0.2300 = 0.230 0.1540 and arr i 1-03 FS _) (40+ j0) 0.484 — j0.684 = 14.45 - j4.375 = 15.09 2 -16.85° V Now, ~ j3.23 = 4.18 2-50,63° A To find Norton impedanee, the circuit is redrawn as shown: From the above figure, Zy = [(Z,|Z,) + Zs] ll Zy = (3.74 + 73.54) || (1 + 72) 0.850 + j1.33 = 1.578 257.41° Q The Norton equivalent circuit is shown in figure below. wwwmadeeasy.inMADE EASY Test No :2 E & TENGINEERING | 51 From the above figure, we get, I= Cara 0.850 + j1.33 0.850+ j1.33+1-j3 174 + j2 = 2.65 248.97° A (2.65 j3. 2a[ Q8 (a) Solution: Put = jw S60) = Gox1Gjor2) . ~iko* or Gia) = Goa?) Bo —jKw® ((2-w?) - j30) or Gv) = wee ) _. 3Ko* —__jKw*(2-w*) C0) = 0?) + Ba)? (2-0) + Ba) (@ lim G(ja) : Re(G(j0)) — -0, Img (Gj0) > + jo (ii) The intersection of G(ja) with positive real axis. Img G(jw) = 0 ~ Ko3(2- 0) (2-0? + Bw)? = 0 2-w=0 = © = 4V2 rad/sec The intersection is obtained by putting © = J in real part of G(ja) ie, 4 -3K (v2) -3K x (2)(2) wirwmadeeasyin52 | ESE 2023: MAINS TEST SERIES MADE EASY ‘As per step (i), (ii) and (iii), general shape of the Nyquist plot is drawn as shown below: Seplane Fig: Nyquist plot forthe system ___ Kjos | C09) = Goin) 1° KI) (joo) = loo}| 90° The closing of Nyquist plot from = = to w =~» is as explained below: Ins-plane, the RHS region is closed from s = je to s = -jee through a semi circle of infinite radius in clockwise direction, hence the corresponding points in G(s)-plane i.e., G(jee) to G(-jee) are closed through a semi circle of infinite radius to account for effective numerator term ie,, Kjee of G(jn) as o> & It is seen that number of poles of G(s) having positive real part is nil ie., P, = 0. The encirclement of critical point (-1 + j0) are determined below: 3 1. K<> The critical point (-1 + j0) lies outside the Nyquist plot, hence N = 0. 3 The system is stable for K <> 3 K>2 2 Kod ‘The critical point (~1 + j0) is encircled twice in clockwise direction of Nyquist plot, ot MADE EASY wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 53 hence System is unstable for K >3 i 3 For stability Ks > Q8 (b) Solution: When terminals of network are open circuited, the circuit takes the form shown below in fig, (b). By KVL in the left-hand mesh, 8230°V go 820°V 4g “ san ‘ WW —8 1 I © + 22 1020° V = Vm so $60 $ I $ Fig. (a) Fig. (b) (2-8)1-1020° + 61 = 0 = 1020 1020" 96. 232° 8-75 9.4342 -32° By KVL in the right-hand mesh in fig. (b) -61 + 10.20° - 8230°-0x4-V,,=0 Vay = ~6 * 1.06 232° + 10.20° - 8 230° 39 ~ j3.37 +10 - 6.928 - j4 = -2.318 - j7.37 = 7.726 Z-107.46° V Determination of Z,,: The voltage sources are short circuited as shown in figure (c). wwwmadeeasy.in54 | ESE 2023: MAINS TEST SERIES MADE EASY sc, 32 4 ° sc ° — Zin spo Zon I ; Fig. (c) 6 ‘The Thevenin impedance Z,, is the impedance between the open-circuited terminals a- b given as Zp, = 44161) 2-15)] = 44 82-15) 642-75 =443,42482 -36,2° 4+ 2.7637 — j2.02 = (6.7637 ~ j2.02)0 Determination of current through R,, Thevenin network Fig. (d) Figure (d) shows the Thevenin equivalent network in which R,, is reconnected at terminals a-b, The current through R,, is given by 1. Zin + Rae Since the resistance of R,, is varied from 2 Q to 10 2, maximum current through R,, is obtained when R,, = 29. _ 7.7262 —107.46° (isda * 67637 = j2.02+2 wwwmadeeasy.inMADE EASY Test No :2 E & T ENGINEERING | 55 = 27264-W7AG* _ 9 9597 94.480 8.998 2-12.98" Minimum current through R,,, is obtained when R,, = 10 (ayn = 27262 -W7AS _ 9 457 7 100.59° A swan = 6.7637 ~ j2.02-+10 Hence, the current through R,, varies from 0.859 2-94.48? A to 0.457 2-100.59° A Q8 (c) Solution: The given circuit is balanced. Hence, V,,, = 0. Current in each resistor I= (V,/2R). When the resistor in branch BC is changed from R to (R + AR), the change in current in any branch may be calculated by assuming that an ideal voltage source of voltage (JAR) is connected in series with (R + AR) and the voltage source V, is replaced by a short circuit. Such an arrangement is shown in below figure. From these figures, R,=R (r+4) wwwmadeeasy.in56 | ESE 2023: MAINS TEST SERIES Nz yg Fig. (b) _ RQ+R/2) _ R(R+2r) R+r+R/2 3R+2r IAR 1° REAR+R, R 2R R+r+R/2) 3R+2r! From fig. (b) From fig. (©), From fig, (b), Voltage drop across BD is 2RrI AR = r= Ven = "2 @Ry2r(R+AR+R,) 2Rr(V, /2R)AR @R+2n| ReaRe R(R+2r) 3R+2r | Ver AR ~ (R+AR)GR+2r)+R(R+2r) Ver AR 4R(R+r) + AR(BR+2r) 9000 score MADE EASY wirwmadeeasyin