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GD25LQ80
DATASHEET
 GD25LQ80xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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- Content - Page
1. FEATURES ------------------------------------------------------------------------------------------------- 4
2. GENERAL DESCRIPTION ----------------------------------------------------------------------------- 5
3. MEMORY ORGANIZATION -------------------------------------------------------------------------- 6
4. DEVICE OPERATION ---------------------------------------------------------------------------------- 7
5. DATA PROTECTION ------------------------------------------------------------------------------------ 8
6. STATUS REGISTER ------------------------------------------------------------------------------------- 10
7. COMMANDS DESCRIPTION ------------------------------------------------------------------------- 11
7.1. Write Enable (WREN) (06H) ----------------------------------------------------------------------- 15
7.2. Write Disable (WRDI) (04H) ----------------------------------------------------------------------- 16
7.3. Write Enable for Volatile Status Register (50H) -------------------------------------------------- 17
7.4. Read Status Register (RDSR) (05H or 35H) ------------------------------------------------------ 18
7.5. Write Status Register (WRSR) (01H) -------------------------------------------------------------- 19
7.6. Read Data Bytes (READ) (03H) -------------------------------------------------------------------- 20
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) ------------------------------------------- 20
7.8. Dual Output Fast Read (3BH) ---------------------------------------------------------------------- 21
7.9. Quad Output Fast Read (6BH) ---------------------------------------------------------------------- 22
7.10. Dual I/O Fast Read (BBH) -------------------------------------------------------------------------- 22
7.11. Quad I/O Fast Read (EBH) -------------------------------------------------------------------------- 23
7.12. Quad I/O Word Fast Read (E7H) ------------------------------------------------------------------ 25
7.13. Set Burst with Wrap (77H) -------------------------------------------------------------------------- 27
7.14. Page Program (PP) (02H) ---------------------------------------------------------------------------- 27
7.15. Quad Page Program (32H) --------------------------------------------------------------------------- 29
7.16. Sector Erase (SE) (20H) ----------------------------------------------------------------------------- 30
7.17. 32KB Block Erase (BE) (52H) --------------------------------------------------------------------- 31
7.18. 64KB Block Erase (BE) (D8H) --------------------------------------------------------------------- 32
7.19. Chip Erase (CE) (60/C7H) -------------------------------------------------------------------------- 33
7.20. Deep Power-Down (DP) (B9H) --------------------------------------------------------------------- 34
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH) ------------------------- 35
7.22. Read Manufacture ID/Device ID (REMS) (90H) ------------------------------------------------- 37
7.23. Read Manufacture ID/Device ID Dual I/O (92H) ------------------------------------------------ 38
7.24. Read Manufacture ID/Device ID Quad I/O (94H) ----------------------------------------------- 39
7.25. Read Identification (RDID) (9FH) ------------------------------------------------------------------ 40
7.26. Program/Erase Suspend (PES) (75H) -------------------------------------------------------------- 41
7.27. Program/Erase Resume (PER) (7AH) -------------------------------------------------------------- 42

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7.28. Erase Security Registers (44H) ---------------------------------------------------------------------- 43

7.29. Program Security Registers (42H) ------------------------------------------------------------------ 44
7.30. Read Security Registers (48H) ---------------------------------------------------------------------- 45
7.31. Set Read Parameters (C0H) ------------------------------------------------------------------------- 46
7.32. Burst Read With Wrap (0CH) ----------------------------------------------------------------------- 47
7.33. Enable QPI (38H) ------------------------------------------------------------------------------------ 47
7.34. Disable QPI (FFH) ----------------------------------------------------------------------------------- 48
7.35. Enable Reset (66H) and Reset (99H) --------------------------------------------------------------- 49
8. ELECTRICAL CHARACTERISTICS --------------------------------------------------------------- 50
8.1. Power-ON timing ------------------------------------------------------------------------------------- 50
8.2. Initial delivery state ---------------------------------------------------------------------------------- 50
8.3. Data retention and endurance ----------------------------------------------------------------------- 50
8.4. Latch up characteristics ----------------------------------------------------------------------------- 50
8.5. Absolute maximum ratings ------------------------------------------------------------------------- 51
8.6. Capacitance measurement conditions ------------------------------------------------------------- 51
8.7. DC characteristics ----------------------------------------------------------------------------------- 52
8.8. AC characteristics ----------------------------------------------------------------------------------- 53
9. ORDERING INFORMATION ------------------------------------------------------------------------- 55
10. PACKAGE INFORMATION --------------------------------------------------------------------------- 56
10.1. Package SOP8 150MIL ----------------------------------------------------------------------------- 56
10.2. Package SOP8 208MIL ----------------------------------------------------------------------------- 57
10.3. Package USON8 (4x3MM) ------------------------------------------------------------------------ 58
10.4. Package WSON8 (6x5MM) ------------------------------------------------------------------------ 59

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1. FEATURES
♦ 8M-bit Serial Flash ♦ Program/Erase Speed
- 1024K-byte - Page Program time: 0.4ms typical
- 256 bytes per programmable page - Sector Erase time: 60ms typical
- Block Erase time: 0.3/0.5s typical
♦ Standard, Dual, Quad SPI, QPI
- Chip Erase time: 7s typical
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ♦ Flexible Architecture
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Sector of 4K-byte
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Block of 32/64K-byte
- Erase/Program Suspend/Resume
♦ High Speed Clock Frequency
- 120MHz for fast read with 30PF load ♦ Low Power Consumption
- Dual I/O Data transfer up to 240Mbits/s - 20mA maximum active current
- Quad I/O Data transfer up to 480Mbits/s - 5μA maximum power down current
- QPI Mode Data transfer up to 480Mbits/s
♦ Advanced security Features
- Continuous Read With 8/16/32/64-byte Wrap
- 4*256-Byte Security Registers With OTP Lock
♦ Software/Hardware Write Protection
♦ Single Power Supply Voltage
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin - Full voltage range: 1.65~1.95V
- Top or Bottom, Sector or Block selection
♦ Minimum 100,000 Program/Erase Cycles

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2. GENERAL DESCRIPTION
The GD25LQ80 (8M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and
I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data
is transferred with speed of 480Mbits/s.

Connection Diagram

8-LEAD SOP 8-LEAD USON/WSON

Pin Description
Pin Name I/O Description

CS# I Chip Select Input

SO (IO1) I/O Data Output (Data Input Output 1)
WP# (IO2) I/O Write Protect Input (Data Input Output 2)
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
HOLD# (IO3) I/O Hold Input (Data Input Output 3)
VCC Power Supply

Block Diagram

WP#(IO2) Write Control

Logic

Status
Write Protect Logic

Register
and Row Decode

Flash
High Voltage
HOLD#(IO3) Memory
Generators
SPI
SCLK Command &
Control Logic Page Address
Latch/Counter
CS#

SI(IO0) Column Decode And

256-Byte Page Buffer
SO(IO1)
Byte Address
Latch/Counter

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3. MEMORY ORGANIZATION
GD25LQ80
Each device has Each block has Each sector has Each page has

1M 64/32K 4K 256 bytes

4K 256/128 16 - pages
256 16/8 - - sectors
16/32 - - - blocks

Uniform Block Sector Architecture

GD25LQ80 64K Bytes Block Sector Architecture
Block Sector Address range

255 0FF000H 0FFFFFH

15 ----- ----- -----
240 0F0000H 0F0FFFH
239 0EF000H 0EFFFFH
14 ----- ----- -----
224 0E0000H 0E0FFFH
----- ----- -----
----- ----- ----- -----
----- ----- -----
----- ----- -----
----- ----- ----- -----
----- ----- -----
47 02F000H 02FFFFH
2 ----- ----- -----
32 020000H 020FFFH
31 01F000H 01FFFFH
1 ----- ----- -----
16 010000H 010FFFH
15 00F000H 00FFFFH
0 ----- ----- -----
0 000000H 000FFFH

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4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25LQ80 feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ80 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ80 supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast
Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad
SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The GD25LQ80 supports Quad Peripheral Interface (QPI) operations only when the device is switched
ftom Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI
mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)”
commands are used to switch between these two modes. Upon power-up and after software reset using “Reset
(99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and then CS# must be at low.

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Figure 1. Hold Condition

CS#

SCLK

HOLD#

HOLD HOLD

5. DATA PROTECTION
The GD25LQ80 provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up / Write Disable (WRDI) / Write Status Register (WRSR)
- Page Program (PP) / Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table 1. GD25LQ80 Protected area size (CMP=0)
Status Register Content Memory Content
BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion
× × 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 15 0F0000H-0FFFFFH 64KB Upper 1/16
0 0 0 1 0 14 to 15 0E0000H-0FFFFFH 128KB Upper 1/8
0 0 0 1 1 12 to 15 0C0000H-0FFFFFH 256KB Upper 1/4
0 0 1 0 0 8 to 15 080000H-0FFFFFH 512KB Upper 1/2
0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/16
0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/8
0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/4
0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/2
0 × 1 0 1 0 to 15 000000H-0FFFFFH 1MB ALL
× × 1 1 × 0 to 15 000000H-0FFFFFH 1MB ALL
1 0 0 0 1 15 0FF000H-0FFFFFH 4KB Top Block
1 0 0 1 0 15 0FE000H-0FFFFFH 8KB Top Block
1 0 0 1 1 15 0FC000H-0FFFFFH 16KB Top Block
1 0 1 0 × 15 0F8000H-0FFFFFH 32KB Top Block
1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block
1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block
1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block
1 1 1 0 × 0 000000H-007FFFH 32KB Bottom Block

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Table 1a. GD25LQ80 Protected area size (CMP=1)

Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

× × 0 0 0 ALL 000000H-0FFFFFH 1M ALL
0 0 0 0 1 0 to 14 000000H-0EFFFFH 960KB Lower 15/16
0 0 0 1 0 0 to 13 000000H-0DFFFFH 896KB Lower 7/8
0 0 0 1 1 0 to 11 000000H-0BFFFFH 768KB Lower 3/4
0 0 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/2
0 1 0 0 1 1 to 15 010000H-0FFFFFH 960KB Upper 15/16
0 1 0 1 0 2 to 15 020000H-0FFFFFH 896KB Upper 7/8
0 1 0 1 1 4 to 15 040000H-0FFFFFH 768KB Upper 3/4
0 1 1 0 0 8 to 15 080000H-0FFFFFH 512KB Upper 1/2
0 × 1 0 1 NONE NONE NONE NONE
× × 1 1 × NONE NONE NONE NONE
1 0 0 0 1 0 to 15 000000H-0FEFFFH 1020KB Lower 255/256
1 0 0 1 0 0 to 15 000000H-0FDFFFH 1016KB Lower 127/128
1 0 0 1 1 0 to 15 000000H-0FBFFFH 1008KB Lower 63/64
1 0 1 0 × 0 to 15 000000H-0F7FFFH 992KB Lower 31/32
1 1 0 0 1 0 to 15 001000H-0FFFFFH 1020KB Upper 255/256
1 1 0 1 0 0 to 15 002000H-0FFFFFH 1016KB Upper 127/128
1 1 0 1 1 0 to 15 004000H-0FFFFFH 1008KB Upper 63/64
1 1 1 0 × 0 to 15 008000H-0FFFFFH 992KB Upper 31/32
Note:
1. X=don’t care
2. If any erase or program command specifies a memory that contains protected data portion, this command will
be ignored.

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6. STATUS REGISTER
S15 S14 S13 S12 S11 S10 S9 S8
SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1

S7 S6 S5 S4 S3 S2 S1 S0
SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP

The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when
WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory
area (as defined in Table1). becomes protected against Page Program (PP), Sector Erase (SE) and Block
Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block
Protect (BP4, BP3, BP2, BP1 and BP0) are set to “None protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply lock-
down or one time programmable protection.
SRP1 SRP0 #WP Status Register Description
The Status Register can be written to after a Write Enable
0 0 × Software Protected
command, WEL=1.(Default)
0 1 0 Hardware Protected WP# = 0, the Status Register locked and can not be written to.
WP# = 1, the Status Register is unlocked and can be written to
0 1 1 Hardware Unprotected
after a Write Enable command, WEL=1.
Power Supply Status Register is protected and can not be written to again until
1 0 ×
Lock-Down(1) the next Power-Down, Power-Up cycle.
1 1 × One Time Program(1) Status Register is permanently protected and can not be written to.
NOTE:
(1). When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

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QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1,
the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0,
the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become
read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-
BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
SUS1, SUS2 bits.
The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend
will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command
as well as a power-down, power-up cycle.

7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit
on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last
bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or
Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-
out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock
pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte
is not a full byte, nothing will happen and WEL will not be reset.

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Table 2. Commands (Standard/Dual/Quad SPI)

Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

Write Enable 06H
Write Disable 04H
Volatile SR Write Enable 50H
Read Status Register 05H (S7-S0) (continuous)
Read Status Register-1 35H (S15-S8) (continuous)
Write Status Register 01H (S7-S0) (S15-S8)
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Dual Output Fast Read 3BH A23-A16 A15-A8 A7-A0 dummy D7-D0 (1) (continuous)
A7-A0
Dual I/O Fast Read BBH A23-A8 (2) (D7-D0) (1) (continuous)
M7-M0 (2)
Quad Output Fast Read 6BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (3) (continuous)
A23-A0
Quad I/O Fast Read EBH dummy (5) (D7-D0) (3) (continuous)
M7-M0 (4)
A23-A0
Quad I/O Word Fast Read (7) E7H dummy (6) (D7-D0) (3) (continuous)
M7-M0 (4)
Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) Next byte
Quad Page Program 32H A23-A16 A15-A8 A7-A0 (D7-D0) (3)
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase (32K) 52H A23-A16 A15-A8 A7-A0
Block Erase (64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Enable QPI 38H
Enable Reset 66H
Reset 99H
Set Burst with Wrap 77H W6-W4
Program/Erase Suspend 75H
Program/Erase Resume 7AH
Deep Power-Down B9H
Release From Deep
Power-Down, ABH dummy dummy dummy (ID7-ID0) (continuous)
And Read Device ID
Release From Deep
ABH
Power-Down
Manufacturer/Device ID 90H dummy dummy 00H (M7- M0) (ID7-ID0) (continuous)
Manufacturer/Device ID A7-A0, (M7-M0)
92H A23-A8 (continuous)
by Dual I/O M[7:0] (ID7-ID0)
Manufacturer/Device ID A23-A0, (M7-M0)
94H dummy (continuous)
by Quad I/O M[7:0] (ID7-ID0)
Read Identification 9FH (M7-M0) (ID15- ID8) (ID7- ID0) (continuous)
Erase Security Registers (8) 44H A23-A16 A15-A8 A7-A0
Program Security Registers (8) 42H A23-A16 A15-A8 A7-A0 (D7-D0) (D7-D0)
Read Security Registers (8) 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0)

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Table 2a. Commands (QPI)

Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Clock Number (0, 1) (2, 3) (4, 5) (6, 7) (8, 9) (10, 11)
Write Enable 06H
Volatile SR Write Enable 50H
Write Disable 04H
Read Status Register 05H (S7-S0)
Read Status Register-1 35H (S15-S8)
Write Status Register 01H (S7-S0) (S15-S8)
Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) Next byte
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase (32K) 52H A23-A16 A15-A8 A7-A0
Block Erase (64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Program/Erase Suspend 75H
Program/Erase Resume 7AH
Deep Power-Down B9H
Set Read Parameters C0H P7-P0
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Burst Read with Wrap 0CH A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Quad I/O Fast Read EBH A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0)
Release From Deep Power-Down,
ABH dummy dummy dummy (ID7- ID0)
and Read Device ID
Manufacturer/Device ID 90H dummy dummy 00H (M7- M0) (ID7-ID0)
Read Identification 9FH (M7-M0) (ID15- ID8) (ID7- ID0)
Disable QPI FFH
Enable Reset 66H
Reset 99H
NOTE:
(1) Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(2) Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
(3) Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)

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(4) Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
(5) Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
(6) Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
(7) Fast Word Read Quad I/O Data: the lowest address bit must be 0.
(8) Security Registers Address:
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0=Byte Address;
Security Register1: A23-A16=00H, A15-A8=10H, A7-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A8=20H, A7-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A8=30H, A7-A0=Byte Address.
(9) QPI Command, Address, Data input/output format:
CLK #0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3

Table of ID Definitions:
GD25LQ80
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH C8 60 14
90H C8 13
ABH 13

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7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN)
command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Figure 2. Write Enable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
06H
High-Z
SO

Figure 2a. Write Enable Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
06H
IO0

IO1

IO2

IO3

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7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands.
Figure 3. Write Disable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
04H
High-Z
SO

Figure 3a. Write Disable Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
04H
IO0

IO1

IO2

IO3

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7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical non-
volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable
for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
Figure 4. Write Enable for Volatile Status Register Sequence Diagram

CS#

SCLK 0 1 2 3 4 5 6 7

Command(50H)

SI

SO High-Z

Figure 4a. Write Enable for Volatile Status Register Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
50H
IO0

IO1

IO2

IO3

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7.4. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will
output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 5. Read Status Register Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI
05H or 35H
S7~S0 or S15~S8 out S7~S0 or S15~S8 out
SO High-Z
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

Figure 5a. Read Status Register Sequence Diagram (QPI)

CS#
0 1 2 3 4 5
SCLK
Command
05H or 35H

IO0 4 0 4 0 4

IO1 5 1 5 1 5

IO2 6 2 6 2 6

IO3 7 3 7 3 7

S7-S0 or S15-S8 out

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7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S14, S10, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the
CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Ta-
ble1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect
(SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1
and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The
Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command Status Register in

SI 01H 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
MSB High-Z
SO

Figure 6a. Write Status Register Sequence Diagram (QPI)

CS#
0 1 2 3 4 5
SCLK
Command
01H

IO0 4 0 12 8

IO1 5 1 13 9

IO2 6 2 14 10

IO3 7 3 15 11

Status Register in

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7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address

SI
03H 23 22 21 3 2 1 0
MSB Data Out1 Data Out2
SO High-Z
7 6 5 4 3 2 1 0
MSB

7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram

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Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is
configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the
Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8.
Figure 8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCLK
Command IOs switch from
0BH
Dummy* Input to output
A23-16 A15-8 A7-0
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

7.8. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Figure 9. Dual Output Fast Read Sequence Diagram

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7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle
from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out.
Figure 10. Quad Output Fast Read Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI(IO0) 6BH 23 22 21 3 2 1 0
SO(IO1) High-Z
WP#(IO2) High-Z
HOLD#(IO3) High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0) 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

7.10. Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)
=(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the
BBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode”
bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to
normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal
command.

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Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4

Figure 11a. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0 ))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4

7.11. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be
set to enable for the Quad I/O Fast read command.

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Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)
= (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the
EBH command code. The command sequence is shown in followed Figure12a. If the “Continuous Read Mode”
bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning
to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing
normal command.
Figure 12. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) EBH 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

Figure 12a. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or
disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.

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The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
Quad I/O Fast Read (EBH) in QPI mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number
of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range
application with different needs for either maximum Fast Read frequency or minimum data access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either
4/6/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous
Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is
not available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data length
wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used.
Figure 12b. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0) QPI)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCLK
Command IOs switch from
EBH Input to output
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6
*"Set Read Parameters"
IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Command (C0H) can
set the number of
A23-16 A15-8 A7-0 M7-0* Byte1 Byte2 Byte3 dummy clocks

7.12. Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure13.
The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to
enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =
(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require
the E7H command code. The command sequence is shown in followed Figure13. If the “Continuous Read
Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to

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normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing
normal command.
Figure 13. Quad I/O Word Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) E7H 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Figure 13a. Quad I/O Word Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable
or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.

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7.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI
mode.
The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send
24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high.
W4=0 W4=1 (default)
W6, W5
Wrap Around Wrap Length Wrap Around Wrap Length
0, 0 Yes 8-byte No N/A
0, 1 Yes 16-byte No N/A
1, 0 Yes 32-byte No N/A
1, 1 Yes 64-byte No N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and
“Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within
any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be
used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W4 in Standard
SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command.
Figure 14. Set Burst with Wrap Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI(IO0) 77H x x x x x x 4 x

SO(IO1) x x x x x x 5 x

WP#(IO2) x x x x x x 6 x

HOLD#(IO3) x x x x x x x x
W6-W4

7.14. Page Program (PP) (02H)

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Program

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command → 3-byte address on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is
shown in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes
are sent to device, they are correctly programmed at the requested addresses without having any effects on the
other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched
in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
Figure 15. Page Program Sequence Diagram

Figure 15a. Page Program Sequence Diagram (QPI)

CS#
516
517
518
519

0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCLK
Command
02H A23-16 A15-8 A7-0 Byte1 Byte2 Byte3 Byte255 Byte256
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3

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7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2 and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE = 1). A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the
Page Program command. The Quad Page Program command is entered by driving CS# Iow, followed by the
command code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in, otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
Figure 16. Quad Page Program Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Byte1 Byte2

SI(IO0) 32H 23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
MSB
SO(IO1) 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3

CS#
537

539
540

542
536

538

541

543

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Byte11 Byte12 Byte253 Byte256

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

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7.16. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)
command is entered by driving CS# low, followed by the command code, and 3-byte address on SI. Any address
inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire
duration of the sequence.
The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on
SI → CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon
as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector
Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase
(SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see
Table1 & Table1a) is not executed.
Figure 17. Sector Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
20H 23 22 2 1 0
MSB

Figure 17a. Sector Erase Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
20H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

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7.17. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address on SI→ CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed.
Figure 18. 32KB Block Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
52H 23 22 2 1 0
MSB

Figure 18a. 32KB Block Erase Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
52H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

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7.18. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte
address on SI → CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed.
Figure 19. 64KB Block Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
D8H 23 22 2 1 0
MSB

Figure 19a. 64KB Block Erase Sequence Diagram (QPI)

CS#

0 1 2 3 4 5 6 7
SCLK

Command
D8H A23-16 A15-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

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7.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code
has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-
timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all
Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are set to “None protected”. The Chip Erase (CE) command
is ignored if one or more sectors are protected.
Figure 20. Chip Erase Sequence Diagram
CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
60H or C7H

Figure 20a. Chip Erase Sequence Diagram (QPI)

CS#
0 1
SCLK
Instruction
C7H/60H
IO0

IO1

IO2

IO3

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7.20. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can
only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep
Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#
goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-
Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 21. Deep Power-Down Sequence Diagram
CS#

0 1 2 3 4 5 6 7 tDP
SCLK

Command Stand-by mode Deep Power-down mode

SI
B9H

Figure 21a. Deep Power-Down Sequence Diagram (QPI)

CS#
tDP
0 1
SCLK

Command
B9H
IO0

IO1

IO2

IO3

Stand-by mode Deep Power-down mode

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7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID is a multi-purpose command. It can be used to release the
device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting
the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take
the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23.
The Device ID value for the GD25LQ80 is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the
same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high
for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal
operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued
while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not
have any effects on the current cycle.
Figure 22. Release Power-Down Sequence Diagram
CS#

0 1 2 3 4 5 6 7 t RES1
SCLK

Command
SI
ABH

Deep Power-down mode Stand-by mode

Figure 22a. Release Power-Down Sequence Diagram (QPI)

CS#
tRES1
0 1
SCLK

Command
ABH
IO0

IO1

IO2

IO3

Deep Power-down mode Stand-by mode

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Figure 23. Release Power-Down and Read Device ID Sequence Diagram

Figure 23a. Release Power-Down and Read Device ID Sequence Diagram (QPI)

CS#
tRES2
0 1 2 3 4 5 6 7 8
SCLK

Command 3 Dummy Bytes IOs switch from

ABH Input to Output
IO0 4 0

IO1 5 1

IO2 6 2

IO3 7 3
Device
ID
Deep Power-down mode Stand-by mode

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7.22. Read Manufacture ID/Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 24. Read Manufacture ID/Device ID Sequence Diagram

Figure 24a. Read Manufacture ID/Device ID Sequence Diagram (QPI)

CS#

0 1 2 3 4 5 6 7 8 9 10
SCLK

Command IOs switch from

A7-0
90H A23-16 A15-8 (00H) Input to Output
IO0 20 16 12 8 4 0 4 0 4 0

IO1 21 17 13 9 5 1 5 1 5 1

IO2 22 18 14 10 6 2 6 2 6 2

IO3 23 19 15 11 7 3 7 3 7 3
MID Device
ID

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7.23. Read Manufacture ID/Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 25. Read Manufacture ID/Device ID Dual I/O Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) 92H 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
MFR ID Device ID MFR ID Device ID MFR ID Device ID
(Repeat) (Repeat) (Repeat) (Repeat)

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7.24. Read Manufacture ID/Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 26. Read Manufacture ID/Device ID Quad I/O Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) 94H 4 0 4 0 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID

CS#
24 25 26 27 28 29 30 31
SCLK

SI(IO0) 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3
MFR ID DID MFR ID DID
(Repeat)(Repeat)(Repeat)(Repeat)

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7.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by
two bytes of device identification. The device identification indicates the memory type in the first byte, and the
memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase
or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read
Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure27. The Read Identification (RDID) command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute commands.
Figure 27. Read Identification ID Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI 9FH
Manufacturer ID
SO 7 6 5 4 3 2 1 0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI

Memory Type ID15-ID8 Capacity ID7-ID0

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

Figure 27a. Read Identification ID Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6
SCLK
Command IOs switch from
9FH Input to Output

IO0 4 0 12 8 4 0

IO1 5 1 13 9 5 1

IO2 6 2 14 10 6 2

IO3 7 3 15 11 7 3

MID ID15-8 ID7-0

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7.26. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block
erase operation and then read data from any other sector or block. The Write Status Register command (01H)
and Erase Security Registers (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program
command are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only during the page
program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to
suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-
going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the
device. The WIP bit will be cleared form 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1
immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and
release the suspend state. The command sequence is show in Figure28.
Figure 28. Program/Erase Suspend Sequence Diagram

CS#

0 1 2 3 4 5 6 7 tSUS
SCLK

Command
SI
75H
High-Z
SO
Accept read command

Figure 28a. Program/Erase Suspend Sequence Diagram (QPI)

CS#
tSUS
0 1
SCLK

Command
75H
IO0

IO1

IO2

IO3

Accept Read

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7.27. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation
after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if
the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register
will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or
Block will complete the erase operation or the page will complete the program operation. The Program/Erase
Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in
Figure29.
Figure 29. Program/Erase Resume Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
7AH

SO Resume Erase/Program

Figure 29a. Program/Erase Resume Sequence Diagram (QPI)

CS#

0 1
SCLK

Command
7AH
IO0

IO1

IO2

IO3

Resume previously suspended

program or Erase

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7.28. Erase Security Registers (44H)
The GD25LQ80 provides three 256-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command
→ CS# goes high. The command sequence is shown in Figure30. CS# must be driven high after the eighth bit
of the command code has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP
protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the
Erase Security Registers command will be ignored.
Address A23-16 A15-12 A11-8 A7-0
Security Register #1 00H 0001 0000 Do not care
Security Register #2 00H 0010 0000 Do not care
Security Register #3 00H 0011 0000 Do not care
Figure 30. Erase Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI 44H 23 22 2 1 0
MSB

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7.29. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.

Address A23-16 A15-12 A11-8 A7-0

Security Register #1 00H 0001 0000 Byte Address
Security Register #2 00H 0010 0000 Byte Address
Security Register #3 00H 0011 0000 Byte Address
Figure 31. Program Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Data Byte 1

SI
42H 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#
2073

2075
2076

2078
2072

2074

2077

2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

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7.30. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the
last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high.
Address A23-16 A15-12 A11-8 A7-0
Security Register #0 00H 0000 0000 Byte Address
Security Register #1 00H 0001 0000 Byte Address
Security Register #2 00H 0010 0000 Byte Address
Security Register #3 00H 0011 0000 Byte Address
Figure 32. Read Security Registers command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
48H 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

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7.31. Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy
clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and
to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap
Length” is set by W5-4 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged
when the device is switched from Standard SPI mode to QPI mode.
P5-P4 Dummy Clocks Maximum Read Freq. P1-P0 Wrap Length
00 4 80MHz 00 8-byte
01 4 80MHz 01 16-byte
10 6 120MHz 10 32-byte
11 8 120MHz 11 64-byte

Figure 33. Set Read Parameters command Sequence Diagram

CS#
0 1 2 3
SCLK
Command Read
C0H Parameters

IO0 P4 P0

IO1 P5 P1

IO2 P6 P2

IO3 P7 P3

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7.32. Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with
“Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except
the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once
the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the
“Set Read Parameters (C0H)” command.
Figure 34. Burst Read with Wrap command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCLK
Command IOs switch from
0CH Input to output
IO0 20 16 12 8 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7
A23-16 A15-8 A7-0
Dummy* Byte1 Byte2 Byte3

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

7.33. Enable QPI (38H)

The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can
switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In
order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first,
and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will
be ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode,
the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain
unchanged.
Figure 35. Enable QPI mode command Sequence Diagram
CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
38H

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7.34. Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must
be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure 36. Disable QPI mode command Sequence Diagram

CS#
0 1
SCLK
Command
FFH
IO0

IO1

IO2

IO3

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7.35. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return
to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write
Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read
Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset
(99H)”command sequence as follow: CS# goes low → Sending Enable Reset command → CS# goes high
→ CS# goes low → Sending Reset command → CS# goes high. Once the Reset command is accepted by the
device, the device will take approximately tRST=30µs to reset. During this period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit
in Status Register before issuing the Reset command sequence.
Figure 37. Enable Reset and Reset command Sequence Diagram
Figure 38. Enable Reset and Reset command Sequence Diagram

7.34. ReadFigure
Serial Flash
37a. Discoverable
Enable Reset and ResetParameter (5AH) Diagram (QPI)
command Sequence

CS#
0 1 0 1
SCLK
Command Command
66H 99H
IO0

IO1

IO2

IO3

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8. ELECTRICAL CHARACTERISTICS
8.1. Power-On Timing

Figure 38. Power-On Timing Sequence Diagram

Table 3. Power-Up Timing and Write Inhibit Threshold

Symbol Parameter Min Max Unit
tVSL VCC(min) To CS# Low 10 us
tPUW Time Delay From VCC(min) To Write Instruction 1 10 ms
VWI Write Inhibit Voltage VCC(min) 1 1.4 V

8.2. Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status
Register contains 00H (all Status Register bits are 0).

8.3. Data Retention and Endurance

Parameter Test Condition Min Unit

150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
Erase/Program Endurance -40 to 85°C 100K Cycles

8.4. Latch Up Characteristics

Parameter Min Max

Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V
VCC Current -100mA 100mA

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8.5. Absolute Maximum Ratings

Parameter Value Unit

Ambient Operating Temperature -40 to 85 °C
Storage Temperature -55 to 125 °C
Output Short Circuit Current 200 mA
Applied Input/Output Voltage -0.6 to VCC+0.4 V
VCC -0.6 to VCC+ 0.4 V

Maximum Negative
MaximumOvershoot
Negative
Waveform
Overshoot Waveform Maximum Positive
MaximumOvershoot
Positive
Waveform
Overshoot Waveform

2.35V 2.35V
20ns 20ns
0V 0V 1.95V 1.95V
20ns 20ns
-0.6V -0.6V

8.6. Capacitance Measurement Conditions

Symbol Parameter Min Typ Max Unit Conditions

CIN Input Capacitance 6 pF VIN=0V
COUT Output Capacitance 8 pF VOUT=0V
Load Capacitance 30 pF
Input Rise And Fall time 5 ns
CL Input Pulse Voltage 0.2VCC to 0.8VCC V
Input Timing Reference Voltage 0.3VCC to 0.7VCC V
Output Timing Reference Voltage 0.5VCC V

Figure 39. Input Test Waveform and Measurement Level

Input timing reference level Output timing reference level

0.8VCC 0.7VCC
AC Measurement Level 0.5VCC
0.2VCC 0.3VCC

Note: Input pulse rise and fall time ara<5ns

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8.7. DC Characteristics
(T= -40°C~85°C, VCC=1.65~1.95V)
Symbol Parameter Test Condition Min. Typ. Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, VIN=VCC or VSS 20 40 μA
ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS 1 5 μA
CLK=0.1VCC/0.9VCC at 120MHz,
15 20 mA
Q=Open(*1,*2,*4 I/O)
ICC3 Operating Current (Read)
CLK=0.1VCC/0.9VCC at 80MHz,
13 18 mA
Q=Open(*1,*2,*4 I/O)
ICC4 Operating Current (PP) CS#=VCC 25 mA
ICC5 Operating Current (WRSR) CS#=VCC 25 mA
ICC6 Operating Current (SE) CS#=VCC 25 mA
ICC7 Operating Current (BE) CS#=VCC 25 mA
VIL Input Low Voltage -0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL=100μA 0.2 V
VOH Output High Voltage IOH=-100μA VCC-0.2 V

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8.8. AC Characteristics
(T= -40°C~85°C, VCC=1.65~1.95V, CL=30pf)
Symbol Parameter Min. Typ. Max. Unit.
fC Serial Clock Frequency For: 0BH, 3BH, BBH, 6BH, EBH, E7H DC. 120 MHz
Serial Clock Frequency For:
fC DC. 80/120/120 MHz
0BH, 0CH, EBH with QPI mode (4 & 6 & 8 Dummy clocks)
fR Serial Clock Frequency For: Read(03H) DC. 80 MHz
tCLH Serial Clock High Time 4 ns
tCLL Serial Clock Low Time 4 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns
tSLCH CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL CS# High Time (Read/Write) 20 ns
tSHQZ Output Disable Time 6 ns
tCLQX Output Hold Time 1.2 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time 2 ns
tHLCH Hold# Low Setup Time (Relative to Clock) 5 ns
tHHCH Hold# High Setup Time (Relative to Clock) 5 ns
tCHHL Hold# High Hold Time (Relative to Clock) 5 ns
tCHHH Hold# Low Hold Time (Relative to Clock) 5 ns
tHLQZ Hold# Low To High-Z Output 6 ns
tHHQX Hold# Low To Low-Z Output 6 ns
tCLQV Clock Low To Output Valid 7 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 20 μs
tRES1 CS# High To Standby Mode Without Electronic Signature Read 20 μs
tRES2 CS# High To Standby Mode With Electronic Signature Read 20 μs
tSUS CS# High To Next Command After Suspend 20 μs
tW Write Status Register Cycle Time 5 15 ms
tPP Page Programming Time 0.4 2.4 ms
tSE Sector Erase Time 60 500 ms
tBE Block Erase Time(32K Bytes/64K Bytes) 0.3/0.5 1.0/1.2 s
tCE Chip Erase Time(GD25LQ80) 7 15 s

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Figure 40. Serial Input Timing
tSHSL
CS#

tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL
tCHDX tCLCH

SI MSB LSB

SO High-Z

Figure 41. Output Timing

CS#
tCLH tSHQZ
SCLK
tCLQV tCLQV tCLL
tCLQX tCLQX
SO LSB

SI
Least significant address bit (LIB) in

Figure 42. Hold Timing

CS#

tCHHL tHLCH tHHCH

SCLK

tCHHH
tHLQZ tHHQX
SO

HOLD#

SI do not care during HOLD operation.

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9. ORDERING INFORMATION

GD 25 LQ 80 x I G x

Packing Type
Y: Tray
R: Tape & Reel

Green Code
G: Pb Free & Halogen Free Green Package

Temperature Range
I: Industrial(-40°C to +85°C)

Package Type
T: SOP8 150mil
S: SOP8 208mil
N: USON8 (4×3mm)
W: WSON8 (6×5mm)

Density
80: 8Mb

Series
LQ: 1.8V, 4KB Uniform Sector

Product Family
25: SPI Interface Flash

Rev.1.0
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10. PACKAGE INFORMATION

10.1. Package SOP8 150MIL

8 5 �

E1 E

L1
L
1 4
C

A2 A

b A1
e
Seating plane

0.10

Dimensions
Symbol
A A1 A2 b c D E E1 e L L1 θ ɑ ß
Unit
Min 1.35 0.05 1.35 0.31 0.15 4.77 5.80 3.80 - 0.40 0.85 0° 6° 11°
mm Nom - - - - - 4.90 6.00 3.90 1.27 - 1.06 - 7° 12°
Max 1.75 0.25 1.55 0.51 0.25 5.03 6.20 4.00 - 0.90 1.27 8° 8° 13°
Min 0.053 0.002 0.053 0.012 0.006 0.188 0.228 0.149 - 0.016 0.033 0° 6° 11°
Inch Nom - - - 0.016 - 0.193 0.236 0.154 0.050 0 0.042 - 7° 12°
Max 0.069 0.010 0.061 0.020 0.010 0.198 0.244 0.158 - 0.035 0.050 8° 8° 13°
Note: Both package length and width do not include mold flash.

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10.2. Package SOP8 208MIL

8 5 �

E1 E

L1
L
1 4
C
D

A2 A

b A1
e

Dimensions
Symbol
A A1 A2 b C D E E1 e L L1 θ
Unit
Min - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0°
mm Nom - 0.15 1.80 0.41 0.21 5.23 7.90 5.28 1.27 0.67 1.31 5°
Max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 - 0.85 1.41 8°
Min - 0.002 0.067 0.012 0.007 0.202 0.303 0.204 - 0.020 0.048 0°
Inch Nom - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 5°
Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 - 0.033 0.056 8°
Note: Both package length and width do not include mold flash.

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10.3. Package USON8 (4×3mm)

D
A2

A1
A
Top View Side View
L D1
1
b
E1

E1

Bottom View

Dimensions
Symbol
A A1 A2 b D D1 E E1 E2 e y L
Unit
Min 0.50 0.00 - 0.25 2.90 0.10 3.90 0.70 - 0.00 0.50
mm Nom 0.55 - 0.15 0.30 3.00 0.25 4.00 0.80 0.80BSC 0.80BSC - 0.60
Max 0.60 0.05 - 0.35 3.10 0.40 4.10 0.90 - 0.08 0.70
Min 0.020 0.000 - 0.010 0.114 0.004 0.153 0.027 - 0.000 0.020
Inch Nom 0.022 - 0.006 0.012 0.118 0.010 0.157 0.031 0.031BSC 0.031BSC - 0.024
Max 0.024 0.002 - 0.014 0.122 0.016 0.161 0.035 - 0.003 0.028
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin), so both
Floating and connecting GND of exposed pad are also available.

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10.4 Package WSON8 (6×5mm)

D
A2

A1
A
Top View Side View
L D1

b 1

e E1

Bottom View

Dimensions
Symbol
A A1 A2 b D D1 E E1 e y L
Unit
Min 0.70 - 0.19 0.35 5.90 3.25 4.90 3.85 - 0.00 0.50
mm Nom 0.75 - 0.22 0.42 6.00 3.37 5.00 3.97 1.27 BSC 0.04 0.60
Max 0.80 0.05 0.25 0.48 6.10 3.50 5.10 4.10 - 0.08 0.75
Min 0.028 - 0.007 0.014 0.232 0.128 0.193 0.151 - 0.000 0.020
Inch Nom 0.030 - 0.009 0.016 0.236 0.133 0.197 0.156 0.05 BSC 0.001 0.024
Max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin), so both
Floating and connecting GND of exposed pad are also available.

59 - 59 Rev.1.0