®

Overhead Transparencies for

Virtuoso Analog Design

®

Environment
Lecture Manual
Version 5.1.41

Education Services
October 11, 2004
 ®

1 Introduction to the Analog Design Environment,

Version 5.1.41

Module 1

October 11, 2004

Topics in this Module
■ Course objectives

■ Course outline

■ Class schedule

■ Getting help, technical support, and documentation

■ What’s new in 5.1.41

■ The Design Framework II Design Environment

■ Accessing design tools

■ Creating a library

■ Creating cells and cell views

■ Schematic capture

■ Analog simulation

■ Analyses

■ Summary

Introduction to the Analog Design Environment, Version 5.1.41 1-3

Course Objectives
■ Learn how to create schematics, symbols, and a design hierarchy

■ Set up and run analog simulations

■ Analyze simulation results

■ Evaluate sensitivities and mismatches to improve circuit performance.

■ Run Corners, Monte Carlo, and Optimization tools to improve yield

■ Create and use OCEAN scripts and SKILL to set up and run simulations

■ Understand the Component Description Format (CDF)

■ Create configurations with the Hierarchy Editor (HED)

■ Use subcircuits and macromodels

■ Run the parasitic simulation flow

■ Use advanced tools to solve special problems

Introduction to the Analog Design Environment, Version 5.1.41 1-5

Course Outline

1 Introduction to the Analog Design 11 Component Description Format (CDF)

Environment, Version 5.1.41
12 Macromodels, Subcircuits, and Inline
2 Schematic Entry Subcircuits
3 Analog Simulation 13 Inherited Connections
4 Simulation Results Display Tools 14 The Hierarchy Editor
5 Analyzing Simulation Results 15 Overview of Parasitic Simulation
6 SKILL and OCEAN 16 Assura Parasitic Simulation Flow
7 Parametric Analysis Appendixes:
A Diva Parasitic Simulation Flow
8 Corners Analysis B Match Analysis, dcmatch
9 Monte Carlo Analysis C Advanced Topics in ADE

10 Optimization Analysis

Introduction to the Analog Design Environment, Version 5.1.41 1-7

Class Schedule

Day 1 Day 3
1 Introduction to the Analog Design 10 Optimization Analysis
Environment, Version 5.1.41 11 Component Description Format (CDF)
2 Schematic Entry 12 Macromodels, Subcircuits, and Inline
3 Analog Simulation Subcircuits
4 Simulation Results Display Tools
Day 2 Day 4
5 Analyzing Simulation Results 13 Inherited Connections
6 SKILL and OCEAN 14 The Hierarchy Editor
7 Parametric Analysis 15 Overview of Parasitic Simulation
8 Corners Analysis 16 Assura Parasitic Simulation Flow
9 Monte Carlo Analysis Class Evaluations

Introduction to the Analog Design Environment, Version 5.1.41 1-9

Getting Help
You can get help with Cadence software from the following sources:
■ Help button on forms and windows

■ Cadence online documentation (CDSDoc)

■ Education Services training manuals

■ SourceLink® online customer support

■ Customer Response Center (CRC)

Introduction to the Analog Design Environment, Version 5.1.41 1-11

What’s New in 5.1.41
■ Spectre device checking interface

■ WaveScan integration

■ UltraSim integration

■ Third-party OASIS integration

■ Parasitic resimulation flow

Introduction to the Analog Design Environment, Version 5.1.41 1-13

Overview of Virtuoso Analog Design Environment
The Virtuoso Analog Design Environment is a software tool set within Design
Framework II that is used to set up and run analog simulations. The Virtuoso
Analog Design Environment also accesses and views the simulation results.
The Virtuoso Analog Design Environment allows you to:
■ Choose the simulator host

■ Choose the type of analysis: ac, dc, transient, parametric, sensitivity, etc.

■ Set design variables: Vdd, frequency, Cout, etc.

■ Append model files and include files

■ Netlist and run simulations

■ Quickly alter the simulation setup and rerun the simulation

■ Plot simulation results in the Waveform display tool

■ Evaluate simulation results using waveform expressions

■ Run multiple simulation tools: Corners, Monte Carlo, Optimizer, etc.

■ Automatically set up, save, and run OCEAN scripts

Introduction to the Analog Design Environment, Version 5.1.41 1-15

Design System Initialization Files
icfb &
Login icms &
msfb &

Operating
System Window Design
Environment System Framework II
( IC - 5.1.41 )
Analog Design Environment,
Window schematic capture tools,
Manager layout, and verification
software.

.cshrc .cdsenv
.login .cdsinit
cds.lib

Introduction to the Analog Design Environment, Version 5.1.41 1-17

Overview of the Design Framework II Environment

Schematic Setup
Capture & Update Simulation Control,
Symbol Editor Design Simulation Results,
Waveforms, and
Expressions
Schematic Editor
2
Window Edit Schematic
Component
Description

The Framework
Framework
ToolsMask
Layout Layout
3
Window Edit Mask Layout
Layout
Verification
R:

Parasitic
Simulation and
Backannotation 5
Physical
Design

Introduction to the Analog Design Environment, Version 5.1.41 1-19

Advantages of Using Design Framework II
■ Common software environment for using schematic capture, simulation,
layout, and design verification
■ Easy-to-learn, consistent user interface

■ Similar appearance between most forms and windows

■ Communication between software tools within the DFII environment

■ Tool windows remain open while running other applications

■ Data can be “back annotated”

❏ From layout to schematic
❏ From simulation to schematic
❏ From simulation to layout

■ Applications may be customized or automated using SKILL or the OCEAN

command language

Introduction to the Analog Design Environment, Version 5.1.41 1-21

The Command Interpreter Window (CIW)
Enter: icfb &, icms &, or msfb &

Pull down menus

Output
Area

Text Field (Enter SKILL Commands)

Prompt Line Mouse Button Cues

Introduction to the Analog Design Environment, Version 5.1.41 1-23

Using a Form
A Sample Form
OK Cancel Defaults Apply Help

Template File Load Save

Library Browser
Run Directory .

Library Name classLib

Top Cell Name

View Name mux2

Output File layout

Output Stream DB ASCII Dump

Show Messages Text entry
area
Library Version 5.1

Toggle Button Radio Button

Cyclic Field

Introduction to the Analog Design Environment, Version 5.1.41 1-25

Initializing the Design Framework II Environment

The Design Framework II software reads your .cdsinit file at startup to set up your
environment. The .cdsinit file:
■ Sets user-defined bindkeys when the Design Framework II environment is
started.
■ Redefines system-wide defaults.

■ Contains SKILL commands.

The search order for the .cdsinit file is:

■ <install_dir>/tools/dfII/local

■ the current directory

■ the home directory

Here is the path to a sample .cdsinit file:

<install_dir>/tools/dfII/samples/artist/cdsinit

Introduction to the Analog Design Environment, Version 5.1.41 1-27

IC Design Flow, Front to Back
System Level Technology Component Circuit
Design: Selection: Level Design: Analysis:
Process selection, Circuit topology,
Product definition, Circuit Simulation,
Device Models, Device geometry,
System specifications, Design Corrections,
Layer definition, Component values,
Interface definitions, Optimization,
Layout rules, Symbol generation
Behavioral simulations Verify Corners
Primitives
Library Manager Library Manager Library Manager Library Manager
Schematic Capture Technology Files Schematic Capture Schematic Capture
AHDL ADE
Verilog-A Circuit Simulation
ADE
Circuit Simulation

System Physical Back End

Integration: Design: Verification: Design
Layout, Data
Schematic Hierarchy, Layout Hierarchy LVS, Out
Mixed-Level Simulations DRC,
Parasitic Extraction,
Parasitic Simulation
Library Manager Library Manager Library Manager
Hierarchy Editor Diva or Assura Diva or Assura
ADE Hierarchy Editor
Verilog-A ADE
Circuit Simulation Circuit Simulation

Introduction to the Analog Design Environment, Version 5.1.41 1-29

The Library Manager
The Library Manager is a graphical data management tool.

Object
Sensitive
Menus

A library in
the cds.lib file

Tools—Library Manager

Introduction to the Analog Design Environment, Version 5.1.41 1-31

The Library Structure

Library Training

Cell VCO

Symbol View

Tools—Library Manager...
Schematic View

Introduction to the Analog Design Environment, Version 5.1.41 1-33

Creating a New Library
In the CIW or the Library Manager, select File—New—Library.

■ Specify the library name and path.

■ Specify the design manager to use.

■ For Physical Design and Verification, specify the ASCII technology file or
technology file library to be attached to the new library.
The new library is entered into the cds.lib file.
Introduction to the Analog Design Environment, Version 5.1.41 1-35
Shared Technology Library
This example shows several libraries sharing the same technology file library.

Technology cellTechLib
Library

drc.rul techfile.cds

compare.rul
symbolic devices

extract.rul

Pcells master
Design Library Design Library

mux2
ntransistor ptransistor

layout layout symbol layout

Introduction to the Analog Design Environment, Version 5.1.41 1-37

Technology File Stored in the Design Library
This example shows a technology file being stored inside a design library and not
being shared with other libraries.

Design Library

master

techfile.cds mux2
drc.rul

extract.rul

compare.rul symbolic devices symbol layout

Introduction to the Analog Design Environment, Version 5.1.41 1-39

Design Data Management
■ Version control

■ Configuration management

■ Access control

■ Release process

Introduction to the Analog Design Environment, Version 5.1.41 1-41

Overview of Schematic Entry Flow
Open Design

Add Component Instances

Add or Edit Component Parameters

Add Pins

Add and Name Wires

Check Schematic

Save

Introduction to the Analog Design Environment, Version 5.1.41 1-43

Overview of Circuit Simulation

Design Hierarchy or Test Circuit

(schematic view)

Stimulus: Transistor Level Load

analogLib: vpulse Schematic analogLib: cap
- or - (symbol view) res
stimulus file Schematic of - or -
- or - amplifier
schematic schematic

Virtuoso ADE Circuit Simulator

Setup simulator Spectre (used in this class),
User Modify Design Variables Spectre/Verilog,
Inputs Choose Analyses cdsSpice,
Select Model Files etc.
Netlist and Run Simulation
Plot Simulation Results
View waveforms OUT: IN: Netlist, temperature, etc.
Evaluate expressions
IN: OUT:.psf,.log, etc.

Introduction to the Analog Design Environment, Version 5.1.41 1-45

Types of Circuit Simulation Analyses

Circuit Simulation Software

Spectre

Single Point Single Sweep Multiple Sweep

dc ac parametric

dcop transient corners

sensitivity dc sweep Monte Carlo

mismatch ac sweep optimization

RF Analyses noise yield

RF Spectral Analysis

Introduction to the Analog Design Environment, Version 5.1.41 1-47

Summary
In this module we discussed:
■ Course objectives

■ Course outline

■ Class schedule

■ Getting Help, including CDSDoc

■ Design Framework II environment

■ Using forms

■ Creating a library

■ Creating cells and cell views

■ Overview of schematic capture

■ Overview of circuit simulation in the Virtuoso Analog Design Environment

■ Types of simulation analyses

Introduction to the Analog Design Environment, Version 5.1.41 1-49

Labs
Lab 1-1 Getting Started

Lab 1-2 Top-Down System Modeling

Introduction to the Analog Design Environment, Version 5.1.41 1-51

 ®

2 Schematic Entry

Module 2

October 11, 2004

Topics in this Module
■ The schematic capture flow

■ Creating a schematic view

■ Contents of a schematic

■ Adding component instances

■ Adding pins

■ Adding wires

■ Editing object properties

■ Using Accelerator keys (also known as bindkeys) and schematic window

icons
■ Checking the schematic for errors

■ Symbol generation and editing

■ Using a design hierarchy

Schematic Entry 2-3

Schematic Entry Flow

Open Design

Add Component Instances

Add or Edit Component Parameters

Add Pins

Add and Name Wires

Check Schematic

Save

Schematic Entry 2-5

Contents of a Schematic

Wire
Tap

Component Instance

Pin

Wire Label Instance Label

Schematic Entry 2-7

Creating a New Cellview
In the CIW or Library Manager, select File—New—Cellview.

Default View Name

subject to override.

Select:
Composer-Schematic

■ Specify the Library Name, Cell Name, View Name, and Tool to use. The
path to the cds.lib file will appear in the form and is not editable.
■ Modify the Tool field to create a layout, verilog, symbol, schematic, vhdl, or
ahdl view.
For an ADE schematic, select Composer-Schematic from the Tool cyclic field

Schematic Entry 2-9

Adding Component Instances
Select Add—Instance or press the i key to display the Add Instance form.
■ Attach multipliers to values. Enter 1k (not 1 k) so that k is not mistaken as a
variable.
■ Parameter units, such as ohms, are implicit.

Use these buttons

while placing
components to
control orientation.

Schematic Entry 2-11

Updating Design Objects
■ Select Edit—Properties—Objects or bindkey q to start the form.
The Next and Previous buttons highlight single objects in a selected set.
■ Use Design—Renumber Instances to renumber instances in a design.

Design—Renumber Instances
Edit—Properties—Objects

Schematic Entry 2-13

Adding Sources and Ground
Sources, taps, and grounds are instances of cells.
Sample source cells are in the analogLib library.
■ Choose from independent, dependent, and piece-wise linear (PWL)
sources.
■ Choose tap and ground cells, which are used to establish global nets.

■ An instance of the cell gnd is required in the design for DC convergence.

vcca vcc
vcc vcca

vdc + +
gnd gnda
gnda
gnda gnda gnd

Schematic Entry 2-15

Pins
Pins have a user-defined Name and a Direction (input, output, or input/Output).
Pins are one of three types:
■ Schematic pins provide ports to a schematic.

■ Symbol pins provide ports to a symbol representing a schematic, and are

connection points to the symbol in a hierarchical design.
■ Offsheet pins are used in large designs without hierarchy.

Pin names and directions must match in all cellviews of a cell.

Offsheet Pin Schematic Pin

IN OUT

Symbol Pin

IN OUT

Schematic Entry 2-17

Wires and Wire Labels
Automatic routing is the default mode.

Wire Label

sig1

Route Entered The System Routes

When not labeling a wire, the system names the net formed by the wires.
If the router cannot find a path between two points,
■ A dotted “flight line” is placed to establish connectivity only.

■ Click on intermediate points to guide the router to yield a solid line of

connectivity.
■ Use the Cmd Options icon or F3 key to modify the wiring options.

Schematic Entry 2-19

Interconnecting Components

Wire to Wire VCC!

Design Global Net

Wire to Pin

Adoption
IN

IN
Pin to Pin

IN OUT By Name (local) IN

IN OUT

Avoid this when possible.

Schematic pins and global symbol pins name wires by adoption.

Note: Inherited connections, not shown, are discussed in the Advanced Topics in ADE
module.

Schematic Entry 2-21

Schematic Checking
During schematic checking, all of the following are performed by default:
■ Update Connectivity

This process associates wires and pins with logical connections called nets.
■ Schematic Rules Check
❏ Logical checks
❏ Physical checks
❏ Name checks

■ Cross-View Checker

This option checks for pin name and direction consistency between
cellviews.

Select Check — Rules Setup from a schematic window to edit the rules. Disable
any or all of these schematic checking features, if not needed.

Schematic Entry 2-23

Schematic Checking Rules
The system sets the default schematic checking rules. The following set and
selections are logical types of rules:

Note:
There are five sets of Rules
Checks as indicated by
the tabs.
- Logical
- Physical
- Name
- Inherited Connections
- AMS

Note: Ignored means do not check for a condition. It is permitted to generate a netlist
and run a simulation with warnings, but not with errors.

Schematic Entry 2-25

Component Parameter Types
Use user-defined functions to describe parameters.

L = nlen L = 10u
W = nwid Variable W = 5u Static constant

L =0.9u SKILL function in an expression

W = 2 * iPar(“L”)

L = nlen*2
W = (nlen*2)/5

Any mathematical expression using the above

Note: iPar is only used on the same sheet of the schematic, and not for hierarchy.

Schematic Entry 2-27

Passing Parameters Through the Hierarchy

L=pPar(“lp”)
W=pPar(“wp”)

Hierarchical variables

L=pPar(“ln”)
W=pPar(“wn”)

ln
IN OUT wn Cell parameters created
lp During ASG
wp

IN OUT IN OUT IN OUT

ln=10u ln=20u ln=25u

wn=5u wn=8u wn=12u
lp=5u lp=15u lp=12u
wp=10u wp=30u wp=30u

During Automatic Symbol Generation (ASG), hierarchical variables are scanned.

The system creates component parameters for the symbol from these variables.
Parameters become editable when the instances are selected.
Schematic Entry 2-29
Symbol Generation
Design—Create Cellview—From Cellview
Select Apply or OK

This form opens with only the top

portion, press these buttons to
extend the symbol generation
capabilities of the form.

Select a symbol generation template,

other than the.cdsinit entry.

Select symbol generation attributes

to control the symbol drawing.

Schematic Entry 2-31

Characteristics of an Automatically Generated Symbol

Selection Box Interpreted Labels

Pin

These features are controlled by Instance Shape

the symbol template used.
Interpreted labels on the symbol act as “placeholders” for different types of
information to be displayed in the schematic.
■ cdsTerm() labels display pin names or the net names.

■ cdsParam() labels display parameters of an instance.

■ cdsName() labels display the instance or cell name.

Schematic Entry 2-33

Schematic Window Icons and Accelerator Keys
The Virtuoso Schematic Editor software provides both icons and “Accelerator”
keys to simplify schematic capture. The icons and Accelerator keys also reduce
the time needed to capture and edit schematics.
■ The icons appear on the left-hand side of the schematic editing window.

■ An icon is activated by using a left click over the icon.

■ Accelerator keys are activated by pressing specified keys on the keyboard.

■ Accelerator keys are sometimes referred to as bindkeys.

Schematic Entry 2-35

Schematic Editor Command Summary

COMMAND: bindkey Mouse Sequence : icon?

Add Component i Add — Instance yes
Select Component(s) LMB left click, or drag LMB
Copy c Edit — Copy yes
Delete Del Edit — Delete yes
Move m Edit — Move
Stretch M Edit — Stretch yes
Rotate r Edit — Rotate
Repeat RMB yes
Modify Properties q Edit — Properties — Objects... yes
Add Wire w Add — Wire yes
Add Wire Name l Add — Wire — Name... yes
Add Pin p Add — Pin yes
Undo u Edit — Undo yes

Redo U Edit — Redo

Schematic Entry 2-37

Bindkeys
Many of the schematic capture commands have alternative ways to be invoked.
1. A command sequence such as: Edit—Properties—Objects
2. An icon such as:
3. A bindkey such as q

Bindkeys include the following features:

■ Speed up schematic capture flow

■ Default set of functions with installation

■ Functions may be customized

■ Full set of may be viewed or changed using Options—Bindkeys in the CIW

Schematic Entry 2-39

Using a Hierarchy
Inv1x
nmos pmos Inv1x
wn=4u wp=8u
ln=0.5u lp=0.5u IN OUT
(symbol of primitive “nmos”) OUT
IN
LEVEL - Primitive
nmos (symbol of Inv1x)
wn=4u
ln=0.5u

LEVEL - Schematic using primitives

(requires symbol to use in a hierarchy)

ringosc
oscout
IN OUT IN OUT IN OUT ringosc

(symbol of rngosc)

IN OUT IN OUT IN OUT

oscout

LEVEL - Schematic with Hierarchy

(schematic uses symbols of other schematics and primitives)

Schematic Entry 2-41

Labs
Lab 2-1 Schematic Entry

Lab 2-2 Symbol Creation

Lab 2-3 Building the Supply Circuit

Lab 2-4 Building the ampTest Design

Schematic Entry 2-43

Lab Reference Material: Mouse Buttons
Left Mouse Button—Select and Deselect Middle Mouse Button
Pop-Up Menus
Click Select point
Click Pop-up menus
Double click Extend select
(EF) Pop-up menus
Shift-click Select point (add)
Control-click Deselect point Right Mouse Button
Repeat, Zoom, Options
Draw through Select box or Direct
Click Repeat last command
Edit*
Draw through Zoom in
Shift draw Select box (add) or
through Direct Edit* Shift draw Zoom out
through
Control draw Deselect box or Direct
through Edit* (EF) Command options
(command-specific
(EF) Add point
bindings)

Note: EF (Enter Function) bindkeys used within an active command.

*Direct Edit applies only when over object.

Schematic Entry 2-45

 ®

3 Analog Simulation

Module 3

October 11, 2004

Topics in this Module
■ Overview of the simulation environment

■ Setting up the simulation environment

■ Model files

■ Design variables

■ Choosing analyses

■ Netlisting

■ Running simulation

■ Viewing simulation results with the Waveform display tool

■ Saving simulator sessions

Analog Simulation 3-3

Overview of the Virtuoso Analog Design Environment
The Analog Design Environment is a user-friendly graphical interface tool to set
up, run, and evaluate analog circuit simulations:

Design Hierarchy or Test Circuit

(schematic view)

Stimulus: Transistor Level Load

analogLib: vpulse Schematic analogLib: cap
- or - (symbol view) res
stimulus file Symbol for schematic of - or -
- or - amplifier
schematic schematic

ANALOG DESIGN ENVIRONMENT Circuit Simulator

(ADE - 5.1.41) Spectre (used in this class),
User
Inputs Set up simulator - or - Spectre/Verilog,
Modify design variables cdsSpice,
Choose analyses etc.
Select model files / include files IN: Netlist, temperature, ...
Netlist and run simulation OUT:
Plot simulation results IN: OUT: .psf, .log, ...
View waveforms
Evaluate expressions

Analog Simulation 3-5

Important Features of the Simulation Window

Menu
The “Analyses” Field Banner

1 Analyses
Choose
3

Outputs

Delete

4 Netlist
and Run

2 Run

Snap
Shot

Output Field Plot Mode

Command Prompt
Icons

Analog Simulation 3-7

Analog Simulation Flow
STEP 1. Start the Simulation Environment

2. Select or verify Simulator Host

3. Select model files and include files

dc
4. Set design variables
dc sweep

5. Choose analyses for simulation ac

transient
6. Set simulator options
etc.

7. Select signals for output

8. Netlist and run simulation

Analog Simulation 3-9

Starting the Simulation Environment
STEP 1. Select Tools—Analog Environment from the schematic menu banner,
or select Tools—Analog Environment—Simulation from the CIW.
Then the Virtuoso Analog Design Environment “Simulation Window” appears.

Analog Simulation 3-11

Setting the Simulator
STEP 2. Select: Setup — Simulator/Directory/Host
Select the simulator to
be used.

For this class select

spectre in the cyclic field.

Analog Simulation 3-13

Setting the Model Libraries
STEP 3.
Select the model files. In
simulation window,
select:
Setup—Model Libraries...

This example uses a

relative path. The path
is set by the Include
Path in the Simulation
Files Setup form.

Analog Simulation 3-15

Simulation Files
STEP 3.
Setup—Simulation Files This is a relative path
For setting the path to
other simulation files

Enter the absolute or relative path into the text field

Include Path Path to location of any Model Library Files, Definition Files, and
Stimulus Files (the paths in these fields can be relative paths)
Definitions Files File or files that contain function definitions and parameter
declarations not in the Design Variables section of the Simulation
Window
Stimulus Files Location of text-based stimulus file

■ Each of the above fields can have one or more paths or file declarations separated
by a space.
■ Any type of Spectre include file can be included in the netlist by either using the
Definitions Files field above or the Model Libraries Setup form.

Analog Simulation 3-17

Setting Design Variables
STEP 4.
■ Extract variables in a design with the Copy From button.

■ Copy variable settings back to the design with the Copy To button.

■ Add variables used in parameterized model files that are not extracted.

■ Update a variable value and run simulation. Netlisting does not occur again.

■ Extract new variables added after a simulation run.

■ Use the Find Button to locate the Selected Variable in your design.

Select Variables—Edit or click the Edit Variables Icon.

Analog Simulation 3-19
Choosing Analyses
STEP 5.

Select

Analyses—Choose
or click the

Choose Analyses icon.

Analog Simulation 3-21

Choosing Analyses Details
The Choosing Analysis form
dynamically changes based
on the host simulator and
the selections made on the
form.

The types of analyses that

are available depend on the
Spectre RF host simulator.
Analyses
Sweep Variables depend on
the selected analysis.

Sweep Range

Analysis Options are entered

by selecting the Options...
button.

Analog Simulation 3-23

Simulation Environment Options
STEP 6.
Select Setup—Environment

■ Switch View List and Stop View List establish netlisting rules

■ Parameter Range Checking File

■ Use the SPICE Netlist Reader (spp)—Read in HSPICE/SPICE netlists and

run with the Spectre simulator.
■ Checkpoint and Restart
Analog Simulation 3-25
Simulator Options
STEP 6.
Select Simulation—Options—Analog

Use this form to set the simulator

tolerance values, convergence
options, and other settings.

NOTE:
This is a very long
form. The scroll
bar indicates the
amount of the
form that is visible.
Analog Simulation 3-27
Probing the Schematic to Save Output Data
STEP 7.

Select signals for

output

Click on pins to save currents.

Click on wires to save

voltages and frequency data.
Select: Outputs—To Be Plotted—Select On Schematic
■ You must terminate this command by pressing the Esc key.

■ Save and load data sets.

Optionally, save quantities associated with all wires, all pins, or both.
Analog Simulation 3-29
Outputs Section of Simulation Window
STEP 7.

# Name/Signal/Expr Value Plot Save March

1 out wave yes allv yes

2 input wave yes allv no
3 VDC(“/out”) -1.004m yes
4 phaseMargin 73.64 yes
5 gainMargin -16.00 yes

Automatically Automatically
Evaluated Plotted

Analog Simulation 3-31

Netlisting

STEP 8.

■ Netlists are hierarchical and created incrementally. Re-netlist only the

modified schematics.
■ Force all schematics to re-netlist with Simulation—Netlist—Recreate
Analog Simulation 3-33
Running the Simulation
STEP 8.
After the netlist has been created or recreated, the simulation is ready to run.
To run the simulation:
■ Select Simulation—Run or

■ Select the Run icon on the right side of the simulation window.

If preselected outputs appear in the output field of the simulation window, then the
Waveform display will automatically appear when the simulation is completed.

Analog Simulation 3-35

Running Additional Simulations
The purpose of running a simulation is to verify the operation and performance of
the circuit. This often requires running additional simulations. Most steps of the
simulation flow have now been completed. So running additional simulations is
greatly simplified.
■ To make changes to the simulation, simply modify the entries to the Design
Variables, Analyses, or Output fields, and then press the Run icon.
■ To change the temperature, select Setup—Temperature in the menu
banner, enter the new value, and the press the Run icon.
■ If you did not edit the schematic, you do not need to netlist the circuit.

■ If you did edit the schematic, you must do a Check and Save in the
schematic window.
■ After the Check and Save, you must select Netlist—Recreate within the
simulation window.
■ The simulation setup can also be saved for running additional simulations at
a later time, or even for running simulations on similar circuits.

Analog Simulation 3-37

Control of Analyses for Simulation
Analyses Control Field

Analog Simulation 3-39

Additional Options Using ADE
The Virtuoso Analog Design Environment provides additional features that
simplify running additional simulations, or modify the performance of the
simulation.
These options are:
■ Analog Default Options

■ Save State

■ Load State

■ Stimulus Template

■ Simulation Environment Options

■ Infotimes

■ Captab

Analog Simulation 3-41

Analog Default Options
In the Simulation window, select Session — Options.
Then an Editing Session Options window appears.

Select this button to be queried to save

the present working state.

Analog Simulation 3-43

Simulation States

Session—Save State

Session—Load State

Analog Simulation 3-45

Stimulus Template
Setup—Stimuli

Analog Simulation 3-47

Save Options

Select: Outputs—Save All

Setting Description
none Does not save any data. (Currently saves one node chosen at random.)

selected Saves only signals selected in schematic.

lvlpub Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This
option is equivalent to allpub for subcircuits.

lvl Saves all signals up to nestlvl deep in subcircuit hierarchy. Relevant to subcircuits.

allpub Saves only signals that are normally useful.

all Saves all signals.

Analog Simulation 3-49

Save Defaults and Save Session

In the CIW, select Options—Save Defaults.

In the CIW, select Options—Save Session.

Analog Simulation 3-51
Infotimes
Infotimes is a transient analysis option to display transient operating point
information.
1. From the Simulation Window, select Analyses—Choose.
2. Select the tran button in the Choosing Analyses form.
3. Select Options at the bottom of the Choosing Analyses form.
4. A very long Transient Options form appears, scroll down to infotimes.
5. Enter infotimes, as shown.

The line on the

Transient Options form
for entering infotimes.

Enter your time points in this

text field in any order.

Analog Simulation 3-53

Infotimes Results
Select Results—Print—Transient Operating Points, then click components on
the schematic.

To print the data of this window as a file select: Window—Print

Scroll bar

Select additional
components!

The scroll bar becomes

smaller as additional
devices are selected on
the schematic. The file
is getting larger, but the
data is added to the
bottom of the file.

Analog Simulation 3-55

Captab
■ Transient analysis option or dc analysis option

■ Provides a table of node capacitances at specified times

■ Has three node detail options: node, nodetoground, and nodetonode

■ Has a threshold feature; default is 0.0F

■ Similar to the CAPTAB option in HSPICE

■ Used with infotimes in the transient analysis options form

■ Simple to use

Analog Simulation 3-57

Selecting the captab Option from ADE
DC and Transient Analysis has CAPTAB PARAMETERS option. For transient
analysis:
1. Select Analyses—Choose.
2. Select the tran button in the Choosing Analyses form.
3. Select Options at the bottom of the Choosing Analyses form.
4. On the Transient Options form scroll down to infotimes.
5. Enter infotimes (see page 353).
6. Scroll down to CAPTAB PARAMETERS at the bottom of Transient Options form.
7. Enter CAPTAB selections.

Analog Simulation 3-59

Reminder to Terminate Select “Outputs...”
When doing the lab activities, it is extremely important to remember to terminate
the command Outputs—To be Plotted—Select On Schematic.
This command allows you to select wires and terminals for plotting. The
command continues to select wires and terminals until it is terminated by pressing
the Esc key.
A common error when using the simulation environment is to continue work
without terminating this command. The user will move the mouse to select Netlist
and Run, or other commands in the menu banner. Then the user attempts to
change a component parameter on a symbol in the schematic. The simulation
environment responds by selecting all terminals of the component to be plotted
and these appear in the “Outputs” field of the simulation window.
Now the user must unselect the terminals and delete the entries in “Outputs” field.

Analog Simulation 3-61

Labs
Lab 3-1 Running Simulation

Lab 3-2 Using the Stimulus Template

Lab 3-3 Transient Operating Point Analysis, “infotimes”

Lab 3-4 Captab

Analog Simulation 3-63

 ®

4 Simulation Results Display Tools

Module 4

October 11, 2004

Topics in this Module
■ Overview for using Waveform Display tools

■ Introduction to WaveScan

■ Viewing simulation results with the Waveform Window

■ Accessing and appending data on the Waveform Window

■ Accessing the Waveform Calculator

■ Using subwindows

■ Label Displays

Simulation Results Display Tools 4-3

Overview of Simulation Display Tools
A useful method to evaluate a simulation is to examine and make measurements
on the simulation results. Waveform display tools are used to display simulation
data. Some waveform display tools and related software tools include:
■ WaveScan

■ Waveform Window (AWD)

■ Waveform Calculator (WaveScan & AWD)

■ Results Browser

■ Snapshot Tool

■ Annotating Component Display

Simulation Results Display Tools 4-5

WaveScan
■ Integrated as the default viewer in 5.1.41

■ Reads psf, digital wsf, and sst2 data

■ Graphical interface is Java-based; data access is C++

■ Accessible from the Session—Options command window in ADE (to

switch between AWD and WaveScan) or from the command line in Unix
(enter wavescan)

Simulation Results Display Tools 4-7

The WaveScan Results Browser
(Select Tools—Results Browser from ADE)
Destination of new graph

Menu Bar

Toolbar

File Location

Left Pane Right Pane

Filter Select

Status Bar

■ Trace Modifier and Graph Type only available for AC data.

Simulation Results Display Tools 4-9
Selecting Signals

Filter Tabs

■ The following methods are available for filtering signals:

❏ View all signals
❏ View only voltage, current, power, or Logic
❏ View by name: net*

■ Available choices depend on the dataset that is open

Simulation Results Display Tools 4-11

Plotting
All your favorite plotting options are here:
■ Rectangular, Polar, Admittance, Impedance, Real vs. Imaginary

■ Swept Data:

■ Y vs. Y:

■ Difference of two signals:

■ Strip mode

■ Buses

■ Hide/Reveal objects

■ Zoom: X and Y, Pan

■ “Active” window: double-click on anything in window and its associated

“Edit Attributes” form pops up.
■ Cursors

■ Labels

■ Accelerator keys: bindkeys

Simulation Results Display Tools 4-13

Plotting (continued)

Label Area
Menu Bar

Tool Bar

Graph Title

Legend

Marker

Grids

Graph Area

Status Bar

Simulation Results Display Tools 4-15

Data Ranging
■ Can plot a portion of a simulation run

■ Does not read the entire simulation run; instead, it only shows a portion of it
(like AWD)—true “range-specific” plotting
■ Execute Settings—Select Sweep (or click “Select sweep dialog” icon: )
■ Change time to desired scale

Simulation Results Display Tools 4-17

Parametric Data

■ Can plot all parametric sweeps or selected sweeps

■ Plots both Virtuoso Analog

Design Environment
parametric data and Spectre
“sweep” data

■ Can modify range data as

well.

Simulation Results Display Tools 4-19

Plotting Options
■ Layout can be quickly changed: Horizontal, Vertical, Strip, Card

■ Strip mode is available (scroll bar is automatically added if many strips are
plotted)

Simulation Results Display Tools 4-21

Plotting Options (continued)
■ Layout may be locked in; aspect ratio no longer the only way to set layout

■ When plotting many subwindows, you can change the view to “Card”

Card view
select

Simulation Results Display Tools 4-23

Tables (Tools—Table from Results Browser)
■ Tables can display a variety of information

■ Tables are data-specific; the above table shows bjt dcOp-Info, but tables
can also show bjt, bsim3v3, capacitor, isource, resistor, vcvs, and vsource
■ Any waveform or calculator expression may be printed in a table

■ Table formatting options: transpose rows and columns, move columns,

modify scale, modify significant digits, column headers, resize columns,
hide columns, sort
■ Table saves data to pointer file; in 5.1.41, ascii save is available
Simulation Results Display Tools 4-25
Reloading Data
■ If you resimulate your design, WaveScan automatically reloads the data:
❏ No “Refresh” needed
❏ New graphs plotted with new data
❏ Existing graphs are not updated

■ File—Reload will update all unfrozen graphs with new data

■ Graphs can be “frozen” using Graph—Freeze On

❏ No new data will be allowed in subwindow
❏ All new plots go in a separate subwindow

Simulation Results Display Tools 4-27

Digital Signals
■ Digital signals are plotted at top of WaveScan window in strip mode

Digital

Analog

■ Create Bus—Select Traces, then Trace—Bus—Create (or click )

■ Expand Bus—Select Bus, then Trace—Bus—Expand (or click )
■ Mixed-signal plotting still available; analog appears below digital.
Simulation Results Display Tools 4-29
Saving and Printing Graphs and Data
You can save the entire waveform window or individual trace information:
■ File—Save to save the graph (saves current waveform window)
❏ Format is XML; file saved as *.grf
❏ Can change suffix by changing a .wsenv variable

■ You can save graph information to a file

❏ Saves a pointer to data file, no real data saved in file.
❏ Need to “save trace” to get ascii data (Trace—Save)

■ Open a saved graph by selecting:

❏ File—Open Graph—Open Graph as Plot...

You can create “template” graph file so new graphs will have same attributes:
■ File—Open Graph—Open Graph as Template...

■ Current graph can become template: Graph—Template—Set Current

You can print the graph or part of a graph, from the Graph Window:
■ File—Print: prints selected subwindow

■ File—Print All: prints all visible subwindows

Simulation Results Display Tools 4-31
Calculator
■ User interface is Java-based

Analysis Mode Select Analysis Tabs

Menu Bar

Dataset Label Buffer Pulldown

Buffer

Functions
Panel Filters

Status Bar

■ RPN and algebraic mode available

Simulation Results Display Tools 4-33

Calculator Functions
■ Select Signal in Results Browser automatically seeds buffer

■ One window: no popup forms

■ Dynamically changes depending on what function is called

Function Panel

Simulation Results Display Tools 4-35

Calculator Functions (continued)
Schematic Expression Buttons Buffer Pull Down

■ Hit “Eval” to evaluate buffer (RPN mode)

■ Can plot expressions that evaluate to a waveform

■ Selecting from the Select Mode tab prompts for a schematic input.

Simulation Results Display Tools 4-37

Calculator Filtering
■ Functions may be filtered to be relevant to a particular data type:

Category Functions Displayed

Frequency bw, gainMargin, phaseMargin
General argmax, argmin, cfft, clip, convolve, cross, crosscorr,
crosses, deltax, fft, flip, histo, ifft, iinteg, integ, pp, rms,
sign, snr, trim, xval, yval
Math abs, avg, ceil, cplx, deriv, exp, floor, int, ln, log10, max,
min, mod, pow, real, round, sqrt
Modifier angle, conj, d2r, db, db10, dbm, im, mag, ph, r2d, re
Statistics stathisto
Transient falltime, overshoot, risetime, slewrate
Trig acos, acosh, asin, asinh, atan, atanh, cos, cosh, sin,
sinh, tan, tanh
PoleZero pzbode, pzfilter

Simulation Results Display Tools 4-39

The Waveform Window (AWD)

Double-click on any item in the window to display an options form that controls it.
Simulation Results Display Tools 4-41
Waveform Window Features
1 2
Layout of Window
Independent Subwindows
Strip Mode

3 4

AC Response
B

Gain (dB)
A*

Phase (deg)
Labels
Vertical and Horizontal Markers
Frequency
Crosshair Markers w/ On-Screen Display
A: (40.37M 270.6m) delta: (-40.08M 1.233)
Select Letters A or B to Delete Markers B: (2.946K 1.26) slope: 3.076u

Simulation Results Display Tools 4-43

Direct Plot
Main Form...
Transient Signal
T
Transient Minus DC
Transient Sum
Transient Difference
AC Magnitude
AC dB10
AC dB20
AC Phase
AC Magnitude & Phase
AC Difference
Equivalent Output Noise
Equivalent Input Noise
Squared Output Noise
Squared Input Noise
Noise Figure
DC
Main Form...
Results—Direct Plot

Simulation Results Display Tools 4-45

Snapshot

Bottom of Simulation Window

■ Set up outputs to plot in the Simulation Window before simulating.

■ During simulation, click the Plot Outputs icon to plot the data available. This
requires the simulation to be running slowly enough for this feature to work.
Each time the icon is clicked, the Waveform Window displays the results
that have accrued since the previous click of the icon.

Simulation Results Display Tools 4-47

Waveform Calculator
The Waveform Calculator is integrated into the Virtuoso Analog Design
Environment as a part of AWD and is used to analyze simulation results. It is
discussed in Module 5.

Simulation Results Display Tools 4-49

Controlling Schematic Label Displays
In the schematic window, select Edit—Component Display.

Modifies cdsTerm ( ) labels

Modifies cdsParam ( ) labels

Modifies Instance labels

Simulation Results Display Tools 4-51

Annotating Simulation Information to the Schematic

DC Operating Points

Annotation labels appear near all components in the design window.

■ Display configurations can be saved and loaded again.

■ Unless explicitly saved, the database is overwritten or lost when exiting the
Design Framework II session.
■ The Design Defaults command removes annotated simulation data and
restore design information on the schematic.
■ Use Results—Print command and menus to print results to a file.
Simulation Results Display Tools 4-53
Labs
Lab 4-1 Displaying Results and Using the Calculator with WaveScan

Lab 4-2 Saving the Simulation Session

Lab 4-3 Displaying Interpreted Labels Near Schematic Components

Lab 4-4 Annotating Simulation Results to the Schematic Window

Simulation Results Display Tools 4-55

Lab Reference Material
When using a command such as
Outputs—To Be Plotted—Select On Schematic or
Outputs—To Be Saved—Select On Schematic in the simulation environment,
follow the prompts in the schematic window or CIW to graphically probe the
design. When finished probing all desired nodes and terminals, press the Esc key
with the cursor in the design entry window to cancel the select function. Failure to
cancel the select function explicitly before starting a different one, might
temporarily disable the system.
If this condition occurs, the Nest Limit of the environment has been violated, and
a warning appears in the CIW. Change the Nest Limit with the
Options—User Preferences form through the CIW to get around this feature.
Make sure to cancel each selection or probing function using the Esc key when
done.

Simulation Results Display Tools 4-57

 ®

5 Analyzing Simulation Results

Module 5

October 11, 2004

Topics in this Module
■ The Waveform Calculator

■ The Print Engine

■ Storing and managing simulation results

■ The Results Browser

■ Conditional search and display

■ The Spectre sweep feature

■ Sensitivity Analysis

■ Stability Analysis

Analyzing Simulation Results 5-3

The Waveform Calculator (AWD Shown)
In the Simulation Environment, select Tools—Calculator.
In the Waveform Window, select Tools—Calculator or click the Calculator Icon.
In the CIW, select Tools—Analog Environment —Calculator.

Menu
Banner
Calculator
Buffer

Selecting Special
waveform data
Functions

Math
Printing and Functions
Plotting

User
Programmable
Enter data from Numeric Function Keys
schematic Keypad

Analyzing Simulation Results 5-5

Postprocessing Data with the Waveform Calculator
There are four ways to enter data into the calculator:
1. Import buttons (vt, vf, it, and if) allow probing in the schematic window.
2. The wave button allows probing in a Waveform Window.
3. Use the Results Browser.
4. Type in a signal name or expression.
■ Plot results or evaluate buffer expressions.

■ Use the printvs button to print data tables to a file.

■ Special functions are available, including Discrete Fourier Transforms

(DFTs), rise times, gain margin, phase margin, and slew rates.
■ Use the Calculator in Reverse Polish Notation (RPN) or Algebraic Mode.

■ A special RF mode is available.

Analyzing Simulation Results 5-7

Waveform Calculator, Special Functions Key

Functions include:
Press “Special Functions” to display integral
waveform processing functions. derivative
dft
delay
eye diagram
thd
Analyzing Simulation Results 5-9
Print Engine
■ Printed results are now displayed in a “smart” print window.

■ Examples of printed results:

❏ All Results—Print commands
❏ Print and Report commands from OCEAN
❏ Simple or parametric waveforms
❏ Generic tabular data (such as Monte Carlo data)

■ Tabular data can be further formatted using form-driven interface. (Move

columns, sort, and expressions.)

Analyzing Simulation Results 5-11

Printing the Results
Specify the results to print:
■ Run a simulation.

■ Then in the Simulation Window, select Results—Select.

A Select Results window appears. This window lets you select other
simulation results. (Make sure the schematic window for the selected design
is open.)
■ To print the results, select Results—Print with one of the following options:
❏ DC Node Voltages or DC Operating Points
❏ Model Parameters
❏ Transient Node Voltages or Transient Operating Points
❏ S-Parameter
❏ Noise Parameters
❏ Noise Summary or PSS Noise Summary
❏ Sensitivities

■ Select a node or device in the schematic window.

Analyzing Simulation Results 5-13

Results Display Window
After a simulation run, select printvs from the
calculator window, and provide the printvs range.

Pull-Down
Menus

Analyzing Simulation Results 5-15

Run Data Storage Directories
Subdirectories are created below the project directory to define a unique storage
location for simulation results.
■ The project directory is specified in the Simulation environment.

Hierarchy Level
Project Directory/Cell_Name/Simulator_Name/Run_Name/Run_Data
Example
~/simulation/ampTest/spectre/schematic/ (netlist/ or psf/)

■ Data storage directories can be managed with UNIX commands.

■ Numerical simulation data is written to a binary file in Parameter Storage

Format (PSF), which is stored in the psf/ directory.
■ The final netlist and text files related to netlist generation are stored in the
netlist/ directory.

Analyzing Simulation Results 5-17

Backing Up Simulation Data Explicitly
The /schematic directory is overwritten during subsequent simulation runs of the
same design. To preserve simulation data, use the Results—Save command.

Results—Save

Analyzing Simulation Results 5-19

Selecting Results
Load results from previous simulations.

Results —Select...

Analyzing Simulation Results 5-21

Setting Plotting Options

Location and size of

Waveform Window

Results—Printing/Plotting Options

Analyzing Simulation Results 5-23

Annotating Data to the Waveform Window
Annotation—Edit Waveform Window

Build expressions in the Calculator

and use them to create labels in the
Waveform Window.

Analyzing Simulation Results 5-25

Starting the Results Browser
In the Simulation Environment or Waveform Window, select Tools—Results
Browser.
In the CIW, select Tools—Analog Environment—Results Browser.
In the Calculator, click the Browser button.

Specify a Project Directory.

The Results Browser accesses data in the Project Directory and below.

Examples of Project Directories

./simulation/ampTest/spectre

Accesses all Spectre results for this design.

./simulation/ampTest

Accesses all results for this design.

Analyzing Simulation Results 5-27

The Results Browser
The Results Browser is similar to the Library Manager. An object menu can
manage or expand the data structure.

Expanding the psf directory Interpretation of the PSF binary data

ac-ac
dcOp-dc
netlist/ dcOpInfo-info
schematic/
element-info
psf/ Run1
finalTimeOP-info
/vin
modelParameter-info
outputParamer-info /out
/net9
tran-tran
Expand (L) /I10/gnode
Expand FS variables
/I10/net18
Plot (R)
/vdd!
Expression
Refresh
Delete Categories of analysis data
Rename...
Properties... Waveform or numerical expressions
Create ROF Right Mouse Button: Plot the signal
Select Results Left Mouse Button: Paste signal expression into Calculator buffer

Analyzing Simulation Results 5-29

Viewing Presimulation Text Data
Click the names of text files with the right mouse button in the Results Browser
to view their contents.

Expanding the Netlist Directory

Final Netlist
Data from
simulation
runs

OCEAN Scripts

Analyzing Simulation Results 5-31

Interactive Postprocessing Tools
Schematic Editor
2
Window Edit Schematic Waveform Window
2
Simulation Environment
Tools Window

Calculator
B

A+B

Analyzing Simulation Results 5-33

Conditional Search and Display
■ Form-driven search, probe, and print for specified device operating
conditions.
■ Finds and displays breakdown conditions, MOSFETs in linear region, and
saturated BJTs.
■ User-configurable search criteria

■ Includes multiple constraint (Boolean) searches.

Analyzing Simulation Results 5-35

Setting Up a Conditional Search
1. Run a simulation or invoke Results—Select Results and choose other
simulation results. This provides the results to search.
2. Choose Results—Circuit Conditions.
3. Select the Device Operating Conditions.
4. Set up the User-Defined Conditions.
5. View the Circuit Conditions results using the Place or Print buttons.

Analyzing Simulation Results 5-37

The Circuit Conditions Form

Analyzing Simulation Results 5-39

Device Check Interface to ADE
■ Allows the user to write custom characterization rules that check device,
model, design parameters, or expressions against specified bounds.
■ Allows user to write rules that are complicated expressions in MDL syntax.

■ Checks the rules in DC, DC Sweep, and Transient analysis.

❏ Device Checking Setup
❏ Simulation Output
❏ Results Violation Display

Analyzing Simulation Results 5-41

Device Checking Setup
Simulation—Device Checking....

Analyzing Simulation Results 5-43

Device Checking Setup (continued)
Simulation—Device Checking... invokes the following form, which is used to
enter and manage asserts

Analyzing Simulation Results 5-45

Editing Device Check

Device/Model/Primitive Tab

Analyzing Simulation Results 5-47

Editing Device Check (continued)

Parameter Tab

Analyzing Simulation Results 5-49

Editing Device Check (continued)

Expression Tab

Analyzing Simulation Results 5-51

Device Checking Setup Options
Click on “Options” button in the Device Checking Setup form gives following:

■ Settings go to checklimit statement

■ This severity setting overrides severity specified for individual assert

Analyzing Simulation Results 5-53

Simulation Output
■ Device Checking Options
❏ ADE: Simulation—Options—Analog
❏ Controls device checking
❏ Write violations to file (spectre.out), psf, or both
❏ checklimitfile written under netlist directory

Analyzing Simulation Results 5-55

Device Check Violations Display
After a successful Device Check simulation, Violations Display is highlighted

Analyzing Simulation Results 5-57

Violations Display

Analyzing Simulation Results 5-59

Violations Display (continued)
Display Info

Analyzing Simulation Results 5-61

Violations Display (continued)
Print

Analyzing Simulation Results 5-63

Sensitivity Analysis
Use the Sensitivity Analysis to:
■ View the parameters that most affect the specified outputs

■ Tune a design to increase or decrease certain goals

■ Determine what parameters to run in an Optimization analysis

The Sensitivity Analysis requires a base analysis to be run first.

■ Only runs with AC and DC analysis at the present time.

Analyzing Simulation Results 5-65

Setting Up Sensitivity Analysis

Select one of these

and run the
base analysis in
addition to any
selection here.

Analyses—Choose

Analyzing Simulation Results 5-67

Viewing Sensitivity Results

Results—Print—Sensitivities
Analyzing Simulation Results 5-69
Spectre Sweep Feature

Temperature Sweep
(DC Analysis)
Model Parameter Sweep
(AC Analysis)
Design Variable Sweep
(AC Analysis)

Analyzing Simulation Results 5-71

Introduction to Stability Analysis
■ Stability analysis is a small-signal analysis that is available for Spectre only.

■ It can be used with Spectre standalone, or with the Analog Design

Environment, to:
❏ Verify the stability of feedback circuits.
❏ Check circuit stability with margin information.
❏ Easily measure loop gain, phase margin, and gain margin.

■ Results can be printed in the Results Display Window and plotted in the
Waveform Window.
■ Two algorithms are available depending on the probe parameter specified:
loop-based and device-based.
❏ The loop-based algorithm produces accurate stability information for
circuit design in which a critical wire can be identified to break all
feedback loops.
❏ The device-based algorithm produces accurate stability information for
a circuit design in which a critical controlled source can be identified such
that nulling this source renders the whole network passive.

Analyzing Simulation Results 5-73

Loop-Based Algorithm
■ Calculates the true loop gain.

■ Invoked when a probe parameter points to a current probe or

zero-DC-valued voltage source.
■ Current probe or zero-DC-valued voltage source is placed on the feedback
loop.
■ Provides accurate stability information for single loop circuits and for
multiloop circuits with a critical wire.
■ Multiloop circuit can be stable if all individual loops have reasonable stability
margins.
■ Determines the stability of the whole network as long as all nested loops are
stable.

Analyzing Simulation Results 5-75

The Device-Based Algorithm
■ Calculates the loop gain around a particular active device.

■ Invoked when a probe parameter points to a supported active device

instance.
■ Used for designs in which local feedback loops cannot be neglected.

■ Can be used to ensure all local loops are stable.

■ Local feedback loops are not accessible from the schematic or netlist level
to insert the probe component.
■ Nulling dominant controlled source renders the active device to be passive.

The supported active device and its dominant gain source are summarized below.
The device-based algorithm produces accurate stability information for a circuit in
which a critical active device can be identified such that nulling the dominant gain
source of this device renders the whole network to be passive. Examples are
multistage amplifier, single-transistor circuit, and S-parameter characterized
microwave component.

Analyzing Simulation Results 5-77

Starting Stability Analysis
In the simulation window, select: Analyses—Choose... .

In the Choosing Analyses

form select the stb button.

Sweep variables allowed

in stability analysis.

Analyzing Simulation Results 5-79

Stability Analysis Results

Results — Direct Plot — Main Form

Results — Print—Stability Summary

Analyzing Simulation Results 5-81

Labs
Lab 5-1 The Waveform Calculator

Lab 5-2 Managing Simulation Results

Lab 5-3 Managing Simulation Data with the Results Browser

Lab 5-4 Viewing Circuit Conditions

Lab 5-5 Using the Spectre Sweep Features

Lab 5-6 Stability Analysis

Analyzing Simulation Results 5-83

Lab Reference Materials
Any import key in the calculator, such as vt, it, wave, when pressed will prompt to
probe in the design entry window. When finished graphically probing, press the
Esc key with the cursor in the design entry window to cancel the probing function.
Failure to cancel the probing function before starting a different one, will
temporarily disable the system. This can be solved by cancelling the current
probing functions using the Esc key.
This condition violates the Nest Limit of the environment, and a warning appears
in the CIW. To avoid this, change the Nest Limit with the Options—User
Preferences form through the CIW.
Currently, the conditional search capability only works for DC operating
conditions.

Analyzing Simulation Results 5-85

 ®

6 SKILL and OCEAN

Module 6

October 11, 2004

Topics in this Module
■ Overview of SKILL and OCEAN

■ SKILL in the DFII Environment

■ Basic SKILL statements

■ Introduction to OCEAN

■ Types of commands

■ Sample OCEAN script

■ Data access commands

■ Plotting commands

■ Aliases

■ Running OCEAN interactively

■ Creating OCEAN scripts in the Virtuoso Analog Design Environment

■ Loading OCEAN scripts

SKILL and OCEAN 6-3

Overview of SKILL and OCEAN
Introduction
This chapter provides some basic instruction in the use and applications of SKILL
programming language.
This chapter provides instruction on SKILL because:
■ SKILL is used as the fundamental program language of DFII and the
Virtuoso Analog Design Environment.
■ The OCEAN Command Language is based on SKILL and many SKILL and
OCEAN commands are similar and interchangeable.
This chapter also provides basic instruction on the use and applications of the
OCEAN Command Language. This information on OCEAN is used to:
■ Run long simulations in batch mode.

■ Run simulations from remote non-graphic terminals

■ Setup and run a large set of simulations, obtain data from the simulation
runs, and evaluate the simulation data automatically.
■ Use the Virtuoso Analog Design Environment to create OCEAN scripts to
run simulations at a later time.
SKILL and OCEAN 6-5
Introduction to SKILL
■ SKILL is a graphics-based program language based on Lisp.

■ DFII and most features and applications of Virtuoso Analog Design

Environment are written in SKILL code.
■ Features of the Virtuoso Analog Design Environment and related tools can
be customized using SKILL.
■ The OCEAN command language is based on SKILL.

■ Many SKILL and OCEAN commands are interchangeable between the two
domains.
■ Training in SKILL is available from Cadence Education Services.

■ Both classroom and internet training (iLS) are available.

■ There are SKILL development tools available in your installation of Virtuoso

Analog Design Environment.

SKILL and OCEAN 6-7

Using SKILL Commands
There are numerous ways to execute SKILL commands and programs.
■ The command line of the CIW accepts SKILL commands.

■ The command line of the CIW executes SKILL programs.

■ The buffer of the Waveform Calculator will evaluate mathematical

expression written in SKILL.
■ There is a SKILL environment that is started by typing “skill” in a unix
window.

SKILL support
■ The Finder utility is a SKILL dictionary for locating the syntax and usage
SKILL commands.
❏ Start the Finder from the CIW by selecting: Tools—SKILL
Development, then select the Finder button.
■ Other SKILL support features include SKILL Development Tool and
CDSDoc.

SKILL and OCEAN 6-9

Basic SKILL Statements
■ SKILL commands can be entered into and evaluated on the command line
of the Command Interpreter Window.
■ You can enter valid SKILL syntax into the CIW. For example, on the
command line enter:
2+2
4 ... SKILL response
■ Now enter:

pi=3.14159
3.14159 ... SKILL response
then enter:
x= 1/( 2 * pi * 1M * 1p ) ... the reactance of a 1pf capacitor at 1MHz
159155.1 ... SKILL response
■ SKILL evaluates the command line, assigns values to variables, and
evaluates expressions.

SKILL and OCEAN 6-11

Parentheses and Double Quotes
There are common SKILL syntax characters. These are also used in OCEAN
scripts:
■ Parentheses [ () ]
Example: path( "./simulation1/schematic/psf")

No space! This very important.

■ Double quotes [ "" ]
Example: path( "./simulation2/schematic/psf" )

SKILL and OCEAN 6-13

Single Quote and Question Mark
■ Single Quotes

Example: analysis( ‘tran .... )

■ Question Mark

Example: analysis( ‘tran ?stop 1u)

SKILL and OCEAN 6-15

Introduction to OCEAN
Open Command Environment for ANalysis
■ OCEAN is a product included in the Virtuoso Analog Design Environment.

■ Use OCEAN for the following tasks:

❏ To create scripts to run batch mode simulations.
❏ To run parametric, Corners, Monte Carlo, and Optimization analyses.
❏ To run long simulations without starting the graphical user interface.
❏ To run simulations from a non-graphical, remote terminal.

■ OCEAN is based on the SKILL programming language.

Scripts are created automatically within the Virtuoso Analog Design

Environment. These scripts can be saved, modified, and used to run batch
simulations.
■ After the design has been debugged in the Virtuoso Analog Design
Environment, use OCEAN to test your circuit under a variety of conditions.

SKILL and OCEAN 6-17

Types of OCEAN Commands
OCEAN Commands Purpose

Specify the analyses to run.

Simulation
Specify the nets and currents to save.
Setup
Specify the simulator option value.
Commands
Specify the circuit stimulus.

OCEAN scripts can Simulator

contain all of these Run Run the simulator.
types of commands. Commands

Perform calculations on the results.

Data Access Print information.
Commands Plot waveforms.
Hardcopy results.

SKILL and OCEAN 6-19

Sample OCEAN Script
simulator( 'spectre )
design("./simulation/ampTest/spectre/schematic/netlist/netlist")
resultsDir( "./simulation/ampTest/spectre/schematic" )
modelFile(
( "./Models/myModels.scs" ““)
)
analysis('ac ?start "100" ?stop "150M" ?dec "20" )
desVar( "CAP" .5p )
temp( 27 )
run()
selectResult( 'ac )
plot(getData("/out") )

Note: Specify the resultsDir() to set the directory where simulation data is saved. In the
example above, resultsDir() points to the default location. When using the default,
the resultsDir() expression is not needed.

SKILL and OCEAN 6-21

OCEAN Help
Online help is available for all the OCEAN commands. In an OCEAN session,
type the following:
ocnHelp( ‘commandName )

For example, enter:

ocnHelp(‘analysis)

An explanation of the command and examples of use are returned.

For a list of all types of OCEAN commands, enter:

ocnHelp()

Additional help and samples of OCEAN scripts are located at:

<install_dir>/tools/dfII/samples/artist/OCEAN

Detailed documentation on OCEAN and OCEAN scripts is accessible through

CDSDoc.

SKILL and OCEAN 6-23

Data Access Commands
Open simulation results and analyze data.
■ Simulation does not have to have been run in the current session.

■ Examples of data access commands include:

openResults( “./simulation/opamp/spectre/schematic/psf” )
results()
selectResult( ‘tran)
ocnPrint( v( “/net56”))
i( “/R1” )
plot(v(“/out”))
pv( “/Q19” “ib”)

■ List of commands includes:

dataTypes, getData, i, noiseSummary, ocnPrint, openResults,
outputParams, outputs, pv, report, results, selectResults,
sweepNames, sweepValues, v

■ Common arithmetic operators and all Calculator functions are available.

SKILL and OCEAN 6-25

Plotting Commands
Use any Waveform Window SKILL command for plotting in OCEAN.
■ By default, the Waveform Window is in overlay mode.
Use the clearAll() command to erase the window.
■ Use graphicsOn() and graphicsOff() to turn plotting on and off.

■ Arithmetic operators and all Calculator functions are available.

Original New Label

label

Examples: plot(getData("/out") ) plot(getData("/out") ?expr list( "Output Node") )

SKILL and OCEAN 6-27

Available OCEAN Aliases
Aliases are available in OCEAN to simplify your scripts.

Alias Syntax Description

vm mag( v( t_net)) Magnitude of voltage on the net
vdb db20( v (t_net)) Power gain in decibels from net
“in” to net “out”
vp phase( v(t_net)) Phase of voltage on net
vr real( v( t_net)) Real part of complex voltage
vim imag( v( t_net)) Imaginary part of complex voltage
im mag( i( t_component)) Magnitude of AC current
ip phase( i( t_component)) Phase of AC current
ir real( i( t_component)) Real part of complex number
representing AC current
iim imag( i( t_component)) Imaginary part of complex
number representing AC current

SKILL and OCEAN 6-29

Running OCEAN Interactively
Run OCEAN from a UNIX prompt or from the CIW.
■ In UNIX:

Enter ocean from the UNIX prompt to start.

This loads awd.exe and loads and reads the .oceanrc startup file. The
.oceanrc file contains OCEAN commands that include alias definitions, and
user-defined procedures and characterization scripts.
An ocean> prompt appears in the UNIX window. Enter commands at the
prompt.
The .cdsinit file is not loaded.
Type exit to quit OCEAN.
■ In the CIW, through the Virtuoso Analog Design Environment:
❏ Enter OCEAN commands at any time.
❏ The .oceanrc is not loaded automatically. If it exists, load it by entering:
load “.oceanrc”

SKILL and OCEAN 6-31

Creating OCEAN Scripts in ADE
It is easy to create OCEAN scripts in the Virtuoso Analog Design Environment.
■ OCEAN commands of tasks performed in the Virtuoso Analog Design
Environment are automatically saved in the
./simulation/design/simulator/schematic/netlist/simulatorX.ocn files.

■ In the Simulation Environment form, select Session—Save Script...

❏ Specify the file name of the script to create.

❏ Only enabled analyses are saved.
❏ The command saves the design, library model file, design variables,
data directory, simulator options, plot set, etc.

SKILL and OCEAN 6-33

Loading OCEAN Scripts
Load OCEAN scripts from a UNIX window or from the CIW.

■ In UNIX:
ocean> load( “script_name.ocn”)

or
load “script_name.ocn”

■ In UNIX, to run an OCEAN script and then have OCEAN quit, enter:
unix> ocean < script_name.ocn

■ In the CIW, enter:

load( “script_name.ocn”)

or
load “script_name.ocn”

This command loads and runs the OCEAN script.

SKILL and OCEAN 6-35

Labs
Lab 6-1 Using an OCEAN Script to Run a Simple Simulation

Lab 6-2 Measuring PSRR and CMRR with OCEAN

Lab 6-3 Introduction to SKILL

Lab 6-4 SKILL Development Tools

SKILL and OCEAN 6-37

 ®

7 Parametric Analysis

Module 7

October 11, 2004

Topics in this Module
■ Introduction to EDFM design tools

■ Parametric analysis flow and methodology

■ Parametric analysis environment

■ Parametric plots

■ Accessing data from parametric analysis

■ Model parameters

■ Running parametric analysis in OCEAN

Parametric Analysis 7-3

Introduction to EDFM Design Tools
Parametric Analysis is one of set of software products called EDFM tools.

Parametric Analysis 7-5

EDFM Tool Usage
The following table provides on overview of the EDFM tool usage. The table
shows the existing common usage for the EDFM tool set. The table also shows
what is now considered the “best usage”. Note that each tool shows usage in
more than one domain. Parametric analysis is suitable for design exploration and
for problem detection.

Table of Design Tool Usage

EDFM Tool Initial Design Design Problem Improve & Final

Exploration Detection Center Verification
Circuit Optimizer High Medium
Parametric Analysis High High
Corners High Medium High
Monte Carlo High Medium Medium
Yield Analysis High High

Parametric Analysis 7-7

Overview of Parametric Analysis and Flow
Open Design

Start Simulation Environment

Start Parametric tool with: Tools—Parametric Analysis

Pick Sweep Variables

Set Sweep Ranges

Add Inclusion/Exclusion Lists

Run Analysis

Parametric Analysis 7-9

Parametric Analysis Methodology
1. Set up the simulation environment.
❏ The environment remains fixed during parametric analysis.
❏ Limit output data if results storage space is limited.

2. Start the Parametric Analysis tool by selecting Tools—Parametric

Analysis from the simulation environment. The tool behaves as a:
❏ Number list generator
❏ Simulation engine controller

3. Generate lists of design variable values.

❏ A simulation is run for each variable value or point.
❏ A parametric analysis on a variable is called a sweep.

4. Plot results by probing in the design window.

❏ A family of curves is displayed.

Parametric Analysis 7-11

The Parametric Analysis Environment

Tools—Parametric Analysis

Parametric Analysis 7-13

Parametric Plots (AWD Shown)

■ Curve identifiers match the curve colors.

■ Put your cursor on a curve to indicate the associated value(s) of variables.

■ Use the calculator to process families of curves.

■ Once plotted, each curve is independent for postprocessing.

Parametric Analysis 7-15
Accessing the Parametric Analysis Data Structure

Access data for specific

variable values with the
Results Browser.

Parametric Analysis 7-17

Parametric Analysis on Model Parameters

1. Add model parameter as a Design Variable.

model trnpn type=npn is=10e-15 bf=beta \

va=58.7 ik=5.63e-3 rb=665 rbm=86 re=3.2 \
cje=0.25e-12 pe=0.76 me=0.34 tf=249e-12 \
cjc=0.34e-12 pc=0.55 mc=0.35 ccs=2.4e-12 \
ms=0.35 ps=0.53 rc=169

2. Point to a model file that

contains the new variable.

3. Start Parametric Analysis and choose the new sweep variable.

Parametric Analysis 7-19

Parametric Analysis in OCEAN
■ The parametric analysis commands are not saved to the OCEAN script
when selecting Session—Save Ocean Script.
■ Use Tool—Save Script to save the parametric analysis.

■ Nest parametric analyses for multiple variables, as shown in this example.

Example
paramAnalysis( “rl” ?start 200 ?stop 600 ?step 200 paramAnalysis(
“rs” ?start 300 ?stop 700 ?step 200 ))
paramRun()

Runs a parametric analysis on rl for each value of rs, yielding a nested

parametric analysis.

Parametric Analysis 7-21

Summary
In this module we discussed:
■ An overview of EDFM tools, their uses and properties.

■ Parametric Analysis flow and methodology

■ The Parametric Analysis environment

■ Plotting results

■ Accessing data from Parametric Analysis

■ Model parameters

■ Running Parametric Analysis in OCEAN

Parametric Analysis 7-23

Labs
Lab 7-1 Running Parametric Analysis

Parametric Analysis 7-25

 ®

8 Corners Analysis

Module 8

October 11, 2004

Topics in this Module
■ Introduction to the Corners Analysis tool

■ Corners Analysis Window

■ Adding a new process

■ Modeling styles used for Corners Analysis

■ Results

Corners Analysis 8-3

Corners Analysis Tool
■ The Corners Analysis tool provides useful performance information on a
design by performing multiple simulations under specified conditions.
■ With the Corners Analysis tool, a design is simulated at specified “corners”
where the process parameters, supply voltages, temperature, and other
operating conditions are altered.
■ The Corners Analysis tool is one of five EDFM software tools that operate
within the Virtuoso Analog Design Environment.
■ As an EDFM tool, the Corners Analysis is intended to automatically set up,
run, and analyze multiple simulations. It is used to explore the design space
and locate problem areas.

Corners Analysis 8-5

Corners Analysis Window
Select Tools—Corners from the Simulation window.

Corners Analysis 8-7

Adding a New Process
Select Setup—Add Process from the Corners Window.

Corners Analysis 8-9

Implementing Modeling Styles
Model styles are specified in a .scs file. There are several ways to implement
models:
■ Single-Model Library Style
■ Multiple-Model Library Style
■ Single-Numeric Style
■ Multiple-Numeric Style
■ Multiple-Parametric Modeling

Two additional types of files used are:

■ Process Customization File (pcf)—ends in .pcf
Adds the name of a new process to the Corners tool and defines the basic
set of corners
■ Design Customization File (dcf)—ends in .dcf
Adds design specific variables and measurements to the Corners tool
Load them explicitly, or with the .cdsinit file:
loadPcf( "./CORNERS/multipleModelLib.dcf" )
loadPcf( "./CORNERS/singleModelLib.pcf" )
Corners Analysis 8-11
Single-Model Library Style
Recommended style:
■ All models for all corners are located in a single model file

■ The model file is located in the base directory and can have any name

■ Can also use the .LIB syntax for this style

■ Works with altergroup function in the Spectre simulator

Path: ./models/fab6 library processA
section slowslow
model npn2 npn tf=120n
model npn9 npn tf=320n
Filename: mylibfile.scs model nmosR nmos tox=120n
model nmos8 nmos tox=320n
endsection
section nom
model npn2 npn tf=100n
model npn9 npn tf=300n
model nmosR nmos tox=100n
model nmos8 nmos tox=300n
endsection
section fastfast
model npn2 npn tf=80n
model npn9 npn tf=380n
model nmosR nmos tox=80n
model nmos8 nmos tox=380n
endsection
endlibrary

Corners Analysis 8-13

Multiple-Model Library Style
Similar to Single-Model Library Style
Example: models might be located in the files:
./models/fab6/path1/npn.scs
./models/fab6/path3/nmos.scs

Path: ~/john/models/fab6/path1 Path: ~/john/models/fab6/path3

Filename: npn.scs Filename: nmos.scs
library npn
section slow library nmos
model npn2 bjt tf=120n section slow
model npn8 bjt tf=80n model nmosR mos3 tox=120n
endsection model nmos2 mos3 tox=140n
endsection
section nom
model npn2 bjt tf=100n section nom
model npn8 bjt tf=60n model nmosR mos3 tox=100n
endsection model nmos2 mos3 tox=115n
endsection
section fast
model npn2 bjt tf=80n section fast
model npn8 bjt tf=50n model nmosR mos3 tox=80n
endsection model nmos2 mos3 tox=90n
endlibrary endsection
endlibrary

Corners Analysis 8-15

Other Styles
Not heavily tested or recommended—provided for backward compatibility
■ Single Numeric

Each corner is located in a separate file. If there are four corners, there are
four model files with the same name.

■ Multiple Numeric

Each model is defined in a separate file. All model parameters are defined
with numeric values.

■ Multiple Parametric

With this style, each model is defined in a separate file. There is a

corresponding parameter file for every model associated with each corner.

Corners Analysis 8-17

Corners Results

Corners Analysis 8-19

Corners Results Window
Textual output

Corners Analysis 8-21

Labs
Lab 8-1 Using the Corners Analysis Tool

Corners Analysis 8-23

 ®

9 Monte Carlo Analysis

Module 9

October 11, 2004

Topics in this Module
■ Overview

■ The Monte Carlo tool

■ Statistical modeling

■ Process variation methodology

■ Setting up Monte Carlo analysis

■ Running Monte Carlo analysis

■ Filtering output data

Monte Carlo Analysis 9-3

Overview of Monte Carlo Analysis
The features of the Monte Carlo Analysis Tool include:
■ An EDFM analysis tool

■ Multiple simulation tool using a large number of samples

■ Uses a statistical approach to evaluate the performance of a design

■ Provides broad coverage in exploring the “Design Space”

■ Emulates the variations in model parameters due to process tolerances

■ Very useful in finding “problem areas”

■ Used to predict process yield

The Monte Carlo Tool is based on the “Monte Carlo” analysis technique. This
analysis uses the random selection of model parameters based on statistical
distributions.

Monte Carlo Analysis 9-5

Simulation Using Process Distributions
N=N+1

Random Number Generator Model Files

Select Value From Model Distribution

Modify Parameter Value

Run Simulation

Append Results

No Yes
N = Number of Samples Exit

Monte Carlo Analysis 9-7

Example of Monte Carlo Using Simple LPF

Uniform Distribution Normal or Gaussian Distribution

Monte Carlo Analysis 9-9

Monte Carlo Analysis Environment

(Spectre Only)
Starts with outputs
from the Simulation
window wave, scalar, or
unknown

Select Tools—Monte Carlo in the Simulation Window.

Setup, expression definition, and statistical analysis forms all in a single window.
Monte Carlo Analysis 9-11
Support of Spectre Direct
■ Spectre includes commands for statistical modeling and Monte Carlo
looping within the simulator.
■ Simplified methodology for specifying statistics, correlation, and mismatch.

■ All runs from a single netlist.

■ 5 to 10 times speed improvement over Spectre implementation in the

cdsSpice socket.
■ Online help available with the following command in an xterm window:
spectre -h montecarlo

Note: The following are only available in Spectre Direct Monte Carlo simulations:
■ Distributed processing

■ Save/plot any data or families of curves

Monte Carlo Analysis 9-13

Spectre Direct Statistical Modeling
Several files are used for modeling of process variations:
■ Model file: Contains variables altered by other include files.

■ Variables include file: used to set global variables in prior versions, as in

this example:

simulator lang=spectre
parameters PiRho=2500 PbRho=200 stat=1 npnbeta=145.5
pnpbeta=200 initstat=1

■ Distribution include file: Defines statistical distributions for all variables.

❏ Contains statistics blocks for process and mismatch variations
❏ Types of distributions available: Gaussian, Uniform, Lognormal
❏ Specify process and mismatch correlations
❏ Support of altergroup statement in Spectre simulator

Monte Carlo Analysis 9-15

Statistical Modeling
simulator lang=spectre
parameters PiRho=2500 PbRho=200 npnbeta=250 pnpbeta=80 CAP=.8p

statistics {
process {
vary PbRho dist=lnorm std=40
vary npnbeta dist=gauss std=20
vary pnpbeta dist=gauss std=25
vary CAP dist=gauss std=30 percent=yes
}
mismatch {
vary PbRho dist=lnorm std=3.75
vary npnbeta dist=gauss std=4
vary pnpbeta dist=gauss std=6
} }
inline subckt trnpn (C B E)
model npnstat bjt type=npn is=10e-15 bf=npnbeta \
va=58.7 ik=5.63e-3 rb=565 rbm=86 re=3.2 cje=1.3e-12 pe=0.76 \
me=0.34 tf=249e-12 cjc=0.8e-12 pc=0.55 mc=0.35 ccs=2.4e-12 \
ms=0.35 ps=0.53 rc=169 vsubfwd=10

trnpn (C B E) npnstat
ends trnpn

inline subckt trpnp (C B E)

model pnpstat bjt type=pnp is=1.2e-16 bf=pnpbeta nf=1 vaf=60 ikf=4e-5 \
ne=1.5 br=80 nr=1 var=5 ikr=5e-5 isc=0 nc=1.5 rb=100 re=15 rc=30\
cje=30e-15 vje=.72 mje=.45 tf=5e-10 ptf=40 cjc=60e-15 vjc=.72\
mjc=.45 xcjc=.9 tr=5e-10 cjs=0 vjs=.99 mjs=.99

trpnp (C B E) pnpstat
ends trpnp ...(continued)

Monte Carlo Analysis 9-17

Other Features in Monte Carlo
■ Save data between runs to plot families of curves for all iterations.

This can consume lots of disk space, so select signals appropriately.

■ Outputs selected in Simulation window prior to starting the Monte Carlo tool
are automatically placed in the Output Expressions section
❏ No need to manually re-enter data to be measured/saved
❏ Expressions can be added/edited/deleted

■ Can run specific iterations again

■ Can save the OCEAN script for batch processing

■ Can save and load Monte Carlo setups

A nominal run not required prior to entering expressions.

■ Use the Check Expressions capability.

This helps to determine whether the output expressions and

signals—defined or selected—are valid.

Monte Carlo Analysis 9-19

Monte Carlo Results Analysis

Monte Carlo Analysis 9-21

Monte Carlo Results Analysis (continued)

Monte Carlo Analysis 9-23

Filtering Output Data

Results—Filter

Results—Specification Limits

Monte Carlo Analysis 9-25

Summary
In this module we discussed:
■ Overview of Monte Carlo analysis

■ The Monte Carlo environment

■ Statistical modeling

■ Process variation methodology

■ Setting up Monte Carlo analysis

■ Running Monte Carlo analysis

■ Filtering output data

Monte Carlo Analysis 9-27

Labs
Lab 9-1 Monte Carlo Analysis

Monte Carlo Analysis 9-29

 ®

10 Optimization Analysis

Module 10

October 11, 2004

Topics in this Module
■ Introduction

■ Optimization design flow

■ Optimization computational flow

■ Optimization options form

■ Algorithms used in optimization

■ Adding goals

■ Curve fitting

■ Iteration history

■ Plotting options

■ Optimization using OCEAN

Optimization Analysis 10-3

Introduction to the Circuit Optimizer Tool
■ The Cadence Analog Circuit Optimizer is a software design tool used to find
the optimum values of circuit components.
■ The Optimizer is one of five EDFM design tools. As such, it is intended to
set up and run multiple simulations. The Optimizer is unique in that the
number of simulation runs is unknown. It is also unique in that the simulation
input files are generated by the previous simulation results. The Optimizer
is used to
❏ explore the design space,
❏ establish circuit component values used for the other EDFM tools,
❏ optimize circuit performance, and
❏ develop accurate behavioral models for the circuit.

■ Use the Optimizer to automatically determine component values based on

design goals.
❏ The Optimizer eliminates the need for the tedious tasks of searching for
component values to obtain specified performance (or to prove it is not
feasible).

Optimization Analysis 10-5

Optimization Analysis Flow

Create Schematic

Start Simulation Environment

Tool—Optimization

Goals—Add

Variables—Add/Edit

Optimizer—Run

Analyze Results

Optimization Analysis 10-7

Optimization Computational Flow
Initial Value

Sensitivity
Simulations (N)

Trial
Trial Solution Loop
Simulation 2~3 simulations

No Compute next
Is this acceptable?
trial point.
If (f<f0)
Yes

Is the Goal Yes

Go Home!
reached?

No
Reset
initial value

Optimization Analysis 10-9

Analog Circuit Optimization Option Form

Tools— Optimization

Optimization Analysis 10-11

Optimization Algorithms
CFSQP—C version Feasible Sequential Quadratic Programming
■ CFSQP is suited for a wide variety of optimization problems, including
constrained and unconstrained, minimizing and maximizing, and
sequentially related goals.
Example: Low-noise amplifier design, in which the goals are to specify gain,
minimize noise, and maintain a phase margin greater than 45 degrees.

LSQ—Least Square
■ Only optimization algorithm used in prior versions

■ Good for measured, noisy, unconstrained data.

Example: To design a filter with an output waveform that matches measured

frequency response data (curve fitting).
■ Primarily used for new curve fitting feature.

Algorithm selection is automatic, unless manually specified.

Optimization Analysis 10-13

Adding Goals

Goals—Add

Goals can be scalar or functional:

■ Scalar—a fixed numerical value.

■ Functional—a waveform or more than one point of data.

Data Fields Scalar Goal Functional Goal

Expression Scalar Waveform

Acceptable Scalar Scalar/Waveform

Target Scalar Scalar/Waveform

Optimization Analysis 10-15

Design Variables Menu

Variables—Add/Edit

Optimization Analysis 10-17

Options Menu

Sessions—Options
■ Algorithm Selection: Specify the optimization algorithm.

■ Percentage Finite Difference Perturbation: Set the step length.

■ Relative Design Variable and Function Value Tolerance: Specify the

relative percentage change in values for the stopping criteria for LSQ.
Note: These are expressed as absolute numbers rather than percentages (for instance,
0.05 is equivalent to 5%.)

Optimization Analysis 10-19

Curve Fitting
■ Optimizing circuit output to match a desired waveform (functional goal).

■ Waveform can be a waveform object or a file of x-y data.

■ Many applications
❏ Real circuit used to match an AHDL model
❏ Filter responses
❏ Impedance matching in RF applications
❏ Design scaling and migration
❏ Design centering in order to increase circuit yield
❏ Filter frequency response can be optimized to meet the required
performance
❏ Balance design tradeoffs

Optimization Analysis 10-21

Curve Fitting (continued)
■ When setting goals, use the Acceptable Percentage option:

Acceptable 5 % within Target

A scalar entry gives the same weight to all calculated points.

■ Use a table or a list to weight different parts of a curve to match.

10%

2%
10%
Calculated Acceptable List
Acceptable%
Target
2%

Sweep Parameter

Target 1 4 9 16 25
Acceptable% 10 10 2 2 2
Calculated Acceptable 1.1 4.4 9.18 16.32 25.5

Optimization Analysis 10-23

Curve Fitting to User-Defined Waveforms

Goals—Add

Click the wave button in the calculator and select a waveform, or enter an
expression or table object.

Optimization Analysis 10-25

Iteration History

Optimization Analysis 10-27

Plotting Options

Results—Set Plot Options

Optimization Analysis 10-29

OCEAN Interface
■ Select Session—Save Ocean Script to create an OCEAN script for batch
optimization jobs.
■ The following OCEAN commands have been added to allow optimization
simulations:
optimizeAlgoControl
optimizeGoal
optimizeRun
optimizeVar
optimizePlotOption

Use ocnHelp() for more information on these commands.

Optimization Analysis 10-31

Labs
Lab 10-1 Running Optimization Analysis

Optimization Analysis 10-33

 ®

11 Component Description Format (CDF)

Module 11

October 11, 2004

Topics in this Module
■ Overview of CDF

■ Types of CDF and CDF levels

■ CDF user interface form

■ Editing a component’s parameters using CDF

■ Editing simulation information using CDF

Component Description Format (CDF) 11-3

CDF Overview
CDF is encoded and attached to design database objects. CDF defines
component behavior within the SKILL language.

Add Instance Schematic Editor

Schematic Editor
2
Window Edit Schematic

Label1
Label2
CDF Label3

Skill
Skill
Skill DLE

Simulation Environment
Layout Editor
FrameworkLayout
Tools Mask Layout
3
Window Edit Mask Layout

R:

Component Description Format (CDF) 11-5

Types of CDF
CDF is a part of a library or cell and is always copied with the database object.
CDF attached to a library is adopted by all CDF attached to a cell in a library is specific
cells in the library. to the cell.
CDF
Example: Library
Label Defaults

Library
NPN device Capacitor A

Cell A Cell C Capacitor C

CDF CDF
Cell B CDF

Cell CDF masks the Library CDF to produce an Effective result.

+ =

Library Cell Effective Cell

The Effective Cell CDF exists only in virtual memory.
Component Description Format (CDF) 11-7
Levels of the CDF
1
Base
Library
2 User Base 4
3 User 5
Effective Cell 6
Effective
7
Instance

Base CDF is stored on disk. User CDF is a user-defined mask in virtual memory.
The Effective CDF is the result of the user mask redefining the Base CDF.

+ =

Base User Effective

The highest Effective level of CDF is used by the system. The highest level of
CDF is the overlapping summation of all the CDFs at lower levels.
Component Description Format (CDF) 11-9
The CDF User Interface Form

In the CIW, select

Tools—CDF—Edit.

NOTE:
This is a long form
that also includes
entry fields for
“Interpreted Labels
Information” and
“Other Information”

Component Description Format (CDF) 11-11

Editing Component Parameters in the CDF

■ Click Add to add new component parameters.

■ Click Move to change the order of listed parameters.

Component Description Format (CDF) 11-13
Editing Simulation Information in the CDF

This is the Spectre simulation information for a 4-terminal NMOS with a model
parameter area1 (in addition to others) that is passed to the model file.
There is a Simulation Information section for each simulator.

Component Description Format (CDF) 11-15

Editing Simulation Information in the CDF (continued)
Set the instParameters field for the Spectre simulator to pass information from the
design to a parameterized model by the following:
1. Create a parameterized model file (inline subcircuit):
inline subckt mynmos4 (d g s b)
parameters area1 = 10
mynmos4 (d g s b) trnmos1 l=sqrt(area1)*1e-6 w=10*sqrt(area1)*1e-6
model trnmos1 mos2 type=n vto=(area1/100)*0.775 tox=400e-10 nsub=8e+15\ ...

2. Define CDF component parameters or add a User Property that passes to

the model file. Example: area1
3. List the component parameters in the instParameters field of the Simulation
Information Section. Example: instParameters =area1
4. Set the componentName=Model Name, OR set a value for the model
component parameter and set otherParameters=model.
Set or reset the model parameter value when placing a component instance.
The netlister sets the value of each parameter for each instance that uses the
model file.

Component Description Format (CDF) 11-17

Summary
In this module we discussed:
■ Overview of CDFs

■ That CDF information is used to provide data between DFII design tools

■ The types of CDFs and CDF Levels

■ How to use the CDF user interface form

■ Editing a component’s parameters using CDF

■ Editing simulation information using CDF

Component Description Format (CDF) 11-19

Labs
Lab 11-1 The CDF User Interface

Lab 11-2 CDF Effects in Simulation

Component Description Format (CDF) 11-21

 ®

12 Macromodels, Subcircuits, and Inline Subcircuits

Module 12

October 11, 2004

Topics in this Module
■ Overview of Macromodels, Subcircuits, and Inline Subcircuits

■ Macromodels

■ Subcircuits

■ Library requirements to use Subcircuits

■ Inline Subcircuits

■ Inline Subcircuit example: Parasitic Devices

■ Advantages of Inline Subcircuits

■ Generalized Binning

Macromodels, Subcircuits, and Inline Subcircuits 12-3

Overview
Macromodels and subcircuits provide high-level descriptions of a cell block.
The macromodel is a behavioral representation of a circuit that is either a
schematic or a text file.
When the macromodel is described with a text file, it is called a subcircuit.

Inline subcircuits are special-case subcircuits where one device has the same
name as the instantiated subcircuit. Use inline subcircuits to:
1. Override model parameters based on the instance parameter.
2. Place virtual components such as a parasitic BJT.
3. Select a component based on instance parameter.

Macromodels, Subcircuits, and Inline Subcircuits 12-5

Advantages of Inline Subcircuits
Advantages of Inline Subcircuits versus a conditional if statement in the Spectre
environment:
■ No need to redefine the instance name, such as mospar.

■ Component shows up in postprocessing tools (Results Browser) with its

instantiated name, rather than a hierarchical name.
■ Allows annotation of operating points in the Virtuoso Analog Design
Environment.
■ Supports binning of models.

■ Supports parasitic modeling.

For example, add parasitics to a component by changing a model card to an

inline subcircuit.

Macromodels, Subcircuits, and Inline Subcircuits 12-7

Macromodels and Subcircuits
A graphic instance can be described by a schematic, a macromodel, or a
user-defined text file called a subcircuit file. The file is a subcircuit description.

IN+ Symbol Schematic

View Macromodels Macromodel

OUT
IN-

Schematic
View
Textual Macromodel
parameters inputCap=500e-15
C1 (plus minus) capacitor c=inputCap
E1 (aout 0 plus minus) vcvs gain=1e6
R3 (aout output) 100e-3
R4 (plus minus) 10e6
ends

A macromodel description or subcircuit file in the final simulation netlist will simulate
faster than the schematic circuit description.
The parameter inputCap allows the capacitor C1 to have the value passed into the
subcircuit when the symbol is instantiated in a schematic.

Macromodels, Subcircuits, and Inline Subcircuits 12-9

Library Requirements to Use Subcircuits
Cells referencing a user-defined subcircuit file require cellviews with:
■ A symbol view.

Create this using the symbol editor. Add symbol pins and a shape.
■ A cellview identifying the cell as a primitive component.

Copy the symbol cellview to one that has the name of the simulator you
are using, such as Spectre, Spectre S, cdsSpice.
■ A cell CDF that contains the name of the subcircuit file and defines any
parameters that are passed to the file.
■ Pins on the subcircuit text that correspond to those on the symbol.

■ Any other parameters to be defined.

■ A subcircuit file can be defined in the Library Model File.

Macromodels, Subcircuits, and Inline Subcircuits 12-11

Inline Subcircuits
Inline subcircuits are an enhancement available only with the Spectre Direct
simulator.
■ Customization of component parameters

Allows access to model parameters from the instance line

■ Virtual Components

Example: Parasitic BJT

Example: Parasitic Estimation
■ Automatic selection of components based on any instance parameter

Macromodels, Subcircuits, and Inline Subcircuits 12-13

Inline Subcircuit Example: Parasitic Devices
inline subckt bjtpar (c b e )
parameters we=10u le=10u // emitter width, length
model npnmod bjt bf=1e3*(we*le/1e-10) is=1e-6*(we+le...)
...
bjtpar (c b e s) npnmod // the inline component
qpar (s c b) parpnp // parasitic device
model parpnp bjt type=pnp.. // model for parasitic
ends bjtpar
Model parameters based
// instantiate with: on instance parameters
q0 (1 2 3) bjtpar we=5u le=2u

Inline subckt masquerades

as a simple BJT.

Macromodels, Subcircuits, and Inline Subcircuits 12-15

Inline Subcircuit Example: Parasitic Estimation
inline subckt mospar (d g s b)
parameters mym=1 min=0 drainwidth=(0.4+0.25+0.3)*1e-6
+sourcewidth =(0.4+0.25+0.3)*1e-6 l=1u
if (min==0)
{mospar d g s b nch ad=mym*l*drainwidth as=
mym*l*sourcewidth
} else if (min==1)
{mospar d g s b nch ad=mym*l*drainwidth as= l*sourcewidth
} else
{mospar d g s b nch ad=l*drainwidth as= mym*l*sourcewidth
}
model nch bsim3v3
ends mospar
Geometry selection based
on instance parameter

Macromodels, Subcircuits, and Inline Subcircuits 12-17

Generalized Binning
inline subckt NPNmod (c b e s)
parameters area=5e-12
if ( area < 100e-12 ) {
Model selection
NPNmod (c b e s) npn10x10
based on
} else if ( area < 400e-12 ) { Instance Parameter
NPNmod (c b e s) npn20x20
} else { NPNmod (c b e s) npn_default }
model npn_default bjt is=3.2e-16 va=59.8
model npn10x10 bjt is=3.5e-16 va=61.5
model npn20x20 bjt is=3.77e-16 va=60.5
ends NPNmod
q1 (1 2 0 0) NPNmod area=350e-12 // gets npn20x20 model
q2 (1 3 0 0) NPNmod area=25e-12 // gets npn10x10 model
q3 (1 3 0 0) NPNmod area=1000e-12 // gets npn_default model

Macromodels, Subcircuits, and Inline Subcircuits 12-19

Using Inlines with the Virtuoso Analog Design
Environment
To use inline subckts in the Virtuoso Analog Design Environment with a primitive
device:
■ Write the text of the inline subckt.

■ Place the component in the schematic.

■ Do one of the following:

❏ Using the CDF editor, create a parameter called model. Set a default
value for this parameter in the Edit Component CDF form or set the value
at the time you place the component in a schematic.
❏ Set the base CDF Spectre simInfo field componentName to the name of
the inline subckt.
❏ Add the model parameter as a User Property to the Edit Object
Properties form with a value that is the name of the inline subckt.
■ Add any additional parameters needed as instanceParams in the simInfo
section of the CDF.

Macromodels, Subcircuits, and Inline Subcircuits 12-21

Labs
Lab 12-1 Creating a Parasitic Transistor Model

Lab 12-2 Using Subcircuit Cells

Lab 12-3 Adding a Subcircuit Representation

Macromodels, Subcircuits, and Inline Subcircuits 12-23

 ®

13 Inherited Connections

Module 13

October 11, 2004

Topics in this Module
■ Applications of inherited connections

■ Setting net expressions and using the netSet property

■ Netlist and Run with inherited connections

Inherited Connections 13-3

Applications of Inherited Connections
Use inherited connections to:
■ Defer where a net is attached until a cell that contains that net is used in the
design hierarchy.
■ Change the attach point on the fly by changing an instance property.

■ Affect many points down a hierarchy with the change of only one parameter.

■ Provide a programmable net capability.

Inherited Connections enhances the link between the physical and logical
tool flows.
Inherited Connections help to solve:
■ Library Duplication—A cell can be designed with the power supplies left as
inherited connections.
■ Substrate Connections—Inherited connections provides a solution that
works in both the physical and logical design space.
■ Inherited Terminals—With inherited connections, add extra terminals to the
layout views that are not hard coded.

Inherited Connections 13-5

Features of Inherited Connections
■ Inherited Connections allow you to create global signals and override their
names for selected branches of the design hierarchy.
■ Inherited Connections enable you to:
❏ Use multiple power supplies in a design.
❏ Add overridable substrate connections.
❏ Parameterize power and ground symbols.

■ This override information can be accessed by other Cadence® tools across

the design flow.
■ Sample library and tutorial
<instal_dir>/tools/dfII/samples/tutorials/inhconn

Inherited Connections 13-7

Defining Inherited Connections
■ Add a net expression label to either a pin or a wire to define an inherited
connection.
■ The net expression defines a default global signal name for the connection
and the name of the property overrides the global signal name.

Example Net Expression Add—Net Expression

[@power:%:vdd!]

Property name Default global signal name

Example Net Expression Labels

[@gnd:%:gnd!]

[@vdd:%:vdd!]

Symbol pin with Schematic wire with

a net expression a net expression

■ The basic library contains sample power and ground symbols.

Inherited Connections 13-9

Setting a Net Expression

Select the wire.

Add—Net Expression

Inherited Connections 13-11

Override Default with the netSet Property

All override global

names must be
assigned at the
level of hierarchy
where used.

Portion of I5
schematic 3.3V!

3.3V!
3
4
mygnd!

Inherited Connections 13-13

Netlisting with Inherited Connections

[@p1:%:vdd1!]
A Y

[@p2:%:vss1!]

Cellview A1
Cellview with Inherited Connections

When netlisted, two pseudo ports are created, because it has two inherited
connections for the supplies.

Pport [@p1:%:vdd1!] Pport [@p2:%:vss1!]

Rport A Rport Y

Rport = “Real” port

Pport = “Pseudo” port Cellview A1

Inherited Connections 13-15

Evaluating Net Expressions

netSet property value =

new net name

found
not found Default net name
specified in the net
expression

No instance found that

has a matching property
name.

System searches up the

hierarchy for a specified
Cellview containing the property.
net expression

Note: Place the netSet property on any instances at any level above the cellviews with
net expressions.

Inherited Connections 13-17

Labs
Lab 13-1 Inherited Connections

Lab 13-2 Using Inherited Connections with the ampTest Design

Inherited Connections 13-19

 ®

14 The Hierarchy Editor

Module 14

October 11, 2004

Topics in this Module
■ Applications of the Hierarchy Editor

■ Overview

■ Creating a configuration

■ The Hierarchy Editor window

■ Selecting views with the Hierarchy Editor

■ The tree view of a Hierarchy

■ Opening a configuration

■ Synchronizing a configured schematic

The Hierarchy Editor 14-3

Applications for the Hierarchy Editor
The Hierarchy Editor is used to select the view to be used within a system
hierarchy.
In the design of a circuit used within a system, there are numerous phases of the
design flow. Each phase of the design has cell views associated to that step. The
Hierarchy Editor is a tool that selects the corresponding cell view for display and
for netlisting the design. The Hierarchy Editor is used extremely useful in system
level design, mixed signal design, and for parasitic analysis.

System Behavioral Mixed-Hierarchy Topology

Front Definition Simulation Design Selection
(ahdl) (ahdl) (schematic) (schem1)
(veriloga) (veriloga) (veriloga) (schem2)

Component Physical Parasitic

Values & Design Back
Analysis
Optimization (schematic) (schematic)
(schematic) (layout) (analog_extracted)

FRONT-TO-BACK FLOW

The Hierarchy Editor 14-5

Overview of the Hierarchy Editor
The Hierarchy Editor (HED) is a graphical tool for creating configurations.

designLib

peakDetect Root cell

Directories that contain
configuration files
schematic layout config mixedConfig Design
Framework II
view

pc.db sch.cdb pc.db layout.cdb expand.cfg expand.cfg UNIX view

Configuration: A set of rules that defines how cellviews in a design are

partitioned and netlisted.

The Hierarchy Editor 14-7

Creating a Configuration
1 File—New—Cellview 4 Select simulator name
for template desired.

Select Spectre,
then OK in form
2 Change myView to
schematic, OK the form.
Set to Hierarchy-Editor

3
Select template

The Hierarchy Editor 14-9

The Hierarchy Editor Window

When this icon is

RED, select it to
incorporate the
selections.

View Lists can be

replaced with a
constant, such as
$analog.

The Hierarchy Editor 14-11

Selecting Views with the HED
The banner prompts to
save the new configuration.

Click the Update icon

to put changes into effect.

The new Cell Binding

The Hierarchy Editor 14-13

HED Tree Format

View tree from here.

The Hierarchy Editor 14-15

Opening a Configured Schematic
Click Open

New Information in Schematic Title Bar

Open a Configured Schematic:

■ From the Open button in the Hierarchy Editor

■ Using the File—Open command in the CIW as you open the config view.

■ Using the Library Manager when you open the config view.
The Hierarchy Editor 14-17
Synchronizing the Configured Schematic
The configured schematic might not match the current configuration file.

To synchronize the configuration schematic to the configured file:

■ Click the Update button after modifying the configuration.

■ Click OK in the Cellviews Need Saving form that appears.

The Hierarchy Editor 14-19

Summary
In this module we discussed:
■ Applications for using the Hierarchy Editor

■ Overview

■ How to create a configuration

■ Selecting views in the Hierarchy Editor and saving the new configuration

■ Opening the configuration to view the hierarchy

■ Running a simulation on the configured schematic

The Hierarchy Editor 14-21

Labs
Lab 14-1 Creating a Configuration File with the Hierarchy Editor

Lab 14-2 Running a Simulation with Subcircuits

Lab 14-3 Rerunning Simulation with the Schematic View

The Hierarchy Editor 14-23

 ®

15 Overview of Parasitic Simulation

Module 15

October 11, 2004

Topics in this Module
■ Background of parasitic simulation

■ Brief overview

■ Design flow

■ Supported layout software

■ Diva and Assura

■ What happens in parasitic simulation

■ An actual parasitic simulation flow

■ Summary

Overview of Parasitic Simulation 15-3

Background
In previous chapters, a large amount of time and effort is applied to designing a
circuit that realizes specific design goals. During the design phase of the circuit,
there was no allowance for the parasitic capacitance and for the resistance of
interconnecting the components of the schematic. Such “interconnect parasitics”
typically cause a 10 to 20 percent increase in the delay times of a circuit and a
corresponding reduction in bandwidth.
To ensure the product meets the specific design goals, the following options are
available:
■ “Over design” or “guard band” the design by using larger devices and
increasing power consumption.
■ Carefully measure and analyze the interconnect parasitics after layout has
been completed and resimulate the design.
■ Run a parasitic extraction simulation on the layout and resimulate the
design.
The first and second options have disadvantages. The first consumes more
power and is at risk for not meeting the design goals. The second option is work
intensive, and is also at risk for errors to occur.
Parasitic extraction requires less time, effort, and is more reliable.
Overview of Parasitic Simulation 15-5
Overview of Parasitic Analysis
Why Is Parasitic Extraction and Simulation Needed?

Fabricated Circuit,
Original Circuit Design Fails to Operate at
Submitted to Layout Specified Frequency!

delay = 1ns delay = 3ns

Simulation without parasitics Simulation with parasitics

Overview of Parasitic Simulation 15-7

Supported Layout Software
The Virtuoso Analog Design Environment, version 5.1.41, supports parasitic
extraction and simulation for:
■ Assura, which is documented in Module 16.

■ Diva, which is documented in Appendix A

Background
Prior to IC 4.4.6, only Diva layout extraction and parasitic simulation was
supported.
■ Diva is now associated for the layout of small circuits.

■ Assura is now replacing Diva in more and more design flows for large
circuits.
■ There is a genuine need for parasitic extraction and simulation tool.

Overview of Parasitic Simulation 15-9

What Happens in Parasitic Simulation?
extracted layout parasitic
“netlist”

design schematic 4

2
test fixture schematic

Overview of Parasitic Simulation 15-11

An Actual Parasitic Simulation Flow

1 2 3
Extract & Run LVS
Create schematic Create layout on design
for design for design (or subblocks)

4 5 6
Create Create test fixture Choose views
in configuration
analog_extracted schematic & (Netlist with or
view of design configuration without Parasitics)

Backannotate

Parasitic
Probe 7 8
Schematic
Run Simulation Waveform Analysis

optional Extracted
Waveform Analysis

Overview of Parasitic Simulation 15-13

Summary
Topics in this module
■ Background of parasitic simulation

■ Brief overview

■ Design flow

■ Supported layout software

■ Diva and Assura

■ What happens in parasitic simulation

■ An actual parasitic simulation flow

Overview of Parasitic Simulation 15-15

Labs
Lab 15-1 Simulating a Schematic Without Parasitics

Overview of Parasitic Simulation 15-17

 ®

16 Assura Parasitic Simulation Flow

Module 16

October 11, 2004

Topics in this Module
■ Overview and background to Assura parasitic simulation

■ Introduction to Assura

■ Schematic requirements

■ LVS requirements and results

■ Parasitic simulation messages and options

■ Selective parasitic simulation

Assura Parasitic Simulation Flow 16-3

Assura in ADE
What is the Assura?
■ Cadence’s next-generation physical verification tool

■ Very similar in concept to Diva

■ Documentation: Chapter 4 of the Cadence Parasitic Simulation User Guide

Why is it needed?
■ Allows extraction of designs that are too large for Diva to extract in a
reasonable amount of time
■ Will support AMS Designer and be the primary extraction tool

Assura Parasitic Simulation Flow 16-5

Assura Flow in Virtuoso Analog Design Environment
The ADE flow using Assura is very similar to the current Diva-driven flow, except
that, instead of Diva, Assura is used to perform layout connectivity, parasitic
extraction, and extracted view creation.
■ Once the extracted view has been created, you can access the Parasitics
menu to create Refined Views or annotate parasitic information.
■ This menu allows you to specify the library, cell, and view for both the
schematic and extracted views. Once these fields are set, you can perform
the same functions found in the Diva flow: Backannotate, Refine View (Build
Analog).
■ The functionality is the same as the current Diva-based flow; however, the
underlying callbacks have been changed to operate on the
Assura-generated extracted view.
■ In addition, the av_analog_extracted and av_extracted views resulting from
the Refine Extracted View allows configured simulation using different
parasitics.
Aside from the existence of this new property, the primary difference is that the
Assura-generated extracted view will use mapped algorithmically hierarchical
schematic names for instances and nets.

Assura Parasitic Simulation Flow 16-7

Assura Design Flow

1 2 3 Assura
Create schematic Create layout 3.1 Run Assura LVS
for design for design 3.2 Run Assura RCX

4 Parasitics
5 6
Create test fixture Choose views
schematic & in configuration
configuration (Netlist with or
without Parasitics)

Backannotate

Probe
7 8
Schematic
Run Simulation Waveform Analysis

Extracted
Waveform Analysis

Assura Parasitic Simulation Flow 16-9

Design Schematic
1
Create schematic
for design

inv
design schematic schematic

Assura Parasitic Simulation Flow 16-11

Design Layout
2
Create layout
for design

inv
layout

design layout

Assura Parasitic Simulation Flow 16-13

Accessing the Assura Commands
2 You are 3
here! Assura
Create layout 3.1 Run Assura LVS
for design
3.2 Run Assura RCX

Assura
pull-down
menu

Run LVS...
Starts the
Assura Run LVS form

Run RCX...
is enabled only after
completing LVS

Assura Parasitic Simulation Flow 16-15

LVS in Assura
3 Assura
3.1 Run Assura LVS
3.2 Run Assura RCX

Assura—Run LVS...

Assura Parasitic Simulation Flow 16-17

Run RCX in Assura
3
Assura
3.1 Run Assura LVS
3.2 Run Assura RCX

Assura Parasitic Simulation Flow 16-19

Assura RCX Output

3 Assura
3.1 Run Assura LVS
3.2 Run Assura RCX

extracted view

Run Assura RCX

design layout

Assura Parasitic Simulation Flow 16-21

Creating av_analog_extracted
4
Parasitics
4.1 Layout/Schematic
4.2 Refine Extracted View The Parasitics menu becomes
available by selecting:
av_analog_extracted created
Tools--Parasitics from the Layout
or Schematic window.
Backannotate

Probe

Parasitics--Refine Extracted View

Assura Parasitic Simulation Flow 16-23

Create Test Fixture Schematic and Configuration
5
Create test fixture
schematic &
configuration

design schematic

test fixture schematic

Assura Parasitic Simulation Flow 16-25

Choose Views in Configuration
6
Choose views
in configuration
(Netlist with or
without Parasitics) Netlist without Netlist with
parasitics parasitics

Assura Parasitic Simulation Flow 16-27

Running Simulation
7
Run Simulation
1. Open the configured schematic from the HED.

2. Start ADE from the configured schematic and run the simulation.

delay = 1ns delay = 3ns

Simulation without parasitics Simulation with parasitics

Assura Parasitic Simulation Flow 16-29

Waveform Analysis
8
Schematic
Waveform Analysis
Extracted
Waveform Analysis

You can choose waveforms in either the schematic or extracted layout:

Assura Parasitic Simulation Flow 16-31

Labs
Lab 16-1 Parasitic Simulation Flow

Assura Parasitic Simulation Flow 16-33

 ®

A Diva Parasitic Simulation Flow

Module A

October 11, 2004

Topics in this Module
■ Overview

■ Design flow

■ Schematic requirements

■ LVS requirements and results

■ Parasitic simulation messages and options

■ Selective parasitic simulation

Diva Parasitic Simulation Flow A-3

Diva Parasitic Extraction
The Diva flow for parasitic extraction is also supported by the Virtuoso Analog
Design Environment. This module is included for the following reasons:
■ For those facilities where Diva is used and Assura is not installed.

■ For classes at the customer sites where Diva is used.

■ For classes at customer sites where Diva is specifically requested.

■ For special circumstances, such as when the class is presented by an

instructor who is not familiar with the Assura tool.
All versions of the Virtuoso Analog Design Environment as well as the previous
versions of the Analog Artist environment support parasitic simulation using Diva.
The Assura parasitic simulation flow has only been available since the release of
IC-4.4.6.
The Diva and Assura parasitic simulation flows have only minor differences.

Diva Parasitic Simulation Flow A-5

Diva Design Flow with Parasitic Simulation

1 2 3
Extract & Run LVS
Create schematic Create layout on design
for design for design (or subblocks)

4 5 6
Build Create test fixture Choose views
in configuration
analog_extracted schematic & (Netlist with or
view of design configuration without Parasitics)

Backannotate

Parasitic
Probe 7 8
Schematic
Run Simulation Waveform Analysis

optional Extracted
Waveform Analysis

Diva Parasitic Simulation Flow A-7

Design Schematic
1
Create schematic
for design

inv
design schematic schematic

Diva Parasitic Simulation Flow A-9

Design Layout
2
Create layout
for design

inv
layout

design layout

Diva Parasitic Simulation Flow A-11

Extraction and LVS
3 extracted design layout
Extract & Run LVS
on design
(or subblocks)

LVS

design schematic

inv
schematic

extracted
LVS inv
layout

Diva Parasitic Simulation Flow A-13

Building analog_extracted
4
Build
analog_extracted
view of design
Do not close the LVS form,
Backannotate but you can iconify it.
Bottom of LVS form:
Parasitic
Probe

Diva Parasitic Simulation Flow A-15

Selective Parasitic Simulation
■ Nets are identified in the schematic using sbaLib components:

Cap to Cap between Series

gnd nets resistor

■ Enabled by set from sch button on Build analog_extracted View form

all parasitics selected parasitics

Diva Parasitic Simulation Flow A-17

Backannotation
4
Build
analog_extracted
view of design

Backannotate

Parasitic
Probe

Diva Parasitic Simulation Flow A-19

Parasitic Probing
4 Bottom of LVS form:
Build
analog_extracted
view of design

Backannotate

Parasitic
Probe

extracted layout

Diva Parasitic Simulation Flow A-21

Create Test Fixture Schematic and Configuration
5
Create test fixture
schematic &
configuration

design schematic

test fixture schematic

Diva Parasitic Simulation Flow A-23

Choose Views in Configuration
6
Choose views
in configuration
(Netlist with or
without Parasitics)

Diva Parasitic Simulation Flow A-25

Running Simulation
7
Run Simulation
1. Open config view of test fixture.

2. Run simulation from the configured schematic view.

delay = 1ns delay = 3ns

Simulation without parasitics Simulation with parasitics

Diva Parasitic Simulation Flow A-27

Waveform Analysis
8
Schematic
Waveform Analysis
Extracted
Waveform Analysis

You can choose waveforms in either the schematic or extracted layout:

Diva Parasitic Simulation Flow A-29

Layout Waveform Analysis
8
Schematic
Waveform Analysis
Extracted
Waveform Analysis
Probed net in extracted
view yields waveform.

poly1 shape
not probed

Probe pins or nets in the extracted layout:

Choose pins or layer shapes for which parasitic devices were not extracted.

Diva Parasitic Simulation Flow A-31

Schematic Waveform Analysis
8
Schematic
Waveform Analysis
Extracted
Waveform Analysis

Use the schematic as a representation of the final netlist:

+ Pin1 Pin2

Click on a wire close to a terminal (not on the terminal)

An X in the schematic indicates the corresponding node probed in the final netlist:

+ Pin2
Pin1

Node referenced in the final simulation netlist:

Diva Parasitic Simulation Flow A-33

Labs
Lab A-1 Simulating a Schematic with Parasitics Using the Diva Layout Flow

Diva Parasitic Simulation Flow A-35

 ®

B Match Analysis, dcmatch

Module B

October 11, 2004

Topics in this Module
■ Special modeling requirements

■ Introduction to device mismatch

■ Effects of device mismatch on analog circuits

■ Design considerations

■ Layout matching

■ dcmatch analysis flow

Match Analysis, dcmatch B-3

Overview of Device Mismatch
■ Two devices “replicated” on the same chip are never identical. To some
degree, differences in the electrical properties of the two devices always
occurs.
■ In a large array of devices replicated on the same chip, no device is identical
to any of the other device. Again, the electrical properties will be different.
■ Mismatches are produced by random processes, and produce the following
effects:
❏ Undesired effects in analog circuits.
❏ Offset errors in comparators and amplifiers
❏ Voltage distributions in band-gap reference
❏ DNL and INL in DACs and ADCs.

■ In simulation, devices are often modeled using identical numerical values

and expressions for the electrical behavior.
■ Simulations often fail to include the effects of mismatch.

■ Precise values of mismatch cannot be predicted.

■ Statistical methods are used to analyze mismatch.

Match Analysis, dcmatch B-5

Design Considerations
Numerous factors either increase or reduce mismatch errors.
These include:
■ Layout dimensions (width and length)

■ Matched physical layout

■ Orientation (rotation, mirror image, misalignment, etc.)

■ Spatial separation (distance between replicated devices)

■ Proximity effects (how close are other unrelated devices)

■ Common centroid techniques (1 and 2 dimensional arrays)

■ Dummy devices

■ Contact resistance

■ Package stress and “edge effects”

Important
These effects shall also influence the model extraction for the mismatch analysis.

Match Analysis, dcmatch B-7

Layout Matching
Matched W and L DU
Matched layout
1300 ohms 1B
Matched orientation
Aligned in Y
1200 ohms 2B

Gradient
Matched W and L 1100 ohms 2A
Matched layout
Mirror orientation! 1000 ohms 1A
Aligned in Y
DL
Matched W and L The 1-Dimensional Array
Matched layout
Rotated orientation! Common Centroid Design
The 2-Dimensional Array
DU DU
Matched W and L
Matched layout 3B 4B
Matched orientation
Misalignment X and Y! 1B 2B

2A 1A
Matched W and L
Unmatched layout! 4A 3A
Matched orientation
Aligned in Y
DL DL

Match Analysis, dcmatch B-9

Special Modeling Requirements for dcmatch
The dcmatch analysis has been added to the Choosing Analysis form. It is
important to know that this new analysis has special model requirements. The
dcmatch analysis works with bsim3v3, bsim4, res, vbic.
The lab activity for this module uses bsim3v3. You will be instructed to view the
model file. The mismatch model parameters shown have been extracted for a
specified process. The model extraction for these parameters is unique to that
process only.
The dcmatch parameters are unique to a specific process. To work properly, the
dcmatch model parameters must be properly extracted for the process used.
When this manual was written very few fabrication facilities supported extraction
of these model parameters.
In addition to the statistical properties of the fabrication facility, the geometric
conditions discussed must be included with the model extraction. Using different
geometric conditions shall alter NMOS and PMOS mismatch model parameters.

Match Analysis, dcmatch B-11

Starting the dcmatch Analysis
From the simulation window, select: Analyses—Choose...
The Choosing Analyses form appears.
In the form select dcmatch.

1. Select this button!

2. The form changes to

allow input of dcmatch
information.

3. Use these
buttons to select
nodes on the
schematic.

4. For a dc sweep
select one of these
buttons.

Match Analysis, dcmatch B-13

dcmatch Analysis Selection

Select OK or Apply in the Choosing Analysis form.

Then verify the dcmatch analysis appears in the

Analyses field of the simulation window.

Match Analysis, dcmatch B-15

Labs
Lab B-1 dcmatch

Match Analysis, dcmatch B-17

 ®

C Advanced Topics in ADE

Module C

October 11, 2004

Topics in this Module
■ Overview of advanced topics

■ Applications of inherited connections

■ Setting net expressions and using the netSet property

■ Netlist and Run with inherited connections

■ Introduction to Verilog-A

■ Introduction to the Mixed Signal Design Environment

Advanced Topics in ADE C-3

Overview of Advanced Topics
This optional module provides instruction on the advanced features of the
Virtuoso Analog Design Environment. The covered topics include:
■ Introduction to Verilog-A

■ Introduction to Mixed Signal Design Environment

Note that the Virtuoso Analog Design Environment is a gateway to using

Verilog-A and the Mixed Signal Design Environment.
■ Classes are provided by Cadence Education Services.

Advanced Topics in ADE C-5

Introduction to Verilog-A
The Verilog®-A Language
■ Is an extension of the Verilog language (with many HDL constructs from the Verilog
language) used to describe analog/mixed signal models, and is an Open Verilog
International (OVI) standard.
■ Is a multidiscipline language that models electrical, mechanical, fluid dynamic, and
thermodynamic systems.
■ Is used with the Virtuoso Spectre Circuit Simulator in the Virtuoso Analog Design
Environment, in the Analog Workbench (AWB), AMS Designer, or in a standalone
mode.
■ Supported simulators in the Virtuoso Analog Design Environment:
❏ Spectre—known as Spectre Direct simulator
❏ Spectre Verilog—mixed Spectre Direct and Verilog-XL simulators
❏ Spectre S—socketed Spectre simulator
❏ Spectre S Verilog—socketed Spectre and Verilog-XL simulators
■ Supports top-down design
❏ Easy to learn and use
❏ Easy to transition from abstract to detailed models

Advanced Topics in ADE C-7

The Verilog-A Module
A code example of a behavioral Verilog-A module

`include "constants.h"
Include natures, `include "disciplines.h"
disciplines, & constants
module res1(p, n);
inout p, n;
Interface Declarations electrical p, n;
parameter real r=1 from (0:inf);
parameter real tc=1.5m from [0:3m);

real reff;
analog begin
@(initial_step) begin
Module Scope reff = r*(1+tc*$temperature);
end
I(p, n) <+ V(p, n)/reff ;
end
endmodule
Behavioral Description

Advanced Topics in ADE C-9

Advantages of Verilog-A
■ Verilog-A is a behavioral language that simulates faster than structural.

■ Can be used to simulate almost anything in Spectre, including:

❏ Mechanical structures
❏ Fluid dynamic systems
❏ Thermodynamic
❏ Magnetic and electromagnetic structures

■ Verilog-A is a modeling language that is easy to learn. Cadence Educational

Services provides both classroom and internet training.
■ Verilog-A modules are very easy to use.

■ Extensive Library support

<install_dir>/tools/dfII/samples/artist/ahdlLib
<install_dir>/tools/dfII/samples/artist/rfLib
<install_dir>/tools/dfII/samples/artist/spectreHDL/Verilog-A

The libraries contain hundreds of samples of predesigned Verilog-A

modules for common circuit structures.
■ Development tools include Modelwriter and AHDL Debugger
Advanced Topics in ADE C-11
Introduction to Mixed Signal Design Environment
Mixed Signal Design Environment

Analog Design Environment

Spectre IPC Verilog-XL

Logic Simulator
Circuit Simulator
(LDV)

Simulation Output Database

The above diagram shows a conceptual overview of the Mixed Signal Design
Environment. MSDE is actually a software extension of the Virtuoso Analog
Design Environment. When LDV is installed along with a valid LDV license file,
then the MSDE extension of Virtuoso Analog Design Environment is enabled.

Advanced Topics in ADE C-13

Advantages of Mixed Signal Design Environment

1. True mixed signal simulation

and waveforms.

2. Mixed Signal Parasitic Simulation.

3. Backannotation.

4. Works with Verilog-A.

Advanced Topics in ADE C-15

Mixed Signal Design Environment and Verilog-A
Analog Design Environment
(IC) Design

Schematic
Verilog Spectre Verilog-A Verilog-A &
HDL Netlist Netlist SpectreHDL
Behavioral

Behavior
Models

Spectre
IPC
Circuit Spectre/
Verilog-XL Simulator
(LDV) SPICE
(IC) Primitives

Advanced Topics in ADE C-17

Labs
Lab C-1 Verilog-A Overview

Advanced Topics in ADE C-19