AN4088

Application note
Migrating between STM32F1 and STM32F0 series microcontrollers

Introduction
For designers of STM32 microcontroller applications, it is important to be able to easily
replace one microcontroller type by another within the same product family. One key
advantage of STM32 microcontrollers is their simplified porting thanks to a strong focus on
compatibility across the portfolio. Migrating an application to a different microcontroller is
often needed to fulfill higher product requirements more demanding on memory size or with
increased number of I/Os. Cost reduction is another reason for change to smaller
components and shrunk PCB area.
This application note is written to help users with the analysis of the steps required to
migrate from an existing STM32F1 series device to an STM32F0 series device. It gathers
the most important information and lists the mandatory aspects that users need to address.
To migrate an application from STM32F1 series to STM32F0 series, users have to analyze
the hardware migration, the peripheral migration and the firmware migration.
To benefit fully from the information included in this application note, users should be
familiar with the STM32 microcontroller family. Refer to the following documents available
from www.st.com.
 STM32F1xx family reference manuals (RM0008 and RM0041), STM32F1xx product
datasheets, and STM32F1xx Flash programming manuals (PM0075, PM0063 and
PM0068).
 STM32F0xx family reference manuals (RM0091 and RM0360) and STM32F0xx
product datasheets.
For an overview of the whole STM32 series and a comparison of the different features of
each STM32 product series, please refer to AN3364 Migration and compatibility guidelines
for STM32 microcontroller applications.
Table 1 lists the microcontrollers and development tools addressed by this application note.

Table 1. Applicable products

Type Part numbers

STM32F0 series,
Microcontroller
STM32F1 series.

Note: The following notational convention is used in the rest of the document:
STM32F0xx is used instead of STM32F0xxxx when referring to products of STM32F0
series, and STM32F1xx is used instead of STM32F1xxxx when referring to products of
STM32F1 series.

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www.st.com 1
Contents AN4088

Contents

1 Hardware migration from STM32F1 to STM32F0

series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Boot mode compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Reset and clock controller (RCC) interface . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7 GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8 EXTI source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 ADC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11 PWR interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Real-time clock (RTC) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.15 USART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16 CEC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.17 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 Firmware migration using the library . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1 Migration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 RCC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3 Flash driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 CRC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5 GPIO configuration update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5.1 Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5.2 Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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4.5.3 Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.5.4 Alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6 EXTI Line0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7 NVIC interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.8 ADC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.9 DAC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.10 PWR driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.11 Backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.12 CEC application code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.13 I2C driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.14 SPI driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.15 USART driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.16 IWDG driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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List of tables AN4088

List of tables

Table 1. Applicable products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F1 series and STM32F03x/STM32F05x device pinout differences. . . . . . . . . . . . . . 6
Table 3. STM32F1 series and STM32F04x device pinout differences . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. STM32F1 series and STM32F07x device pinout differences . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. STM32F1 series and STM32F09x device pinout differences . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. STM32 peripheral compatibility analysis, STM32F1 versus STM32F0 series . . . . . . . . . . . 9
Table 8. IP bus mapping differences between STM32F0 and STM32F1 series. . . . . . . . . . . . . . . . 12
Table 9. RCC differences between STM32F1 and STM32F0 series . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Example of migrating system clock configuration code from STM32F1 to STM32F0 . . . . 16
Table 11. RCC registers used for peripheral access configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. DMA request differences between STM32F1 series and STM32F09x family . . . . . . . . . . 18
Table 13. DMA request differences between STM32F1 series and STM32F07x family . . . . . . . . . . 21
Table 14. DMA request differences between STM32F1 series and STM32F05x/STM32F03x
families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Interrupt vector differences between STM32F1 series and STM32F0
series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. GPIO differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . . 29
Table 17. Flash differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . . 31
Table 18. ADC differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . . . 33
Table 19. PWR differences between STM32F1 series and STM32F0 series. . . . . . . . . . . . . . . . . . . 34
Table 20. STM32F10x and STM32F0xx source clock API correspondence . . . . . . . . . . . . . . . . . . . 41
Table 21. STM32F10x and STM32F0xx Flash driver API correspondence . . . . . . . . . . . . . . . . . . . . 42
Table 22. STM32F10xx and STM32F0xx CRC driver API correspondence. . . . . . . . . . . . . . . . . . . . 44
Table 23. STM32F10x and STM32F0xx MISC driver API correspondence . . . . . . . . . . . . . . . . . . . . 50
Table 24. STM32F10x and STM32F0xx DAC driver API correspondence. . . . . . . . . . . . . . . . . . . . . 52
Table 25. STM32F10x and STM32F0xx PWR driver API correspondence . . . . . . . . . . . . . . . . . . . . 54
Table 26. STM32F10xx and STM32F0xx CEC driver API correspondence . . . . . . . . . . . . . . . . . . . . 56
Table 27. STM32F10xx and STM32F0xx I2C driver API correspondence . . . . . . . . . . . . . . . . . . . . . 58
Table 28. STM32F10xx and STM32F0xx SPI driver API correspondence. . . . . . . . . . . . . . . . . . . . . 62
Table 29. STM32F10x and STM32F0xx USART driver API correspondence . . . . . . . . . . . . . . . . . . 65
Table 30. STM32F10xx and STM32Fxx IWDG driver API correspondence. . . . . . . . . . . . . . . . . . . . 69
Table 31. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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AN4088 List of figures

List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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Hardware migration from STM32F1 to STM32F0 series AN4088

1 Hardware migration from STM32F1 to STM32F0

series

The entry-level STM32F1xx and general-purpose STM32F0xx families are pin-to-pin

compatible. All peripherals shares the same pins in the two families, but there are some
minor differences between packages.
The transition from the STM32F1 series to the STM32F0 series is simple as only a few pins
are impacted. The impacted pins are shown in bold in the following tables.

Table 2. STM32F1 series and STM32F03x/STM32F05x device pinout differences

STM32F1 series STM32F03x/5x devices
LQFP64 LQFP48
Pinout Pinout Pinout
STM32F031/51 STM32F038/58
5 5 PD0 - OSC_IN PF0 - OSC_IN PF0 - OSC_IN
6 6 PD1 - OSC_OUT PF1 - OSC_OUT PF1 - OSC_OUT
18 - VSS_4 PF4 PF4
19 - VDD_4 PF5 PF5
28 20 BOOT1 - PB2 PB2 NPOR
47 35 VSS_2 PF6 PF6
48 36 VDD_2 PF7 PF7

Table 3. STM32F1 series and STM32F04x device pinout differences

STM32F1 series STM32F04x devices
LQFP48
Pinout Pinout Pinout
STM32F042 STM32F048
5 PD0 - OSC_IN PF0 - OSC_IN PF0 - OSC_IN
6 PD1 - OSC_OUT PF1 - OSC_OUT PF1 - OSC_OUT
20 BOOT1 - PB2 PB2 NPOR
35 VSS_2 PF6 PF6
36 VDD_2 VDDIO2 VDDIO2
44 BOOT0 BOOT0 - PF11 BOOT0 - PF11

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Table 4. STM32F1 series and STM32F07x device pinout differences

STM32F1 series STM32F07x devices
LQFP100
Pinout Pinout Pinout
STM32F071/72 STM32F078
10 VSS_5 PF9 PF9
11 VDD_5 PF10 PF10
12 OSC_IN PF0 - OSC_IN PF0 - OSC_IN
13 OSC_OUT PF1 - OSC_OUT PF1 - OSC_OUT
19 VSSA PF2 PF2
20 VREF - VSSA VSSA
21 VREF + VDDA VDDA
22 VDDA PF3 PF3
37 BOOT1 - PB2 PB2 NPOR
73 NC PF6 PF6
75 VDD_2 VDDIO2 VDDIO2

Table 5. STM32F1 series and STM32F09x device pinout differences

STM32F1 series STM32F09x devices
LQFP100
Pinout Pinout Pinout
STM32F091 STM32F098
10 VSS_5 PF9 PF9
11 VDD_5 PF10 PF10
12 OSC_IN PF0 - OSC_IN PF0 - OSC_IN
13 OSC_OUT PF1 - OSC_OUT PF1 - OSC_OUT
19 VSSA PF2 PF2
20 VREF - VSSA VSSA
21 VREF + VDDA VDDA
22 VDDA PF3 PF3
37 BOOT1 - PB2 PB2 NPOR
73 NC PF6 PF6
75 VDD_2 VDDIO2 VDDIO2
94 BOOT0 BOOT0-PF11 BOOT0-PF11

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Boot mode compatibility AN4088

2 Boot mode compatibility

The way to select the boot mode on the STM32F0xx products differs from STM32F1xx
product family. Instead of using two pins for the boot mode setting, STM32F0xx products
use BOOT0 pin and retrieve the nBOOT1 value from an option bit located in the User option
bytes at 0x1FFFF800 memory address.
On the STM32F04x and STM32F09x devices the BOOT0 pin can be replaced by nBOOT0
bit using the BOOT_SEL bit in the User option bytes. This provides the ability to use PF11
GPIO on the device.
Table 6 summarizes the different configurations available for the Boot mode selection.

Table 6. Boot modes(1)

Boot mode configuration
Mode
n BOOT1 BOOT0 BOOT_SEL nBOOT0
bit pin bit bit

x 0 1 x Main Flash memory is selected as boot space

1 1 1 x System memory is selected as boot space
0 1 1 x Embedded SRAM is selected as boot space
x x 0 1 Main Flash memory is selected as boot space
1 x 0 0 System memory is selected as boot space
0 x 0 0 Embedded SRAM is selected as boot space
1. Gray options are available on STM32F04x and STM32F09x devices only.

Note: The BOOTx value is the opposite of the nBOOTx option bit, where x stands for 1 and 2.

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AN4088 Peripheral migration

3 Peripheral migration

As shown in Table 7, there are three categories of peripherals. The common peripherals are
supported with the dedicated firmware library without any modification, except if the
peripheral instance is no longer present. You can change the instance and, of course, all the
related features (clock configuration, pin configuration, interrupt/DMA request).
The modified peripherals such as ADC, RCC and RTC are different from the STM32F1
series ones and should be updated to take advantage of the enhancements and the new
features in STM32F0 series.
All these modified peripherals in the STM32F0 series are enhanced to obtain smaller silicon
print with features designed to offer advanced high-end capabilities in economical end
products and to fix some limitations present in the STM32F1 series.

3.1 STM32 product cross-compatibility

The STM32 series embeds a set of peripherals which can be classed in three categories:
 The first category is for the peripherals which are, by definition, common to all products.
Those peripherals are identical, so they have the same structure, registers and control
bits. There is no need to perform any firmware change to keep the same functionality,
at the application level, after migration. All the features and behavior remain the same.
 The second category is for the peripherals which are shared by all products but have
only minor differences (in general to support new features). The migration from one
product to another is very easy and does not need any significant new development
effort.
 The third category is for peripherals which have been considerably changed from one
product to another (new architecture, new features...). For this category of peripherals,
the migration will require new development, at the application level.
Table 7 gives a general overview of this classification.

Table 7. STM32 peripheral compatibility analysis, STM32F1 versus STM32F0 series(1)

Compatibility
Peripheral STM32F1 STM32F0
Features Pinout Firmware driver

Two FIFO available, 4 bit to

SPI Yes Yes+ Identical Partial compatibility
16 bit data size selection
WWDG Yes Yes Same features NA Full compatibility
IWDG Yes Yes++ added a Window mode NA Partial compatibility
DBGMCU Yes Yes No JTAG, No Trace Identical for the SWD Partial compatibility
added reverse capability and
CRC Yes Yes++ NA Partial compatibility
initial CRC value
Some peripherals are able to
EXTI Yes Yes+ Identical Full compatibility
generate event in stop mode

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Table 7. STM32 peripheral compatibility analysis, STM32F1 versus STM32F0 series(1) (continued)
Compatibility
Peripheral STM32F1 STM32F0
Features Pinout Firmware driver

Kernel clock, arbitration lost

flag and automatic
CEC Yes Yes++ transmission retry, multi- Identical Partial compatibility
address config., wake up
from stop mode
1 DMA controller with up to 7
DMA Yes Yes NA Full compatibility
channels
Identical for same
TIM Yes Yes+ enhancement Partial compatibility
feature
No VREF, VDDA can be
Identical for the
PWR Yes Yes+ greater than VDD, 1.8 mode Partial compatibility
same feature
for core.
New HSI14 dedicated to
PD0 & PD1 => PF0
RCC Yes Yes+ ADC & HSI48 for the Partial compatibility
& PF1 for the HSE
STM32F07x devices
Choice for independent clock
USART Yes Yes+ sources, time-out feature, Identical Full compatibility
wake-up from stop mode
Communication events
managed by hardware, FM+,
I2C Yes Yes++ Identical New driver
wake up from stop mode,
digital filter
DAC Yes Yes+ DMA underrun interrupt Identical Full compatibility
Same analog part, but new
ADC Yes Yes++ Identical Partial compatibility
digital interface
sub second precision, digital
calibration circuit, time-stamp
function for event saving,
Identical for the
RTC Yes Yes++ programmable alarm, and New driver
same feature
additional auto-wakeup
feature on STM32F07x
devices
FLASH Yes Yes+ Option byte modified NA Partial compatibility
GPIO Yes Yes++ New peripheral 4 new GPIOs Partial compatibility
CAN Yes Yes Same features NA Full compatibility
Support low-power mode
USB FS
Yes Yes+ (LPM) and battery charging Identical Partial compatibility
Device
detection
CRS NA Yes New peripheral NA NA
Touch
NA Yes New peripheral NA NA
sensing
COMP NA Yes New peripheral NA NA

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Table 7. STM32 peripheral compatibility analysis, STM32F1 versus STM32F0 series(1) (continued)
Compatibility
Peripheral STM32F1 STM32F0
Features Pinout Firmware driver

SYSCFG NA Yes New peripheral NA NA

Ethernet Yes NA NA NA NA
SDIO Yes NA NA NA NA
FSMC Yes NA NA NA NA
1. Yes++ = New feature or new architecture,
Yes+ = Same feature, but specification change or enhancement,
Yes = Feature available,
NA = Feature not available

3.2 System architecture

The STM32F0xx MCU family has been designed to target an entry-level market, with low-
power capabilities and easy handling. In order to fulfill this aim while keeping the advanced
high-end features proper to the STM32, the core has been changed for a ARM® Cortex®-
M0. Its small silicon area, coupled to a minimal code footprint, allows for low-cost
applications with 32-bit performance. Figure 1 shows the correspondence between the
Cortex®-M3 and Cortex®-M0 sets of instructions. Moving from STM32F1 to STM32F0
series requires a recompilation of the code to avoid the use of unavailable features.

Figure 1. System architecture

Important modifications have been performed on the MCU organization too, starting by
switching from a Harvard to Von Neumann architecture, decreasing the system complexity,
or focusing on SW Debug in order to simplify this precise feature.

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3.3 Memory mapping

The peripheral address mapping has been changed in the STM32F0 series versus
STM32F1 series. The main change concerns the GPIOs which have been moved from the
APB bus to the AHB bus to allow them to operate at the maximum speed.
Table 8 provides the peripheral address mapping correspondence between STM32F0 and
STM32F1 series.

Table 8. IP bus mapping differences between STM32F0 and STM32F1 series(1)

STM32F0 series STM32F1 series
Peripheral
Bus Base address Bus Base address

TSC 0x40024000 NA NA
CRC 0x40023000 0x40023000
FLITF AHB1 0x40022000 0x40022000
AHB
RCC 0x40021000 0x40021000
DMA1/DMA 0x40020000 0x40020000
GPIOG NA NA 0x40012000
GPIOF 0x48001400 0x40011C00
GPIOE 0x4800 1000 0x40011800
GPIOD 0x48000C00 APB2 0x40011400
AHB2
GPIOC 0x48000800 0x40011000
GPIOB 0x48000400 0x40010C00
GPIOA 0x48000000 0x40010800
DBGMCU 0x40015800 NA NA
TIM17 0x40014800 NA NA
TIM16 0x40014400 NA NA
TIM15 0x40014000 NA NA
APB2
USART1 0x40013800 0x40013800
SPI1 / I2S1 0x40013000 0x40013000
TIM1 0x40012C00 0x40012C00
APB2
ADC / ADC1 0x40012400 0x40012400
APB2 (through
EXTI 0x40010400 0x40010400
SYSCFG)
SYSCFG + COMP APB2 0x40010000 NA NA

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Table 8. IP bus mapping differences between STM32F0 and STM32F1 series(1) (continued)
STM32F0 series STM32F1 series
Peripheral
Bus Base address Bus Base address

CEC 0x40007800 0x40007800

DAC 0x40007400 APB1 0x40007400
PWR 0x40007000 0x40007000
CRS 0x40006C00 NA NA
USB/CAN SRAM 0x40006000 0x40006000
USB 0x40005C00 0x40005C00
APB1
I2C2 0x40005800 0x40005800
I2C1 0x40005400 0x40005400
USART4 0x40004C00 0x40004C00
USART3 0x40004800 0x40004800
APB1
USART2 0x40004400 0x40004400
SPI2 0x40003800 0x40003800
IWDG Own Clock 0x40003000 0x40003000
WWDG APB1 0x40002C00 0x40002C00
APB1 (through 0x40002800
RTC
PWR) (inc. BKP registers)
TIM14 0x40002000 NA NA
TIM7 0x40001400 0x40001400
TIM6 APB1 0x40001000 0x40001000
APB1
TIM3 0x40000400 0x40000400
TIM2 0x40000000 0x40000000
TIM4 NA NA APB1 0x40000800
FSMC Registers NA NA 0xA0000000
USB OTG FS NA NA 0x50000000
ETHERNET MAC NA NA AHB 0x40028000
DMA2 NA NA 0x40020400
SDIO NA NA 0x40018000
TIM11 NA NA 0x40015400
TIM10 NA NA 0x40015000
TIM9 NA NA 0x40014C00
APB2
ADC2 NA NA 0x40012800
ADC3 NA NA 0x40013C00
TIM8 NA NA 0x40013400

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Table 8. IP bus mapping differences between STM32F0 and STM32F1 series(1) (continued)
STM32F0 series STM32F1 series
Peripheral
Bus Base address Bus Base address

CAN2 NA NA 0x40006800
CAN1 NA NA 0x40006400
UART5 NA NA 0x40005000
SPI3/I2S3 NA NA 0x40003C00
APB1
TIM13 NA NA 0x40001C00
TIM12 NA NA 0x40001800
TIM5 NA NA 0x40000C00
BKP registers NA NA 0x40006C00
AFIO NA NA APB2 0x40010000
1. NA in table cells with gray shading = feature not available.
STM32F0 series devices have only one APB bus, APB1 and APB2 indicate on which APB register the clock configuration
bits of those peripherals are defined.

3.4 Reset and clock controller (RCC) interface

The main differences related to the RCC (Reset and clock controller) in the STM32F0 series
versus STM32F1 series are presented in Table 9.

Table 9. RCC differences between STM32F1 and STM32F0 series

RCC STM32F1 series STM32F0 series

HSI 48 NA High speed internal oscillator at 48MHz

High speed internal oscillator dedicated to
HSI 14 NA
ADC
HSI 8 MHz RC factory-trimmed Similar
LSI 40 kHz RC Similar
3 - 25 MHz
HSE 4 - 32 MHz(1)
Depending on the product line used
LSE 32.768 kHz Similar
– Connectivity line: main PLL + 2 PLLs for
PLL I2S, Ethernet and OTG FS clock Main PLL
– Other product lines: main PLL
System clock source HSI, HSE or PLL HSI48, HSI, HSE or PLL
– Up to 72 MHz depending on the product – Up to 48 MHz depending on the product
System clock line used, line used
frequency
– 8 MHz after reset using HSI – 8 MHz after reset using HSI(1)
APB1/APB frequency Up to 36 MHz Up to 48 MHz(1)
RTC clock source LSI, LSE or HSE/128 LSI, LSE or HSE clock divided by 32

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AN4088 Peripheral migration

Table 9. RCC differences between STM32F1 and STM32F0 series (continued)

RCC STM32F1 series STM32F0 series

– MCO pin (PA8)

– Connectivity Line: HSI, HSE, PLL/2,
MCO(PA8): SYSCLK, HSI, HSE, HSI14,
MCO clock source SYSCLK, PLL2, PLL3 or XT1
HSI48, PLLCLK/2, LSE, LSI(1)
– Other product lines: HSI, HSE, PLL/2 or
SYSCLK
– LSE and LSI clock are indirectly measured
through MCO by the timer TIM14 with
respect to HSI/HSE clock.(1)
– HSI14/HSE are indirectly measured
Int. oscillator
LSI connected to TIM5 CH4 IC: can measure through MCO by means of the TIM14
measurement /
LSI w/ respect to HSI/HSE clock channel 1 input capture with respect to HSI
calibration
clock.(1)
– HSI48 can be calibrated on the run by the
mean of the CRS using a reference
clock.(1)
1. Same feature but spec change or enhancement.

In addition to the differences described in the table above, the following additional
adaptation steps may be needed for the migration.
1. System clock configuration: when moving from STM32F1 series to STM32F0 series,
only a few settings need to be updated in the system clock configuration code; mainly
the Flash settings (configure the right wait states for the system frequency, prefetch
enable/disable) or/and the PLL parameters configuration:
a) In case HSE or HSI is used directly as the system clock source, only the Flash
parameters should be modified.
b) In case PLL (clocked by HSE or HSI) is used as the system clock source, the
Flash parameters and PLL configuration need to be updated.
Table 10 below provides an example of porting a system clock configuration from STM32F1
to STM32F0 series:
– STM32F100x value line running at maximum performance: system clock at
24 MHz (PLL, clocked by the HSE (8 MHz), used as the system clock source),
Flash with 0 wait states and Flash prefetch queue enabled.
– STM32F0 series running at maximum performance: system clock at 48 MHz (PLL,
clocked by the HSE (8 MHz), used as the system clock source), Flash with 1 wait
state and Flash prefetch enabled.
As shown in Table 10, only the Flash settings and PLL parameters (code in Bold Italic)
need to be rewritten to run on STM32F0 series. However, HSE, AHB prescaler and the
system clock source configuration are left unchanged, and APB prescalers are adapted to
the maximum APB frequency in the STM32F0 series.
Note: 1 The source code presented in Table 10 is intentionally simplified (timeout in wait loop
removed) and is based on the assumption that the RCC and Flash registers are at their
reset values.
2 For STM32F0xx, you can use the clock configuration tool,
STM32F0xx_Clock_Configuration.xls, to generate a customized system_stm32f0xx.c file

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containing a system clock configuration routine, depending on your application

requirements.

Table 10. Example of migrating system clock configuration code from STM32F1 to STM32F0
STM32F100x Value Line running at 24 MHz (PLL as STM32F0xx running at 48 MHz (PLL as clock source)
clock source) with 0 wait states with 1 wait state

/* Enable HSE ----------------------------*/

/* Enable HSE ----------------------------*/ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready */
/* Wait till HSE is ready */ while((RCC->CR & RCC_CR_HSERDY) == 0)
while((RCC->CR & RCC_CR_HSERDY) == 0) {
{ }
}
/* Flash configuration -------------------*/
/* Flash configuration -------------------*/ /* Prefetch ON, Flash 1 wait state */
/* Prefetch ON, Flash 0 wait state */ FLASH->ACR |= FLASH_ACR_PRFTBE |
FLASH->ACR |= FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
FLASH_ACR_LATENCY_0;
/* AHB and APB prescaler configuration --*/
/* AHB and APB prescaler configuration --*/ /* HCLK = SYSCLK */
/* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
/* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PLL configuration = HSE * 6 = 48 MHz -*/
/* PCLK1 = HCLK */ RCC->CFGR |=
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);

/* PLL configuration = (HSE / 2) * 6 = 24 MHz /* Enable PLL */

*/ RCC->CR |= RCC_CR_PLLON;
RCC->CFGR |=
(uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | /* Wait till PLL is ready */
RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
RCC_CFGR_PLLMULL6); {
}
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON; /* Select PLL as system clock source ----*/
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0) /* Wait till PLL is used as system clock
{ source */
} while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS)
!= (uint32_t)RCC_CFGR_SWS_PLL)
/* Select PLL as system clock source ----*/ {
RCC->CFGR &= }
(uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock

source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS)
!= (uint32_t)0x08)
{
}

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2. Peripheral access configuration: since the address mapping of some peripherals has
been changed in STM32F0 series versus STM32F1 series, you need to use different
registers to [enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode].

Table 11. RCC registers used for peripheral access configuration

Bus Register Comments

RCC_AHBRSTR Used to [enter/exit] the AHB peripheral from reset

AHB
RCC_AHBENR Used to [enable/disable] the AHB peripheral clock
RCC_APB1RSTR Used to [enter/exit] the APB1 peripheral from reset
APB1
RCC_APB1ENR Used to [enable/disable] the APB1 peripheral clock
RCC_APB2RSTR Used to [enter/exit] the APB2 peripheral from reset
APB2
RCC_APB2ENR Used to [enable/disable] the APB2 peripheral clock

To configure the access to a given peripheral, you have first to know to which bus this
peripheral is connected; refer to Table 8 then, depending on the action needed, program
the right register as described in Table 11 above. For example, if USART1 is connected to
the APB2 bus, to enable the USART1 clock you have to configure APB2ENR register as
follows:
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;

3. Peripheral clock configuration: some peripherals have a dedicated clock source

independent from the system clock, and used to generate the clock required for their
operation:
a) ADC: in STM32F0 series, the ADC features two possible clock sources:
– The first one is based on the PCLK; a prescaler allows you to reduce the ADC
input frequency by a factor 2 or 4 before getting to the ADC.
– The other one is a completely new feature on stingray; a dedicated 14 MHz
oscillator (HSI14) is integrated on the chip and can be used for the ADC input
frequency.
b) RTC: in STM32F0 series, the RTC features three possible clock sources:
– The first one is based on the HSE Clock; a prescaler divides its frequency by 32
before going to the RTC.
– The second one is the LSE oscillator.
– The third clock source is the LSI RC with a value of 40 KHz.
c) USB: in STM32F0x2 family, the USB may take benefit of different clock sources to
have the necessary 48 MHz:
– The first source is the sysclk to get for example the PLL associated to a precise
HSE crystal providing an accurate 48 MHz to the peripheral.
– The second source is the internal HSI48 associated to the CRS peripheral that
allows the HSI48 to be trimmed in run time on a precise reference clock, that is the
start of frame signal, making the USB usable without crystal.

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3.5 DMA interface

STM32F1 and STM32F0 series use the same fully compatible DMA controller.
The STM32F03x/05x product families use one 5-channel and the STM32F07x family uses
one 7-channel DMA controller. The STM32F09x family uses a 7-channel DMA controller
and an additional 5-channel DMA2 controller, while the STM32F1 series uses two 5-channel
DMA controllers. Each channel is dedicated to managing memory access requests from one
or more peripherals.
The tables below present the correspondence between the DMA requests of the peripherals
in STM32F1 series and STM32F0 series.

Table 12. DMA request differences between STM32F1 series and STM32F09x family(1)
Peripheral DMA request STM32F1 series STM32 F09x family

DMA1_Channel1 /
ADC1 / ADC ADC1 / ADC DMA1_Channel1 DMA1_Channel2 /
DMA2_Channel5
ADC3 ADC3 DMA2_Channel5 NA
DAC_Channel1 / DMA2_Channel3 / DMA1_Channel3 /
DAC
DAC DMA1_Channel3(*) DMA2_Channel3
DMA1_Channel2 /
SPI1_Rx DMA1_Channel2 DMA2_Channel3
SPI1
SPI1_Tx DMA1_Channel3 DMA1_Channel3 /
DMA2_Channel4
DMA1_Channel4 /
SPI2_Rx DMA1_Channel4 DMA1_Channel6
SPI2
SPI2_Tx DMA1_Channel5 DMA1_Channel5 /
DMA1_Channel7
SPI3_Rx DMA2_Channel1
SPI3 NA
SPI3_Tx DMA2_Channel2
USART1_Rx DMA1_Channel5 DMA1_Channel1 /
USART1
USART1_Tx DMA1_Channel4 DMA1_Channel3 /
DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART2_Rx DMA1_Channe6 DMA2_Channel3
USART2
USART2_Tx DMA1_Channel7 DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5

USART3_Rx DMA1_Channe3 DMA1_Channel1 /

USART3
USART3_Tx DMA1_Channel2 DMA1_Channel3 /

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Table 12. DMA request differences between STM32F1 series and STM32F09x family(1) (continued)
Peripheral DMA request STM32F1 series STM32 F09x family

DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART4_Rx DMA2_Channel3 DMA2_Channel3
USART4
USART4_Tx DMA2_Channel5 DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5
DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART5_Rx DMA2_Channe4 DMA2_Channel3
USART5
USART5_Tx DMA2_Channel1 DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5
DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART6_Rx DMA2_Channel3
USART6 NA
USART6_Tx DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5
DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART7_Rx DMA2_Channel3
USART7 NA
USART7_Tx DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5

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Table 12. DMA request differences between STM32F1 series and STM32F09x family(1) (continued)
Peripheral DMA request STM32F1 series STM32 F09x family

DMA1_Channel1 /
DMA1_Channel3 /
DMA1_Channel5 /
DMA1_Channel6 /
DMA2_Channel2 /
USART8_Rx DMA2_Channel3
USART8 NA
USART8_Tx DMA1_Channel2 /
DMA1_Channel4 /
DMA1_Channel7 /
DMA2_Channel1 /
DMA2_Channel4 /
DMA2_Channel5
DMA1_Channel3 /
I2C1_Rx DMA1_Channe7 DMA1_Channel6
I2C1
I2C1_Tx DMA1_Channel6 DMA1_Channel2 /
DMA1_Channel7
I2C2_Rx DMA1_Channel5
I2C2 NA
I2C2_Tx DMA1_Channel4
SDIO SDIO DMA2_Channel4 NA

TIM1_UP DMA1_Channel5 DMA1_Channel5

TIM1_CH1 DMA1_Channel2 DMA1_Channel2 /
TIM1_CH2 DMA1_Channel3 DMA1_Channel6
TIM1 TIM1_CH3 DMA1_Channel6 DMA1_Channel3 /
TIM1_CH4 DMA1_Channel4 DMA1_Channel6
TIM1_TRIG DMA1_Channel4 DMA1_Channel5 /
TIM1_COM DMA1_Channel4 DMA1_Channel6
DMA1_Channel4
TIM8_UP DMA2_Channel1
TIM8_CH1 DMA2_Channel3
TIM8_CH2 DMA2_Channel5
TIM8 TIM8_CH3 DMA2_Channel1 NA
TIM8_CH4 DMA2_Channel2
TIM8_TRIG DMA2_Channel2
TIM8_COM DMA2_Channel2

DMA1_Channel2
TIM2_UP DMA1_Channel2 DMA1_Channel5
TIM2_CH1 DMA1_Channel5 DMA1_Channel3 /
TIM2 TIM2_CH2 DMA1_Channel7 DMA1_Channel7
TIM2_CH3 DMA1_Channel1 DMA1_Channel1
TIM2_CH4 DMA1_Channel7 DMA1_Channel4 /
DMA1_Channel7

TIM3_UP DMA1_Channel3 DMA1_Channel3

TIM3_CH1 DMA1_Channel6 DMA1_Channel4 /
TIM3 TIM3_TRIG DMA1_Channel6 DMA1_Channel6
TIM3_CH3 DMA1_Channel2 DMA1_Channel4 /
TIM3_CH4 DMA1_Channel3 DMA1_Channel6

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Table 12. DMA request differences between STM32F1 series and STM32F09x family(1) (continued)
Peripheral DMA request STM32F1 series STM32 F09x family

TIM4_UP DMA1_Channel7
TIM4_CH1 DMA1_Channel1
TIM4 NA
TIM4_CH2 DMA1_Channel4
TIM4_CH3 DMA1_Channel5

TIM5_UP DMA2_Channel2
TIM5_CH1 DMA2_Channel5
TIM5_CH2 DMA2_Channel4
TIM5 NA
TIM5_CH3 DMA2_Channel2
TIM5_CH4 DMA2_Channel1
TIM5_TRIG DMA2_Channel1

DMA2_Channel3 / DMA1_Channel3 /
TIM6 TIM6_UP
DMA1_Channel3(*) DMA2_Channel3

DMA2_Channe4 / DMA1_Channel4 /
TIM7 TIM7_UP
DMA1_Channel4 (*) DMA2_Channel4
TIM15_UP DMA1_Channel5 DMA1_Channel5
TIM15_CH1 DMA1_Channel5 DMA1_Channel5
TIM15
TIM15_TRIG DMA1_Channel5 DMA1_Channel5
TIM15_COM DMA1_Channel5 DMA1_Channel5
DMA1_Channel3 /
DMA1_Channel4 /
TIM16_UP DMA1_Channel6 DMA1_Channel6
TIM16
TIM16_CH1 DMA1_Channel6 DMA1_Channel3 /
DMA1_Channel4 /
DMA1_Channel6
DMA1_Channel1 /
DMA1_Channel2 /
TIM17_UP DMA1_Channel7 DMA1_Channel7
TIM17
TIM17_CH1 DMA1_Channel7 DMA1_Channel1 /
DMA1_Channel2 /
DMA1_Channel7
1. NA in table cells with gray shading means Not Applicable.

Table 13. DMA request differences between STM32F1 series and STM32F07x family(1)
Peripheral DMA request STM32F1 series STM32 F07x family

ADC1 / ADC ADC1 / ADC DMA1_Channel1 DMA_Channel1 / DMA_Channel2

ADC3 ADC3 DMA2_Channel5 NA
DMA2_Channel3 /
DAC_Channel1 /
DMA1_Channel3(*)
DAC DAC DMA_Channel3
DMA2_Channel4 /
DAC_Channel2
DMA1_Channel4(*)

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Table 13. DMA request differences between STM32F1 series and STM32F07x family(1) (continued)
Peripheral DMA request STM32F1 series STM32 F07x family

SPI1_Rx DMA1_Channel2 DMA_Channel2

SPI1
SPI1_Tx DMA1_Channel3 DMA_Channel3
SPI2_Rx DMA1_Channel4 DMA_Channel4 / DMA_Channel6
SPI2
SPI2_Tx DMA1_Channel5 DMA_Channel5 / DMA_Channel7
SPI3_Rx DMA2_Channel1
SPI3 NA
SPI3_Tx DMA2_Channel2
USART1_Rx DMA1_Channel5 DMA_Channel3 / DMA_Channel5
USART1
USART1_Tx DMA1_Channel4 DMA_Channel2 / DMA_Channel4
USART2_Rx DMA1_Channe6 DMA_Channel5 / DMA_Channel6
USART2
USART2_Tx DMA1_Channel7 DMA_Channel4 / DMA_Channel7
USART3_Rx DMA1_Channe3 DMA_Channel3 / DMA_Channel6
USART3
USART3_Tx DMA1_Channel2 DMA_Channel2 / DMA_Channel7
UART4_Rx DMA2_Channel3 DMA_Channel6
UART4
UART4_Tx DMA2_Channel5 DMA_Channel7
UART5_Rx DMA2_Channe4
UART5 NA
UART5_Tx DMA2_Channel1
I2C1_Rx DMA1_Channe7 DMA_Channel3 / DMA_Channel6
I2C1
I2C1_Tx DMA1_Channel6 DMA_Channel2 / DMA_Channel7
I2C2_Rx DMA1_Channel5 DMA_Channel5
I2C2
I2C2_Tx DMA1_Channel4 DMA_Channel4
SDIO SDIO DMA2_Channel4 NA
TIM1_UP DMA1_Channel5 DMA_Channel5
TIM1_CH1 DMA1_Channel2 DMA_Channel2 / DMA_Channel6
TIM1_CH2 DMA1_Channel3 DMA_Channel3 / DMA_Channel6
TIM1 TIM1_CH3 DMA1_Channel6 DMA_Channel5 / DMA_Channel6
TIM1_CH4 DMA1_Channel4 DMA_Channel4
TIM1_TRIG DMA1_Channel4 DMA_Channel4
TIM1_COM DMA1_Channel4 DMA_Channel4

TIM8_UP DMA2_Channel1
TIM8_CH1 DMA2_Channel3
TIM8_CH2 DMA2_Channel5
TIM8 TIM8_CH3 DMA2_Channel1 NA
TIM8_CH4 DMA2_Channel2
TIM8_TRIG DMA2_Channel2
TIM8_COM DMA2_Channel2
TIM2_UP DMA1_Channel2 DMA_Channel2
TIM2_CH1 DMA1_Channel5 DMA_Channel5
TIM2 TIM2_CH2 DMA1_Channel7 DMA_Channel3 / DMA_Channel7
TIM2_CH3 DMA1_Channel1 DMA_Channel1
TIM2_CH4 DMA1_Channel7 DMA_Channel4 / DMA_Channel7
TIM3_UP DMA1_Channel3 DMA_Channel3
TIM3_CH1 DMA1_Channel6 DMA_Channel4 / DMA_Channel6
TIM3 TIM3_TRIG DMA1_Channel6 DMA_Channel4 / DMA_Channel6
TIM3_CH3 DMA1_Channel2 DMA_Channel2
TIM3_CH4 DMA1_Channel3 DMA_Channel3

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Table 13. DMA request differences between STM32F1 series and STM32F07x family(1) (continued)
Peripheral DMA request STM32F1 series STM32 F07x family

TIM4_UP DMA1_Channel7
TIM4_CH1 DMA1_Channel1
TIM4 NA
TIM4_CH2 DMA1_Channel4
TIM4_CH3 DMA1_Channel5
TIM5_UP DMA2_Channel2
TIM5_CH1 DMA2_Channel5
TIM5_CH2 DMA2_Channel4
TIM5 NA
TIM5_CH3 DMA2_Channel2
TIM5_CH4 DMA2_Channel1
TIM5_TRIG DMA2_Channel1
DMA2_Channel3 /
TIM6 TIM6_UP DMA_Channel3
DMA1_Channel3(*)
DMA2_Channe4 /
TIM7 TIM7_UP DMA_Channel4
DMA1_Channel4 (*)
TIM15_UP DMA1_Channel5 DMA_Channel5
TIM15_CH1 DMA1_Channel5 DMA_Channel5
TIM15
TIM15_TRIG DMA1_Channel5 DMA_Channel5
TIM15_COM DMA1_Channel5 DMA_Channel5
DMA_Channel3 / DMA_Channel4
TIM16_UP DMA1_Channel6 / DMA_Channel6
TIM16
TIM16_CH1 DMA1_Channel6 DMA_Channel3 / DMA_Channel4
/ DMA_Channel6
DMA_Channel1 / DMA_Channel2
TIM17_UP DMA1_Channel7 / DMA_Channel7
TIM17
TIM17_CH1 DMA1_Channel7 DMA_Channel1 / DMA_Channel2
/ DMA_Channel7
1. NA in table cells with gray shading means Not Applicable.

Table 14. DMA request differences between STM32F1 series and STM32F05x/STM32F03x
families(1)
STM32 F05x/STM32F03x
Peripheral DMA request STM32F1 series
families

DMA_Channel1
ADC1 / ADC ADC1 / ADC DMA1_Channel1
DMA_Channel2
ADC3 ADC3 DMA2_Channel5 NA
DMA2_Channel3 /
DAC_Channel1 /
DMA1_Channel3(*)
DAC DAC DMA_Channel3
DMA2_Channel4 /
DAC_Channel2
DMA1_Channel4(*)
SPI1_Rx DMA1_Channel2 DMA_Channel2
SPI1
SPI1_Tx DMA1_Channel3 DMA_Channel3
SPI2_Rx DMA1_Channel4 DMA_Channel4
SPI2
SPI2_Tx DMA1_Channel5 DMA_Channel5
SPI3_Rx DMA2_Channel1
SPI3 NA
SPI3_Tx DMA2_Channel2

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Table 14. DMA request differences between STM32F1 series and STM32F05x/STM32F03x
families(1) (continued)
STM32 F05x/STM32F03x
Peripheral DMA request STM32F1 series
families

USART1_Rx DMA1_Channel5 DMA_Channel3 / DMA_Channel5

USART1
USART1_Tx DMA1_Channel4 DMA_Channel2 / DMA_Channe4
USART2_Rx DMA1_Channe6 DMA_Channel5
USART2
USART2_Tx DMA1_Channel7 DMA_Channel4
USART3_Rx DMA1_Channe3
USART3 NA
USART3_Tx DMA1_Channel2
UART4_Rx DMA2_Channel3
UART4 NA
UART4_Tx DMA2_Channel5
UART5_Rx DMA2_Channe4
UART5 NA
UART5_Tx DMA2_Channel1
I2C1_Rx DMA1_Channe7 DMA_Channel3
I2C1
I2C1_Tx DMA1_Channel6 DMA_Channel2
I2C2_Rx DMA1_Channel5 DMA_Channel5
I2C2
I2C2_Tx DMA1_Channel4 DMA_Channel4
SDIO SDIO DMA2_Channel4 NA
TIM1_UP DMA1_Channel5 DMA_Channel5
TIM1_CH1 DMA1_Channel2 DMA_Channel2
TIM1_CH2 DMA1_Channel3 DMA_Channel3
TIM1 TIM1_CH3 DMA1_Channel6 DMA_Channel5
TIM1_CH4 DMA1_Channel4 DMA_Channel4
TIM1_TRIG DMA1_Channel4 DMA_Channel4
TIM1_COM DMA1_Channel4 DMA_Channel4

TIM8_UP DMA2_Channel1
TIM8_CH1 DMA2_Channel3
TIM8_CH2 DMA2_Channel5
TIM8 TIM8_CH3 DMA2_Channel1 NA
TIM8_CH4 DMA2_Channel2
TIM8_TRIG DMA2_Channel2
TIM8_COM DMA2_Channel2
TIM2_UP DMA1_Channel2 DMA_Channel2
TIM2_CH1 DMA1_Channel5 DMA_Channel5
TIM2 TIM2_CH2 DMA1_Channel7 DMA_Channel3
TIM2_CH3 DMA1_Channel1 DMA_Channel1
TIM2_CH4 DMA1_Channel7 DMA_Channel4
TIM3_UP DMA1_Channel3 DMA_Channel3
TIM3_CH1 DMA1_Channel6 DMA_Channel4
TIM3 TIM3_TRIG DMA1_Channel6 DMA_Channel4
TIM3_CH3 DMA1_Channel2 DMA_Channel2
TIM3_CH4 DMA1_Channel3 DMA_Channel3
TIM4_UP DMA1_Channel7
TIM4_CH1 DMA1_Channel1
TIM4 NA
TIM4_CH2 DMA1_Channel4
TIM4_CH3 DMA1_Channel5

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Table 14. DMA request differences between STM32F1 series and STM32F05x/STM32F03x
families(1) (continued)
STM32 F05x/STM32F03x
Peripheral DMA request STM32F1 series
families

TIM5_UP DMA2_Channel2
TIM5_CH1 DMA2_Channel5
TIM5_CH2 DMA2_Channel4
TIM5 NA
TIM5_CH3 DMA2_Channel2
TIM5_CH4 DMA2_Channel1
TIM5_TRIG DMA2_Channel1
DMA2_Channel3 /
TIM6 TIM6_UP DMA_Channel3
DMA1_Channel3(*)
DMA2_Channe4 /
TIM7 TIM7_UP NA
DMA1_Channel4 (*)
TIM15_UP DMA1_Channel5 DMA_Channel5
TIM15_CH1 DMA1_Channel5 DMA_Channel5
TIM15
TIM15_TRIG DMA1_Channel5 DMA_Channel5
TIM15_COM DMA1_Channel5 DMA_Channel5
TIM16_UP DMA1_Channel6 DMA_Channel3 / DMA_Channel4
TIM16
TIM16_CH1 DMA1_Channel6 DMA_Channel3 / DMA_Channel4
TIM17_UP DMA1_Channel7 DMA_Channel1 / DMA_Channel2
TIM17
TIM17_CH1 DMA1_Channel7 DMA_Channel1 / DMA_Channel2
1. NA in table cells with gray shading means Not Applicable.

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3.6 Interrupt vectors

Table 15 presents the interrupt vectors in STM32F0 series versus STM32F1 series.
The switch from ARM® Cortex®-M3 to ARM® Cortex®-M0 has introduced a reduction of the
vector table. This leads to many differences between the two devices.

Table 15. Interrupt vector differences between STM32F1 series and STM32F0
series(1)
Position STM32F1 series STM32F0 series

0 WWDG WWDG
1 PVD PVD_VDDIO2
2 TAMPER RTC
3 RTC FLASH
4 FLASH RCC_CRS
5 RCC EXTI0_1
6 EXTI0 EXTI2_3
7 EXTI1 EXTI4_15
8 EXTI2 TSC
9 EXTI3 DMA_CH1
DMA_CH2_3
10 EXTI4
DMA2_CH1_2
DMA_CH4_5_6_7
11 DMA1_Channel1
DMA2_CH3_4_5
12 DMA1_Channel2 ADC_COMP
13 DMA1_Channel3 TIM1_BRK_UP_TRG_COM
14 DMA1_Channel4 TIM1_CC
15 DMA1_Channel5 TIM2
16 DMA1_Channel6 TIM3
17 DMA1_Channel7 TIM6_DAC
18 ADC1_2 TIM7
CAN1_TX /
19 TIM14
USB_HP_CAN_TX
CAN1_RX0 /
20 TIM15
USB_LP_CAN_RX0
21 CAN1_RX1 TIM16
22 CAN1_SCE TIM17
23 EXTI9_5 I2C1
TIM1_BRK /
24 I2C2
TIM1_BRK _TIM9

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Table 15. Interrupt vector differences between STM32F1 series and STM32F0
series(1) (continued)
Position STM32F1 series STM32F0 series

TIM1_UP /
25 SPI1
TIM1_UP_TIM10
TIM1_TRG_COM /
26 SPI2
TIM1_TRG_COM_TIM11
27 TIM1_CC USART1
28 TIM2 USART2
29 TIM3 USART3_4_5_6_7_8
30 TIM4 CEC_CAN
31 I2C1_EV USB
32 I2C1_ER NA
33 I2C2_EV NA
34 I2C2_ER NA
35 SPI1 NA
36 SPI2 NA
37 USART1 NA
38 USART2 NA
39 USART3 NA
40 EXTI15_10 NA
41 RTC_Alarm NA
42 OTG_FS_WKUP / USBWakeUp NA
43 TIM8_BRK / TIM8_BRK_TIM12 NA
44 TIM8_UP / TIM8_UP_TIM13 NA
TIM8_TRG_COM /
45 NA
TIM8_TRG_COM_TIM14
46 TIM8_CC NA
47 ADC3 NA
48 FSMC NA
49 SDIO NA
50 TIM5 NA
51 SPI3 NA
52 UART4 NA
53 UART5 NA
54 TIM6 NA
55 TIM7 NA
56 DMA2_Channel1 NA

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Table 15. Interrupt vector differences between STM32F1 series and STM32F0
series(1) (continued)
Position STM32F1 series STM32F0 series

57 DMA2_Channel2 NA
58 DMA2_Channel3 NA
59 DMA2_Channel4 / DMA2_Channel4_5 NA
60 DMA2_Channel5 NA
61 ETH NA
62 ETH_WKUP NA
63 CAN2_TX NA
64 CAN2_RX0 NA
65 CAN2_RX1 NA
66 CAN2_SCE NA
67 OTG_FS NA
1. NA in gray table cells means Not Applicable.

3.7 GPIO interface

The STM32F0 GPIO peripheral embeds new features compared to STM32F1 series, below
the main features:
 GPIO mapped on AHB bus for better performance
 I/O pin multiplexer and mapping: pins are connected to on-chip peripherals/modules
through a multiplexer that allows only one peripheral alternate function (AF) connected
to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing
the same I/O pin.
 More possibilities and features for I/O configuration
The STM32F0 GPIO peripheral is a new design and thus the architecture, features and
registers are different from the GPIO peripheral in the STM32F1 series. Any code written for
the STM32F1 series using the GPIO needs to be rewritten to run on STM32F0 series.
For more information about STM32F0 GPIO programming and usage, please refer to the
“I/O pin multiplexer and mapping” section in the GPIO chapter of the STM32F0xx Reference
Manual (RM0091).
The table below presents the differences between GPIOs in the STM32F1 series and
STM32F0 series.

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Table 16. GPIO differences between STM32F1 series and STM32F0 series
GPIO STM32F1 series STM32F0 series

Floating Floating
Input mode PU PU
PD PD
PP
PP + PU
PP PP + PD
General purpose output
OD OD
OD + PU
OD + PD
PP
PP + PU
PP PP + PD
Alternate function output
OD OD
OD + PU
OD + PD
Input / Output Analog Analog

2 MHz 2 MHz
Output speed 10 MHz 10 MHz
50 MHz 48 MHz

To optimize the number of peripheral I/O

functions for different device packages, it Highly flexible pin multiplexing allows no
Alternate function
is possible to remap some alternate conflict between peripherals sharing the
selection
functions to some other pins (software same I/O pin.
remap).

Max IO toggle frequency 18 MHz 12 MHz

Alternate function mode

In STM32F1 series
1. The configuration to use an I/O as an alternate function depends on the peripheral
mode used. For example, the USART Tx pin should be configured as an alternate
function push-pull, while the USART Rx pin should be configured as input floating or
input pull-up.
2. To optimize the number of peripheral I/O functions for different device packages
(especially those with a low pin count), it is possible to remap some alternate functions
to other pins by software. For example, the USART2_RX pin can be mapped on PA3
(default remap) or PD6 (by software remap).
In STM32F0 series
1. Whatever the peripheral mode used, the I/O must be configured as an alternate
function, then the system can use the I/O in the proper way (input or output).
2. The I/O pins are connected to on-chip peripherals/modules through a multiplexer that
allows only one peripheral alternate function to be connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals sharing the same I/O pin. Each

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I/O pin has a multiplexer with eight alternate function inputs (AF0 to AF7) that can be
configured through the GPIOx_AFRL and GPIOx_AFRH registers:
– The peripheral alternate functions are mapped by configuring AF0 to AF7.
3. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped on different I/O pins to optimize the number of peripheral I/O
functions for different device packages. For example, the USART2_RX pin can be
mapped on PA3 or PA15 pin.
Note: Please refer to the “Alternate function mapping” table in the STM32F0x datasheet for the
detailed mapping of the system and the peripheral alternate function I/O pins.
4. Configuration procedure
– Configure the desired I/O as an alternate function in the GPIOx_MODER register
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively
– Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

3.8 EXTI source selection

In STM32F1, the selection of the EXTI line source is performed through EXTIx bits in
AFIO_EXTICRx registers, while in STM32F0 series this selection is done through EXTIx bits
in SYSCFG_EXTICRx registers.
Only the mapping of the EXTICRx registers has been changed, without any changes to the
meaning of the EXTIx bits. However, the maximum range of EXTIx bit values is 0b0101 as
the last PORT is F (in STM32F1 series, the maximum value is 0b0110).

3.9 Flash interface

The table below presents the difference between the Flash interface of STM32F1 series and
STM32F0 series, which can be grouped as follows:
 New interface, new technology
 New architecture
 New read protection mechanism, 3 read protection levels
Consequently, the STM32F0 Flash programming procedures and registers are different
from the STM32F1 series, and any code written for the Flash interface in the STM32F1
series needs to be rewritten to run on STM32F0 series.

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Table 17. Flash differences between STM32F1 series and STM32F0 series(1)
FLASH STM32F1 series STM32F0 series

Start Address 0x0800 0000 0x0800 0000

End Address up to 0x080F FFFF up to 0x0803 FFFF
up to 32 Sector of 4 Kbytes:
Main/Program sector is 4 Pages of 1 Kbytes on
memory Page of 2 Kbytes size STM32F03x, STM32F04x and
Granularity except for Low and Medium density STM32F05x or 2pages of 2Kbytes on
Page of 1 Kbytes STM32F07x.
The STM32F09x has 31 sectors of
4 Kbytes and 1 sector of 132 Kbytes.

EEPROM Start Address

Available by SW emulation Available by software emulation
memory End Address
0x1FFF EC00 on STM32F03/5x
0x1FFF C800 on STM32F07x
Start Address 0x1FFF F000
System memory 0x1FFF C400 on STM32F04x
0x1FFF D800 on STM32F09x
End Address 0x1FFF F7FF 0x1FFF F7FF
Start Address 0x1FFF F800 0x1FFF F800
0x1FFF F80B on STM32F03x,
Option Bytes STM32F04x and STM32F05x
End Address 0x1FFF F80F
0x1FFF F80F on STM32F07x and
STM32F09x
Start address 0x4002 2000 0x4002 2000
Same as STM32F1 series for Flash
Flash interface Programming program and erase operations.
Same for all product lines
procedure Different from STM32F1 series for
Option byte programming(2)
Read protection disable Level 0 no protection
Unprotection
RDP = 0xA55A RDP = 0xAA

Level 1 memory protection

Read Protection
Read protection enable RDP != (Level 2 & Level 0)
Protection
RDP != 0xA55A Level 2: Lvl 1 +Debug disabled
RDP = 0xCC(3)

Write protection Protection by 4Kbytes Protection by sector(3)

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Table 17. Flash differences between STM32F1 series and STM32F0 series(1) (continued)
FLASH STM32F1 series STM32F0 series

STOP STOP
STANDBY STANDBY
WDG WDG
NA RAM_PARITY_CHECK
User Option bytes
NA VDDA_MONITOR
NA nBOOT1
NA nBOOT0
NA BOOT_SEL
Erase granularity Page (1 or 2 Kbytes) Page (1 Kbytes or 2Kbytes)
Program mode Half word (16 bit) Half word (16 bit)
Same feature but spec change or enhancement
New features
1. NA in gray table cells means Not Applicable.
2. New feature.
3. Same feature but with specification change or enhancement.

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3.10 ADC interface

The table below presents the differences between the ADC interface of STM32F1 series
and STM32F0 series; these differences are the following:
 New digital interface
 New architecture and new features

Table 18. ADC differences between STM32F1 series and STM32F0 series
ADC STM32F1 series STM32F0 series

ADC Type SAR structure SAR structure

Repartition ADC1 / ADC2 / ADC3 ADC
Max Sampling freq 1 MSPS 1 MSPS
up to 16 channels + 3
Number of channels up to 21 channels
internal(1)
Resolution 12-bit 12-bit
Single / continuous / Scan /
Conversion Modes Single / continuous / Scan / Discontinuous / Dual Mode Discontinuous
Dual Mode
DMA Yes Yes
External Trigger External event for regular External event for injected
group group
For ADC1 and ADC2: For ADC1 and ADC2:
TIM1 CC1 TIM1 TRGO
TIM1 CC2 TIM1 CC4
TIM1 CC3 TIM2 TRGO
TIM2 CC2 TIM2 CC1 External event
TIM3 TRGO TIM3 CC4
TIM1_TRGO
TIM4 CC4 TIM4 TRGO
TIM1_CC4
EXTI line 11 / EXTI line15 /
TIM2_TRGO
TIM8_TRGO TIM8_CC4
TIM3_TRGO
For ADC3: For ADC3:
TIM15_TRGO(1)
TIM3 CC1 TIM1 TRGO
TIM2 CC3 TIM1 CC4
TIM1 CC3 TIM4 CC3
TIM8 CC1 TIM8 CC2
TIM8 TRGO TIM8 CC4
TIM5 CC1 TIM5 TRGO
TIM5 CC3 TIM5 CC4

Supply requirement 2.4 V to 3.6 V 2.4 V to 3.6 V

Input range Vref- ≤ Vin ≤ Vref+ VSSA ≤ VIN ≤ VDDA ≤ 3.6 V
1. Same feature but specification change or enhancement.

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3.11 PWR interface

In STM32F0 series the PWR controller presents some differences vs. STM32F1 series,
these differences are summarized in the table below. However, the programming interface is
unchanged.

Table 19. PWR differences between STM32F1 series and STM32F0 series
PWR STM32F1 series STM32F0x0/x1/x2 devices STM32F0x8 devices

1-VDD = 2.0 to 3.6 V: external

1-VDD = 1.8 V +/- 8%: external
1-VDD = 2.0 to 3.6 V: external power supply for I/Os and the
power supply for I/Os. Provided
power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
internal regulator. Provided externally through VDD pins.
2-VDDA = 1.65 to 3.6 V: external
externally through VDD pins. 2-VDDA = 2.0 to 3.6 V: external
analog power supplies for ADC,
2-VDDA = 2.0 to 3.6 V: external analog power supplies for ADC,
DAC, Reset blocks, RCs and
analog power supplies for ADC, DAC, Reset blocks, RCs and
PLL. VDDA and VSSA must be
Reset blocks, RCs and PLL. PLL. VDDA and VSSA must be
Power connected to VDD and VSS,
VDDA and VSSA must be connected to VDD and VSS,
supplies respectively.
connected to VDD and VSS, respectively.
3-VBAT = 1.65 to 3.6 V: power
respectively. 3-VBAT = 1.65 to 3.6 V: power
supply for RTC, external clock
3-VBAT = 1.8 to 3.6 V: power supply for RTC, external clock
32 kHz oscillator and backup
supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch)
32 kHz oscillator and backup registers (through power switch)
when VDD is not present.
registers (through power switch) when VDD is not present.
when VDD is not present. 4-VDDIO2 = 0V to 3.6V available
4-VDDIO2 = 0V to 3.6V available
only STM32F07x
only STM32F07x
Backup registers Backup registers
Backup registers
Battery RTC RTC
RTC
backup LSE LSE
LSE
domain RCC Backup Domain Control RCC Backup Domain Control
PC13 to PC15 I/Os
Register(1) Register(1)

Power Integrated POR / PDR circuitry Integrated POR / PDR circuitry Power ON reset must be
supply Programmable Voltage Detector Programmable Voltage Detector controlled externally through the
supervisor (PVD) (PVD) dedicated NPOR pin.
Sleep mode Sleep mode
Low-power Stop mode Stop mode Sleep mode
modes Standby mode (1.8 V domain Standby mode (1.8 V domain Stop mode
powered-off) powered-off)
Sleep mode Sleep mode
– Any peripheral – Any peripheral
interrupt/wakeup event interrupt/wakeup event
Sleep mode
Stop mode Stop mode
– Any peripheral
Wake-up – Any EXTI line event/interrupt – Any EXTI line event/interrupt
interrupt/wakeup event
sources Standby mode Standby mode
Stop mode
– WKUP pin rising edge – WKUPx pins rising edge
– Any EXTI line event/interrupt
– RTC alarm – RTC alarm / autowakeup
– External reset in NRST pin – External reset in NRST pin
– IWDG reset – IWDG reset
1. Same feature but specification change or enhancement

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3.12 Real-time clock (RTC) interface

The STM32F0 series embeds a new RTC peripheral versus the STM32F1 series. The
architecture, features and programming interface are different.
As a consequence, the STM32F0 RTC programming procedures and registers are different
from those of the STM32F1 series, so any code written for the STM32F1 series using the
RTC needs to be rewritten to run on STM32F0 series.
The STM32F0 RTC provides best-in-class features:
 BCD timer/counter
 Time-of-day clock/calendar featuring subsecond precision with programmable daylight
saving compensation
 Automatic wake-up unit generating a periodic flag that triggers an automatic wake-up
interrupt
 A programmable alarm
 Digital calibration circuit
 Time-stamp function for event saving
 Accurate synchronization with an external clock using the subsecond shift feature.
 5 backup registers (20 bytes) which are reset when a tamper detection event occurs
For more information about STM32F0 RTC features, please refer to RTC chapter of
STM32F0xx Reference Manual (RM0091).
For advanced information about the RTC programming, please refer to Application Note
AN3371 Using the STM32 HW real-time clock (RTC).

3.13 SPI interface

The STM32F0 series embeds a new SPI peripheral versus the STM32F1 series. The
architecture, features and programming interface are modified to introduce new capabilities.
As a consequence, the STM32F0 SPI programming procedures and registers are similar to
those of the STM32F1 series but with new features. The code written for the STM32F1
series using the SPI needs little rework to run on STM32F0 series, if it did not use new
capabilities.
The STM32F0 SPI provides best-in-class added features:
 Enhanced NSS control - NSS pulse mode (NSSP) and TI mode
 Programmable data frame length from 4-bit to 16-bit
 Two 32-bit Tx/Rx FIFO buffers with DMA capability and data packing access for frames
fitted into one byte (up to 8-bit)
 8-bit or 16-bit CRC calculation length for 8-bit and 16-bit data.
Furthermore, the SPI peripheral, available in the STM32F0 family, fixes the CRC limitation
present in the STM32F1 family product. For more information about STM32F0 SPI features,
please refer to SPI chapter of STM32F0xx Reference Manual (RM0091).

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3.14 I2C interface

The STM32F0 series embeds a new I2C peripheral versus the STM32F1 series. The
architecture, features and programming interface are different.
As a consequence, the STM32F0 I2C programming procedures and registers are different
from those of the STM32F1 series, so any code written for the STM32F1 series using the
I2C needs to be rewritten to run on STM32F0 series.
The STM32F0 I2C provides best-in-class new features:
 Communication events managed by hardware.
 Programmable analog and digital noise filters.
 Independent clock source: HSI or SYSCLK.
 Wake-up from STOP mode.
 Fast mode + (up to 1MHz) with 20mA I/O output current drive.
 7-bit and 10-bit addressing mode, multiple 7-bit slave address support with
configurable masks.
 Address sequence automatic sending (both 7-bit and 10-bit) in master mode.
 Automatic end of communication management in master mode.
 Programmable Hold and Setup times.
 Command and Data Acknowledge control.
For more information about STM32F0 I2C features, please refer to I2C chapter of
STM32F0xx Reference Manual (RM0091).

3.15 USART interface

The STM32F0 series embeds a new USART peripheral versus the STM32F1 series. The
architecture, features and programming interface are modified to introduce new capabilities.
As a consequence, the STM32F0 USART programming procedures and registers are
modified from those of the STM32F1 series, so any code written for the STM32F1 series
using the USART needs to be updated to run on STM32F0 series.

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The STM32F0 USART provides best-in-class added features:

 A choice of independent clock sources allowing
– UART functionality and wake-up from low power modes,
– convenient baud-rate programming independently of the APB clock
reprogramming.
 Smartcard emulation capability: T=0 with auto retry and T=1
 Swappable Tx/Rx pin configuration
 Binary data inversion
 Tx/Rx pin active level inversion
 Transmit/receive enable acknowledge flags
 New Interrupt sources with flags:
– Address/character match
– Block length detection and timeout detection
 Timeout feature
 Modbus communication
 Overrun flag disable
 DMA disable on reception error
 Wake-up from STOP mode
 Auto baud rate detection capability
 Driver Enable signal (DE) for RS485 mode
For more information about STM32F0 USART features, please refer to USART chapter of
STM32F0xx Reference Manual (RM0091).

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3.16 CEC interface

The STM32F0 series embeds a new CEC peripheral versus the STM32F1 series. The
architecture, features and programming interface are modified to introduce new capabilities.
As a consequence, the STM32F0 CEC programming procedures and registers are different
from those of the STM32F1 series, so any code written for the STM32F1 series using the
CEC needs to be rewritten to run on STM32F0 series.
The STM32F0 CEC provides best-in-class added features:
 32 KHz CEC kernel with dual clock
– LSE
– HSI/244
 Reception in listen mode
 Rx tolerance margin: standard or extended
 Arbitration (signal free time): standard (by H/W) or aggressive (by S/W)
 Arbitration lost detected flag/interrupt
 Automatic transmission retry supported in case of arbitration lost
 Multi-address configuration
 Wake-up from STOP mode
 Receive error detection
– Bit rising error (with stop reception)
– Short bit period error
– Long bit period error
 Configurable error bit generation
– on bit rising error detection
– on long bit period error detection
 Transmission under run detection
 Reception overrun detection
The following features present in the STM32F1 family are now handled by the new
STM32F0 CEC features and thus are no more available.
 Bit timing error mode & bit period error mode, by the new error handler
 Configurable prescaler frequency divider, by the CEC fixed kernel clock
For more information about STM32F0 CEC features, please refer to CEC chapter of
STM32F0xx Reference Manual (RM0091).

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3.17 USB interface

The STM32F0 series embeds an enhanced USB peripheral versus the STM32F1 series.
New features are introduced to provide more capabilities to users.
The STM32F0 USB provides best-in-class added features:
 Up to 1024 Bytes of dedicated packet buffer memory SRAM (last 256 Bytes are
exclusively shared with CAN peripheral)
 Battery Charging Specification Revision 1.2 support
 USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)
 USB 2.0 Link Power Management (LPM) support
 Crystal-less capability with the HSI48 RC oscillator and the CRS, that can use the USB
SOF signal to adjust the frequency on-fly

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4 Firmware migration using the library

This section describes how to migrate an application based on STM32F1xx Standard

Peripherals Library in order to use the STM32F0xx Standard Peripherals Library.
The STM32F1xx and STM32F0xx libraries have the same architecture and are CMSIS
compliant; they use the same driver naming and the same APIs for all compatible
peripherals.
Only a few peripheral drivers need to be updated to migrate the application from an
STM32F1 series to an STM32F0 series product.
Note: In the rest of this chapter (unless otherwise specified), the term “STM32F0xx Library” is
used to refer to the STM32F0xx Standard Peripherals Library, and the term “STM32F10x
Library” is used to refer to the STM32F10x Standard Peripherals Library.

4.1 Migration steps

To update your application code to run on STM32F0xx Library, you have to follow the steps
listed below:
1. Update the toolchain startup files
a) Project files: device connections and Flash memory loader. These files are
provided with the latest version of your toolchain that supports STM32F0xxx
devices. For more information, please refer to your toolchain documentation.
b) Linker configuration and vector table location files: these files are developed
following the CMSIS standard and are included in the STM32F0xx Library install
package under the following directory: Libraries\CMSIS\Device\ST\STM32F0xx.
2. Add STM32F0xx Library source files to the application sources
a) Replace the stm32f10x_conf.h file of your application with stm32f0xx_conf.h
provided in STM32F0xx Library.
b) Replace the existing stm32f10x_it.c/stm32f10x_it.h files in your application with
stm32f0xx_it.c/Stm32f0xx_it.h provided in STM32F0xx Library.
3. Update the part of your application code that uses the RCC, PWR, GPIO, FLASH, ADC
and RTC drivers. Further details are provided in the next section.
Note: The STM32F0xx Library comes with a rich set of examples (67 in total) demonstrating how
to use the different peripherals (under Project\STM32F0xx_StdPeriph_Examples\).

4.2 RCC driver

1. System clock configuration: as presented in section 3.4: Reset and clock controller
(RCC) interface, the STM32F0 and STM32F1 series have the same clock sources and
configuration procedures. However, there are some differences related to the product
voltage range, PLL configuration, maximum frequency and Flash wait state
configuration. Thanks to the CMSIS layer, these differences are hidden from the
application code; you only have to replace the system_stm32f10x.c file by
system_stm32f0xx.c file. This file provides an implementation of SystemInit() function

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used to configure the microcontroller system at start-up and before branching to the
main() program.
Note: For STM32F0xx, you can use the clock configuration tool,
STM32F0xx_Clock_Configuration.xls, to generate a customized SystemInit() function
depending on your application requirements. For more information, refer to AN4055 “Clock
configuration tool for STM32F0xx microcontrollers”.
2. Peripheral access configuration: as presented in section 3.4: Reset and clock controller
(RCC) interface, you need to call different functions to [enable/disable] or [enter/exit]
the peripheral [clock] or [from reset mode]. For example, GPIOA is mapped on AHB
bus on STM32F0 series (APB2 bus on STM32F1 series). To enable its clock, you have
to use the RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
function instead of:
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
in the STM32F1 series.
Refer to Table 8 for the peripheral bus mapping changes between STM32F0 and
STM32F1 series.
3. Peripheral clock configuration
Some STM32F0xx peripherals support dual clock features. The table below summarizes the
clock sources for those IPs in comparison with STM32F10xx peripherals.

Table 20. STM32F10x and STM32F0xx source clock API correspondence

Source clock in STM32F10xx
Peripherals Source clock in STM32F0xx device
device

– HSI14: by default
ADC APB2 clock with prescaler – APB2 clock/2
– APB2 clock/4
HSI/244: by default
LSE
CEC APB1 clock with prescaler APB clock: Clock for the digital interface
(used for register read/write access). This
clock is equal to the APB2 clock.
I2C1can be clocked with:
– System clock
I2C APB1 clock – HSI
I2C2 can be only clocked with:
– HSI
SPI/I2S System clock System clock
USART1, USART2 and USART3 can be
clocked with:
USART1 can be clocked with – system clock
– PCLK2 (72 MHz Max) – LSE clock
USART
Other USARTs can be clocked with – HSI clock
– PCLK1 (36 MHz Max) – APB clock (PCLK)
For STM32F051 devices, USART2 can be
only clocked with system clock

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4.3 Flash driver

The table below presents the Flash driver API correspondence between STM32F10x and
STM32F0xx Libraries. You can easily update your application code by replacing
STM32F10x functions by the corresponding function in the STM32F0xx Library.

Table 21. STM32F10x and STM32F0xx Flash driver API correspondence

STM32F10x Flash driver API STM32F0xx Flash driver API

void FLASH_SetLatency(uint32_t
void FLASH_SetLatency(uint32_t FLASH_Latency);
FLASH_Latency);
void FLASH_PrefetchBufferCmd(uint32_t void FLASH_PrefetchBufferCmd(FunctionalState
Interface configuration

FLASH_PrefetchBuffer); NewState);
void FLASH_HalfCycleAccessCmd(uint32_t
NA
FLASH_HalfCycleAccess);

void FLASH_ITConfig(uint32_t FLASH_IT, void FLASH_ITConfig(uint32_t FLASH_IT,

FunctionalState NewState); FunctionalState NewState);

void FLASH_Unlock(void); void FLASH_Unlock(void);

void FLASH_Lock(void); void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t FLASH_Status FLASH_ErasePage(uint32_t
Memory Programming

Page_Address); Page_Address);
FLASH_Status FLASH_EraseAllPages(void); FLASH_Status FLASH_EraseAllPages(void);
FLASH_STATUS
FLASH_STATUS FLASH_OB_ERASE(void);
FLASH_ERASEOPTIONBYTES(void);
FLASH_Status
FLASH_Status FLASH_ProgramWord(uint32_t
FLASH_ProgramWord(uint32_t Address,
Address, uint32_t Data);
uint32_t Data);
FLASH_Status
FLASH_Status FLASH_ProgramHalfWord(uint32_t
FLASH_ProgramHalfWord(uint32_t Address,
Address, uint16_t Data);
uint16_t Data);

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Table 21. STM32F10x and STM32F0xx Flash driver API correspondence (continued)
STM32F10x Flash driver API STM32F0xx Flash driver API

NA void FLASH_OB_Unlock(void);
NA void FLASH_OB_Lock(void);
FLASH_Status
FLASH_Status FLASH_ProgramOptionByteData(uint32_t
FLASH_ProgramOptionByteData(uint32_t
Address, uint8_t Data);
Address, uint8_t Data);
FLASH_Status
FLASH_Status FLASH_OB_EnableWRP(uint32_t
FLASH_EnableWriteProtection(uint32_t
OB_WRP);
FLASH_Pages);
FLASH_Status
FLASH_Status FLASH_OB_RDPConfig(uint8_t
FLASH_ReadOutProtection(FunctionalState
OB_RDP);
NewState);
FLASH_Status
Option Byte Programming

FLASH_UserOptionByteConfig(uint16_t FLASH_Status FLASH_OB_UserConfig(uint8_t

OB_IWDG, uint16_t OB_STOP, uint16_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
OB_STDBY);
NA FLASH_Status FLASH_OB_Launch(void);
FLASH_Status FLASH_OB_WriteUser(uint8_t
NA
OB_USER);
FLASH_Status FLASH_OB_BOOTConfig(uint8_t
NA
OB_BOOT1);
FLASH_Status FLASH_OB_VDDAConfig(uint8_t
NA
OB_VDDA_ANALOG);
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t
NA
OB_SRAM_Parity);
FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t
NA
OB_BOOT0SW); (*)
uint32_t FLASH_GetUserOptionByte(void); uint8_t FLASH_OB_GetUser(void);
uint32_t
uint16_t FLASH_OB_GetWRP(void);
FLASH_GetWriteProtectionOptionByte(void);
FlagStatus
FlagStatus FLASH_OB_GetRDP(void);
FLASH_GetReadOutProtectionStatus(void);

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Table 21. STM32F10x and STM32F0xx Flash driver API correspondence (continued)
STM32F10x Flash driver API STM32F0xx Flash driver API

FlagStatus FLASH_GetFlagStatus(uint32_t FlagStatus FLASH_GetFlagStatus(uint32_t

FLASH_FLAG); FLASH_FLAG);
void FLASH_ClearFlag(uint32_t
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_FLAG);
FLAG management

FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_GetStatus(void);

FLASH_Status
FLASH_WaitForLastOperation(uint32_t FLASH_Status FLASH_WaitForLastOperation(void);
Timeout);
FlagStatus
FlagStatus FLASH_GetPrefetchBufferStatus(void);
FLASH_GetPrefetchBufferStatus(void);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)
Note: (*) This function is applicable only for STM32F042 devices.

4.4 CRC driver

The table below presents the CRC driver API correspondence between STM32F10x and
STM32F0xx Libraries.

Table 22. STM32F10xx and STM32F0xx CRC driver API correspondence

STM32F10xx CRC driver API STM32F0xx CRC driver API

NA void CRC_DeInit(void);
void CRC_ResetDR(void); void CRC_ResetDR(void);
void CRC_ReverseInputDataSelect(uint32_t
NA
CRC_ReverseInputData);
Configuration

void CRC_ReverseOutputDataCmd(FunctionalState
NA
NewState);
NA void CRC_SetInitRegister(uint32_t CRC_InitValue);
void CRC_PolynomialSizeSelect(uint32_t
NA
CRC_PolSize)(*)
NA void CRC_SetPolynomial(uint32_t CRC_Pol)(*)
uint32_t CRC_CalcCRC(uint32_t CRC_Data); uint32_t CRC_CalcCRC(uint32_t CRC_Data);
Computation

uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[],

uint32_t BufferLength); uint32_t BufferLength);
uint32_t CRC_GetCRC(void); uint32_t CRC_GetCRC(void);
NA void CRC_CalcCRC16bits(uint32_t CRC_Data)(*)
NA void CRC_CalcCRC8bits(uint32_t CRC_Data)(*)

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Table 22. STM32F10xx and STM32F0xx CRC driver API correspondence (continued)
STM32F10xx CRC driver API STM32F0xx CRC driver API

void CRC_SetIDRegister(uint8_t CRC_IDValue); void CRC_SetIDRegister(uint8_t CRC_IDValue);

IDR access

uint8_t CRC_GetIDRegister(void); uint8_t CRC_GetIDRegister(void);

Note: (*) This function is only applicable for STM32F07x, STM32F04x and STM32F091 devices.
Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

4.5 GPIO configuration update

This section explains how to update the configuration of the various GPIO modes when
porting the application code from STM32F1 series to STM32F0 series.

4.5.1 Output mode

The example below shows how to configure an I/O in output mode (for example to drive a
LED) in STM32F1 series:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_xxMHz; /* 2, 10 or 50 MHz */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOy, &GPIO_InitStructure);
In STM32F0 series, you have to update this code as follows:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; /* Push-pull or open drain
*/
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; /* None, Pull-up or pull-down
*/
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_xxMHz; /* 10, 2 or 50MHz */
GPIO_Init(GPIOy, &GPIO_InitStructure);

4.5.2 Input mode

The example below shows how to configure an I/O in input mode (for example to be used as
an EXTI line) in STM32F1 series:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOy, &GPIO_InitStructure);
In STM32F0 series, you have to update this code as follows:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x;

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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; /* None, Pull-up or pull-
down */
GPIO_Init(GPIOy, &GPIO_InitStructure);

4.5.3 Analog mode

The example below shows how to configure an I/O in analog mode (for example, an ADC or
DAC channel) in STM32F1 series:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
GPIO_Init(GPIOy, &GPIO_InitStructure);
In STM32F0 series, you have to update this code as follows:
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_x ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
GPIO_Init(GPIOy, &GPIO_InitStructure);

4.5.4 Alternate function mode

In STM32F1 series
1. The configuration to use an I/O as an alternate function depends on the peripheral
mode used; for example, the USART Tx pin should be configured as an alternate
function push-pull while the USART Rx pin should be configured as an input floating or
an input pull-up.
2. To optimize the number of peripheral I/O functions for different device packages, it is
possible, by software, to remap some alternate functions to other pins. For example,
the USART2_RX pin can be mapped on PA3 (default remap) or PD6 (by software
remap).
In STM32F0 series
1. Whatever the peripheral mode used, the I/O must be configured as an alternate
function, then the system can use the I/O in the proper way (input or output).
2. The I/O pins are connected to on-board peripherals/modules through a multiplexer that
allows only one peripheral alternate function to be connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals sharing the same I/O pin. Each
I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can
be configured through the GPIO_PinAFConfig () function:
– After reset, all I/Os are connected to the system alternate function 0 (AF0)
– The peripherals’ alternate functions are mapped by configuring AF1 to AF7.
3. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripheral I/O

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functions for different device packages; for example, the USART2_RX pin can be
mapped on PA3 or PA15 pin.
4. Configuration procedure:
– Connect the pin to the desired peripherals' Alternate Function (AF) using
GPIO_PinAFConfig() function
– Use GPIO_Init() function to configure the I/O pin:
- Configure the desired pin in alternate function mode using
GPIO_InitStructure->GPIO_Mode = GPIO_Mode_AF;
- Select the type, pull-up/pull-down and output speed via
GPIO_PuPd, GPIO_OType and GPIO_Speed members
The example below shows how to remap USART2 Tx/Rx I/Os on PD5/PD6 pins in
STM32F1 series:
/* Enable APB2 interface clock for GPIOD and AFIO (AFIO peripheral is used
to configure the I/Os software remapping) */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO,
ENABLE);

/* Enable USART2 I/Os software remapping

[(USART2_Tx,USART2_Rx):(PD5,PD6)] */
GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);

/* Configure USART2_Tx as alternate function push-pull */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);

/* Configure USART2_Rx as input floating */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
In STM32F0 series, you have to update this code as follows:
/* Enable GPIOA's AHB interface clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);

/* Select USART2 I/Os mapping on PA14/15 pins

[(USART2_TX,USART2_RX):(PA.14,PA.15)] */
/* Connect PA14 to USART2_Tx */
GPIO_PinAFConfig(GPIOA, GPIO_PinSource14, GPIO_AF_2);
/* Connect PA15 to USART2_Rx*/
GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_2);

/* Configure USART2_Tx and USART2_Rx as alternate function */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;

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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOA, &GPIO_InitStructure);

4.6 EXTI Line0

The example below shows how to configure the PA0 pin to be used as EXTI Line0 in
STM32F1 series:
/* Enable APB interface clock for GPIOA and AFIO */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO,
ENABLE);

/* Configure PA0 pin in input mode */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Connect EXTI Line0 to PA0 pin */

GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource0);

/* Configure EXTI line0 */

EXTI_InitStructure.EXTI_Line = EXTI_Line0;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);

In STM32F0 series, the configuration of the EXTI line source pin is performed in the
SYSCFG peripheral (instead of AFIO in STM32F1 series). As a result, the source code
should be updated as follows:
/* Enable GPIOA's AHB interface clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
/* Enable SYSCFG's APB interface clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

/* Configure PA0 pin in input mode */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Connect EXTI Line0 to PA0 pin */

SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);

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/* Configure EXTI line0 */

EXTI_InitStructure.EXTI_Line = EXTI_Line0;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);

4.7 NVIC interrupt configuration

This section describes the configuration of the NVIC interrupts (IRQ).
In STM32F1 series, the NVIC supports:
– up to 81 interrupts
– A programmable priority level of 0-15 for each interrupt (4 bits of interrupt priority
are used). A higher level corresponds to a lower priority; level 0 is the highest
interrupt priority.
– Grouping of priority values into group priority and sub priority fields.
– Dynamic changing of priority levels.
The Cortex-M3 exceptions are managed by CMSIS functions:
 Enable and configure the preemption priority and sub priority of the selected IRQ
channels according to the Priority grouping configuration.
The example below shows how to configure the CEC interrupt in STM32F1 series:
/* Configure two bits for preemption priority */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Enable the CEC global Interrupt (with higher priority) */
NVIC_InitStructure.NVIC_IRQChannel = CEC_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
In STM32F0 series, the NVIC supports:
– Up to 32 interrupts
– 4 programmable priority levels (2 bits of interrupt priority are used).
– The priority level of an interrupt should not be changed after it is enabled.
The Cortex-M0 exceptions are managed by CMSIS functions:
 Enable and configure the priority of the selected IRQ channels. The priority ranges
between 0 and 3. Lower priority values give a higher priority.
In STM32F0 series, the configuration of the CEC Interrupt source code should be updated
as follows:
/* Enable the CEC global Interrupt (with higher priority) */
NVIC_InitStructure.NVIC_IRQChannel = CEC_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);

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The table below presents the MISC driver API correspondence between STM32F10x and
STM32F0xx Libraries.

Table 23. STM32F10x and STM32F0xx MISC driver API correspondence

STM32F10xx MISC Driver API STM32F0xx MISC Driver API

void NVIC_Init(NVIC_InitTypeDef*
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
NVIC_InitStruct);
void NVIC_SystemLPConfig(uint8_t void NVIC_SystemLPConfig(uint8_t
LowPowerMode, FunctionalState NewState); LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t void SysTick_CLKSourceConfig(uint32_t
SysTick_CLKSource); SysTick_CLKSource);
NVIC_PriorityGroupConfig(uint32_t
NA
NVIC_PriorityGroup);
void NVIC_SetVectorTable(uint32_t
NA
NVIC_VectTab, uint32_t Offset);

4.8 ADC configuration

This section gives an example of how to port existing code from STM32F1 series to
STM32F0 series.
The example below shows how to configure the ADC1 to convert continuously channel 14 in
STM32F1 series:

/* ADCCLK = PCLK2/4 */
RCC_ADCCLKConfig(RCC_PCLK2_Div4);

/* Enable ADC's APB interface clock */

RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

/* Configure ADC1 to convert continously channel14 */

ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = ENABLE;
ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_Init(ADC1, &ADC_InitStructure);
/* ADC1 regular channel14 configuration */
ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1,
ADC_SampleTime_55Cycles5);

/* Enable ADC1's DMA interface */

ADC_DMACmd(ADC1, ENABLE);

/* Enable ADC1 */

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ADC_Cmd(ADC1, ENABLE);

/* Enable ADC1 reset calibration register */

ADC_ResetCalibration(ADC1);
/* Check the end of ADC1 reset calibration register */
while(ADC_GetResetCalibrationStatus(ADC1));

/* Start ADC1 calibration */

ADC_StartCalibration(ADC1);
/* Check the end of ADC1 calibration */
while(ADC_GetCalibrationStatus(ADC1));

/* Start ADC1 Software Conversion */

ADC_SoftwareStartConvCmd(ADC1, ENABLE);
...
In STM32F0 series, you have to update this code as follows:
...
/* ADCCLK = PCLK/2 */
RCC_ADCCLKConfig(RCC_ADCCLK_PCLK_Div2);

/* Enable ADC1 clock */

RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

/* ADC1 configuration */
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge =
ADC_ExternalTrigConvEdge_None;

ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_ScanDirection = ADC_ScanDirection_Backward;
ADC_Init(ADC1, &ADC_InitStructure);

/* Convert the ADC1 Channel 1 with 55.5 Cycles as sampling time */

ADC_ChannelConfig(ADC1, ADC_Channel_11 , ADC_SampleTime_55_5Cycles);

/* ADC Calibration */
ADC_GetCalibrationFactor(ADC1);

/* ADC DMA request in circular mode */

ADC_DMARequestModeConfig(ADC1, ADC_DMAMode_Circular);

/* Enable ADC_DMA */
ADC_DMACmd(ADC1, ENABLE);

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/* Enable ADC1 */
ADC_Cmd(ADC1, ENABLE);

/* Wait the ADCEN falg */

while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_ADEN));

/* ADC1 regular Software Start Conv */

ADC_StartOfConversion(ADC1);
...

4.9 DAC driver

The table below describes the difference between STM32F10x functions and the
STM32F0xx Library.

Table 24. STM32F10x and STM32F0xx DAC driver API correspondence

STM32F10x DAC driver API STM32F0xx DAC driver API

void DAC_DeInit(void); void DAC_DeInit(void);

void DAC_Init(uint32_t DAC_Channel, void DAC_Init(uint32_t DAC_Channel,
DAC_InitTypeDef* DAC_InitStruct); DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* void DAC_StructInit(DAC_InitTypeDef*
DAC_InitStruct); DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, void DAC_Cmd(uint32_t DAC_Channel,
FunctionalState NewState); FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t void DAC_SoftwareTriggerCmd(uint32_t
DAC_Channel, FunctionalState NewState); DAC_Channel, FunctionalState NewState);
void
NA DAC_DualSoftwareTriggerCmd(FunctionalState
NewState);(**)
void DAC_WaveGenerationCmd(uint32_t
NA DAC_Channel, uint32_t DAC_Wave,
FunctionalState NewState)(**)
void DAC_SetChannel1Data(uint32_t DAC_Align, void DAC_SetChannel1Data(uint32_t DAC_Align,
uint16_t Data); uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, void DAC_SetChannel2Data(uint32_t DAC_Align,
uint16_t Data); uint16_t Data);(**)
Configuration

void DAC_SetDualChannelData(uint32_t void DAC_SetDualChannelData(uint32_t

DAC_Align, uint16_t Data2, uint16_t Data1); DAC_Align, uint16_t Data2, uint16_t Data1);(**)
uint16_t DAC_GetDataOutputValue(uint32_t uint16_t DAC_GetDataOutputValue(uint32_t
DAC_Channel); DAC_Channel);

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Table 24. STM32F10x and STM32F0xx DAC driver API correspondence (continued)
STM32F10x DAC driver API STM32F0xx DAC driver API
Interrupts and flags management DMA management

void DAC_DMACmd(uint32_t DAC_Channel, void DAC_DMACmd(uint32_t DAC_Channel,

FunctionalState NewState); FunctionalState NewState);

void DAC_ITConfig(uint32_t DAC_Channel, void DAC_ITConfig(uint32_t DAC_Channel,

uint32_t DAC_IT, FunctionalState NewState);(*) uint32_t DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(uint32_t FlagStatus DAC_GetFlagStatus(uint32_t
DAC_Channel, uint32_t DAC_FLAG);(*) DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, void DAC_ClearFlag(uint32_t DAC_Channel,
uint32_t DAC_FLAG);(*) uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t ITStatus DAC_GetITStatus(uint32_t
DAC_Channel, uint32_t DAC_IT);(*) DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t void DAC_ClearITPendingBit(uint32_t
DAC_Channel, uint32_t DAC_IT);(*) DAC_Channel, uint32_t DAC_IT);

Note: (*) These functions exist only on STM32F10X_LD_VL, STM32F10X_MD_VL, and

STM32F10X_HD_VL devices.
(**)This function is only applicable for STM32F072 and STM32F091 devices.
The main changes in the source code/procedure in STM32F051 devices versus STM32F1
are described below:
 No Dual mode for DAC channels
 No Noise generator
 No Triangle generator
 In the DAC structure definition, only two fields (external trigger, OutputBuffer) should be
initialized.
The example below shows how to configure the DAC channel 1 STM32F1 series:
/* DAC channel1 Configuration */
DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
DAC_Init(DAC_Channel_1, &DAC_InitStructure);
Only for STM32F051devices, you have to update this code as follows:
/* DAC channel1 Configuration */
DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
/* DAC Channel1 Init */
DAC_Init(DAC_Channel_1, &DAC_InitStructure);

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4.10 PWR driver

The table below presents the PWR driver API correspondence between STM32F10x and
STM32F0xx Libraries. You can easily update your application code by replacing
STM32F10x functions by the corresponding function in the STM32F0xx Library.

Table 25. STM32F10x and STM32F0xx PWR driver API correspondence

STM32F10x PWR driver API STM32F0xx PWR driver API

void PWR_DeInit(void); void PWR_DeInit(void);

configuration
Interface

void PWR_BackupAccessCmd(FunctionalState void PWR_BackupAccessCmd(FunctionalState

NewState); NewState);

void PWR_PVDLevelConfig(uint32_t void PWR_PVDLevelConfig(uint32_t

PWR_PVDLevel); PWR_PVDLevel);
Power Management Wakeup PVD

void PWR_PVDCmd(FunctionalState NewState); void PWR_PVDCmd(FunctionalState NewState);

void PWR_WakeUpPinCmd(FunctionalState void PWR_WakeUpPinCmd(uint32_t

NewState); PWR_WakeUpPin, FunctionalState NewState);(*)

void PWR_EnterSleepMode(uint8_t
NA
PWR_SLEEPEntry);
void PWR_EnterSTOPMode(uint32_t void PWR_EnterSTOPMode(uint32_t
PWR_Regulator, uint8_t PWR_STOPEntry); PWR_Regulator, uint8_t PWR_STOPEntry);

void PWR_EnterSTANDBYMode(void); void PWR_EnterSTANDBYMode(void);

FlagStatus PWR_GetFlagStatus(uint32_t FlagStatus PWR_GetFlagStatus(uint32_t

management

PWR_FLAG); PWR_FLAG);
FLAG

void PWR_ClearFlag(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

(*) More Wake up pins are available on STM32F0 series.

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4.11 Backup data registers

In STM32F1 series, the Backup data registers are managed through the BKP peripheral,
while in STM32F0 series they are a part of the RTC peripheral (there is no BKP peripheral).
The example below shows how to write to/read from Backup data registers in STM32F1
series:

uint16_t BKPdata = 0;

...
/* Enable APB2 interface clock for PWR and BKP */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);

/* Enable write access to Backup domain */

PWR_BackupAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

BKP_WriteBackupRegister(BKP_DR1, 0x3210);

/* Read data from Backup data register 1 */

BKPdata = BKP_ReadBackupRegister(BKP_DR1);

In STM32F0 series, you have to update this code as follows:

uint16_t BKPdata = 0;

...
/* PWR Clock Enable */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);

/* Enable write access to RTC domain */

PWR_RTCAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

RTC_WriteBackupRegister(RTC_BKP_DR1, 0x3220);

/* Read data from Backup data register 1 */

BKPdata = RTC_ReadBackupRegister(RTC_BKP_DR1);
The main changes in the source code in STM32F0 series versus STM32F1 are described
below:
1. There is no BKP peripheral
2. Write to/read from Backup data registers are done through RTC driver
3. Backup data registers naming changed from BKP_DRx to RTC_BKP_DRx, and
numbering starts from 0 instead of 1.

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4.12 CEC application code

You can easily update your CEC application code by replacing STM32F10x functions by the
corresponding function in the STM32F0xx Library.The table below presents the CEC driver
API correspondence between STM32F10x and STM32F0xx Libraries.

Table 26. STM32F10xx and STM32F0xx CEC driver API correspondence

STM32F10xx CEC driver API STM32F0xx CEC driver API

void CEC_DeInit(void); void CEC_DeInit(void);

void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
NA void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
Interface Configuration

void CEC_Cmd(FunctionalState NewState); void CEC_Cmd(FunctionalState NewState);

NA void CEC_ListenModeCmd(FunctionalState NewState);
void CEC_OwnAddressConfig(uint8_t void CEC_OwnAddressConfig(uint8_t
CEC_OwnAddress); CEC_OwnAddress);
NA void CEC_OwnAddressClear(void);
void CEC_SetPrescaler(uint16_t CEC_Prescaler); NA
void CEC_SendDataByte(uint8_t Data); void CEC_SendData(uint8_t Data);
Interrupt and Flag management DATA Transfers

uint8_t CEC_ReceiveDataByte(void); uint8_t CEC_ReceiveData(void);

void CEC_StartOfMessage(void); void CEC_StartOfMessage(void);
void CEC_EndOfMessageCmd(FunctionalState
void CEC_EndOfMessage(void);
NewState);
void CEC_ITConfig(uint16_t CEC_IT, FunctionalState
void CEC_ITConfig(FunctionalState NewState)
NewState);
FlagStatus CEC_GetFlagStatus(uint32_t
FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
CEC_FLAG);
void CEC_ClearFlag(uint32_t CEC_FLAG) void CEC_ClearFlag(uint32_t CEC_FLAG);
ITStatus CEC_GetITStatus(uint8_t CEC_IT) ITStatus CEC_GetITStatus(uint16_t CEC_IT);

void CEC_ClearITPendingBit(uint16_t CEC_IT) void CEC_ClearITPendingBit(uint16_t CEC_IT);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

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The main changes in the source code/procedure in STM32F0 series versus STM32F1 are
described below:
 Dual Clock Source (Refer to RCC section for more details).
 No Prescaler feature configuration.
 It supports more than one address (multiple addressing).
 Each event flag has an associate enable control bit to generate the adequate interrupt.
 In the CEC structure definition, seven fields should be initialized.
The example below shows how to configure the CEC STM32F1 series:
/* Configure the CEC peripheral */
CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
CEC_Init(&CEC_InitStructure);

In STM32F0 series, you have to update this code as follows:

/* Configure CEC */
CEC_InitStructure.CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
CEC_InitStructure.CEC_RxTolerance = CEC_RxTolerance_Standard;
CEC_InitStructure.CEC_StopReception = CEC_StopReception_Off;
CEC_InitStructure.CEC_BitRisingError = CEC_BitRisingError_Off;
CEC_InitStructure.CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
CEC_InitStructure.CEC_BRDNoGen = CEC_BRDNoGen_Off;
CEC_InitStructure.CEC_SFTOption = CEC_SFTOption_Off;
CEC_Init(&CEC_InitStructure);

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4.13 I2C driver

STM32F0xx devices incorporate new I2C features. The table below presents the I2C driver
API correspondence between STM32F10x and STM32F0xx Libraries. You can update your
application code replacing STM32F10x functions by the corresponding function in the
STM32F0xx Library.

Table 27. STM32F10xx and STM32F0xx I2C driver API correspondence

STM32F10xx I2C Driver API STM32F0xx I2C Driver API

void I2C_DeInit(I2C_TypeDef* I2Cx); void I2C_DeInit(I2C_TypeDef* I2Cx);

void I2C_Init(I2C_TypeDef* I2Cx, void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef*
I2C_InitTypeDef* I2C_InitStruct); I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef*
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState
FunctionalState NewState); NewState);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT,
I2C_IT, FunctionalState NewState); FunctionalState NewState);
Initialization and Configuration

void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, void I2C_StretchClockCmd(I2C_TypeDef* I2Cx,

FunctionalState NewState); FunctionalState NewState);
void I2C_StopModeCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, void I2C_DualAddressCmd(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx,
I2Cx, uint8_t Address); uint16_t Address, uint8_t Mask);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx,
NA
uint16_t Address);
void I2C_10BitAddressingModeCmd(I2C_TypeDef*
NA
I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef*
NA
I2Cx, uint16_t I2C_NACKPosition);
void I2C_ARPCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);

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Table 27. STM32F10xx and STM32F0xx I2C driver API correspondence (continued)
STM32F10xx I2C Driver API STM32F0xx I2C Driver API

void I2C_AutoEndCmd(I2C_TypeDef* I2Cx,

NA
FunctionalState NewState);
void I2C_ReloadCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx,
NA
uint8_t Number_Bytes);
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx,
NA
uint16_t I2C_Direction);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, void I2C_GenerateSTART(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
Communications handling

void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, void I2C_GenerateSTOP(I2C_TypeDef* I2Cx,

FunctionalState NewState); FunctionalState NewState);
void I2C_10BitAddressHeaderCmd(I2C_TypeDef*
NA
I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
NA uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
uint16_t I2C_GetTransferDirection(I2C_TypeDef*
NA
I2Cx);
void I2C_TransferHandling(I2C_TypeDef* I2Cx,
NA uint16_t Address, uint8_t Number_Bytes, uint32_t
ReloadEndMode, uint32_t StartStopMode);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,
NA
uint32_t I2C_EVENT)
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx,
NA
uint8_t Address, uint8_t I2C_Direction)

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Table 27. STM32F10xx and STM32F0xx I2C driver API correspondence (continued)
STM32F10xx I2C Driver API STM32F0xx I2C Driver API

void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx,

uint16_t I2C_SMBusAlert); FunctionalState NewState);
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef*
NA
I2Cx, FunctionalState NewState);
SMBUS management

void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx,

NA
FunctionalState NewState);
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t
NA
Timeout);
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t
NA
Timeout);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, void I2C_CalculatePEC(I2C_TypeDef* I2Cx,
FunctionalState NewState); FunctionalState NewState);
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx,
NA
FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx,
Data transfers

uint8_t I2C_Register); uint8_t I2C_Register);

void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_DMACmd(I2C_TypeDef* I2Cx, void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t
DMA management

FunctionalState NewState); I2C_DMAReq, FunctionalState NewState);

void I2C_DMALastTransferCmd(I2C_TypeDef*
NA
I2Cx, FunctionalState NewState);

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Table 27. STM32F10xx and STM32F0xx I2C driver API correspondence (continued)
STM32F10xx I2C Driver API STM32F0xx I2C Driver API

FlagStatus I2C_GetFlagStatus(I2C_TypeDef* FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx,

Interrupts and flags management

I2Cx, uint32_t I2C_FLAG); uint32_t I2C_FLAG);

void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t
I2C_FLAG); I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t
uint32_t I2C_IT); I2C_IT);

void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx,

uint32_t I2C_IT); uint32_t I2C_IT);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

Though some API functions are identical in STM32F1 and STM32F0, in most cases the
application code needs to be rewritten when moving from STM32F1 to STM32F0. However,
STMicroelectronics provides an “I2C Communication peripheral application library (CPAL)”,
which allows to move seamlessly from STM32F1 to STM32F0: user needs to modify only
few settings without any changes on the application code. For more details about STM32F1
I2C CPAL, please refer to UM1029. For STM32F0, the I2C CPAL is provided within the
Standard Peripherals Library package.”

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4.14 SPI driver

The STM32F0xx SPI includes some new features as compared with STM32F10xx SPI.
Table 28 presents the SPI driver API correspondence between STM32F10x and
STM32F0xx Libraries.

Table 28. STM32F10xx and STM32F0xx SPI driver API correspondence

STM32F10xx SPI driver API STM32F0xx SPI driver API

void SPI_I2S_DeInit(SPI_TypeDef* SPIx); void SPI_I2S_DeInit(SPI_TypeDef* SPIx);

void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef*
SPI_InitStruct); SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef*
I2S_InitStruct); I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_TIModeCmd(SPI_TypeDef* SPIx,
NA
Initialization and Configuration

FunctionalState NewState);
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx,
NA
FunctionalState NewState);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState
NewState); NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState
NewState); NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, void SPI_DataSizeConfig(SPI_TypeDef* SPIx,
uint16_t SPI_DataSize); uint16_t SPI_DataSize);
void SPI_RxFIFOThresholdConfig(SPI_TypeDef*
NA
SPIx, uint16_t SPI_RxFIFOThreshold);
void SPI_BiDirectionalLineConfig(SPI_TypeDef*
NA
SPIx, uint16_t SPI_Direction);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* void SPI_NSSInternalSoftwareConfig(SPI_TypeDef*
SPIx, uint16_t SPI_NSSInternalSoft); SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, void SPI_SSOutputCmd(SPI_TypeDef* SPIx,
FunctionalState NewState); FunctionalState NewState);
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t
void SPI_I2S_SendData(SPI_TypeDef* SPIx, Data);
Data Transfers

uint16_t Data); void SPI_I2S_SendData16(SPI_TypeDef* SPIx,

uint16_t Data);
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef*
SPIx);

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Table 28. STM32F10xx and STM32F0xx SPI driver API correspondence (continued)
STM32F10xx SPI driver API STM32F0xx SPI driver API

void SPI_CRCLengthConfig(SPI_TypeDef* SPIx,

Hardware CRC Calculation functions

NA
uint16_t SPI_CRCLength);
void SPI_TransmitCRC(SPI_TypeDef* SPIx); void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, void SPI_CalculateCRC(SPI_TypeDef* SPIx,
FunctionalState NewState); FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t
SPI_CRC); SPI_CRC);

uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* uint16_t SPI_GetCRCPolynomial(SPI_TypeDef*

SPIx); SPIx);

void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, void SPI_I2S_DMACmd(SPI_TypeDef* SPIx,

DMA transfers

uint16_t SPI_I2S_DMAReq, FunctionalState uint16_t SPI_I2S_DMAReq, FunctionalState

NewState); NewState);

void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx,

NA
uint16_t SPI_LastDMATransfer);

void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t

SPI_I2S_IT, FunctionalState NewState); SPI_I2S_IT, FunctionalState NewState);
Interrupts and flags management

uint16_t
NA SPI_GetTransmissionFIFOStatus(SPI_TypeDef*
SPIx);
uint16_t
NA
SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef*
SPIx, uint16_t SPI_I2S_FLAG); SPIx, uint16_t SPI_I2S_FLAG);(*)
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx,
uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx,
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* uint16_t SPI_I2S_FLAG);(*)
SPIx, uint8_t SPI_I2S_IT);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx,
uint8_t SPI_I2S_IT); uint8_t SPI_I2S_IT);(*)

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

(*) One more flag in STM32F0xx (TI frame format error) can generate an event in comparison with STM32F10xx driver API.

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4.15 USART driver

The STM32F0xx USART includes enhancements in comparison with STM32F10xx USART.
Table 29 presents the USART driver API correspondence between STM32F10x and
STM32F0xx Libraries.

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Table 29. STM32F10x and STM32F0xx USART driver API correspondence

STM32F10xx USART driver API STM32F0xx USART driver API

void USART_DeInit(USART_TypeDef* USARTx); void USART_DeInit(USART_TypeDef* USARTx);

void USART_Init(USART_TypeDef* USARTx, void USART_Init(USART_TypeDef* USARTx,
USART_InitTypeDef* USART_InitStruct); USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* void USART_StructInit(USART_InitTypeDef*
USART_InitStruct); USART_InitStruct);
void USART_ClockInit(USART_TypeDef*
void USART_ClockInit(USART_TypeDef* USARTx,
USARTx, USART_ClockInitTypeDef*
USART_ClockInitTypeDef* USART_ClockInitStruct);
USART_ClockInitStruct);
void void
USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockStructInit(USART_ClockInitTypeDef*
USART_ClockInitStruct); USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, void USART_Cmd(USART_TypeDef* USARTx,
FunctionalState NewState); FunctionalState NewState);
void
USART_DirectionModeCmd(USART_TypeDef*
NA
USARTx, uint32_t USART_DirectionMode,
Initialization and Configuration

FunctionalState NewState);
void USART_SetPrescaler(USART_TypeDef* void USART_SetPrescaler(USART_TypeDef*
USARTx, uint8_t USART_Prescaler); USARTx, uint8_t USART_Prescaler);
void
void USART_OverSampling8Cmd(USART_TypeDef*
USART_OverSampling8Cmd(USART_TypeDef*
USARTx, FunctionalState NewState);
USARTx, FunctionalState NewState);
void
void USART_OneBitMethodCmd(USART_TypeDef*
USART_OneBitMethodCmd(USART_TypeDef*
USARTx, FunctionalState NewState);
USARTx, FunctionalState NewState);
void USART_MSBFirstCmd(USART_TypeDef*
NA
USARTx, FunctionalState NewState);
void USART_DataInvCmd(USART_TypeDef*
NA
USARTx, FunctionalState NewState);
void USART_InvPinCmd(USART_TypeDef*
NA USARTx, uint32_t USART_InvPin, FunctionalState
NewState);
void USART_SWAPPinCmd(USART_TypeDef*
NA
USARTx, FunctionalState NewState);
void
NA USART_ReceiverTimeOutCmd(USART_TypeDef*
USARTx, FunctionalState NewState);
void
NA USART_SetReceiverTimeOut(USART_TypeDef*
USARTx, uint32_t USART_ReceiverTimeOut);

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Table 29. STM32F10x and STM32F0xx USART driver API correspondence (continued)
STM32F10xx USART driver API STM32F0xx USART driver API

void USART_STOPModeCmd(USART_TypeDef*
NA
USARTx, FunctionalState NewState);
STOP Mode

void
USART_StopModeWakeUpSourceConfig(USART_
NA
TypeDef* USARTx, uint32_t
USART_WakeUpSource);
void
NA USART_AutoBaudRateCmd(USART_TypeDef*
AutoBaudRate

USARTx, FunctionalState NewState);

void
NA USART_AutoBaudRateConfig(USART_TypeDef*
USARTx, uint32_t USART_AutoBaudRate);
void USART_SendData(USART_TypeDef* USARTx, void USART_SendData(USART_TypeDef*
Data transfers

uint16_t Data); USARTx, uint16_t Data);

uint16_t USART_ReceiveData(USART_TypeDef* uint16_t USART_ReceiveData(USART_TypeDef*

USARTx); USARTx);

void USART_SetAddress(USART_TypeDef* void USART_SetAddress(USART_TypeDef*

USARTx, uint8_t USART_Address); USARTx, uint8_t USART_Address);
void
Multi-Processor
Communication

NA USART_MuteModeWakeUpConfig(USART_TypeD
ef* USARTx, uint32_t USART_WakeUp);
void USART_MuteModeCmd(USART_TypeDef*
NA
USARTx, FunctionalState NewState);
void
NA USART_AddressDetectionConfig(USART_TypeDe
f* USARTx, uint32_t USART_AddressLength);
void void
USART_LINBreakDetectLengthConfig(USART_Type USART_LINBreakDetectLengthConfig(USART_Ty
LIN mode

Def* USARTx, uint32_t peDef* USARTx, uint32_t

USART_LINBreakDetectLength); USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, void USART_LINCmd(USART_TypeDef* USARTx,
FunctionalState NewState); FunctionalState NewState);
Half-duplex
mode

void USART_HalfDuplexCmd(USART_TypeDef* void USART_HalfDuplexCmd(USART_TypeDef*

USARTx, FunctionalState NewState); USARTx, FunctionalState NewState);

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Table 29. STM32F10x and STM32F0xx USART driver API correspondence (continued)
STM32F10xx USART driver API STM32F0xx USART driver API

void USART_SmartCardCmd(USART_TypeDef* void USART_SmartCardCmd(USART_TypeDef*

USARTx, FunctionalState NewState); USARTx, FunctionalState NewState);
void void
USART_SmartCardNACKCmd(USART_TypeDef* USART_SmartCardNACKCmd(USART_TypeDef*
Smart Card mode

USARTx, FunctionalState NewState); USARTx, FunctionalState NewState);

void USART_SetGuardTime(USART_TypeDef* void USART_SetGuardTime(USART_TypeDef*
USARTx, uint8_t USART_GuardTime); USARTx, uint8_t USART_GuardTime);
void
NA USART_SetAutoRetryCount(USART_TypeDef*
USARTx, uint8_t USART_AutoCount);
void USART_SetBlockLength(USART_TypeDef*
NA
USARTx, uint8_t USART_BlockLength);
void USART_IrDAConfig(USART_TypeDef* USARTx, void USART_IrDAConfig(USART_TypeDef*
IrDA mode

uint32_t USART_IrDAMode); USARTx, uint32_t USART_IrDAMode);

void USART_IrDACmd(USART_TypeDef* USARTx, void USART_IrDACmd(USART_TypeDef*
FunctionalState NewState); USARTx, FunctionalState NewState);
void USART_DECmd(USART_TypeDef* USARTx,
NA
FunctionalState NewState);
void USART_DEPolarityConfig(USART_TypeDef*
NA
RS485 mode

USARTx, uint32_t USART_DEPolarity);

void
NA USART_SetDEAssertionTime(USART_TypeDef*
USARTx, uint32_t USART_DEAssertionTime);
void
NA USART_SetDEDeassertionTime(USART_TypeDef
* USARTx, uint32_t USART_DEDeassertionTime);
void USART_DMACmd(USART_TypeDef* USARTx, void USART_DMACmd(USART_TypeDef*
DMA transfers

uint32_t USART_DMAReq, FunctionalState USARTx, uint32_t USART_DMAReq,

NewState); FunctionalState NewState);
void void
USART_DMAReceptionErrorConfig(USART_TypeDe USART_DMAReceptionErrorConfig(USART_Type
f* USARTx, uint32_t USART_DMAOnError); Def* USARTx, uint32_t USART_DMAOnError);

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Firmware migration using the library AN4088

Table 29. STM32F10x and STM32F0xx USART driver API correspondence (continued)
STM32F10xx USART driver API STM32F0xx USART driver API

void USART_ITConfig(USART_TypeDef* USARTx, void USART_ITConfig(USART_TypeDef* USARTx,

uint16_t USART_IT, FunctionalState NewState); uint32_t USART_IT, FunctionalState NewState);
void USART_RequestCmd(USART_TypeDef*
NA USARTx, uint32_t USART_Request,
Interrupts and flags management

FunctionalState NewState);
void
NA USART_OverrunDetectionConfig(USART_TypeDe
f* USARTx, uint32_t USART_OVRDetection);
FlagStatus
FlagStatus USART_GetFlagStatus(USART_TypeDef*
USART_GetFlagStatus(USART_TypeDef*
USARTx, uint16_t USART_FLAG);
USARTx, uint32_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, void USART_ClearFlag(USART_TypeDef*
uint16_t USART_FLAG); USARTx, uint32_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* ITStatus USART_GetITStatus(USART_TypeDef*
USARTx, uint32_t USART_IT); USARTx, uint32_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* void USART_ClearITPendingBit(USART_TypeDef*
USARTx, uint32_t USART_IT); USARTx, uint32_t USART_IT);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

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4.16 IWDG driver

Existing IWDG available on STM32F10xx and STM32F0xx devices have the same
specifications, with window capability additional feature in STM32F0 series which detect
over frequency on external oscillators. The table below lists the IWDG driver APIs.

Table 30. STM32F10xx and STM32Fxx IWDG driver API correspondence

STM32F10xx IWDG driver API STM32F0xx IWDG driver API

void IWDG_WriteAccessCmd(uint16_t void IWDG_WriteAccessCmd(uint16_t

IWDG_WriteAccess); IWDG_WriteAccess);
Prescaler and Counter

void IWDG_SetPrescaler(uint8_t
configuration

void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);

IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload); void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void); void IWDG_ReloadCounter(void);
void IWDG_SetWindowValue(uint16_t
NA
WindowValue);
management activation
IWDG

void IWDG_Enable(void); void IWDG_Enable(void);

FlagStatus IWDG_GetFlagStatus(uint16_t FlagStatus IWDG_GetFlagStatus(uint16_t

Flag

IWDG_FLAG); IWDG_FLAG);

Color key:
= New function

= Same function, but API was changed

= Function not available (NA)

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Revision history AN4088

5 Revision history

Table 31. Document revision history

Date Revision Changes

10-Jul-2012 1 Initial release

Modified Table 2: STM32F1 series and STM32F03x/STM32F05x
device pinout differences.
Added note under Table 9.
24-Jan-2013 2 Modified Read protection for STM32F0 series in Table 17.
Modified Supply requirement for STM32F0 series in Table 18.
Modified Table 19: PWR differences between STM32F1 series and
STM32F0 series (added column for STM32F06x series).
Extended the applicability of the document o all products of
STM32F0 series. The following sections were updated:
– Introduction,
– Section 1: Hardware migration from STM32F1 to STM32F0
06-Feb-2015 3 series,
– Section 2: Boot mode compatibility,
– Section 3: Peripheral migration,
– Section 4: Firmware migration using the library.

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AN4088

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