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Issue Date: Feb.22.2006

Model No.:V420H1-L05
Approval

TFT LCD Approval Specification

MODEL NO.: V420H1 - L05

Customer:___________________________________

Approval by:_________________________________

Note: _________________________________

LCD TV Head Division

郭振隆

陳永一 李汪洋 藍文錦 林文聰

林孟慧

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Approval

- CONTENTS -
1. GENERAL DESCRIPTION -------------------------------------------------------3
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT INVERTER UNIT

3. ELECTRICAL CHARACTERISTICS --------------------------------------------------------7

3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS
3.2.2 INVERTER CHARACTERISTICS
3.2.3 INVERTER INTERTFACE CHARACTERISTICS

4. BLOCK DIAGRAM -------------------------------------------------------13

4.1 TFT LCD MODULE

5. V420H1-L05 LCD INPUT TERMINAL PIN ASSIGNMENT --------------------------------------------------------14

5.1 TFT LCD MODULE INPUT
5.2 BACKLIGHT UNIT
5.3 INVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING -------------------------------------------------------22

6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS -------------------------------------------------------25

7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS

8. PRECAUTIONS -------------------------------------------------------29
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS

9.DEFINITION OF LABELS -------------------------------------------------------30

9.1 CMO MODULE LABEL

10.PACKAGING ------------------------------------------------------31

11.MECHANICAL CHARACTERISTICS ------------------------------------------------------33

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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H1-L05 is a 42” TFT Liquid Crystal Display module with 20-CCFL Backlight unit and 2ch-LVDS
interface. This module supports 1920 x 1080 HDTV format and can display true 16.7M colors (8-bit/color).
The inverter module for backlight is built-in.
1.2 FEATURES
- High brightness (500 nits)
- High contrast ratio (1200:1)
- Fast response time (Gray to gray average 6.5ms)
- High color saturation (NTSC 75%)
- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for 50/60 Hz frame rate
- Ultra wide viewing angle : Super MVA technology
- 180 degree rotation display option
1.3 APPLICATION
- Standard Living Room TVs.
- Public Display Application.
- Home Theater Application.
- MFM Application.
1.4 GENERAL SPECIFICATIONS

× Specification Unit Note

Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
(1)
Bezel Opening Area 938.3 (H) x 531.3 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920x R.G.B. x 1080 pixel -
Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Anti-Glare coating (Haze 25%)
Surface Treatment - (2)
Hard coating (3H)

Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and
back outlines.
Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to
change this feature.

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1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note
Horizontal (H) 982.3 983.0 984.0 mm
Module Size Vertical (V) 575.3 576.0 577.0 mm (1), (2)
Depth (D) 51.3 52.3 53.3 mm
Weight 13100 13300 13500 g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol Unit Note
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - (50) G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE
Value
Item Symbol Unit Note
Min. Max.
Power Supply Voltage VCC -0.3 20 V
(1)
Logic Input Voltage VIN -0.3 3.6 V

2.2.2 BACKLIGHT INVERTER UNIT

Value
Item Symbol Unit Note
Min. Max.
Lamp Voltage VW － 3000 VRMS
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level － -0.3 7 V (1), (3)

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3)The control signals include On/Off Control, Internal PWM Control, External PWM Control and
Internal/External PWM Selection.

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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)
Value
Parameter Symbol Unit Note
Min. Typ. Max.
10.8 12 13.2
Power Supply Voltage VCC V (1)
16.2 18 19.8
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current IRUSH 2.5 - 3.5 A (2)
White - 0.80 1.0 A
Black ICC - 0.35 - A (3)
Vertical Stripe - 0.62 - A
Power Supply Current
White - 1.20 1.5 A
Black ICC - 0.50 - A (4)
Vertical Stripe - 0.90 - A
Differential Input High
VLVTH - - +100 mV
Threshold Voltage
LVDS
Differential Input Low
Interface VLVTL -100 - - mV
Threshold Voltage
Common Input Voltage VLVC 1.125 1.25 1.375 V
Terminating Resistor RT - 100 - ohm
CMOS Input High Threshold Voltage VIH 2.7 - 3.3 V
interface Input Low Threshold Voltage VIL 0 - 0.7 V
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:

Vs (12/18V)
Q1 2SK1475
Vcc
C3
FUSE (LCD Module Input)

R1 1uF

47K

(High to Low)
(Control Signal)
Q2
R2
SW 2SK1470

1K
+24V

VR1 47K C2

C1
0.01uF

1uF

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

GND
470us

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Note (3)&(4) The specified power supply current is under the conditions at Vcc = 18 V(Note(3)), Vcc =
12V(Note(4)), Ta = 25 ± 2 ºC, fv = 60 Hz, whereas a power dissipation check pattern below is displayed.

a. White Pattern b. Black Pattern

Active Area Active Area

c. Vertical Stripe Pattern

R G B R G B

B R G B R G B R

B R G B R G B R

R G B R G B

Active Area

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3.2 BACKLIGHT UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Lamp Input Voltage VL - 1300 - VRMS -
Lamp Current IL 6.0 6.5 7.0 mARMS (1)
- - 2200 VRMS (2), Ta = 0 ºC
Lamp Turn On Voltage VS
- - 2000 VRMS (2), Ta = 25 ºC
Operating Frequency FL 40 - 70 KHz (3)
Lamp Life Time LBL 50,000 - - Hrs (4)

3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)

Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Consumption PBL - 182 192 W (5)(6), IL = 6.5mA
Power Supply Voltage VBL 22.8 24 25.2 VDC
Power Supply Current IBL - 7.6 8.0 A Non Dimming
Input Ripple Noise - - - 500 mVP-P VBL=22.8V
Backlight Turn on 2200 - - VRMS Ta = 0 ºC
VBS
Voltage 2000 - - VRMS Ta = 25 ºC
Oscillating Frequency FW 47 50 53 kHz
Dimming frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 20 - %
Note (1) Lamp current is measured by utilizing high frequency current meters as shown below:
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
±2℃ and IL = 6.0~ 7.0mArms.
Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 42" backlight unit under input voltage 24V,
average lamp current 6.8 mA and lighting 30 minutes later.

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HV (White -) HV (Pink +)
A 1 1 A
HV(Pink -) HV (White +)
A 2 2 A
HV (White +) HV (Pink -)
A 1 HV(Pink +) 1 A
HV (White -)
A 2 2 A
HV (White -) HV (Pink +)
A 1 1 A
HV(Pink -) HV (White +)
A 2 2 A
HV (White +) HV (Pink -)
A 1 1 A
A 2 HV(Pink +) HV (White -)
2 A
HV (White -) HV (Pink +)
A 1 A
HV(Pink -) HV (White +) 1
A 2 2 A
HV (White +) HV (Pink -)
A 1 A
HV(Pink +) HV (White -) 1
A 2 2 A
Inverter Inverter
LCD Module
(Master) HV (White -) HV (Pink +) (Slavor)
A 1 1 A
HV(Pink -) HV (White +)
A 2 2 A
HV (White +) HV (Pink -)
A 1 A
HV(Pink +) HV (White -) 1
A 2 2 A
HV(Blue -) HV (Pink +)
A 1 1 A
HV (Pink -) HV (White +)
A 2 2 A
HV(Blue +) HV (Pink -)
A 1 1 A
HV (Pink +) HV (White -)
A 2 2 A

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3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Test Value
Parameter Symbol Unit Note
Condition Min. Typ. Max.
ON － 2.0 － 5.0 V
On/Off Control Voltage VBLON
OFF － 0 － 0.8 V
Internal/External PWM HI － 2.0 －- 5.0 V
VSEL
Select Voltage LO － 0 － 0.8 V
Internal PWM Control MAX － － 3.0 V maximum duty ratio
VIPWM VSEL = L
Voltage MIN － 0 － V minimum duty ratio
External PWM Control HI 2.0 － 5.0 V duty on
VEPWM VSEL = H
Voltage LO 0 － 0.8 V duty off
Control Signal Rising Time Tr － － － 100 ms
Control Signal Falling Time Tf － － － 100 ms
PWM Signal Rising Time TPWMR － － － 50 us
PWM Signal Falling Time TPWMF － － － 50 us
Input impedance RIN － 1 － － MΩ
BLON Delay Time Ton － 1 － － ms
BLON Off Time Toff － 1 － － ms
Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change
the internal/external PWM selection (SEL) during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure.
Note (3) The power sequence and control signal timing must follow the figure below. For a certain reason,
the inverter has a possibility to be damaged with wrong power sequence and control signal
timing.

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VBL

0
Ton1 Toff1

VBLON 2.0V
0.8V
0
Backlight on duration
Tr Tf

VSEL 2.0V
0.8V Int. Dimming Function
0 Ext. Dimming Function

TPWMR TPWMF
VEPWM 2.0V
0.8V
0

3.0V
VIPWM

VW

External External
PWM PWM Duty
Period
100% Minimun
Duty

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4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

ERX0(+/-)

ERX1(+/-)
FRAME
BUFFER

SCAN DRIVER
ERX2(+/-)

ERX3(+/-)
TFT LCD PANEL
ECLK(+/-)
(1920x3x1080)
INPUT CONNECTOR
(FI-RE51S-HF )

DCLK(+/-)
TIMING
DE
CONTROLLER
ORX0(+/-)

ORX1(+/-)
DATA DRIVER (RSDS)
ORX2(+/-)

ORX3(+/-) DC/DC CONVERTER

OCLK(+/-) & REFERENCE
VOLTAGE
Vcc GENERATOR
GND
CN2.
CN1. CN3-CN22:SM02 (12.0)B-BHS-1-TB(LF)(JST) VBL
VBL
INVERTER GND
GND INVERTER or equivalent
CONNECTOR CONNECTOR
SEL BACKLIGHT
E_PWM CN1:S14B-PH-SM3-TB CN2:S12B-PH-SM3-TB
(D)(LF) or equivalent UNIT (D)(LF) or equivalent
I_PWM
(Master) (Slave)
BLON

CN23-CN26: 53261-1060(Molex) or equivalent

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module Input
Connector part no. : FI-RE51S-HF (JAE) or equivalent.
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
(4)
5 N.C. No Connection
6 N.C. No Connection
7 NC No Connection
8 RPF Display Rotation (1)
9 ODSEL Overdrive Lookup Table Selection (2)
10 LCS Low color shift (3)
11 GND Ground
12 ORX0- Odd pixel, Negative LVDS differential data input. Channel 0
13 ORX0+ Odd pixel, Positive LVDS differential data input. Channel 0
14 ORX1- Odd pixel, Negative LVDS differential data input. Channel 1
15 ORX1+ Odd pixel, Positive LVDS differential data input. Channel 1
16 ORX2- Odd pixel, Negative LVDS differential data input. Channel 2
17 ORX2+ Odd pixel, Positive LVDS differential data input. Channel 2
18 GND Ground
19 OCLK- Odd pixel, Negative LVDS differential clock input.
20 OCLK+ Odd pixel, Positive LVDS differential clock input.
21 GND Ground
22 ORX3- Odd pixel, Negative LVDS differential data input. Channel 3
23 ORX3+ Odd pixel, Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
(4)
26 N.C. No Connection
27 N.C. No Connection
28 ERX0- Even pixel, Negative LVDS differential data input. Channel 0
29 ERX0+ Even pixel, Positive LVDS differential data input. Channel 0
30 ERX1- Even pixel, Negative LVDS differential data input. Channel 1
31 ERX1+ Even pixel, Positive LVDS differential data input. Channel 1
32 ERX2- Even pixel, Negative LVDS differential data input. Channel 2
33 ERX2+ Even pixel, Positive LVDS differential data input. Channel 2
34 GND Ground
35 ECLK- Even pixel, Negative LVDS differential clock input.
36 ECLK+ Even pixel, Positive LVDS differential clock input.
37 GND Ground
38 ERX3- Even pixel, Negative LVDS differential data input. Channel 3
39 ERX3+ Even pixel, Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
(4)
42 N.C. No Connection
43 N.C. No Connection
44 GND Ground
45 GND Ground

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46 GND Ground
47 GND Ground
48 VCC Power input (+12V or +18.0V)
49 VCC Power input (+12V or +18.0V)
50 VCC Power input (+12V or +18.0V)
51 VCC Power input (+12V or +18.0V)
Note (1) Low : normal display (default), High : display with 180 degree rotation
Note (2) Overdrive lookup table selection. The overdrive lookup table should be selected in
accordance to the frame rate to optimize image quality.
ODSEL Note
L Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
Note (3) Low : normal display (default), High : Low Color Shift function enable.
Note (4) Reserved for interval use. Left it open.

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.
CN3-CN22: BHR-04VS-1 (JST).
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST.
The mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).

1 HV(White) 1 HV(Pink)

2 HV(Pink) 2 HV(White)

1 HV(White) 1 HV(Pink)

2 HV(Pink) 2 HV(White)

1 HV(White) 1 HV(Pink)

2 HV(Pink) 2 HV(White)

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5.3 INVERTER UNIT

CN1 (Header): S14B-PH-SM3-TB (D)(LF)(JST) or equivalent.
Pin No. Symbol Description
1
2
3 VBL +24VDC power input
4
5
6
7
8 GND GND
9
10
Internal/external PWM selection
11 SEL High : external dimming
Low : internal dimming
External PWM control signal
12 E_PWM E_PWM should be connected to ground when internal PWM was selected
(SEL = Low).
Internal PWM Control Signal
13 I_PWM I_PWM should be connected to ground when external PWM was selected
(SEL = High).
14 BLON Backlight on/off control

CN2 (Header): S12B-PH-SM3-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description
1
2
3 VBL +24VDC power input
4
5
6
7
8 GND GND
9
10
11 NC NC
12 NC NC

CN3- CN22 (Header): SM02(12.0)B-BHS-1-TB (LF)(JST) or equivalent

Pin No. Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage

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CN23-CN26 (Header): 53261-1060(Molex) or equivalent

Pin No. Symbol Description
1 Board to Board
2 Board to Board
3 Board to Board
4 Board to Board
5 Control Board to Board
6 Signal Board to Board
7 Board to Board
8 Board to Board
9 Board to Board
10 Board to Board
Note (1) Floating of any control signal is not allowed.

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5.4 BLOCK DIAGRAM OF INTERFACE

CNF1

ERx0+ 51Ω
100pF RxOUT
TxIN ERx0-
ER0-ER7 51Ω ER0-ER7
ERx1+ 51Ω
EG0-EG7 100pF
EG0-EG7
ERx1-
51Ω EB0-EB7
EB0-EB7
ERx2+ 51Ω
DE 100pF DE
ERx2-
51Ω
ERx3+ 51Ω OR0-OR7
OR0-OR7
100pF
OG0-OG7 ERx3- OG0-OG7
51Ω
OB0-OB7 OB0-OB7
ECLK+ 51Ω
DCLK PLL ECLK-
100pF
PLL DCLK
51Ω
Host
Graphics Timing
Controller Controller
ORx0+ 51Ω
100pF
ORx0-
51Ω
ORx1+ 51Ω
100pF
ORx1-

ORx2+ 51Ω
100pF
ORx2-
51Ω
ORx3+ 51Ω
100pF
ORx3-
51Ω

OCLK+ 51Ω
PLL OCLK-
100pF
PLL
51Ω

LVDS Transmitter LVDS Receiver

THC63LVDM83A
(LVDF83A)

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ER0~ER7 : Even pixel R data

EG0~EG7 : Even pixel G data
EB0~EB7 : Even pixel B data
OR0~OR7 : Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7 : Odd pixel B data
DE : Data enable signal
DCLK : Data clock signal

Notes: (1) The system must have the transmitter to drive the module.
(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
(3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is even pixel
and the second pixel is odd pixel.

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5.5 LVDS INTERFACE

TRANSMITTER RECEIVER
INTERFACE CONNECTOR TFT CONTROL
SIGNAL THC63LVDM83A THC63LVDF84A
INPUT
PIN INPUT Host TFT-LCD PIN OUTPUT

R0 51 TxIN0 27 Rx OUT0 R0
R1 52 TxIN1 29 Rx OUT1 R1
R2 54 TxIN2 30 Rx OUT2 R2
TA OUT0+ Rx 0+
R3 55 TxIN3 32 Rx OUT3 R3
R4 56 TxIN4 33 Rx OUT4 R4
R5 3 TxIN6 35 Rx OUT6 R5
TA OUT0- Rx 0-
G0 4 TxIN7 37 Rx OUT7 G0
G1 6 TxIN8 38 Rx OUT8 G1
G2 7 TxIN9 39 Rx OUT9 G2
G3 11 TxIN12 43 Rx OUT12 G3
TA OUT1+ Rx 1+
G4 12 TxIN13 45 Rx OUT13 G4
G5 14 TxIN14 46 Rx OUT14 G5
B0 15 TxIN15 47 Rx OUT15 B0
TA OUT1- Rx 1-
B1 19 TxIN18 51 Rx OUT18 B1
B2 20 TxIN19 53 Rx OUT19 B2
24bit B3 22 TxIN20 54 Rx OUT20 B3
B4 23 TxIN21 55 Rx OUT21 B4
TA OUT2+ Rx 2+
B5 24 TxIN22 1 Rx OUT22 B5
DE 30 TxIN26 6 Rx OUT26 DE
R6 50 TxIN27 7 Rx OUT27 R6
TA OUT2- Rx 2-
R7 2 TxIN5 34 Rx OUT5 R7
G6 8 TxIN10 41 Rx OUT10 G6
G7 10 TxIN11 42 Rx OUT11 G7
B6 16 TxIN16 49 Rx OUT16 B6
TA OUT3+ Rx 3+
B7 18 TxIN17 50 Rx OUT17 B7
RSVD 1 25 TxIN23 2 Rx OUT23 Not connect
RSVD 2 27 TxIN24 3 Rx OUT24 Not connect
TA OUT3- Rx 3-
RSVD 3 28 TxIN25 5 Rx OUT25 Not connect

TxCLK TxCLK OUT+ RxCLK IN+

DCLK 31 26 RxCLK OUT DCLK
IN TxCLK OUT- RxCLK IN-
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the
color versus data input.
Data Signal
Color Red Green Blue
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Red (253) 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red
Red (254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Green (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Green (253) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
Green
Green (254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Green (255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Blue (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Blue (253) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1
Blue
Blue (254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
Blue (255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage

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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc (60) 74 (80) MHZ -
LVDS Receiver Clock Input cycle to
Trcl - - 200 ps -
cycle jitter
Setup Time Tlvsu 600 - - ps -
LVDS Receiver Data
Hold Time Tlvhd 600 - - ps -
Fr5 47 50 53 Hz (1)
Frame Rate
Fr6 57 60 63 Hz (2)
Vertical Active Display Term Total Tv (1115) 1125 (1139) Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th -
Blank Tvb (35) 45 (59) Th -
Total Th (2100) 2200 (2300) Tc Th=Thd+Thb
Horizontal Active Display Term Display Thd 1920 1920 1920 Tc -
Blank Thb (180) 280 (380) Tc -
Note (1) (ODSEL) = (H). Please refer to 5.1 for detail information.
(2) (ODSEL) = (L). Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

Tv

Tvd
Tvb

DE
Th

DCLK

Tc
Thd
Thb
DE

DATA Valid display data ( 960 clocks)

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LVDS INPUT INTERFACE TIMING DIAGRAM

Tc

RXCLK+

RXn+/-
Tlvsu

Tlvhd

1T‘ 3T‘ 5T‘ 7T‘ 9T‘ 11T‘ 13T‘

14 14 14 14 14 14 14

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the
diagram below.

Power Supply 0.9 VCC 0.9 VCC

VCC
0.1VCC 0.1Vcc
0V

0.5≦T1≦10ms T1 T3
0≦T2≦50ms
0≦T3≦50ms
500ms ≦T4 T2 T4

VALID
Signals
0V

Power On Power Off

Backlight (Recommended) 50% 50%

500ms≦T5
100ms≦T6

T5 T6

Power ON/OFF Sequence

Note.
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the
LCD operation or the LCD turns off before the backlight turns off, the display may momentarily
become abnormal screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on
period.
(5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
o
Ambient Temperature Ta 25±2 C
Ambient Humidity Ha 50±10 %RH
Supply Voltage VCC 12/18 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL 6.5±0.5 mA
Oscillating Frequency (Inverter) FW 50±3 KHz
Vertical Frame Rate Fr 60 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 900 1200 - Note (2)
Gray to
Response Time 6.5 12 ms Note (3)
gray
2
Center Luminance of White LC 400 500 cd/m Note (4)
White Variation δW 1.3 - Note (7)
Cross Talk CT 4 % Note (5)
Rx θx=0°, θY =0° 0.651 -
Red
Ry Viewing Normal Angle 0.330 -
Gx 0.274 -
Green Typ. Typ.
Gy 0.596 -
Color Note (6)
Bx -0.03 0.142 +0.03 -
Chromaticity Blue
By 0.067 -
Wx 0.285 -
White
Wy 0.293 -
Color Gamut 72 75 % NTSC
θx+ 80 88
Horizontal
Viewing θx- 80 88
CR≥20 Deg. Note (1)
Angle θY+ 80 88
Vertical
θY- 80 88

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Note (1) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Eldim EZ-Contrast 160R

Normal
θx = θy = 0º

θy- θy+

θX- = 90º x- 12 o’clock direction

y+
θx− θy+ = 90º
θx+

6 o’clock
y- x+ θX+ = 90º
θy- = 90º

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note
(7).

Note (3) Definition of Gray to Gray Switching Time :

100%
90%

Optical
Response
10%
0%

Time
Gray to gray Gray to gray
switching time switching time

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.
Gray to gray average time means the average switching time of gray level 0, 63,127,191,255 to each
other.

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Note (4) Definition of Luminance of White (LC, LAVE):

Measure the luminance of gray level 255 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA × 100 (%)
Where:
2
YA = Luminance of measured location without gray level 0 pattern (cd/m )
2
YB = Luminance of measured location with gray level 0 pattern (cd/m )

(0, 0) Active Area (0, 0)

Active Area
YA, U (D/2,W/8) YB, U (D/2,W/8)
(D/4,W/4)

YA, L (D/8,W/2) YB, L (D/8,W/2) YB, R (7D/8,W/2)

Gray 128 Gray
Gray00
YA, R (7D/8,W/2)
(3D/4,3W/4)
YA, D (D/2,7W/8)
YB, D (D/2,7W/8) Gray 128
(D, W) (D, W)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be
executed after lighting backlight for 1 hour in a windless room.

LCD Module

LCD Panel

Center of the Screen Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (7) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line
D
D/4 D/2 3D/4
Vertical Line

W/4 1 2

W W/2 5 X : Test Point

X=1 to 5

3W/4 3 4

Active Area

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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.

8.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI MEI E207943

OPTOELECTRONICS V420H1 -L05 Rev. XX MADE IN TAIWAN

XXXXXXXYMDLNNNN

(a) Model Name: V420H1-L05

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Serial ID: X X X X X X X Y M D L N N N N

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

CMO Internal Use

Revision

CMO Internal Use

Serial ID includes the information as below:
(a) Manufactured Date: Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
st st
Day: 1~9, A~Y, for 1 to 31 , exclude I ,O, and U.
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

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10. PACKAGING
10.1 packing specifications
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1086(L) X 356 (W) X 715 (H)
(3) Weight : approximately 46.5Kg ( 3 modules per box)

10.2 PACKING METHOD

Figures 10-1 and 10-2 are the packing method

LCD TV Module

Anti-static Bag

Cushion(Bottom)

3pcs Drier

Carton Label
Carton

Figure.10-1 packing
h d

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Corner Protector:L1400*50mm*50mm
L1000*50mm*50mm
Pallet:L1100*W1100*H140mm
Pallet Stack:L1100*W1100*H1575mm
Gross:294kg

PE Sheet

Film

Carton Label

Pallet
PP Belt

Figure.10-2 Packing method

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a a a a a

4 4 0 .0 ± 0 .5
0 .7
7 7 6 .0 ± 0 .5
SEC TION B - B

14 .3 5 ± 0 .5 0
SC ALE 3 : 1
9 8 3 .0 -+ 01.0.7
B

B
9 3 0 .2 4
9 3 8 .3 ± 0 .7

14 .0 9 ± 0 .5 0 14 .0 9 ± 0 .5 0

a a
11. MECHANICAL CHARACTERISTICS

4 9 1.2

33
5 7 6 .0 -+ 01.0.7

2 3 6 .8 ± 0 .5
2 3 6 .8 ± 0 .5

a
a

5 2 3 .2 6 DISPLA Y A REA
A

5 3 1.3 ± 0 .7 B EZEL OPENING AREA

Sc r ew Ma x. Dep t h < 5 m m

A
M4 ( a )
M4 ( Pit c h: 0 .7 / Ma c h in e)
7 7 6 .0 ± 0 .5
( Ma x. To r q u e: 5 kg f - c m ) SEC TION A - A
4 4 0 .0 ± 0 .5
SC A LE 3 : 1

5 2 .3 ± 1.0
14 .3 5 ± 0 .5 0
a a a a a

4 5 .2 7
CHI MEI 奇美電子股份有限公司
2 8 .9

2 3 .3 2 3 1.2

3 2 .1

4 4 .9
4 4 .9
4 4 .9

3 3 .10
7 18 .8

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9 .0
1.5

? 4 .0
M4 ( Pit c h: 0 .7 / Mac hine
( Max .To r q ue: 5 kgf - c m )

3 2 .0 ± 0 .5 5 4 0 .0 ± 0 .5 3 2 .0 ± 0 .5
4 2 .0 ± 0 .5 4 2 .0 ± 0 .5
2 3 0 .0

M3 ( c )
Sc r ew Ma x. Dept h< 9 .0 m m
C on nec t or 3
SEC TION A- A
SC ALE 2 : 1
b b b b
b b b b
C o nn ec t o r 1
2 2 .0 Sc r ew Max . Dept h < 12 .0 m m
4 2 .0 ± 0 .5 4 2 .0 ± 0 .5
? 4 .0

4 4 0 .0 ± 0 .5

c c C o nn ec t or 2
M3 ( b)

2 5 .0
15 5 .2 5

15 .0 ± 0 .5

2 3 0 .0 ± 0 .5
12 .8 ± 0 .5

34
SEC TION C - C

4 7 8 .0 ± 0 .5
4 3 4 .0 ± 0 .5
SC ALE 2 : 1

2 5 .0
c c
M3 ( b)

.0
R8

15 .0 ± 0 .5
2 7 .0
b b b b
? 4 .0

b b b b

1.5

SEC TION D- D
SC A LE 2 : 1
R4
.0

3 6 3 .0 3 6 3 .0

NOTE: CHI MEI

C onnec t or 1: JAE_ FI_ R5 1S_ HF
奇美電子股份有限公司
C onnec t or 2 : JST_ S12 B _ PH_ SM3 _ TB
C onnec t or 3 : JST_ S14 B _ PH_ SM3 _ TB

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35
Not e:
1. It is r ec o m m en d ed t h a t a ll sc r ews sh o u ld b e in c lu d ed when C MO' s pr o d uc t is ap p lied
in o r d er t o g u a r a n t ee st r u c t u r e st r en g t h o f pr o d uc t .
2 . Sc r ew: M4 ( Pit c h 0 .7 / Ma c h in e)
3 . To r q u e: 4 ~ 5 kg f .c m
CHI MEI 奇美電子股份有限公司

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