Interfacing and Communication
CSC159 – Computer Organization
Lesson Outcomes
• Peripherals
• I/O considerations (speed and coordination issues)
• Programmed I/O
• I/O Modules
• Interrupts and Stacks (Little Endian, Big Endian)
• Direct Memory Access (DMA)
• I/O System Architectures (Bus architecture and channel
architecture)
Peripherals
Devices that are separate from the basic
computer
Not the CPU, memory, power supply
Classified as input, output, and storage
Connect via
Ports
parallel, USB, serial
Interface to systems bus
SCSI, IDE, PCMCIA
I/O Considerations
Speed Issues
CPU operates at speeds much faster than the fastest I/O device
Devices operate at different speeds
Bursts of data
Block data transfer required for some devices
Coordination
Several devices perform I/O simultaneously
Unexpected input
Various input formats
Status information needed for each device
I/O Architecture
There are various ways to interconnect the CPU,
memory, & I/O peripherals, each with their own
advantages & disadvantages
Programmed I/O & Direct Memory Access (DMA)
Basic CPU-Memory-I/O Pathway
Memory
CPU I/O
module
I/O device
I/O Architecture
Buffering – holding & releasing parts of data at
particular times
Handshaking – a process that takes place when a
computer is about to communicate with a foreign
device to establish rules for communication
I/O Architecture
Programmed I/O
CPU controlled I/O
Interrupt Driven I/O
External input controls
Direct Memory Access Controllers
Method for transferring data between main memory and a
device that bypasses the CPU
Programmed I/O (in I/O Architecture)
Programmed input/output (PIO) is a method of transferring data
between the CPU and a peripheral, such as a network adapter or an
ATA storage device
Happens when software running on the CPU uses instructions that
access I/O address space to perform data transfers to or from an I/O
device
Programmed I/O (in I/O Architecture)
Simplest method for performing I/O where an I/O module is
connected to a pair of I/O registers in the CPU via a bus
CPU I/O module(s) I/O device
CPU Device
interface interface
I/O Modules Functions (in Programmed I/O)
Recognizes messages from device(s) addressed to it and
accepts commands from the CPU
Provides a buffer where the data from memory can be held until
it can be transferred to the disk
Provides the necessary registers and controls to
perform a direct memory transfer
Physically controls the device
Copiesdata from its bufferto the device/from the CPU to its
buffer
Notifies with interrupts
Interrupts (in I/O Architecture)
Signal that causes the CPU to alter its normal flow on instruction
execution
frees CPU from waiting for events
provides control for external input
examples: unexpected input, abnormal situation, illegal instructions,
multitasking, multiprocessing
An interrupt is a call for the CPU to interact or service the
interrupting unit
Interrupt causes the temporary suspension of the program in
progress
Interrupts (in I/O Architecture) (cont.)
All the information about the program being suspended,
including the last location of the last instruction executed, &
the values of data in various registers, is saved in a known
part of memory (either the process control block (PCB) or
the stack area)
Computer then branches to a special interrupt handler
program (or interrupt routine) elsewhere in memory
The process where the interrupt handler program
determines the appropriate course of action is known as
servicing the interrupt
Interrupt Normal Execution
1) Finish Current Instruction
Suspend Operation Contents of registers
2)
Store Registers stored in stack
Jump to Interrupt Routine
3)
& Execute
Return to Normal Contents of
4)
Operation – registers returned
Restore MP Status from stack
Normal Execution
Continues
Uses of Interrupts
External event notifier
frees CPU from polling, a means for the user to control the computer
from an input device
Completion signal
means of controlling the flow of data to an external device (i.e. printer
ready or buffer full)
Allocation of CPU time
time sharing
Abnormal event indicator
power failure, illegal operation, hardware error
Software interrupts
SW simulation of interrupts, address space indicates which interrupt is
called (INT)
Multiple Interrupts
Multiple interrupts will occur from time to time
Are there other interrupts already awaiting service, and if so,
how does the computer determine the order in which the
interrupts get serviced? How does the computer identify the
interrupting device?
Two different processing methods for
determining which device initiated the
interrupt:
Multiple Interrupts - Vectored
1. Vectored Interrupt
the address of the interrupting device is included as part of
the interrupt
faster, but requires additional hardware to implement
Multiple Interrupts - Vectored
Address of interrupt A
Interrupt K
occurs Address of interrupt B
…
Address of interrupt K
…
Jump to K
Interrupt A service routine service
… routine
Interrupt K service routine
Multiple Interrupts - Polled
2. Polled Interrupt
checking for input in rotation
provides a general interrupt that is shared
by all devices
the computer identifies which the
interrupting device by polling each device
Multiple Interrupts - Polled
Interrupt K
occurs
General interrupt polling
routine
Jump to K
… service
routine
Interrupt A service routine
…
Interrupt K service routine
Multiple Interrupts Example
Multiple Interrupts & Prioritization
Multiple interrupts can be handled by assigning priorities
to each interrupt
A higher-priority interrupts can interrupt other interrupts of
lower priority, but a lower-priority interrupts will have to
wait until a higher-priority interrupt is completed
Priorities are established in a logical way
highest priorities are reserved for time-sensitive
situations, such as power failure or external events that
are being time measured
task completion interrupts usually take lower
priorities
Categories of Interrupts
1. Maskable the interrupt will not be accepted (can be
selectively disabled)
2. Nonmaskable the interrupt will always be acknowledged
& accepted, such as a power failure
STACK
Used by the CPU to store information from registers
temporarily.
This is because there is limited number of register inside the
microprocessor.
The two main registers to access the stack are SS and SP
registers.
Stack
Functions of stack:
1. Interrupt
Stack is the location where the contents of the registers
in the CPU are temporarily stored
i) Hardware stack ii) Software stack
2. Subroutine call
3. Stack instruction
Stack Functions/Usages
1. When a subroutine is called
2. When an interrupt occurs
3. When stack instruction occurs
4. To store data when the most recently used data will
also be the first needed
5. Efficient way of storing intermediate data values
during complex calculations
Hardware Stack
Only some specialized microprocessors have a given
number of registers set aside within the processor to
serve as the stack location
Fast access BUT size of stack is limited
restrict flexibility of the micropeocessors
Software Stack
Almost unlimited in size & can reside anywhere in memory
therefore, need a special register in the CPU to hold address of
the stack stack pointer register (SPR)
Whenever a stack is required, the SPR will track its location
by holding the 16-bit stack address
Stack is built one-byte at a time following LIFO (last in first
out)
Last byte put on the stack will be the first byte retrieved
from the stack
Software Stack
Assembly language stack instructions:
1. PUSH to push a byte onto the stack
2. POP or PULL to take a byte off the stack
Last plate put in will
be first plate out
First plate put in will
be last plate out
Operation of Stacks
The stack address is built, one byte
at a time (similar to the memory
operations)
Stack operates by Last In First Out
(LIFO)
The last byte put on the stack will be
the first byte retrieved from the
stack
Examples of Operations:
◦ To store data onto the stack
(PUSH AX)
◦ To retrieve data from the stack
(POP AX)
Stack Pointer
The job of SP is very critical when push and pop are
performed
The SP points to the top of the stack
(which is not empty)
SPincremented when data is popped off the stack
(removed from)
SP is decremented when data is pushed onto the
stack (put onto)
Pushing Onto Stack
Question
Assuming that:
SP = 1236h AX = 24B6h BX
= 85C2h DX = 5F93h
show the contents of the stack as each of the following instructions is
executed
PUSH AX
PUSH BX
PUSH DX
Pushing Onto Stack
Solution
1230 93
1231 5F
1232 C2
SP 1233 85
SS
1234 B6
1235 24
1236 ///////
Finally, SP is : 1230
Popping Off Stack
Question
Given the following stack and SP = 18FA, show the contents of the
stack and registers after executing the following instructions.
18FA 23
18FB 14
SP 18FC 6B
18FD 2C SS
18FE 91
18FF F6
1900 25
(usually the stack is build following the little endian method)
Popping Off Stack
Solution
POP CX
18FA 23
POP DX 18FB 14
POP BX 18FC 6B
18FD 2C
18FE 91
SP : 1900
18FF F6
CX: 1423 1900 25
DX: 2C6B
BX: F691
Endian Order
Refers to the way computer stores the bytes of a
multiple byte integer
Two orders:
1. Little endian
2. Big endian
FYI, Intel processor PCs are little endian machines,
whereas Motorolla processors (used in Macs) are big
endian machines
Little Endian
Low-order byte of number is stored in memory at the lowest
address, & high-order byte at the highest address little end comes first
Example: a 4 byte LongInt
Byte3 Byte2 Byte1 Byte0
will be arranged in memory as follows:
Base Address + 0 Byte0
Base Address + 1 Byte1
Base Address + 2 Byte2
Base Address + 3 Byte3
Big Endian
High-order byte of number is stored in memory at lowest
address, & low-order byte at the highest address big end
comes first
Example: a 4 byte LongInt
Byte3 Byte2 Byte1 Byte0
will be arranged in memory as follows:
Base Address + 0 Byte3
Base Address + 1 Byte2
Base Address + 2 Byte1
Base Address + 3 Byte0
Endian Order
Why should it matter to you?
Most of the time it won’t, but if you try to read data files
created on a machine that is of different endian nature from
your machine, the bytes must be swapped to obtain same
values on both machines
Common file formats & their endian order:
.psd big endian
.bmp little endian
.gif little endian
.jpeg big endian
Exercise
Based from the instructions given below, draw an appropriate
stack diagram, starting from address 2000
MOV AX, 1234h
MOV BX, 9ABCh PUSH BX
PUSH AX
State the content of the stack pointer after the execution of the
above instructions
Arrange the words in the stack using
◦ Big Endian
◦ Little Endian
Past semester Question
Given the content of registers and the byte that follows the PUSH
instruction at the time interrupt occurs:
PC : 2602h
AX : F6h
BX : 82h
CX : 3624h
DX : FB12h
Flag Register : 15h
BYTE
X X 1 0 1 1 1 1
PC DX CX Flag Register BX AX
Direct Memory Access (DMA)
DMA allows certain hardware subsystems to access main
system memory independently of the CPU
With DMA, the CPU initiates the transfer, does other operations
while the transfer is in progress, and receives an interrupt from
the DMA controller when the operation is done
Direct Memory Access (DMA)
Useful any time the CPU cannot keep up with the rate
of data transfer, or where the CPU needs to perform
useful work while waiting for a relatively slow I/O
data transfer
Many hardware systems use DMA,
including disk drive controllers, graphic
cards, network cards and sound cards
Direct Memory Access (DMA)
Transferring large blocks of data
Direct transfer to and from memory
CPU not actively involved in transfer itself
Required conditions for DMA
The I/O interface and memory must be connected
The I/O module must be capable of reading and writing to memory
Conflicts between the CPU and the I/O module must be avoided
DMA Instruction Set
Application program requests I/O service from operating
system
privileged instructions
To initiate DMA, programmed I/O is used to send the
following information:
1. location of data on I/O device
2. the starting location in memory
3. the size of the block
4. read/write
Interrupt to CPU upon completion
CPU - Memory I/O Architecture
Five basic components involved in the interface between
the CPU & the I/O peripheral:
1. The CPU
2. The I/O peripheral device
3. Memory
4. One or more I/O modules
5. The buses connecting the various components
together
CPU - Memory I/O Architecture
Two basic I/O system architectures in
common use:
1. Bus architecture
used in almost all PCs, workstations, & in some
mainframe computers (Alpha-based)
2. Channel architecture
found primarily in IBM mainframe computers
I/O Bus Architecture
A single system bus connects the CPU to memory & to all the
various modules that control I/O devices
The system bus in a bus architecture consists of a number of
different interconnected buses
The various buses in a PC are interconnected by bus interfaces,
sometimes known as expansion bus interfaces or bus bridges
A general bus interface configuration
CPU bus Special bus
Bus bridge or
CPU bus interface
Memory
I/O module
I/O module
I/O Bus Architecture
I/O Bus Architecture
Bus interfaces expand the flexibility of the system bus architecture
by converting the bus signals from one bus to another so that
different types of buses can be used together
The ability to interconnect buses:
makes possible the design & use of industry standard buses on
equipment of different vendors (leads to the concept of open
architectures)
provides flexibility for the future; as bus designs evolve, new bus
interfaces can be implemented to add the capabilities of new &
improved buses to the system
I/O Bus Architecture
Each bus provides the necessary data & address lines, lines for interrupt, &
various lines to control timing, reads & writes, & so on
The major differences, other than specifications, actual pin assignments, &
physical differences, lie in the way the control signals are implemented
ISA bus PCI bus
Data width = 16-bit Data width = 32- or 64-bit
Has separate data & address Address & data share same lines using
lines the “multiplexing” technique
Designed to transfer several pieces of
Other buses include: XMI bus, Futurebus+ data in a rapid sequence called a
burst once a starting address is
established
Bus Characteristics
Buses are characterized primarily by their:
1. Configuration
2. Width
3. Speed
4. Particular use
Bus topology
point-to-point bus
a bus that carry signals from a specific source to specific destination
example: the cable that connects the parallel or serial port in a PC
from the computer to a printer
multipoint bus (multidrop bus / broadcast bus)
a bus used to connect several points together
the signals produced by a source on the bus are “broadcast” to every
other point on the bus requires addressing signals to identify the
desired destination
example: the Ethernet network
Bus characterization
Parallel bus
an individual line for each bit of data, address, & control being
used
all the bits being transferred can be transferred
simultaneously
characterized by high throughput capability
every bus internal to the computer is a parallel bus since high
speed is essential
can be expensive for external use when distance is more than a
few feet
Serial bus
data is transferred sequentially, one bit at a time, using a single
data line pair
low throughput but cost per foot of line is much lower
many serial buses are used for point-to-point connections
I/O Channel Architecture
The channel architecture is based on a separate I/O processor
known as a channel subsystem
I/O processor acts as separate computer just for I/O operations, thus
freeing the CPU for other tasks
The channel subsystem executes its own set of instructions,
known as channel control words, independent of the CPU
Channel control words are stored as “programs” in memory, just like
other computer instructions
I/O Channel Architecture
The channel subsystem is made up of subchannels, each of which is connected
through a control unit module to an individual device by one or more channel
paths.
I/O Channel Architecture
The design allows multiple channel paths between the
channel subsystem & the CU, so that if one is busy
another can be selected
Up to 8 different channel paths can exist for a particular
I/O device
Channel paths can also be used to interconnect
computers into cluster
Physically, the channel subsystem is connected to the
CPU by a bus, & the various control units & I/O devices
are also connected by buses BUT conceptually, the
channel architecture is very different
