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2 Iteration Bound

This document discusses iteration bound, which is a fundamental lower bound on the achievable iteration or sample period for recursive algorithms with feedback loops. It can be calculated using two methods: longest path matrix (LPM) or minimum cycle mean (MCM). The LPM method constructs matrices representing the longest computation times between delay elements, with the iteration bound being the maximum value in the final matrix. This provides an inherent limit for recursive DSP algorithms implemented in hardware.

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78 views19 pages

2 Iteration Bound

This document discusses iteration bound, which is a fundamental lower bound on the achievable iteration or sample period for recursive algorithms with feedback loops. It can be calculated using two methods: longest path matrix (LPM) or minimum cycle mean (MCM). The LPM method constructs matrices representing the longest computation times between delay elements, with the iteration bound being the maximum value in the final matrix. This provides an inherent limit for recursive DSP algorithms implemented in hardware.

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Iteration Bound

Shao-Yi Chien

1
Iteration Bound
 Only for recursive algorithms which have
feedback loops
 Impose an inherent fundamental lower bound on
the achievable iteration or sample period
 A characteristic of data-flow graph (DFG)
 Two methods to calculate iteration bound
 Longestpath matrix (LPM)
 Minimum cycle mean (MCM)

DSP in VLSI Design Shao-Yi Chien 2


Data-Flow Graph
Representations (1/2)

Block diagram Data-flow graph (DFG)

DSP in VLSI Design Shao-Yi Chien 3


Data-Flow Graph
Representations (2/2)
 Iteration
 Execution of each node in the DFG exactly once
 Xk: k-th iteration of node X

 Precedence constraints
Intra-iteration
precedence constraint

Inter-iteration
precedence constraint

DSP in VLSI Design Shao-Yi Chien 4


Critical Path
 The path with the longest computation
time among all paths that contain zero
delays

6u.t.

5u.t.

DSP in VLSI Design Shao-Yi Chien 5


Loop Bound (1/2)
 Loop (cycle)
A directed path that begins and ends at the
same node

 Precedence constraints

DSP in VLSI Design Shao-Yi Chien 6


Loop Bound (2/2)
 Loop bound
 The lower bound on the loop computation time
 Loop bound of l-th loop: tl/wl
 tl: loop computation time
 wl: the number of delays in the loop

6/2=3 u.t.

DSP in VLSI Design Shao-Yi Chien 7


Iteration Bound (1/3)
 Critical loop
 The loop with the maximum loop bound
 Iteration bound
 Loop bound of the critical loop
Loop 2
ABCA
Loop bound: 11/1=11 u.t.

Loop 1
ABA
Loop bound: 6/2=3 u.t.
DSP in VLSI Design Shao-Yi Chien 8
Iteration Bound (2/3)
 An other example
L1: 1421

L2: 15321

L3: 16321

DSP in VLSI Design Shao-Yi Chien 9


Iteration Bound (3/3)
 Iteration bound is the lower bound on the
iteration or sample period of the DSP
program regardless of the amount of
computing resources available

DSP in VLSI Design Shao-Yi Chien 10


Algorithms for Computing
Iteration Bound
 Longest path matrix algorithm
 We only introduce this one
 Minimum cycle mean algorithm
 Negative cycle detection algorithm

DSP in VLSI Design Shao-Yi Chien 11


Longest Path Matrix Algorithm
(LPM) (1/8)
 There are d delay elements in the DFG
 First, construct a series of matrices L(m),
m=1,2,…,d
 li,j(m)
 Longest computation time of all paths from
delay element di to dj that pass through
exactly m-1 delays
 If no such path exists, then li,j(m)=-1

DSP in VLSI Design Shao-Yi Chien 12


LPM (2/8)
 Ex:
 l3,1(1)
 d3n5n3n2n1d1
 So l3,1(1)=5

 l4,3(1)
 No such path (2 delays, at
least)
 So l4,3(1)=-1

DSP in VLSI Design Shao-Yi Chien 13


LPM (3/8)

O/P d1 d2 d3 d4
I/P d1
d2
d3
d4

DSP in VLSI Design Shao-Yi Chien 14


LPM (4/8)
 The higher order matrices
 Can be derived from L(1)

K is the set of integers k in the interval [1,d]


such that neither li,k(1)=-1 nor lk,j(m)=-1 holds

DSP in VLSI Design Shao-Yi Chien 15


LPM (5/8)
 Ex:
 l2,1(2) lk,j(m)
O/P d1 d2 d3 d4
I/P d1 4 -1
d2 li,k(1) -1 4
d3 0 5
d4 -1 5

DSP in VLSI Design Shao-Yi Chien 16


LPM (6/8)
 L1, L1L2
 L1, L2L3
 L1, L3L4

DSP in VLSI Design Shao-Yi Chien 17


LPM (7/8)
 Iteration bound:

DSP in VLSI Design Shao-Yi Chien 18


LPM (8/8)
 An other example

DSP in VLSI Design Shao-Yi Chien 19

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