International Conference on Nanoscience and Technology, ICFANT 2010

An Analytical Approach for Statistical Modeling of the Effect of Process

Parameter Variation on the Performance of Nano-Scale CMOS VCO
S. Sengupta1, S. Pandit2, IC Design Laboratory, Centre of Advanced Study, Institute of Radio Physics and
Electronics
University of Calcutta, Kolkata- 700009
E-mail Id: 1 sarmista.sengupta@gmail.com, 2 soumya_pandit@ieee.org
Abstract – With the advent in complementary-metal-oxide-semiconductor (CMOS) technology, the device
dimension has shrunk into a few tens of nanometer. This aggressive scaling of the device introduces various non-
reliability issues to the performance of the device and circuit. In this paper we study the effect of process variation
on the performance of a voltage controlled oscillator (VCO). Here, the performance metric studied is the center
frequency of a five stage, current starved CMOS-VCO. An analytical expression is derived for the standard
deviation (STDEV) of the oscillation frequency. The input process parameters, channel length (L), threshold voltage
(Vth) and the oxide thickness (tox) are randomly varied around their nominal values and Monte Carlo simulation is
performed. The simulation result is compared with the model derived one.
Key words – process variation, performance metric, spread, statistical modeling,
I. Introduction
For the last few years, CMOS technology has been the mainstream in digital integrated
circuit (IC) design and in recent years CMOS technology has become the dominant path for
analog and RF IC design as well. Delay and dynamic power consumption in digital CMOS
circuits have been continuously improved by scaling of MOS transistor feature size and mobility
enhancement techniques; technology has also had remarkable impact on analog circuit design,
greatly improving the operating frequency of the active and passive components in analog
building blocks in particular [1]. However, not every scaling impact is positive in circuit design.
In particular, the process variability in the device and interconnect parameters has become one of
the severe bottlenecks in analog/digital circuit designs in nano-scale technologies [2], [3]. The
design of analog/RF integrated circuits are characterized by a series of performance parameters
that are measured in order to test whether their values satisfy the design constraints. During
commercial manufacturing a circuit is replicated on several dies of a wafer and on several
wafers. However, every replica does not result in compliance with the others, in terms of
electrical performances. This is because the manufacturing steps are affected by various random
factors that make the outcome non-uniform. The random variation at the process level inputs,
termed as process variation, in general, is classified into two broad categories: inter-die and intra-
die [4], [5] variations. This process variation results in a variation of the electrical performances
e. With the continued scaling of device dimension, the process variability induced circuit
performance variability has become a critical issue in very large scale integrated (VLSI) circuit
design procedure. The circuit performances are becoming more sensitive to uncontrollable
statistical process variations. From an IC design perspective, a shift in paradigm, from
deterministic to probabilistic design procedure, is needed to handle the unpredictable nature of
these process parameter variations. The variation of the process level parameters being a random
event, its effect is modeled statistically.
The statistical models relate the variation of electrical performances of a device/circuit as
functions of the variation of the process parameters [6]. There exist two types of approaches for
statistical modeling: analytical and numerical. This work presents a study for the impact of
random variation of the process parameters on the performance of a nano-scale current-starved
voltage controlled oscillator (VCO). Then the variation of the centre frequency of the VCO is
modeled statistically by analytical approach. The model estimates the maximum normalized
spread of the oscillation frequency, σfo/μfo. The random variation is simulated by large number of
Monte Carlo runs. The technology parameters chosen are the transistor channel length L, oxide
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International Conference on Nanoscience and Technology, ICFANT 2010

thickness tox (nMOS and pMOS transistor oxide thicknesses toxn and toxp respectively) and the
threshold voltage Vth (nMOS and pMOS transistor threshold voltages Vthn and Vthp). The model
predicted result is compared with the simulated results.
The rest of the paper is organized as follows. The statistical model developed for the current
starved nano CMOS VCO is presented in section II. The simulation and model predicted results
are discussed in section III. We conclude our work in section III.
II. Statistical Model Development
The general formulation for deriving the performance variation of a device or a circuit is
presented in the following subsection. Subsequently, the analytical expression for σfo in our
particular case (VCO) is derived.
II.A. Statistical Modeling Concepts
The technology parameters may be represented as a set of independent, normally distributed
components, expressed as,
p = {p1, p2, p3, ……….pi ,…………..pNp}
(1)
Here, pi (e.g. channel length L) is an element of the set p. Each of the elements is considered to
be a random variable that follows some distribution. Typically two parameters, namely, mean (μ)
and standard deviation (σ), are used to describe the distribution of a random variable. These are
defined as follows.

   p f ( p )dp
p i i i
i 
(2)
 2
 pi    pi   pi  f ( pi)dpi

(3)
Here f is the density function of the random variable pi.
The electrical performances of a circuit are dependent upon the technology parameters and
random variations of the technology parameters result in the deviation of the electrical
performance around its mean value. Normally, the pi values are found to follow a Gaussian
distribution [7]. The goal of statistical modeling is to mathematically represent the variation of
device or circuit-level electrical performances as functions of variation of the technology
parameters. The electrical performance ej of a circuit is related to the technology parameters as
follows,
ej  ej( p)  ej( p1, p2, p3,... pi... pNp)
(4)
Expanding ej in 1st order Taylor series around the nominal value
 p    p ,  p ,.........,  p ,......Np  , we get,
1 2 i

e j  e j ( p )   s j ,i  pi   p 
Np

i
i 1
(5)
where
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International Conference on Nanoscience and Technology, ICFANT 2010

e j
s j ,i 
pi p  μ
p
(6)
is termed as the sensitivity parameter.
The metric which quantifies the reliability of the device/circuit performance, is the normalized
spread (ζei/ei), expressed in percentage. An increase in its value implies larger deviation of the
performance from that of the nominal circuit. For a linear e(p) mapping we can define the
statistical mean and standard deviation of the electrical performance as:
e j  e j ( μ p )
(7)
Np
e  j s
i 1
j ,i p2
2
i

(8)
From (5), it can be argued that the performances will also have a similar distribution provided
the variation is small. It is to be noted that the statistical mean value for any electrical
performance is different its nominal value.
II.B. Formulation of a σfo of a CMOS VCO
The circuit diagram of a five-stage current starved CMOS VCO is shown in Figure 1.The
circuit consists of three parts; the topmost row of transistors forms the pMOS current mirror, the
bottom row of transistors forms the nMOS current mirror, and in between them the five stage
ring oscillator operates. The frequency of oscillation of the VCO is given as follows [8].
ID
fo 
NVDDCT
(9)
In (9), N is the number of inverter stages, and CT is the total (input and output) capacitance on the
drains of each inverter stage. ID in general represents current flowing through each of the five
stages of the oscillator. Expanding fo in 1st order Taylor series we get,
f o f o
f o ( I D , CT )  f o ( I , C )  I D  CT
D T  ID  CT
I D I D CT C T
(10)
From (9) the sensitivity parameters are found to be,
f o f o (  I D , CT ) 
  fo

 ID I I
ID  ID D D

(11)
f o f o (  I D , CT ) 
and,   fo

 CT C C
CT CT T T

(12)
Using (8), (11) and (12), the spread in oscillation frequency is found to be,
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International Conference on Nanoscience and Technology, ICFANT 2010

  f
2 2
 
f   fo   I D    o
2
  CT
2
 I
 CT
o
 D  
(13)
Hence the normalized spread of the oscillation frequency becomes,
2 2
f I    CT 
o
  D
   
  I
fo  D   CT 
(14)
The drain current ID and drain capacitance CT depend directly on the technology parameters
(namely channel length L, oxide thickness tox and threshold voltage Vth) as follows [8].
s ox WCM
ID  VGS  Vth 
2

tox 2 LCM
(15)
5  Wpi W 
CT   ox Li   ni 
2  tox toxn 
 p 
(16)
where
μs = carrier mobility when the transistor is in saturation region.
WCM = channel-width of the current mirror transistor.
LCM = channel-length of the current mirror transistor.
Wpi =channel-width of the pMOS transistor of the inverter circuit.
Wni =channel-width of the nMOS transistor of the inverter circuit.
Li =channel-length of the transistors (equal for pMOS and nMOS transistors) of the inverter
circuit.
The other symbols have their usual significance.
It is clear from (14) that the variation in the ring oscillator (through CT variation) and the current
mirror (through ID variation) sub-circuits contributes to the ultimate performance variation of the
VCO.
Using (8) and (16) the normalized spread in the drain capacitance becomes,

C  2 5 Wpi 
2
 
2

 L 5 W 2
T
  2 i
   ox Li   toxp    ox Li
2 ni
  toxn 
C 2   
 L    
2 2

 2 CT toxn  
T
 i  CT toxp 

(17)
The process variations affect the pMOS and nMOS transistor performances independently.
So we can write,
2 2
I I    I D ,SI 
D
  D ,SO
  
I  I   I 
D  D ,SO   D ,SI 
(18)
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International Conference on Nanoscience and Technology, ICFANT 2010

It is evident from (15) that drain current is a function of the threshold voltage. Again
threshold voltage for a short channel device strongly depends on L. Hence the effective threshold
voltage is modeled as [9],
Vth  Vtho   Vth
(19)
where
eN a xdT  rj  2x 
 Vth     1  dT  1  
Cox  L  rj 

(20)
Vtho = equivalent long channel threshold voltage
Na= carrier concentration in the depletion region
xdT = maximum depletion depth
rj = source/drain junction depth and other symbols are with usual significance.

Figure 1: Five-stage current starved CMOS VCO

Thus, Vth = Vth (LCM, tox, Vtho)

(21)
Now, Vth can also be expanded in 1 st order Taylor series to obtain,

Vth Vth Vth

Vth  LCM  tox 
LCM LCM   LCM
tox tox  tox
Vtho Vtho  Vtho

(22)
Here, ―CM‖ stands for current mirror sub circuit. The spread in Vth thus becomes,

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International Conference on Nanoscience and Technology, ICFANT 2010

1/2
  rj   
2

  eN x   2 x
a dT tox
  1 dT
 1    LCM  
2
   tox  2 
  LCM  r  

j   
V 
th
  
2 
  eN a xdT   rj  1  2 xdT  1    2   2 
     tox Vtho 
    LCM  rj 
 tox  
(23)
σVthp and σVthn can be calculated according to (23). From (15),

 
I  LCSO 2  toxp  Vthp 2
2 2
D ,SO
   4 
 2  2
 
2
I 2
VGS  Vthp
D ,SO
 LCSO t oxp

(24)

Finally, we get the maximum normalized spread in centre frequency of the VCO as,

  
   LCSO  toxp  Vthp 2
2 2
 
  2   2  4 
 
2
 fo   LCSO toxp VGS  Vthp  
 
 fo     2
 2  2  Vthn 2
2 2

  LCSI  toxn  4     Li   5  oxLi Wpi   toxp 2   5  oxLi Wni   toxn 2  
   Li 2  2  CT  toxp 2  
 CT  toxn 2 
   LCSI 2 toxn 2    
2
VGS  Vthn  2
 

(25)

III. Results
The experiments are carried out to observe the effect of i) technology parameter variation on
fo, ii) technology scaling on σfo/μfo, iii) different variations of technology parameter on σfo/μfo for
a particular technology node. The statistical model is derived for 45 nm. technology node, and
the simulation result is compared with the model predicted one. Berkley Predictive Technology
Model (BPTM) files are used for simulation purposes and HSPICE is chosen as the simulation
platform. The randomness of the technology parameters is simulated by 1000 Monte Carlo runs.

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International Conference on Nanoscience and Technology, ICFANT 2010

III.A. Effect of technology node variation on σfo/fo

Figure 1 shows that the distribution of the frequency of oscillation follows a Gaussian
distribution, which supports our argument in section II.B. The experiment is carried out for three
different technology nodes, namely, 32, 45 and 90 nm. technologies. Though the graphs
presented corresponds to simultaneous variation of all chosen technology parameters, the
simulation is performed also for i) only L, ii) only tox and iii) only Vth variations. For all of the
cases the oscillation frequency follows a Gaussian distribution.
For all the above experiments standard deviation and mean of the distribution is determined
and summarized in Table I. Table I shows that the process parameter variation reflects in the
spread of the performances of the circuit. Secondly, with technology scaling down, the
performance deviation from the nominal value increases. Therefore the simulation results again
support the prediction made earlier. It is also evident from the results that the effect of the
threshold voltage variation is more pronounced in the circuit performance variation behavior in
comparison with the other technology parameters.

III.B. Effect of different variations of technology parameter on σfo/fo

Comparing Figure 2 (a) and 3, we can clearly infer that σfo and hence σfo/fo increases
remarkably with increase in the extent of technology parameter variation even within a particular
technology node. The respective quantities are also summarized in Table II. Moreover the nature
of the distribution of fo deviates from a perfect Gaussian one, as we move towards higher
percentage variation of the technology parameters.
Table II shows that the model predicted results correctly describe the maximum normalized
spread of the VCO performance as in none of the cases the simulation result exceed them.

IV. Conclusion
The effect of process variability has become a critical issue in the design of nano-scale VLSI
circuits. An in-depth study of the effect of process variability is thus essential for robust
designing of a nano-scale CMOS circuits. With process variation, the variation in performances
is found to be Gaussian in nature. The spread of performances is found to be significant
compared to the mean value of the performances. Further, this increases with technology scaling.
In this paper, the normalized performance spread for a particular nano-CMOS circuit has been
mathematically formulated and have been verified through HSPICE simulation results.

V. Acknowledgement
The authors would like to thank Department of Science and Technology (DST), Govt. of India
and Centre for Research in Nanoscience and Nanotechnology (CRNN), CU for financially
supporting the work carried out.

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 International Conference on Nanoscience and Technology, ICFANT 2010

600

300

NO. OF SAMPLES
400

NO. OF SAMPLES
200

200
100

0 0
600.0M 1.2G 1.8G 2.4G 3.0G 800.0M 1.6G 2.4G 3.2G
FREQUENCY FREQUENCY

(a) 300 (b) (c)

NO. OF SAMPLES

200

100

0
1.6G 1.8G 2.0G 2.2G
FREQUENCY

Figure 2: fo of the VCO varying all parameters (10% variation) using (a)
32 nm., (b) 45 nm. and (c) 90 nm. technology nodes

TABLE I: STANDARD DEVIATIONS OF fo WITH SCALING

Tech. ALL toxp and toxn simultaneously Vtn L
node (σfo/μfo) (σfo/μfo ) (σfo/μfo ) ( σfo/μfo )
σfo μfo σfo μfo σfo μfo σfo μfo
(nm.) × 100 × 100 × 100 × 100
(GHz) (GHz) (GHz) (GHz) (GHz) (GHz) (GHz) (GHz)
(%) (%) (%) (%)
32 0.387 1.81 21.38 0.272 1.83 14.86 0.387 1.81 21.38 0.067 1.83 3.66
45 0.432 2.18 19.72 0.237 1.75 13.54 0.318 1.74 18.28 0.060 1.76 3.41
90 0.141 2.06 6.84 0.097 2.08 4.66 0.108 2.07 5.22 0.057 2.08 2.74

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International Conference on Nanoscience and Technology, ICFANT 2010

500

400

NO. OF SAMPLES
300

200

100

0
1.6G 2.0G 2.4G 2.8G
FREQUENCY
(a) (b)
Figure 3: fo of the VCO varying all parameters by (a) 5%
160 and (b) 15% using 45 nm. technology nodes
NO. OF SAMPLES

120

80

40

0
0 1G 2G 3G
FREQUENCY

TABLE II: COMPARISON SIMULATION AND MODEL PREDICTED RESULTS

% variation of the Simulation results Model predicted

technology (σfo/μfo ) × 100 σfo/fo
parameters σfo (GHz) μfo (GHz) (%)
(%)
5 0.133 2.411 5.52 14.31
10 0.432 2.181 19.81 28.77
15 0.645 1.853 34.81 42.92

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International Conference on Nanoscience and Technology, ICFANT 2010

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