(EN 312) Integrated

Electronics
MOS Transistor Theory

By Prof. Dr. Yaseer A.

Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
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Outline
❑ Semiconductor IC Chip
❑ Transistor Characteristics
❑ MOSFET Characteristics
❑ DC Characteristics of CMOS Inverter
❑ Propagation Delay, Noise Margin, Timing/Sizing, RC
Delay Model

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 Silicon Chip
❑ A pattern of interconnected switches & gates on surface of crystal of
semiconductor (typically Si)
❑ Silicon is a Group IV semiconducting material
❑ Crystal lattice: covalent bonds hold each atom to four neighbours
❑ These switches & gates are made of:
– Areas of n-type silicon
– Areas of p-type silicon
– Areas of insulator
– Lines of conductor (interconnects) joining areas together
• Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten
❑ Geometry of these areas is known as layout of the chip
❑ Connections from chip to outside world are made around the edge of the chip to
facilitate connections to other devices

n & p Type
❑ n-type
– Semiconductor has free electrons
– Dopant is (typically) phosphorus, arsenic, antimony
❑ p-type
– Semiconductor has free holes
– Dopant is (typically) boron, indium, gallium
❑ Dopants are usually implanted into the semiconductor using Implant
Technology, followed by thermal process to diffuse the dopants

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

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 p-n Junction
❑ A p-n junction is a boundary or interface b/w two types of semiconductor
material, p-type & n-type, inside a single crystal of semiconductor

❑ p–n junctions are elementary "building blocks" of most semiconductor

electronic devices such as diodes, transistors, solar cells, LEDs, ICs
❑ Common type of transistor, bipolar junction transistor, consists of two p–n
junctions in series, in the form n–p–n or p–n–p
❑ Types of Junction:
– Homojunction: is a semiconductor interface that occurs b/w layers of
similar semiconductor material, these materials have equal band gaps but
typically have different doping
– Heterojunction: is interface that occurs b/w two layers or regions of
dissimilar crystalline semiconductors. These semiconducting materials
have unequal band gaps as opposed to a homojunction

Idealized p-n Junction

❑ Holes diffused to metalurgical junction & combine with electrons. They leave
behind -vely charged acceptor, while electrons diffused & leave behind +vely
charged donor
❑ Diffusion process can not go on forever, because, increasing amount of fixed
charge wants to electrostatically attract the carriers that are trying to diffuse
away & equlibrium is reached
❑ Fixed charge produce an electric field which slows down the diffusion process
❑ Fixed charge region is called depletion/space charge region

❑ When p & n-type materials are joined, electrons & holes diffuse due to their
large carrier concentration gradients at junction where holes diffuse from p-side
into n-side, & electron diffuse from n to p. Thus, concentration gradients creates
a diffusion component of current from p to n region

+ + - -

+ + - -

+ + - -
-
+ + - -
+
+ +

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 Transistor Behavior
❑ If the width of a transistor increases, the current will
increase, decrease, not change
❑ If the length of a transistor increases, the current will
increase, decrease, not change
❑ If the supply voltage of a chip increases, the maximum transistor current will
increase, decrease, not change
❑ If the width of a transistor increases, its gate capacitance will
increase, decrease, not change
❑ If the length of a transistor increases, its gate capacitance will
increase, decrease, not change
❑ If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase, decrease, not change

Logic Families
❑ Most IC are manufacturing Bipolar Devices or MOS Devices based on
Power dissipation, Power Supply, Speed, Noise etc.
❑ MOS Logic Families
– PMOS Family (uses p-Channel MOSFET)
– NMOS Family (uses n-Channel MOSFET)
– CMOS Family (uses both p-Channel & n-Channel MOSFET)
❑ Bipolar Logic Families
Diode Logic (DL)
– Resistor Transistor Logic (RTL)
– Diode Transistor Logic (DTL)
– Transistor Transistor Logic (TTL)
– Emitter Coupled Logic (ECL)
– Integrated Injection Logic (I2L)

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 FET Types
❑ N Channel (as NPN transistor)
❑ P Channel (as PNP transistor)
❑ N & P channel each come as:
❑ Enhancement mode (just IGFET)
❑ Depletion mode (IGFET or JFET)
❑ MOSFET: Metal Oxide Semiconductor FET
❑ JFET: Junction FET
❑ IGFET: Insulated FET
❑ MESFET: Metal Semiconductor FET
❑ HEMT: High Electron Mobility Transistor
❑ MODFET: Modulation Doped FET
❑ FGMOS: Floating Gate MOS
❑ Most common are n-type MOSFET or JFET

JFET

Types of Transistors
❑ MOSFET - Metal Oxide Semiconductor Field-Effect Transistor
❑ CMOSFET - Complementary MOSFET
❑ DEMOSFET - Depletion Enhancement MOSFET
❑ DMOSFET - Double-Implanted MOSFET
❑ LDMOSFET - Lateral Diffusion MOSFET
❑ NMOSFET - Negative – MOSFET
❑ PMOSFET - Positive – MOSFET
❑ UMOSFET - U-Shape MOSFET
❑ VDMOSFET - Vertical Double-Diffused MOSFET
❑ VMOSFET - Vertical MOSFET
❑ MEISFET - Metal-Epitaxial Insulator SFET
❑ MESFET - Metal Electrode SFET
❑ MESFET - Metal-Epitaxial SFET
❑ SC-MOSFET - Surface-Channel MOSFET
❑ MISFET - Metal-Insulator-Silicon FET
❑ Metal–insulator–semiconductor field-effect transistor (MISFET)
❑ Floating-gate MOSFET (FGMOS)
❑ Power MOSFET
❑ Double-diffused metal–oxide–semiconductor (DMOS)
❑ Thin-film transistor (TFT)
❑ Bipolar Junction transistor (BJT)
❑ Multi-gate field-effect transistor (MuGFET)
❑ Quantum field-effect transistor (QFET) 10

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 Transistors Types
❑ MOS transistor is a majority carrier device in which current in a conducting
channel b/w source and drain is modulated by Vth
❑ Majority carriers of NMOS transistor: Electrons
❑ Majority carriers of PMOS transistor: Holes

P-channel

N-channel

MOSFET– MOSFET
JFET MOSFET-Enh (no bulk)
Enh Dep-

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Basic Operation of FET

❑ FET operation can be compared to a water spigot:
❑ Source of water pressure: Accumulated electrons at –ve pole of applied voltage
from Drain to Source
❑ Drain of water: Electron deficiency (or holes) at +ve pole of applied voltage from
Drain to Source
❑ Control of flow of water: Gate voltage that controls the width of n-channel, which
in turn controls the flow of electrons in n-channel from Source to Drain
Region Criteria Effect on Current
Cut-off VGS < Vth IDS=0
Linear VGS > Vth Transistor acts like
And a variable resistor,
VDS <VGS-Vth controlled by Vgs

Saturatio VGS > Vth Essentially

n And constant current
Gate Oxide
Gate VDS >VGS-Vth
Polysilicon Field-Oxyde
Source Drain
(SiO
2)
n+ n+

p-substrate p+ stopper

Bulk Contact
CROSS-SECTION of NMOS Transistor 12

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 nFET and pFET
❑ FET Polarity (n or p) is determined by polarity of drain & source regions
❑ nFET: Drain & source are “n+” to indicate heavily doped
❑ pFET: Source & drain are “p+” that are embedded in n-type “well” layer
❑ All pn-junction used to prevent current flow between adjacent layers

nFET cross-section pFET cross-section

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JFET
❑ JFET consists of high-resistivity semiconductor material (usually Si) which
constitutes a channel for majority carrier flow
❑ If channel is doped with donor impurity, n-type material is formed & channel
current will consist of electrons
❑ If channel is doped with acceptor impurity, p-type material will be formed &
channel current will consist of holes
❑ N-channel devices have greater conductivity than p-channel types, since
electrons have higher mobility than do holes; thus n-channel JFETs are
approximately twice as efficient conductors compared to their p-channel
counterparts
❑ Magnitude of current is controlled by voltage applied to gate, which is reverse-
biased

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 JFET
Source Gate Drain Source Gate Drain Source Gate + Drain

Channel

NType Insulator NType Insulator NType Insulator

Substrate Substrate Substrate
P Type Metal P Type Metal P Type Metal
An Insulated Gate FET Insulated Gate FET n-Channel enhancement
n-Channel Enhancement mode IGFET turned on

Source Gate+ Drain+ Source Gate + Drain++Source Gate Drain Source Gate - Drain

Channel Channel Channel NoChannel

NType Insulator NType Insulator NType Insulator

Substrate Substrate NType Insulator
Substrate P Type Metal P Type Metal Substrate
P Type Metal P Type Metal
N enhance FET at N enhance FET n-Channel Depletion mode n-Channel Depletion
Pinchoff beyond Pinchoff FET ON – No gate bias mode FET off

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Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET)

❑ MOSFET is a transistor used for amplifying or switching electronic signals
❑ Source & Drain terminals are specified by operation voltage
❑ MOSFET is a small area set of two basic patterned layers that together act like a
controlled switch
❑ Voltage applied to gate determines current flow between D & S

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MOSFETs
❑ MOSFETs have characteristics similar to JFETs and additional characteristics
that make then very useful
❑ Depletion-Type MOSFET
– Drain (D) & Source (S) connect to n-doped regions. These n-doped regions
are connected via n-channel. This n-channel is connected to Gate (G) via
thin insulating layer of SiO2. The n-doped material lies on a p-doped
substrate that may have additional terminal connection called SS
❑ Enhancement-Type MOSFET
– Drain (D) & Source (S) connect to n-doped regions. These n-doped regions
are connected via n-channel. The Gate (G) connects to the p-doped
substrate via a thin insulating layer of SiO2. There is no channel. The n-
. doped material lies on a p-doped substrate that may have additional
terminal connection called SS

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Physical Structure of MOSFET

 Drain & Source regions are patterned into a silicon wafer
 Length L of gate is called channel length
 Width W of drain & source regions is called channel width
 Aspect ratio (W/L) and is most important parameter to VLSI designer

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 PMOS/NMOS
 P-channel MOS (PMOS) & N-channel MOS (NMOS) logic uses p-channel/n-
channel MOSFETs to implement logic gates & digital circuits
 For devices of equal current driving capability, n-channel MOSFETs can be made
smaller than p-channel MOSFETs, due to p-channel charge carriers (holes)
having lower mobility than do n-channel charge carriers (electrons)
 NMOS logic consumes power even when no switching is taking place
NMOS Operation PMOS Operation

Vgsn = Vin VDD Vgsp = Vin - VDD VDD

Vdsn = Vout Vdsp = Vout - VDD Idsp

Idsp Vin Vout
Vin Vout
Idsn Idsn

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Four Modes of Transistors

❑ Enhancement mode NMOS transistor:
– Vtn>0
– If Vgs>Vtn, transistor starts to conduct. The number of electrons in channel
increases so that Idsn increases accordingly. If Vgs<Vtn, transistor is cut off
and Ids is almost zero
❑ Depletion mode NMOS transistor:
– Vtn<0 or (-Vtn & Vtn>0)
– Even if Vgs=0>Vtn, transistor is “ON”
– If Vgs<Vtn<0, transistor is cut off
❑ Enhancement mode PMOS transistor:
– Vtp<0 or (-Vtp and Vtp>0)
– If Vgs<Vtp<0, transistor starts to conduct. The number of holes in channel
increases so that Idsp increases accordingly
– If Vgs>Vtp, transistor is cut off
❑ – Depletion mode PMOS transistor:
– Vtp>0
– Even if Vgs=0<Vtp, transistor is “ON”
– If Vgs>Vtp>0, transistor is cut off

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 MOS Transistor
❑ Normal conduction characteristics of a MOS transistor:
– “Cut-off” region: Ids≈0
– “Non-saturated” region: Channel is weakly inverted. I ds is dependent on the
gate and drain voltage with respect to the substrate
– “Saturated” region: Channel is strongly inverted. I ds is ideally independent
of Vds
❑ For a fixed Vds and Vgs, the factors that influence Ids:
– Distance b/w source and drain
– Channel width
– Vt
– Thickness of gate oxide
– Dielectric constant of the gate oxide
– Carrier mobility

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JFET Vs MOSFET Transistors

MOSFET JFET D
I
High switching speed Will operate at VG<0
Can have very low RDS Better suited for low signal
B
amplification G
Susceptible to ESD
More commonly used as a S
power transistor

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VMOS
❑ VMOS – Vertical MOSFET increases the surface area of device
❑ V shape gate allows to deliver a higher amount of current from source to drain
❑ Shape of depletion region creates a wider channel, allowing more current to flow
through it
❑ Sharp corner at bottom of groove enhances electric field at edge of channel in
depletion region, thus reducing the breakdown voltage of device
❑ This electric field launches electrons into gate oxide & trapped electrons shift the
MOSFET VT
❑ Advantage:
❑ This allows the device to handle higher currents by providing it more
surface area to dissipate the heat
❑ VMOSs also have faster switching times

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CMOS
❑ CMOS – Complementary MOSFET p & n-channel MOSFET on same substrate
❑ CMOS technology employs both PMOS & NMOS devices
❑ If substrate is p-type, PMOS transistors are formed in n-well (n-type body need)
❑ If substrate is n-type, NMOS transistors are formed in p-well (p-type body need)
❑ Substrate & well are connected to voltages which reverse bias the junctions for
device isolation
❑ Advantage:
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
• High temperature stability
• High noise immunity

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 MISFET
❑ Metal–Insulator–Semiconductor Field-Effect-Transistor (MISFET) is a more
general term than MOSFET and synonym to IGFET. All MOSFETs are MISFETs,
but not all MISFETs are MOSFETs
❑ The gate dielectric insulator is SiO2 & directly below gate electrode & above
channel of MISFET
❑ The term metal is historically used for gate material, even though now it is
usually highly doped polysilicon or some other non-metal

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FGMOS
❑ Floating-Gate MOSFET (FGMOS) is a type of MOSFET where gate is
electrically isolated, creating a floating node in DC and a number of secondary
gates or inputs are deposited above the floating gate (FG) and are electrically
isolated from it
❑ FGMOS is commonly used in floating-gate memory cell, digital storage element
in EPROM, EEPROM & flash memories
❑ FGMOS is used in neuronal computational element in neural networks, analog
storage element, digital potentiometers & single-transistor DACs

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 BJT
❑ BJT is current controlled device
❑ Base (B): very thin & lightly doped central region, Emitter (E) & Collector (C)
are two outer regions sandwiched to B
❑ Operational modes are B-E & B-C voltages
❑ When there is no (B) current, almost no (C) current flows & when (B) current
flow, (C) current can flow
❑ Normal operation in linear & active regions
❑ B-E junction forward biased, B-C junction reverse biased
❑ (E) emits (injects) majority charge into base region . Due to very thin base,
most will ultimately reach the collector
❑ (E) is highly doped, (C) is lightly doped & has at higher voltage than (E)
❑ pnp transistor operates in similar manner to npn device

Emitter Base Collector Emitter Base Collector

p+ n p n+ p n
Emitter emits holes Collector collects holes Emitter emits electrons Collector collects electrons
Narrow base controls number of holes emitted Narrow base controls number of electrons emitted

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Threshold Voltage
❑ Voltage applied b/w gate & source of MOS device below which Ids effectively
drops to zero
❑ In general, VT is a function of following parameters:
– Gate conduction material
– Gate insulation material
– Gate insulator thickness
– Channel doping
– Impurities at the silicon-insulator interface
– Voltage b/w source & substrate, Vsb

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 MOS Models
❑ Most CMOS digital foundry operations have been standardized on
LEVEL 3 models in SPICE as level of circuit modeling that is required
for CMOS digital system design
❑ In Table 2.1 SPICE DC parameters are used in LEVELS 1, 2, 3 with
representative values for 1m n-well CMOS process

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MOSFETS Characteristics
❑ 4-Terminal Device: Drain, Source, Gate, Bulk
❑ Insulator SiO2 generally guartz glass

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 MOSFETS
❑ For small VG creates depletion region that
consists of –ve space charge

Surface Potential

Acceptor Doping Density

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n-Channel MOSFETS
❑ When VG=VTn: Initiates the formation of thin electron inversion layer with
surface charge density at silicon surface
❑ When VG>VTn gives buildup of inversion charge
❑ Inversion charge is due to mobile electrons that are free to move in a direction
parallel to face

Surface Potential Boltzman Constant

Bulk Fermi Potential Intrinsic Density

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 n-Channel MOSFETS
❑ When VG=VTn: Qn=0, Qs=QB is the total charge at surface
❑ Using Q=CV,

Kirchhoff eq gives
For ideal VTn

❑ Ideal VTn assume perfect MOS insulator, ignore gate/substrate made with
different materials
❑ Real MOS has 1. trapped charge within oxide that alters electric field 2.
Difference in electric characteristics of gate & substrate. Then:

Flatband voltage Work function difference

Volume charge density
Fixed surface
charge density

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n-Channel MOSFETS
❑ Incorporating VFB contributions to VTn gives:

❑ VFB is –ve but switching circuits use +ve power supply that accomplished by
threshold adjustment ion implant with dose DI

❑ Once VG>VT, electron inversion charge density is:

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 Example

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n-Channel MOSFETS
❑ When bias transistor with VD & VS, p-substrate is grounded & induces
body-bias effect & VTn increased due to VSBn adds reverse-bias
across p-substrate/n-channel boundary which increases bulk depletion
charge

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 Example

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n-Channel MOSFET Current Voltage Characteristics

❑ At cutoff VGSn<VTn: IDn=0
❑ At active VGSn≥VTn: Creates electron inversion layer beneath oxide, so
Idn is a function of VGSn & VDSn
❑ Two conditions needs to flow current: 1. VGSn≥VTn 2. VDSn must be
applied to produce channel E

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 n-Channel MOSFET Current Voltage Characteristics

Rearranging & integrating y from

Y=0 to y=L

Process transconductance

Device transconductance

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n-Channel MOSFET Current Voltage Characteristics

❑ At VDSn=Vsat Channel is pincked off at drain side of transistor

❑ At VDSn≥Vsat, current flow only weak dependence on VDS

❑ When VDS increases, affective length of Lsat decreases called channel-
length modulation

Channel length modulation

With ʎ=0

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 p-Channel MOSFET Current Voltage Characteristics
❑ p-Channel MOSET, pFET or pMOS is complement of n-channel device
❑ Change n-type to p-type region and
❑ Change p-type to n-type regions then we
❑ Reverse the roll of electrons and holes
❑ Reverse the polarities of all voltages
❑ Reverse the direction of current flow

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p-Channel MOSFET Current Voltage Characteristics

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 MOSFET Resistance Modelling

Non saturated device

Voltage dependence resistance

Linear Time-Invariant (LTI) FET resistance

Vref=VDD

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MOSFET Capacitance Modelling

Gate overlap

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 MOSFET Capacitance Modelling

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MOSFET Capacitance Modelling

Zero-bias depletion

Built-in voltage
Reverse-bias voltage

Junction capacitance

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 MOSFET Capacitance Modelling

Parameter length

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MOSFET Capacitance Modelling

Average capacitance

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 Simplified Linear FET Model
❑ In simplified model total capacitance at every node by simply adding all
contributions that required to change voltage during switching
❑ It estimates performance during design phases

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Junction Leakage Currents

❑ Leakage current is often important in high-performance circuit design
❑ Leakage current is proportional to junction area A and increases with
reverse bias VR
❑ MOSFET switching model includes both capacitances and junction
leakage current:

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 Geometric Scale
𝐴𝑟𝑒𝑎 𝐿
𝑡ℎ𝑒𝑛 𝐿 →
2 2
1
𝑆𝑐𝑎𝑙𝑖𝑛𝑔 𝐹𝑎𝑐𝑡𝑜𝑟 𝜆 = = 0.7
2

Low cost= Wafer diameter use more chips

High speed due to Lch/2
Low Power 𝑉 → 𝑉 𝐼
I→ 2
2

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DC Characteristics of CMOS Inverter

❑ DC transfer characteristics of inverter are function of Vout with respect to Vin
❑ Curve is determined by plotting the common points of Vgs intersection after
taking the absolute value of p-device IV curves, reflecting them about x-axis &
superimposing them on n-device IV curves

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 Inverter Voltage Transfer Characteristics

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Noise Margin

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 Switching Threshold

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Effect of Transistor Size on VTC

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 Transient Analysis

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Transient Response

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 Inverter Transient Response
VDD=2.5V
3
0.25m
Vin
W/Ln = 1.5 2.5
W/Lp = 4.5
2
Reqn= 13 k ( 1.5)
Reqp= 31 k ( 4.5) 1.5

1 tpHL tf tpLH tr
tpHL = 36 psec
0.5
tpLH = 29 psec
0
so
-0.5
tp = 32.5 psec 0 0.5 1 1.5 2 2.5
t (sec) x 10-10
From simulation: tpHL = 39.9 psec & tpLH = 31.7 psec

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Rise/Fall Time

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 Propagation Delay

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Switching Speed-Resistance

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 Switching Speed-Capacitance

Decreasing L (reducing feature size)

is best way to improve speed

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CMOS Power Consumption

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 RC Delay Model
❑ Use RC delay models to estimate delay
– C=Total capacitance on output node, Use effective resistance R & tpd = RC
– Characterize transistors by finding their effective R
– Depends on average current as gate switches
❑ Use equivalent circuits for MOS transistors
– Ideal switch + capacitance & ON resistance
– NMOS has R, C while PMOS has 2R, C
❑ Capacitance proportional to width & Resistance inversely proportional to width

d
❑ Capacitance s
kC
kC
– C = Cg = Cs = Cd = 2 fF/m of gate width R/k
d 2R/k
– Values similar across many processes d
g k g kC
❑ Resistance s
g k g
kC kC
– R  6 K*m in 0.6um process kC s
– Improves with shorter channel lengths s
d
❑ Unit transistors k
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 m wide device
– Doesn’t matter as long as you are consistent

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Example
❑ 3-input NAND with transistor widths chosen to achieve effective rise & fall
resistances equal to unit inverter (R)
❑ Annotate 3-input NAND gate with gate & diffusion capacitance

2C 2C 2C 2
2 2 2 2C 2C 2C 2 2
2 2 2
2C 2C 2C 3 9C
3
5C
3C 3 3C
3 3 5C
3C
3C 3 3C
3 3 5C
3C
3C
3
3C
3 input NAND gate 3C

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 Switch Delay Model
❑ Propagation delay depends on input patterns
❑ Example: Two input NAND gate
– Two PMOS transistors are ON
– Delay: 0.69x(Rp/2)xCL
– Only one PMOS transistor ON then
– Delay: 0.69xRpxCL
❑ Large number of transistors (2N) increases overall capacitance of gate
❑ Series connection of transistors in PUN/PDN of gate causes additional slow down

DD V VDD
V DD Rp Rp Rp
Rp A B B
F Rp
A Rn
CL
= R ON F B A
Rn F
CL Rn Rn Rn
CL
A A B
A

Inverter 2 input NAND 2-input NOR

t = 0.69 R on C L
p
(assuming that C dominates!)
L 67

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Switch Delay Model

VDD VDD
1. Assume Rn =Rp = resistance of minimum VDD
sized NMOS inverter Rp Rp
1 1 B 4
2. Determine “Worst Case Input” transition A B 2
A
(Delay depends on input values) FA B
Rn C 4
CL F
3. Example: t pLH for 2input NAND
B 2 CL
- Worst case when only ONE PMOS Pulls D 2
up the output node Rn
B
- For 2 PMOS devices in parallel, the
F
resistance is lower A A 2
2
D 1
t pLH = 0.69Rp CL A
2-input NAND B 2C 2
4. Example: t pHL for 2input NAND
- Worst case : 2 NMOS in series
t pHL = 0.69(2R n )CL Here it is assumed that Rp = Rn

Design for worse case

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 Elmore Delay
❑ Elmore delay is equivalent to first-order time constant of n/w
❑ Time constant represents simple approx. of actual delay b/w source node & node i
❑ ON transistors look like resistors
❑ Pullup or pulldown network modeled as RC ladder
❑ Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

t pd  R
nodes i
i −to − source Ci

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

N i N
 DN =  C i  R j =  C i Rii
i =1 j =1 i =1

Delay Optimization

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Example
❑ Example: Estimate worst-case rising & falling delay of 2-input NAND driving h
identical gates
t pdr = ( 6 + 4h ) RC
R
2 2 Y
Y
(6+4h)C
A 2 Rising
2x
h copies
B

x R/2 Y t pdf = ( 2C ) ( R2 ) + ( 6 + 4h ) C  ( R2 + R2 )

2 2 2C (6+4h)C
= ( 7 + 4h ) RC
Y R/2
A 2 6C 4hC
Falling
B 2x 2C

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