EXPERIMENT-6
A. Write a VHDL code for synchronous D latch using dataflow modelling.
Main Code-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Dff is
Port ( d : in STD_LOGIC;
enable : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end Dff;
architecture Behavioral of Dff is
begin
process(d,enable)
begin
if(enable ='1') then
q<= d;
qbar <= not d;
end if;
end process;
RTL Schematic-
Waveform-
Another way-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SYNCD is
Port ( d : in STD_LOGIC;
en : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end SYNCD;
architecture Behavioral of SYNCD is
signal s,r:std_logic;
begin
s<= d nand en;
r<= (not d) nand en;
Q<= s nand Qbar;
Qbar <= r nand Q;
end Behavioral;
B. Write a VHDL code for synchronous D flip flop using behavioral modelling.
Main Code
entity Dbeh is
Port ( D : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC);
end Dbeh;
architecture Behavioral of Dbeh is
begin
process(Clock)
begin
if(Clock'event and Clock='1') then
Q<=D;
end if;
end process;
end Behavioral;
Another way-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SYNCD is
Port ( d : in STD_LOGIC;
en : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end SYNCD;
architecture Behavioral of SYNCD is
signal s,r:std_logic;
begin
s<= d nand en;
r<= (not d) nand en;
Q<= s nand Qbar;
Qbar <= r nand Q;
end Behavioral;
RTL Schematic-
Waveform-
C. Write a VHDL code for synchronous RS flip flop using behavioral modeling.
Main code-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sr is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end sr;
architecture Behavioral of sr is
signal qn, qnbar:std_logic;
begin
process(s,r,clock,reset)
begin
if (reset ='1') then
q<= '0';
elsif (clock'event and clock ='1') then
if(s='0' and r='0')then
q<=qn;
qbar<= not qn;
elsif(s='0' and r='1')then
qn<=s;
qnbar<=not qn;
elsif(s='1' and r='0')then
qn<=s;
qnbar<=not qn;
elsif(s='1' and r='1')then
qn<='Z';
qnbar<='Z';
end if;
q<=qn;
qbar <=not qn;
end if;
end process;
end Behavioral;
RTL-
Waveform
SR FLIPFLOP FOR JK FLIPFLOP IMPLEMENATATION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sro is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clock:in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end sro;
architecture Behavioral of sro is
signal qn, qnbar:std_logic;
begin
process(s,r,clock)
begin
if (clock'event and clock ='1') then
if(s='0' and r='0')then
q<=qn;
qbar<= not qn;
elsif(s='0' and r='1')then
qn<=s;
qnbar<=not qn;
elsif(s='1' and r='0')then
qn<=s;
qnbar<=not qn;
elsif(s='1' and r='1')then
qn<='Z';
qnbar<='Z';
end if;
q<=qn;
qbar <=not qn;
end if;
end process;
end Behavioral;
Waveform-
RTL-
NAND GATE LOGIC FOR JK FLIPFLOP IMPLEMENATATION
entity NAND1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
d : in STD_LOGIC;
c : out STD_LOGIC);
end NAND1;
architecture Behavioral of NAND1 is
begin
c<= not(a and b and d);
end Behavioral;
D. Write a VHDL code for synchronous JK flip flop using structural modeling.
Code
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity JKNEW is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JKNEW;
Architecture behavioral of JKNEW is
begin
PROCESS(CLOCK)
variable TMP: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(J='0' and K='0')then
TMP:=TMP;
elsif(J='1' and K='1')then
TMP:= not TMP;
elsif(J='0' and K='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
Q<=TMP;
Q <=not TMP;
end PROCESS;
end behavioral;
Waveform-
OTHER WAY-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clock : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : inout STD_LOGIC);
end JK;
architecture Behavioral of JK is
component sro is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clock:in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end component;
component NAND1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
d : in STD_LOGIC;
c : out STD_LOGIC);
end component;
signal S,R:STD_LOGIC;
begin
N1: NAND1 port map(j,qbar,clock,S);
N2: NAND1 port map(k,q,clock,R);
ff1:sro port map(S,R,clock,q,qbar);
end Behavioral;
E. Write a VHDL code for synchronous T flip flop using behavioral modeling.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T is
Port ( T : in STD_LOGIC;
clk : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end T;
architecture Behavioral of T is
begin
process(T, clk)
variable int : STD_LOGIC:='0';
begin
if clk'event and clk = '1' then
if T = '0' then
int :=int;
else
int := not int ;
end if;
end if;
Q <= int ;
Qbar <= not int ;
end process;
end Behavioral;
Waveform
