Intel® Pentium® D Processor

900Δ Sequence and Intel®

Pentium® Processor Extreme
Edition 955Δ, 965Δ
Datasheet

– On 65 nm Process in the 775-land LGA Package supporting

Intel® 64 Architecture and supporting Intel® Virtualization
Technology±

January 2007

Document Number: 310306-007

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT
INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium D processor 900 sequence and Intel® Pentium processor Extreme Edition 955, 965 may contain design defects or errors known as
errata which may cause the product to deviate from published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
†Hyper-Threading Technology requires a computer system with an Intel® Pentium® processor Extreme Edition supporting Hyper-Threading Technology
and an HT Technology enabled chipset, BIOS, and an operating system. Performance will vary depending on the specific hardware and software you use.
See <http://www.intel.com/products/ht/hyperthreading_more.htm> for information including details on which processors support HT Technology.
ΦIntel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64.
Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and
software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support
Intel 64, or consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
±
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some
uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations
and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at
http://processorfinder.intel.com or contact your Intel representative for more information.
Intel, Pentium, Intel NetBurst, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005–2007 Intel Corporation.

2 Datasheet
ContentsContents

1 Introduction ............................................................................................................ 11
1.1 Terminology ..................................................................................................... 12
1.1.1 Processor Packaging Terminology ............................................................. 12
1.2 References ....................................................................................................... 13
2 Electrical Specifications ........................................................................................... 15
2.1 Power and Ground Lands.................................................................................... 15
2.2 Decoupling Guidelines ........................................................................................ 15
2.2.1 VCC Decoupling ...................................................................................... 15
2.2.2 VTT Decoupling ...................................................................................... 15
2.2.3 FSB Decoupling...................................................................................... 16
2.3 Voltage Identification ......................................................................................... 16
2.4 Reserved, Unused, and TESTHI Signals ................................................................ 18
2.5 Voltage and Current Specification ........................................................................ 19
2.5.1 Absolute Maximum and Minimum Ratings .................................................. 19
2.5.2 DC Voltage and Current Specification ........................................................ 20
2.5.3 VCC Overshoot ...................................................................................... 24
2.5.4 Die Voltage Validation ............................................................................. 25
2.6 Signaling Specifications...................................................................................... 25
2.6.1 FSB Signal Groups.................................................................................. 26
2.6.2 GTL+ Asynchronous Signals..................................................................... 28
2.6.3 Processor DC Specifications ..................................................................... 28
2.6.3.1 GTL+ Front Side Bus Specifications ............................................. 31
2.7 Clock Specifications ........................................................................................... 32
2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 32
2.7.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 32
2.7.3 Phase Lock Loop (PLL) and Filter .............................................................. 33
2.7.4 BCLK[1:0] Specifications ......................................................................... 35
3 Package Mechanical Specifications .......................................................................... 37
3.1 Package Mechanical Drawing............................................................................... 37
3.2 Processor Component Keep-Out Zones ................................................................. 41
3.3 Package Loading Specifications ........................................................................... 41
3.4 Package Handling Guidelines............................................................................... 41
3.5 Package Insertion Specifications.......................................................................... 41
3.6 Processor Mass Specification ............................................................................... 42
3.7 Processor Materials............................................................................................ 42
3.8 Processor Markings............................................................................................ 42
3.9 Processor Land Coordinates ................................................................................ 43
4 Land Listing and Signal Descriptions ....................................................................... 45
4.1 Processor Land Assignments ............................................................................... 45
4.2 Alphabetical Signals Reference ............................................................................ 70
5 Thermal Specifications and Design Considerations .................................................. 81
5.1 Processor Thermal Specifications ......................................................................... 81
5.1.1 Thermal Specifications ............................................................................ 81
5.1.2 Thermal Metrology ................................................................................. 85
5.2 Processor Thermal Features ................................................................................ 85
5.2.1 Thermal Monitor..................................................................................... 85
5.2.2 On-Demand Mode .................................................................................. 86
5.2.3 PROCHOT# Signal .................................................................................. 86
5.2.4 FORCEPR# Signal................................................................................... 87

Datasheet 3
 5.2.5 THERMTRIP# Signal ................................................................................88
5.2.6 TCONTROL and Fan Speed Reduction ...........................................................88
5.2.7 Thermal Diode........................................................................................88
6 Features ..................................................................................................................91
6.1 Power-On Configuration Options ..........................................................................91
6.2 Clock Control and Low Power States .....................................................................91
6.2.1 Normal State .........................................................................................92
6.2.2 HALT and Enhanced HALT Powerdown States..............................................92
6.2.2.1 HALT Powerdown State ..............................................................92
6.2.2.2 Enhanced HALT Powerdown State................................................93
6.2.3 Stop Grant State ....................................................................................93
6.2.4 Enhanced HALT Snoop or HALT Snoop State,
Stop Grant Snoop State...........................................................................94
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................94
6.2.4.2 Enhanced HALT Snoop State .......................................................94
6.2.5 Enhanced Intel® SpeedStep® Technology ..................................................94
7 Boxed Processor Specifications................................................................................95
7.1 Mechanical Specifications ....................................................................................95
7.1.1 Boxed Processor Cooling Solution Dimensions.............................................95
7.1.2 Boxed Processor Fan Heatsink Weight .......................................................97
7.1.3 Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly...............................................................................97
7.2 Electrical Requirements ......................................................................................97
7.2.1 Fan Heatsink Power Supply ......................................................................97
7.3 Thermal Specifications........................................................................................99
7.3.1 Boxed Processor Cooling Requirements......................................................99
8 Balanced Technology Extended (BTX) Boxed Processor Specifications ................... 101
8.1 Mechanical Specifications .................................................................................. 102
8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor
Cooling Solution Dimensions .................................................................. 102
8.1.2 Boxed Processor Thermal Module Assembly Weight ................................... 104
8.1.3 Boxed Processor Support and Retention Module (SRM) .............................. 104
8.2 Electrical Requirements .................................................................................... 105
8.2.1 Thermal Module Assembly Power Supply .................................................. 105
8.3 Thermal Specifications...................................................................................... 107
8.3.1 Boxed Processor Cooling Requirements.................................................... 107
8.3.2 Variable Speed Fan ............................................................................... 108
9 Debug Tools Specifications .................................................................................... 111
9.1 Logic Analyzer Interface (LAI) ........................................................................... 111
9.1.1 Mechanical Considerations ..................................................................... 111
9.1.2 Electrical Considerations ........................................................................ 111

4 Datasheet
Figures
1 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and
775_VR_CONFIG_05B (Performance) Processors .......................................................... 24
2 VCC Overshoot Example Waveform ............................................................................. 25
3 Phase Lock Loop (PLL) Filter Requirements .................................................................. 34
4 Processor Package Assembly Sketch ........................................................................... 37
5 Processor Package Drawing Sheet 1 of 3 ..................................................................... 38
6 Processor Package Drawing Sheet 2 of 3 ..................................................................... 39
7 Processor Package Drawing Sheet 3 of 3 ..................................................................... 40
8 Processor Top-Side Markings Example (Intel® Pentium® D Processor 900 Sequence) ........ 42
9 Processor Top-Side Markings Example (Intel® Pentium® Processor Extreme Edition 955,
965)....................................................................................................................... 43
10 Processor Land Coordinates and Quadrants (Top View) ................................................. 44
11 land-out Diagram (Top View – Left Side) ..................................................................... 46
12 land-out Diagram (Top View – Right Side) ................................................................... 47
13 Thermal Profile for 775_VR_CONFIG_05B Processors (Performance) ............................... 83
14 Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)................................. 84
15 Case Temperature (TC) Measurement Location ............................................................ 85
16 Processor Low Power State Machine ........................................................................... 92
17 Mechanical Representation of the Boxed Processor ....................................................... 95
18 Space Requirements for the Boxed Processor (Side View: applies to all four side views) .... 96
19 Space Requirements for the Boxed Processor (Top View)............................................... 96
20 Space Requirements for the Boxed Processor (Overall View) .......................................... 97
21 Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 98
22 Baseboard Power Header Placement Relative to Processor Socket ................................... 99
23 Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(Side 1 View) ........................................................................................................ 100
24 Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(Side 2 View) ........................................................................................................ 100
25 Mechanical Representation of the Boxed Processor with a Type I TMA ........................... 101
26 Mechanical Representation of the Boxed Processor with a Type II TMA .......................... 102
27 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes ..... 103
28 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume ..... 104
29 Assembly Stack Including the Support and Retention Module ....................................... 105
30 Boxed Processor TMA Power Cable Connector Description ............................................ 106
31 Balanced Technology Extended (BTX) Mainboard Power Header Placement
(Hatched Area) ...................................................................................................... 107
32 Boxed Processor TMA Set Points............................................................................... 108

Datasheet 5
Tables
1 References ..............................................................................................................13
2 Voltage Identification Definition ..................................................................................17
3 Absolute Maximum and Minimum Ratings ....................................................................19
4 Voltage and Current Specifications..............................................................................20
5 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and
775_VR_CONFIG_05B (Performance) Processors ..........................................................23
6 VCC Overshoot Specifications......................................................................................24
7 FSB Signal Groups ....................................................................................................26
8 Signal Characteristics................................................................................................27
9 Signal Reference Voltages .........................................................................................27
10 GTL+ Signal Group DC Specifications ..........................................................................28
11 GTL+ Asynchronous Signal Group DC Specifications ......................................................29
12 TAP Signal Group DC Specifications.............................................................................29
13 VTTPWRGD DC Specifications .....................................................................................30
14 BSEL[2:0] and VID[5:0] DC Specifications ...................................................................30
15 MSID [1,0] and BOOTSELECT DC Specifications............................................................30
16 GTL+ Bus Voltage Definitions .....................................................................................31
17 Core Frequency to FSB Multiplier Configuration.............................................................32
18 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................33
19 Front Side Bus Differential BCLK Specifications .............................................................35
20 Processor Loading Specifications.................................................................................41
21 Package Handling Guidelines......................................................................................41
22 Processor Materials ...................................................................................................42
23 Alphabetical Land Assignments...................................................................................48
24 Numerical Land Assignment .......................................................................................59
25 Signal Description (Sheet 1 of 9) ................................................................................70
26 Processor Thermal Specifications ................................................................................82
27 Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)................................83
28 Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream) .................................84
29 Thermal “Diode” Parameters using Diode Model ............................................................88
30 Thermal “Diode” Parameters using Transistor Model ......................................................89
31 Thermal “Diode” ntrim and Diode_Correction_Offset.......................................................90
32 Thermal Diode Interface ............................................................................................90
33 Power-On Configuration Option Signals .......................................................................91
34 Fan Heatsink Power and Signal Specifications ...............................................................98
35 TMA Power and Signal Specifications ......................................................................... 106
36 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors ............ 109

6 Datasheet
Revision HistoryRevision History

Revision
Description Date
Number

-001 • Initial release December 2005

-002 • Added specifications for Intel Pentium D processors 950, 940, 930, and 920 January 2006

• Added specifications for Intel Pentium processor Extreme Edition 965

-003 • Updated Table 2-13. March 2006
• Updated Figures 3-5 and 3-6.

-004 • Added specifications for Intel Pentium D processor 960 May 2006

• Added specifications for Intel Pentium D processors 945 and 915.

• Added specifications for the Intel Pentium D processors 960 for 775_VR_CONFIG_05A
-005 July 2006
(Mainstream)
• Updated RTT specification in Table 16, “GTL+ Bus Voltage Definitions“.

-006 • Added specifications for Intel Pentium D processors 925 September 2006

-007 • Added specifications for Intel Pentium D processors 935 January 2007

§§

Datasheet 7
8 Datasheet
Intel® Pentium® D Processor 900 Sequence and Intel®
Pentium® Processor Extreme Edition 955, 965 Features

• Available at 3.46 GHz and 3.73 GHz (Intel • Enhanced branch prediction
Pentium processor Extreme Edition 955, 965
• Optimized for 32-bit applications running on
only)
advanced 32-bit operating systems
• Available at 3.60 GHz, 3.40 GHz, 3.20 GHz,
• Two 16-KB Level 1 data caches
3 GHz, and 2.80 GHz (Intel Pentium D
processor 900 sequence only) • Two 2 MB Advanced Transfer Caches (on-die,
® full-speed Level 2 (L2) cache) with 8-way
• Enhanced Intel Speedstep Technology
associativity and Error Correcting Code
(Intel Pentium D processor 900 sequence
(ECC)
only)
• 144 Streaming SIMD Extensions 2 (SSE2)
• Supports Intel® 64Φ architecture
instructions
• Supports Intel® Virtualization Technology
• 13 Streaming SIMD Extensions 3 (SSE3)
(Not on Pentium D processors 945, 925, and
instructions
915)
• Enhanced floating point and multimedia unit
• Supports Execute Disable Bit capability
for enhanced video, audio, encryption, and
• Binary compatible with applications running 3D performance
on previous members of the Intel
• Power Management capabilities
microprocessor line
• System Management mode
• Intel NetBurst® microarchitecture
• FSB frequency at 800 MHz (Pentium D • Multiple low-power states
processor 900 sequence only) • 8-way cache associativity provides improved
• FSB frequency at 1066 MHz (Pentium cache hit rate on load/store operations
processor Extreme Edition 955, 965 only) • 775-land Package
• Hyper-Pipelined Technology
• Advance Dynamic Execution
• Very deep out-of-order execution

The Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955,
965 deliver Intel's advanced, powerful processors for desktop PCs that are based on the Intel
NetBurst® microarchitecture. The processor is designed to deliver performance across applications
and usages where end-users can truly appreciate and experience the performance. These applications
include Internet audio and streaming video, image processing, video content creation, speech, 3D,
CAD, games, multimedia, and multitasking user environments.

Intel® 64Φ architecture enables the processor to execute operating systems and applications written
to take advantage of the Intel® 64 architecture. The processor supporting Enhanced Intel
Speedstep® technology allows tradeoffs to be made between performance and power consumption.

The Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 also include
the Execute Disable Bit capability. This feature, combined with a supported operating system, allows
memory to be marked as executable or non-executable.

The Pentium D processors 960, 950, 940, 930, and 920 and Pentium processor Extreme Edition 955,
965 support Intel® Virtualization Technology. Virtualization Technology provides silicon-based
functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve
on software-only solutions.

§§

Datasheet 9
10 Datasheet
Introduction

1 Introduction
The Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965 are Intel’s first desktop dual-core products on the 65 nm
process. The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology,
and plug into the LGA775 socket. The Pentium D processor 900 sequence and Pentium
processor Extreme Edition 955, 965, like the Intel® Pentium® D processor on 90 nm
process in the 775-land LGA package, use the Intel NetBurst® microarchitecture and
maintains the tradition of compatibly with IA-32 software.

Note: In this document, unless otherwise specified, the Intel® Pentium® D processor 900
sequence refers to Intel Pentium D processors 960, 950, 945, 940, 935, 930, 925, 920,
and 915.

Note: In this document the Intel Pentium D processor 900 sequence on 65 nm process in the
775-land LGA package and the Intel Pentium processor Extreme Edition 955, 965 on
65 nm process in the 775-land LGA package are referred to simply as “processor.”

The processor functions as two physical processors in one package. This allows a
duplication of execution resources to provide increased system responsiveness in
multitasking environments, and headroom for next generation multithreaded
applications and new usages.

The processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and
Streaming SIMD Extensions 3 (SSE3). Streaming SIMD Extensions 3 (SSE3) are 13
additional instructions that further extend the capabilities of Intel processor technology.
These new instructions enhance the performance of optimized applications for the
digital home such as video, image processing, and media compression technology.

The processor supports the Intel® 64 architecture as an enhancement to Intel's IA-32

architecture. This enhancement allows the processor to execute operating systems and
applications written to take advantage of the Intel 64 architecture. Further details on
the 64-bit extension architecture and programming model can be found in the Intel®
Extended Memory 64 Technology Software Developer Guide at http://
developer.intel.com/technology/64bitextensions/.

The processor’s Intel NetBurst® microarchitecture front side bus (FSB) uses a split-
transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The Intel
NetBurst microarchitecture FSB uses Source-Synchronous Transfer (SST) of address
and data to improve performance by transferring data four times per bus clock (4X
data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can
deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus
bandwidth of up to 6.4 GB/s (800 MHz FSB) or 8.5 GB/s (1066 MHz FSB).

Intel will enable support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.

The processor also includes the Execute Disable Bit capability. This feature, combined
with a supported operating system, allows memory to be marked as executable or non-
executable. If code attempts to run in non-executable memory the processor raises an
error to the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel® Architecture Software Developer's Manual for
more detailed information.

Datasheet 11
 Introduction

The Intel Pentium D processor 900 sequence supports Enhanced Intel® SpeedStep®
technology that allows trade-offs to be made between performance and power
consumptions. This may lower average power consumption (in conjunction with OS
support).

The Pentium D processors 960, 950, 940, 930, and 920, and the Pentium processor
Extreme Edition 955, 965 support Intel® Virtualization Technology. Intel Virtualization
Technology provides silicon-based functionality that works together with compatible
Virtual Machine Monitor (VMM) software to improve upon software-only solutions.
Because this virtualization hardware provides a new architecture upon which the
operating system can run directly, it removes the need for binary translation. Thus, it
helps eliminate associated performance overhead and vastly simplifies the design of
the VMM, in turn allowing VMMs to be written to common standards and to be more
robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel®
Architecture for more details.

The processor includes an address bus powerdown capability which removes power
from the address and data signals when the FSB is not in use. This feature is always
enabled on the processor.

1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:
• Intel® Pentium® processor Extreme Edition 955, 965 on 65 nm process in
the 775-land LGA package — Processor in the FC-LGA6 package with two 2 MB
L2 caches1.
• Intel® Pentium® D processor 900 sequence on 65 nm process in the 775-
land LGA package — Processor in the FC-LGA6 package with two 2 MB L2
caches1.
• Processor — For this document, the term processor is the generic term for the
Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme
Edition 955, 965.
• Keep-out zone — The area on or near the processor that system design can not
use.
• Intel® 945G/945GZ/945P/945PL Express chipsets — Chipset that supports
DDR2 memory technology for the processor.
• Intel® 955X Express chipset — Chipset that supports DDR2 memory technology
for the processor.

1. Total accessible size of L2 caches may vary by one cache line pair (128 bytes), depending on
usage and operating environment.

12 Datasheet
Introduction

• Intel® 975X Express chipset — Chipset that supports DDR2 memory technology
for the processor.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The processor mates with the system board through a surface
mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material), the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.

1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document.

Table 1. References

Document Location

http://www.intel.com/
Intel® Pentium® D Processor 900 Sequence and Intel® Pentium®
design/pentiumXE/
Processor Extreme Edition 955, 965 Specification Update
specupdt/310307.htm
Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme http://www.intel.com/
Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical design/pentiumXE/
Design Guidelines designex/306830.htm
http://intel.com/design/
Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and
Pentium4/guides/
Transportable LGA775 Socket
302356.htm
http://www.intel.com/
Intel® Virtualization Technology Specification for the IA-32 Intel®
technology/computing/
Architecture
vptech/index.htm
http://intel.com/design/
LGA775 Socket Mechanical Design Guide Pentium4/guides/
302666.htm
Balanced Technology Extended (BTX) System Design Guide www.formfactors.org

Datasheet 13
 Introduction

Table 1. References

Document Location

Intel® 64 and IA-32 Intel Architecture Software Developer's Manual

Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
http://www.intel.com/
Volume 2B: Instruction Set Reference, N-Z products/processor/
manuals/
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide

§§

14 Datasheet
Electrical Specifications

2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip
power distribution. All power lands must be connected to VCC, while all VSS lands must
be connected to a system ground plane. The processor VCC lands must be supplied by
the voltage determined by the Voltage IDentification (VID) lands.

Twenty-four (24) signals are denoted as VTT that provide termination for the front side
bus and power to the I/O buffers. A separate supply must be implemented for these
lands, that meets the VTT specifications outlined in Table 4.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of
the component.

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Additionally,
a sufficient quantity of low ESR ceramic capacitors are required in the socket cavity to
ensure proper high frequency noise suppression. Consult the Voltage Regulator-Down
(VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further
information.

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To insure compliance with the specifications, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution would consist of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors.

Datasheet 15
 Electrical Specifications

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775
Socket. The voltage set by the VID signals is the reference VR output voltage to be
delivered to the processor VCC pins (see Chapter 2.5.3 for VCC overshoot
specifications). Refer to Table 14 for the DC specifications for these signals. A minimum
voltage for each processor frequency is provided in Table 4.

Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 4. Refer to the Intel® Pentium® D
Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965
Specification Update for further details on specific valid core frequency and VID values
of the processor. Note that this differs from the VID employed by the processor during
a power management event (Enhanced Intel SpeedStep® technology or Enhanced
HALT State).

The processor uses 6 voltage identification signals, VID[5:0], to support automatic

selection of power supply voltages. Table 2 specifies the voltage level corresponding to
the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. See the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and
Transportable LGA775 Socket for further details.

The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 4 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 5 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in Table 4 and
Table 5. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop
and Transportable LGA775 Socket for further details.

16 Datasheet
Electrical Specifications

Table 2. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125
1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250
0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375
1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500
0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625
1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750
0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875
1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000
0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125
1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250
0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375
1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500
0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625
1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750
0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875
1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000
0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125
1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250
0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375
1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500
0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625
1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.4750
0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.4875
1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000
0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125
1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250
0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375
1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500
0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625
1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750
0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875
1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000

Datasheet 17
 Electrical Specifications

2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 7 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected; however, this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details see Table 16.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the motherboard.
Unused outputs may be terminated on the motherboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing.

All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor
that matches the nominal trace impedance.

The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8 – cannot be grouped with other TESTHI signals
• TESTHI9 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals

However, using boundary scan test will not be functional if these lands are connected
together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0]
lands should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a
value between 40 Ω and 60 Ω should be used.

18 Datasheet
Electrical Specifications

2.5 Voltage and Current Specification

2.5.1 Absolute Maximum and Minimum Ratings
Table 3 specifies absolute maximum and minimum ratings. Within functional operation
limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.

Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.

Table 3. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes1,2

VCC Core voltage with respect to VSS –0.3 1.55 V -

FSB termination voltage with
VTT –0.3 1.55 V -
respect to VSS
See See
TC Processor case temperature °C -
Chapter 5 Chapter 5
TSTORAGE 3, 4, 5
Processor storage temperature –40 85 °C
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be
satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive
a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-
term reliability of the device. For functional operation, refer to the processor case temperature specifications.
4. This rating applies to the processor and does not include any tray or packaging.
5. Failure to adhere to this specification can affect the long term reliability of the processor.

Datasheet 19
 Electrical Specifications

2.5.2 DC Voltage and Current Specification

Table 4. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes1, 2

3
VID Range VID 1.200 - 1.3375 V
Processor number VCC for 775_VR_CONFIG_05B
(Performance)

Extreme Edition 965 3.73 GHz

Extreme Edition 955 3.46 GHz
960 3.60 GHz
950 3.40 GHz
940 3.20 GHz Refer to Table 5 and
VCC 4, 5, 6
V
Processor number VCC for 775_VR_CONFIG_05A Figure 1
(Mainstream)

960 3.60 GHz

950/945 3.40 GHz
940/935 3.20 GHz
930/925 3.00 GHz
920/915 2.80 GHz
Processor number ICC for 775_VR_CONFIG_05B
(Performance)

Extreme Edition 965 3.73 GHz 125

— —
Extreme Edition 955 3.46 GHz 125
960 3.60 GHz 125
950 3.40 GHz 125
940 3.20 GHz 125
7
ICC A
Processor number ICC for 775_VR_CONFIG_05A
(Mainstream)

960 3.60 GHz 100

950/945 3.40 GHz — — 100
940/935 3.20 GHz 100
930/925 3.00 GHz 100
920/915 2.80 GHz 100

20 Datasheet
Electrical Specifications

Table 4. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes1, 2

Processor number ICC when PWRGOOD and

RESET# are active for
775_VR_CONFIG_05B
(Performance)

Extreme Edition 965 3.73 GHz — — 125

Extreme Edition 955 3.46 GHz 125
960 3.60 GHz 125
950 3.40 GHz 125
940 3.20 GHz 125
ICC_RESET 8
A
Processor number ICC when PWRGOOD and
RESET# are active for
775_VR_CONFIG_05A
(Mainstream)

960 3.60 GHz — — 100

950/945 3.40 GHz 100
940/935 3.20 GHz 100
930/925 3.00 GHz 100
920/915 2.80 GHz 100
Processor number ICC Stop-Grant for
775_VR_CONFIG_05B
(Performance)

Extreme Edition 965 3.73 GHz — — 70

Extreme Edition 955 3.46 GHz 70
960 3.60 GHz 70
950 3.40 GHz 70
940 3.20 GHz 70
9,10,11
ISGNT A
Processor number ICC Stop-Grant for
775_VR_CONFIG_05A
(Mainstream)

960 3.60 GHz — — 50

950/945 3.40 GHz 50
940/935 3.20 GHz 50
930/925 3.00 GHz 50
920/915 2.80 GHz 50

Datasheet 21
 Electrical Specifications

Table 4. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes1, 2

Processor number ICC Enhanced Auto Halt for

775_VR_CONFIG_05B
(Performance)

Extreme Edition 965 3.73 GHz — — 68

Extreme Edition 955 3.46 GHz 68
960 3.60 GHz 60
950 3.40 GHz 60
IENHANCED_ 940 3.20 GHz 60
10,11
A
AUTO_HALT Processor number ICC Enhanced Auto Halt for
775_VR_CONFIG_05A
(Mainstream)

960 3.60 GHz — — 48

950/945 3.40 GHz 48
940/935 3.20 GHz 48
930/925 3.00 GHz 48
920/915 2.80 GHz 48
12
ITCC ICC TCC active — — ICC A
FSB termination voltage 13, 14
VTT 1.14 1.20 1.26 V
(DC + AC specifications)
VTT_OUT_
LEFT and DC Current that may be drawn from VTT_OUT_LEFT and
— — 580 mA
VTT_OUT_ VTT_OUT_RIGHT per pin
RIGHT ICC
ITT 15, 16
Steady-state FSB termination current — — 4.5 A
15, 17
ITT_POWER-UP Power-up FSB termination current — — 7.5 A
ICC_VCCA ICC for PLL lands — — 70 mA
ICC_VCCIOPLL ICC for I/O PLL land — — 52 mA
ICC_GTLREF ICC for GTLREF — — 200 μA
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can
not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same
frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during
a power management event (Enhanced Intel SpeedStep technology or Enhanced HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required.
See Section 2.3 and Table 2 for more information.
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz
bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire
on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
6. Refer to Table 5 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not
be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
7. ICC_MAX specification is based on VCC Maximum loadline. Refer to Figure 1 for details.
8. ICC_RESET is specified while RESET# is active.
9. The current specified is also for AutoHALT State.
10.ISGNT and ICC_ENHANCED_AUTO_HALT are specified at VCC_TYP and TC = 50 °C.
11.These parameters are based on design characterization and are not tested.
12.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the
assertion of PROCHOT#) is the same as the maximum ICC for the processor.
13.VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.
14.Baseboard bandwidth is limited to 20 MHz.

22 Datasheet
Electrical Specifications

15. This is maximum total current drawn from VTT plane by only the processor. This specification does not include the
current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For
Desktop and Transportable LGA775 Socket to determine the total ITT drawn by the system.
16.This is a steady-state ITT current specification, which is applicable when both VTT and VCC are high.
17.This is a power-up peak current specification, which is applicable when VTT is high and VCC is low.

Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream)

and 775_VR_CONFIG_05B (Performance) Processors
Voltage Deviation from VID Setting (V)1, 2, 3, 4

ICC (A) Maximum Voltage Typical Voltage Minimum Voltage

1.5 mΩ 1.55 mΩ 1.6 mΩ
0 0.000 -0.019 -0.038
5 -0.008 -0.027 -0.046
10 -0.015 -0.035 -0.054
15 -0.023 -0.042 -0.062
20 -0.030 -0.050 -0.070
25 -0.038 -0.058 -0.078
30 -0.045 -0.066 -0.086
35 -0.053 -0.073 -0.094
40 -0.060 -0.081 -0.102
45 -0.068 -0.089 -0.110
50 -0.075 -0.097 -0.118
55 -0.083 -0.104 -0.126
60 -0.090 -0.112 -0.134
65 -0.098 -0.120 -0.142
70 -0.105 -0.128 -0.150
75 -0.113 -0.135 -0.158
80 -0.117 -0.140 -0.163
85 -0.128 -0.151 -0.174
90 -0.135 -0.159 -0.182
95 -0.143 -0.166 -0.190
100 -0.150 -0.174 -0.198
105 -0.158 -0.182 -0.206
110 -0.165 -0.190 -0.214
115 -0.173 -0.197 -0.222
120 -0.180 -0.205 -0.230
125 -0.188 -0.213 -0.238
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
as shown in Section 2.5.3.
2. This table is intended to aid in reading discrete points on Figure 1.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and
Transportable LGA775 Socket for socket loadline guidelines and VR implementation details.
4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

Datasheet 23
 Electrical Specifications

Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream)

and 775_VR_CONFIG_05B (Performance) Processors

Icc [A]
0 10 20 30 40 50 60 70 80 90 100 110 120
VID - 0.000

VID - 0.019

VID - 0.038 Vcc Maximum

VID - 0.057

VID - 0.076

VID - 0.095
Vcc [V]

Vcc Typical
VID - 0.114

VID - 0.133

Vcc Minimum
VID - 0.152

VID - 0.171

VID - 0.190

VID - 0.209

VID - 0.228

NOTES:
1. The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.5.3.
2. This loadline specification shows the deviation from the VID set point.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 10.1
Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines
and VR implementation details.

2.5.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 6. VCC Overshoot Specifications1,2

Symbol Parameter Min Max Unit Figure Note1,2

VOS_MAX Magnitude of VCC overshoot above VID — 0.050 V 2

Time duration of VCC overshoot above
TOS_MAX — 25 μs 2
VID
NOTES:
1. Adherence to these specifications for the processor is required to ensure reliable processor operation.
2. Consult the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket
for proper application of the overshoot specification.

24 Datasheet
Electrical Specifications

Figure 2. VCC Overshoot Example Waveform

Exam ple O vershoot W aveform

VID + 0.050 V OS

Voltage (V) VID

T OS

Tim e
T O S : O vershoot tim e above VID
V O S : O vershoot above VID

NOTES:
1. VOS is measured overshoot voltage.
2. TOS is measured time duration above VID.

2.5.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 6 when measured
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.

2.6 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 16 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.

Datasheet 25
 Electrical Specifications

2.6.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers that use GTLREF[1:0] as a reference level. In this
document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+
I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as
well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 7 identifies which signals are common clock, source synchronous,
and asynchronous.

Table 7. FSB Signal Groups (Sheet 1 of 2)

Signal Group Type Signals1

GTL+ Common Synchronous to

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
Clock Input BCLK[1:0]
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#,
GTL+ Common Synchronous to
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
Clock I/O BCLK[1:0]
MCERR#

Signals Associated Strobe

REQ[4:0]#, A[16:3]#3 ADSTB0#

3
GTL+ Source Synchronous to A[35:17]# ADSTB1#
Synchronous I/O assoc. strobe
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#

Synchronous to
GTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
BCLK[1:0]
GTL+ Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,
Input LINT1/NMI, SMI#, STPCLK#, PWRGOOD
GTL+ Asynchronous
FERR#/PBE#, IERR#, THERMTRIP#
Output
GTL+ Asynchronous
PROCHOT#
Input/Output
Synchronous to
TAP Input TCK, TDI, TMS, TRST#
TCK

26 Datasheet
Electrical Specifications

Table 7. FSB Signal Groups (Sheet 2 of 2)

Signal Group Type Signals1

Synchronous to
TAP Output TDO
TCK
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]2
VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,
GTLREF[1:0], COMP[7:6,5:4,3:2,1:0], RESERVED,
TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
Power/Other
VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#2,
VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0],
FCx, IMPSEL

NOTES:
1. Refer to Section 4.2 for signal descriptions.
2. In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3. The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
.

Table 8. Signal Characteristics

Signals with RTT Signals with No RTT

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
COMP[7:6, 5:4,3:2,1:0], FERR#/PBE#,
BINIT#, BNR#, BOOTSELECT1, BPRI#,
IERR#, IGNNE#, INIT#, ITP_CLK[1:0],
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
LINT0/INTR, LINT1/NMI, PWRGOOD,
DP[3:0]#, DRDY#, DSTBN[3:0]#,
RESET#, SKTOCC#, SMI#, STPCLK#, TDO,
DSTBP[3:0]#, FROCEPR#, HIT#, HITM#,
TESTHI[13:0], THERMDA, THERMDC,
LOCK#, MCERR#, MSID[1:0]1, PROCHOT#,
THERMTRIP#, VID[5:0], VTTPWRGD,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#, IMPSEL1
GTLREF[1:0], TCK, TDI, TMS, TRST#

Open Drain Signals2

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BR0#, TDO, VTT_SEL, LL_ID[1:0], FCx
NOTES:
1. These signals have a 500–5000 Ω pull-up to VTTrather than on-die termination.
2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

Table 9. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,

BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BOOTSELECT, VTTPWRGD, A20M#,
BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, IGNNE#, INIT#, MSID[1,0],
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, PWRGOOD1, SMI#, STPCLK#, TCK1,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, TDI1, TMS1, TRST#1
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 12 for more
information.

Datasheet 27
 Electrical Specifications

2.6.2 GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, PWRGOOD, SMI#, and STPCLK#
use CMOS input buffers. All of these signals follow the same DC requirements as GTL+
signals; however, the outputs are not actively driven high (during a logical 0-to-1
transition) by the processor. These signals do not have setup or hold time specifications
in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at

least six BCLKs in order for the processor to recognize the proper signal state. See
Section 2.6.3 for the DC specifications for the GTL+ Asynchronous signal groups. See
Section 6.2 for additional timing requirements for entering and leaving the low power
states.

2.6.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 10. GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
2, 3
VIL Input Low Voltage 0.0 GTLREF – (0.10 * VTT) V
4, 5, 3
VIH Input High Voltage GTLREF + (0.10 * VTT) VTT V
5, 3
VOH Output High Voltage — VTT V
VTT_MAX/
IOL Output Low Current N/A A -
[(0.50*RTT_MIN)+(RON_MIN)]
Input Leakage 6
ILI N/A ± 200 µA
Current
Output Leakage 7
ILO N/A ± 200 µA
Current
Buffer On
RON 6 12 W
Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The VTT referred to in these specifications is the instantaneous VTT.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality
specifications.
6. Leakage to VSS with land held at VTT.
7. Leakage to VTT with land held at 300 mV.

28 Datasheet
Electrical Specifications

Table 11. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1
2, 3
VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) V
VIH Input High Voltage VTT/2 + (0.10 * VTT) VTT V 4, 5, 6, 3

VOH Output High Voltage 0.90*VTT VTT V 7, 5, 6

VTT/ 8
IOL Output Low Current — A
[(0.50*RTT_MIN)+(RON_MIN)]
9
ILI Input Leakage Current N/A ± 200 µA
Output Leakage 10
ILO N/A ± 200 µA
Current
RON Buffer On Resistance 6 12 W
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals VIH = GTLREF + (0.10 * VTT) and
VIL= GTLREF – (0.10 * VTT).
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality
specifications.
6. The VTT referred to in these specifications refers to instantaneous VTT.
7. All outputs are open drain.
8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
9. Leakage to VSS with land held at VTT.
10.Leakage to VTT with land held at 300 mV.
.

Table 12. TAP Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1, 2

3, 4
VHYS Input Hysteresis 120 396 mV
PWRGOOD Input low-
0.5 * (VTT + VHYS_MIN 0.5 * (VTT + VHYS_MAX 5, 6
to-high threshold V
+ 0.24) + 0.24)
VT+ voltage
TAP Input low-to-high 5
0.5 * (VTT + VHYS_MIN) 0.5 * (VTT + VHYS_MAX) V
threshold voltage
PWRGOOD Input high- 5
0.4 * VTT 0.6 * VTT V
to-low threshold voltage
VT-
TAP Input high-to-low 5
0.5 * (VTT – VHYS_MAX) 0.5 * (VTT – VHYS_MIN) V
threshold voltage
5
VOH Output High Voltage N/A VTT V
IOL Output Low Current — 22.2 mA 7

8
ILI Input Leakage Current — ± 200 µA
3
ILO Output Leakage Current — ± 200 µA
RON Buffer On Resistance 6 12 W
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
3. Leakage to VTT with land held at 300 mV.
4. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.
5. The VTT referred to in these specifications refers to instantaneous VTT.
6. 0.24 V is defined at 20% of nominal VTT of 1.2 V.
7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
8. Leakage to Vss with land held at VTT.

Datasheet 29
 Electrical Specifications

Table 13. VTTPWRGD DC Specifications

Symbol Parameter Min Typ Max Unit

VIL Input Low Voltage — — 0.3 V

VIH Input High Voltage 0.9 — - V

Table 14. BSEL[2:0] and VID[5:0] DC Specifications

Symbol Parameter Max Unit Notes1
RON BSEL[2:], VID[5:0] Buffer On Resistance 120 W 2

2,3
IOL Max Land Current 2.4 mA
IOH Output High Current 460 µA 2,3

VTOL Voltage Tolerance 1.05*VTT V 4

NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. IOL is measured at 0.10*VTT. IOH is measured at 0.90*VTT.
4. Refer to the appropriate platform design guide for implementation details.

Table 15. MSID [1,0] and BOOTSELECT DC Specifications

Symbol Parameter Min Typ Max Unit Notes1

VIL Input Low Voltage — — 0.24 V

VIH Input High Voltage 0.96 — — V
NOTES:
1. These parameters are not tested and are based on design simulations.

30 Datasheet
Electrical Specifications

2.6.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 8 for details on which GTL+ signals do not include on-die
termination.

Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 16 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 16. GTL+ Bus Voltage Definitions
Symbol Parameter Min Typ Max Units Notes1
GTLREF_PU GTLREF pull up resistor 124 * 0.99 124 124 * 1.01 W 2

2
GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 W
On die pull-up for 3
RPULLUP 500 — 5000 W
BOOTSELECT signal
60 Ω Platform Termination 4
51 60 66 W
Resistance
RTT
50 Ω Platform Termination
39 50 55 W 3
Resistance
60 Ω Platform Termination 5
59.8 60.4 61 W
COMP Resistance
COMP[7:6]
50 Ω Platform Termination 5
49.9 * 0.99 49.9 49.9 * 1.01 W
COMP Resistance
60 Ω Platform Termination 5
59.8 60.4 61 W
COMP Resistance
COMP[5:4]
50 Ω Platform Termination 5
49.9 * 0.99 49.9 49.9 * 1.01 W
COMP Resistance
60 Ω Platform Termination 5
59.8 60.4 61 W
COMP Resistance
COMP[3:2]
50 Ω Platform Termination 5
49.9 * 0.99 49.9 49.9 * 1.01 W
COMP Resistance
60 Ω Platform Termination 5
59.8 60.4 61 W
COMP Resistance
COMP[1:0]
50 Ω Platform Termination 5
49.9 * 0.99 49.9 49.9 * 1.01 W
COMP Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLREF
land). Refer to the applicable platform design guide for additional implementation details.
3. These pull-ups are to VTT.
4. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver. The IMPSEL pin is used to
select a 50 Ω or 60 Ω buffer and RTT value.
5. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] resistors are to VSS.
COMP[7:4] resistors are to VTT.

Datasheet 31
 Electrical Specifications

2.7 Clock Specifications

2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 17 for the processor supported
ratios.

The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.

Table 17. Core Frequency to FSB Multiplier Configuration

Multiplication of Core Frequency Core Frequency

System Core Frequency to (200 MHz BCLK/ (266 MHz BCLK/ Notes1, 2

FSB Frequency 800 MHz FSB) 1066 MHz FSB)

1/12 2.40 GHz 3.20 GHz -

1/13 2.60 GHz 3.46 GHz -
1/14 2.80 GHz 3.73 GHz -
1/15 3 GHz 4 GHz -
1/16 3.20 GHz 4.26 GHz -
1/17 3.40 GHz 4.53 GHz -
1/18 3.60 GHz 4.80 GHz -
1/19 3.80 GHz 5.06 GHz -
1/20 4 GHz RESERVED -
1/21 4.20 GHz RESERVED -
1/22 4.40 GHz RESERVED -
1/23 4.60 GHz RESERVED -
1/24 4.80 GHz RESERVED -
1/25 5 GHz RESERVED -
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.

2.7.2 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 18 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.

The Pentium D processor 900 sequence operates at 800 MHz FSB frequency (selected
by a 200 MHz BCLK[1:0] frequency). The Pentium processor Extreme Edition 955, 965
operate at 1066 MHz FSB frequency (selected by a 266 MHz BCLK[1:0] frequency).

32 Datasheet
Electrical Specifications

Table 18. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L 266 MHz
L L H RESERVED
L H H RESERVED
L H L 200 MHz
H H L RESERVED
H H H RESERVED
H L H RESERVED
H L L RESERVED

2.7.3 Phase Lock Loop (PLL) and Filter

VCCA and VCCIOPLL are power sources required by the PLL clock generators for the
processor silicon. Since these PLLs are analog, they require low noise power supplies
for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings
as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from VTT.

The AC low-pass requirements, with input at VTT are as follows:

• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 3.

Datasheet 33
 Electrical Specifications

Figure 3. Phase Lock Loop (PLL) Filter Requirements

0.2 dB
0 dB
–0.5 dB

Forbidden
Zone

Forbidden
Zone
–28 dB

–34 dB

DC 1 Hz fpeak 1 MHz 66 MHz fcore

Passband High
Frequency
Band

NOTES:
1. Diagram not to scale.
2. No specification for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
4. fcore represents the maximum core frequency supported by the platform.

34 Datasheet
Electrical Specifications

2.7.4 BCLK[1:0] Specifications

Table 19. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Notes1
VL Input Low Voltage -0.150 0.000 N/A V -
VH Input High Voltage 0.660 0.700 0.850 V -
2, 3
VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V
0.250 + 0.550 + 3, 4, 5
VCROSS(rel) Relative Crossing Point N/A V
0.5(VHavg – 0.700) 0.5(VHavg – 0.700)
ΔVCROSS Range of Crossing Points N/A N/A 0.140 V -
6
VOS Overshoot N/A N/A VH + 0.3 V
VUS Undershoot -0.300 N/A N/A V 7

VRBM Ringback Margin 0.200 N/A N/A V 8

9
VTM Threshold Region VCROSS – 0.100 N/A VCROSS + 0.100 V
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of
BCLK1.
3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
4. VHavg is the statistical average of the VH measured by the oscilloscope.
5. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
6. Overshoot is defined as the absolute value of the maximum voltage.
7. Undershoot is defined as the absolute value of the minimum voltage.
8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the
maximum Falling Edge Ringback.
9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver
switches. It includes input threshold hysteresis.

§§

Datasheet 35
 Electrical Specifications

36 Datasheet
Package Mechanical Specifications

3 Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 4 shows a sketch of
the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 4 include the following:

• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors

Figure 4. Processor Package Assembly Sketch

Core (die) TIM

IHS
Substrate

Capacitors

LGA775 Socket
System Board

NOTE:
1. Socket and motherboard are included for reference and are not part of processor package.

3.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 5, Figure 6 and Figure 7. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal/Mechanical
Design Guidelines.

Datasheet 37
 Package Mechanical Specifications

Figure 5. Processor Package Drawing Sheet 1 of 3

38 Datasheet
Package Mechanical Specifications

Figure 6. Processor Package Drawing Sheet 2 of 3

Datasheet 39
 Package Mechanical Specifications

Figure 7. Processor Package Drawing Sheet 3 of 3

40 Datasheet
Package Mechanical Specifications

3.2 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 5 and Figure 6 for keep-out
zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.

3.3 Package Loading Specifications

Table 20 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.

Table 20. Processor Loading Specifications

Parameter Minimum Maximum Notes

1, 2, 3
Static 80 N [17 lbf] 311 N [70 lbf]
1, 3, 4
Dynamic — 756 N [170 lbf]
NOTES:
1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the
minimum specified load on the processor package.
3. These specifications are based on limited testing for design characterization. Loading limits are for the
package only and do not include the limits of the processor socket.
4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

3.4 Package Handling Guidelines

Table 21 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 21. Package Handling Guidelines
Parameter Maximum Recommended Notes

Shear 311 N [70 lbf] 1, 2

Tensile 111 N [25 lbf] 2, 3

2, 4
Torque 3.95 N-m [35 lbf-in]
NOTES:
1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. These guidelines are based on limited testing for design characterization.
3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.

3.5 Package Insertion Specifications

The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.

Datasheet 41
 Package Mechanical Specifications

3.6 Processor Mass Specification

The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.

3.7 Processor Materials

Table 22 lists some of the package components and associated materials.

Table 22. Processor Materials

Component Material

Integrated Heat Spreader

Nickel Plated Copper
(IHS)
Substrate Fiber Reinforced Resin
Substrate Lands Gold Plated Copper

3.8 Processor Markings

Figure 8 and Figure 9 show the topside markings on the processor. This diagram is to
aid in the identification of the processor.
Figure 8. Processor Top-Side Markings Example (Intel® Pentium® D Processor 900
Sequence)

Brand
Processor Number/ S-Spec/
Country of Assy
INTEL M ©'05
Frequency/L2 Cache/Bus/ PENTIUM® D
775_VR_CONFIG_05x 960 SLxxx [COO]
FPO 3.60GHZ/4M/800/05B
[FPO] e4
Pb-free 2LI Symbol Unique Unit
Identifier
2-D Matrix Mark ATPO Serial #
ATPO
S/N

42 Datasheet
Package Mechanical Specifications

Figure 9. Processor Top-Side Markings Example (Intel® Pentium® Processor Extreme

Edition 955, 965)

Brand
Processor Number/ S-Spec/
Country of Assy INTEL m © ‘05
Frequency/L2 Cache/Bus/ XXXXXXXX
775_VR_CONFIG_05x 965 SLxxx [COO]
3.73GHZ/4M/1066/05B
FPO
[FPO] e4

Pb-free 2LI Symbol Unique Unit

Identifier
2-D Matrix Mark ATPO Serial #
ATPO
S/N

3.9 Processor Land Coordinates

Figure 10 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.

Datasheet 43
 Package Mechanical Specifications

Figure 10. Processor Land Coordinates and Quadrants (Top View)

VCC/VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

AN AN
AM AM
AL AL
AK AK
AJ AJ
AH AH
AG AG
AF AF
AE AE
AD AD
AC AC
AB AB
Address/
AA AA Common Clock
Y
Socket 775 Quadrants
Y Async
W W
V
U
Top View V
U
T T
R R
P P
N N
M M
L L
K K
J J
H H
G G
F F
E E
D D
C C
B B
A A

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

VTT / Clocks Data

§§

44 Datasheet
Land Listing and Signal Descriptions

4 Land Listing and Signal

Descriptions
This chapter provides the processor land assignment and signal descriptions.

4.1 Processor Land Assignments

This section contains the land listings for the processor. The land-out footprint is shown
in Figure 11 and Figure 12. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 23 is a listing of all processor lands ordered alphabetically by land
(signal) name. Table 24 is also a listing of all processor lands; the ordering is by land
number.

Datasheet 45
 Land Listing and Signal Descriptions

Figure 11. land-out Diagram (Top View – Left Side)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

AN
VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC

AD VCC VCC VCC VCC VCC VCC VCC VCC

AC VCC VCC VCC VCC VCC VCC VCC VCC

AB VSS VSS VSS VSS VSS VSS VSS VSS

AA VSS VSS VSS VSS VSS VSS VSS VSS

Y VCC VCC VCC VCC VCC VCC VCC VCC

W VCC VCC VCC VCC VCC VCC VCC VCC

V VSS VSS VSS VSS VSS VSS VSS VSS

U VCC VCC VCC VCC VCC VCC VCC VCC

T VCC VCC VCC VCC VCC VCC VCC VCC

R VSS VSS VSS VSS VSS VSS VSS VSS

P VSS VSS VSS VSS VSS VSS VSS VSS

N VCC VCC VCC VCC VCC VCC VCC VCC

M VCC VCC VCC VCC VCC VCC VCC VCC

L VSS VSS VSS VSS VSS VSS VSS VSS

K VCC VCC VCC VCC VCC VCC VCC VCC

J
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DP3# DP0# VCC

H
BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DP2# DP1#

G BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31#

F RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30#

E VSS VSS VSS VSS VSS FC10 RSVD D45# D42# VSS D40# D39# VSS D34# D33#

D VTT VTT VTT VTT VTT VTT VSS F9 D46# VSS D48# DBI2# VSS D49# RSVD VSS

VCCIO
C VTT VTT VTT VTT VTT VTT VSS VSS D58# DBI3# VSS D54# DSTBP3# VSS D51#
PLL

B VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53#

A VTT VTT VTT VTT VTT VTT VSS VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

46 Datasheet
Land Listing and Signal Descriptions

Figure 12. land-out Diagram (Top View – Right Side)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

VSS_MB_ VCC_MB_ VSS_ VCC_

VCC VSS VCC VCC VSS VCC VCC FC16 VSS VSS AN
REGULATION REGULATION SENSE SENSE

VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 VSS VID2 VID0 VSS AM

VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VSS PROCHOT# THERMDA AL

VCC VSS VCC VCC VSS VCC VCC VSS FORCEPR# VSS VID4 ITP_CLK0 VSS THERMDC AK

VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS ITP_CLK1 BPM0# BPM1# AJ

VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS AH

VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST# AG

VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO AF

VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD COMP7 VSS TCK AE

VCC VSS A22# ADSTB1# VSS BINIT# BPM2# TDI AD

VCC VSS VSS A25# RSVD VSS DBR# TMS AC

VCC VSS A17# A24# A26# MCERR# IERR# VSS AB

VTT_OUT_
VCC VSS VSS A23# A21# VSS LL_ID1 AA
RIGHT

BOOT
VCC VSS A19# VSS A20# COMP6 VSS Y
SELECT

VCC VSS A18# A16# VSS TESTHI1 TESTHI12 MSID0 W

VCC VSS VSS A14# A15# VSS LL_ID0 MSID1 V

VCC VSS A10# A12# A13# AP1# AP0# VSS U

VCC VSS VSS A9# A11# VSS COMP5 COMP1 T

FERR#/
VCC VSS ADSTB0# VSS A8# VSS COMP3 R
PBE#

VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11 P

VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD N

VCC VSS REQ2# A5# A7# STPCLK# THERMTRIP# VSS M

VCC VSS VSS A3# A6# VSS TESTHI13 LINT1 L

VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0 K

VTT_OUT_
VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS FC22 COMP4 J
LEFT

H
VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 RSP# VSS GTLREF1 GTLREF0

D29# D27# DSTBN1# DBI1# RSVD D16# BPRI# DEFER# RSVD FC7 TESTHI9 TESTHI8 COMP2 VSS G

D28# VSS D24# D23# VSS D18# D17# VSS IMPSEL RS1# VSS BR0# FC5 F

VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD FC20 HITM# TRDY# VSS E

RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD D

C
D52# VSS D14# D11# VSS RSVD DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY#

VSS FC19 D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# VSS B

D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS A

14 13 12 11 10 9 8 7 6 5 4 3 2 1

Datasheet 47
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

A10# U6 Source Synch Input/Output ADSTB1# AD5 Source Synch Input/Output

A11# T4 Source Synch Input/Output AP0# U2 Common Clock Input/Output
A12# U5 Source Synch Input/Output AP1# U3 Common Clock Input/Output
A13# U4 Source Synch Input/Output BCLK0 F28 Clock Input
A14# V5 Source Synch Input/Output BCLK1 G28 Clock Input
A15# V4 Source Synch Input/Output BINIT# AD3 Common Clock Input/Output
A16# W5 Source Synch Input/Output BNR# C2 Common Clock Input/Output
A17# AB6 Source Synch Input/Output BOOTSELECT Y1 Power/Other Input
A18# W6 Source Synch Input/Output BPM0# AJ2 Common Clock Input/Output
A19# Y6 Source Synch Input/Output BPM1# AJ1 Common Clock Input/Output
A20# Y4 Source Synch Input/Output BPM2# AD2 Common Clock Input/Output
A20M# K3 Asynch GTL+ Input BPM3# AG2 Common Clock Input/Output
A21# AA4 Source Synch Input/Output BPM4# AF2 Common Clock Input/Output
A22# AD6 Source Synch Input/Output BPM5# AG3 Common Clock Input/Output
A23# AA5 Source Synch Input/Output BPRI# G8 Common Clock Input
A24# AB5 Source Synch Input/Output BR0# F3 Common Clock Input/Output
A25# AC5 Source Synch Input/Output BSEL0 G29 Power/Other Output
A26# AB4 Source Synch Input/Output BSEL1 H30 Power/Other Output
A27# AF5 Source Synch Input/Output BSEL2 G30 Power/Other Output
A28# AF4 Source Synch Input/Output COMP0 A13 Power/Other Input
A29# AG6 Source Synch Input/Output COMP1 T1 Power/Other Input
A3# L5 Source Synch Input/Output COMP2 G2 Power/Other Input
A30# AG4 Source Synch Input/Output COMP3 R1 Power/Other Input
A31# AG5 Source Synch Input/Output COMP4 J2 Power/Other Input
A32# AH4 Source Synch Input/Output COMP5 T2 Power/Other Input
A33# AH5 Source Synch Input/Output COMP6 Y3 Power/Other Input
A34# AJ5 Source Synch Input/Output COMP7 AE3 Power/Other Input
A35# AJ6 Source Synch Input/Output D0# B4 Source Synch Input/Output
A4# P6 Source Synch Input/Output D1# C5 Source Synch Input/Output
A5# M5 Source Synch Input/Output D10# B10 Source Synch Input/Output
A6# L4 Source Synch Input/Output D11# C11 Source Synch Input/Output
A7# M4 Source Synch Input/Output D12# D8 Source Synch Input/Output
A8# R4 Source Synch Input/Output D13# B12 Source Synch Input/Output
A9# T5 Source Synch Input/Output D14# C12 Source Synch Input/Output
ADS# D2 Common Clock Input/Output D15# D11 Source Synch Input/Output
ADSTB0# R6 Source Synch Input/Output D16# G9 Source Synch Input/Output

48 Datasheet
Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

D17# F8 Source Synch Input/Output D5# B6 Source Synch Input/Output

D18# F9 Source Synch Input/Output D50# A14 Source Synch Input/Output
D19# E9 Source Synch Input/Output D51# C15 Source Synch Input/Output
D2# A4 Source Synch Input/Output D52# C14 Source Synch Input/Output
D20# D7 Source Synch Input/Output D53# B15 Source Synch Input/Output
D21# E10 Source Synch Input/Output D54# C18 Source Synch Input/Output
D22# D10 Source Synch Input/Output D55# B16 Source Synch Input/Output
D23# F11 Source Synch Input/Output D56# A17 Source Synch Input/Output
D24# F12 Source Synch Input/Output D57# B18 Source Synch Input/Output
D25# D13 Source Synch Input/Output D58# C21 Source Synch Input/Output
D26# E13 Source Synch Input/Output D59# B21 Source Synch Input/Output
D27# G13 Source Synch Input/Output D6# B7 Source Synch Input/Output
D28# F14 Source Synch Input/Output D60# B19 Source Synch Input/Output
D29# G14 Source Synch Input/Output D61# A19 Source Synch Input/Output
D3# C6 Source Synch Input/Output D62# A22 Source Synch Input/Output
D30# F15 Source Synch Input/Output D63# B22 Source Synch Input/Output
D31# G15 Source Synch Input/Output D7# A7 Source Synch Input/Output
D32# G16 Source Synch Input/Output D8# A10 Source Synch Input/Output
D33# E15 Source Synch Input/Output D9# A11 Source Synch Input/Output
D34# E16 Source Synch Input/Output DBI0# A8 Source Synch Input/Output
D35# G18 Source Synch Input/Output DBI1# G11 Source Synch Input/Output
D36# G17 Source Synch Input/Output DBI2# D19 Source Synch Input/Output
D37# F17 Source Synch Input/Output DBI3# C20 Source Synch Input/Output
D38# F18 Source Synch Input/Output DBR# AC2 Power/Other Output
D39# E18 Source Synch Input/Output DBSY# B2 Common Clock Input/Output
D4# A5 Source Synch Input/Output DEFER# G7 Common Clock Input
D40# E19 Source Synch Input/Output DP0# J16 Common Clock Input/Output
D41# F20 Source Synch Input/Output DP1# H15 Common Clock Input/Output
D42# E21 Source Synch Input/Output DP2# H16 Common Clock Input/Output
D43# F21 Source Synch Input/Output DP3# J17 Common Clock Input/Output
D44# G21 Source Synch Input/Output DRDY# C1 Common Clock Input/Output
D45# E22 Source Synch Input/Output DSTBN0# C8 Source Synch Input/Output
D46# D22 Source Synch Input/Output DSTBN1# G12 Source Synch Input/Output
D47# G22 Source Synch Input/Output DSTBN2# G20 Source Synch Input/Output
D48# D20 Source Synch Input/Output DSTBN3# A16 Source Synch Input/Output
D49# D17 Source Synch Input/Output DSTBP0# B9 Source Synch Input/Output

Datasheet 49
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

DSTBP1# E12 Source Synch Input/Output REQ0# K4 Source Synch Input/Output

DSTBP2# G19 Source Synch Input/Output REQ1# J5 Source Synch Input/Output
DSTBP3# C17 Source Synch Input/Output REQ2# M6 Source Synch Input/Output
FC11 AM5 Power/Other Output REQ3# K6 Source Synch Input/Output
FC12 AM7 Power/Other Output REQ4# J6 Source Synch Input/Output
FC15 H29 Power/Other Output RESERVED A20
FC16 AN7 Power/Other Output RESERVED AC4
FC10 E24 Power/Other Output RESERVED AE4
FC5 F2 Power/Other Output RESERVED AE6
FC19 B13 Power/Other Output RESERVED AH2
FC22 J3 Power/Other Output RESERVED C9
FC9 D23 Power/Other Output RESERVED D1
FC7 G5 Power/Other Output RESERVED D14
FC20 E5 Power/Other Output RESERVED D16
FORCEPR# AK6 Asynch GTL+ Input RESERVED E23
FERR#/PBE# R3 Asynch GTL+ Output RESERVED E6
GTLREF0 H1 Power/Other Input RESERVED E7
GTLREF1 H2 Power/Other Input RESERVED F23
HIT# D4 Common Clock Input/Output RESERVED F29
HITM# E4 Common Clock Input/Output RESERVED G10
IERR# AB2 Asynch GTL+ Output RESERVED G6
IGNNE# N2 Asynch GTL+ Input RESERVED N4
IMPSEL F6 Power/Other Input RESERVED N5
INIT# P3 Asynch GTL+ Input RESERVED P5
ITP_CLK0 AK3 TAP Input RESET# G23 Common Clock Input
ITP_CLK1 AJ3 TAP Input RS0# B3 Common Clock Input
LINT0 K1 Asynch GTL+ Input RS1# F5 Common Clock Input
LINT1 L1 Asynch GTL+ Input RS2# A3 Common Clock Input
LL_ID0 V2 Power/Other Output RSP# H4 Common Clock Input
LL_ID1 AA2 Power/Other Output SKTOCC# AE8 Power/Other Output
LOCK# C3 Common Clock Input/Output SMI# P2 Asynch GTL+ Input
MCERR# AB3 Common Clock Input/Output STPCLK# M3 Asynch GTL+ Input
MSID0 W1 Power/Other Output TCK AE1 TAP Input
MSID1 V1 Power/Other Output TDI AD1 TAP Input
PROCHOT# AL2 Asynch GTL+ Input/Output TDO AF1 TAP Output
PWRGOOD N1 Power/Other Input TESTHI0 F26 Power/Other Input

50 Datasheet
Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

TESTHI1 W3 Power/Other Input VCC AD29 Power/Other

TESTHI10 H5 Power/Other Input VCC AD30 Power/Other
TESTHI11 P1 Power/Other Input VCC AD8 Power/Other
TESTHI12 W2 Power/Other Input VCC AE11 Power/Other
TESTHI13 L2 Asynch GTL+ Input VCC AE12 Power/Other
TESTHI2 F25 Power/Other Input VCC AE14 Power/Other
TESTHI3 G25 Power/Other Input VCC AE15 Power/Other
TESTHI4 G27 Power/Other Input VCC AE18 Power/Other
TESTHI5 G26 Power/Other Input VCC AE19 Power/Other
TESTHI6 G24 Power/Other Input VCC AE21 Power/Other
TESTHI7 F24 Power/Other Input VCC AE22 Power/Other
TESTHI8 G3 Power/Other Input VCC AE23 Power/Other
TESTHI9 G4 Power/Other Input VCC AE9 Power/Other
THERMDA AL1 Power/Other VCC AF11 Power/Other
THERMDC AK1 Power/Other VCC AF12 Power/Other
THERMTRIP# M2 Asynch GTL+ Output VCC AF14 Power/Other
TMS AC1 TAP Input VCC AF15 Power/Other
TRDY# E3 Common Clock Input VCC AF18 Power/Other
TRST# AG1 TAP Input VCC AF19 Power/Other
VCC AA8 Power/Other VCC AF21 Power/Other
VCC AB8 Power/Other VCC AF22 Power/Other
VCC AC23 Power/Other VCC AF8 Power/Other
VCC AC24 Power/Other VCC AF9 Power/Other
VCC AC25 Power/Other VCC AG11 Power/Other
VCC AC26 Power/Other VCC AG12 Power/Other
VCC AC27 Power/Other VCC AG14 Power/Other
VCC AC28 Power/Other VCC AG15 Power/Other
VCC AC29 Power/Other VCC AG18 Power/Other
VCC AC30 Power/Other VCC AG19 Power/Other
VCC AC8 Power/Other VCC AG21 Power/Other
VCC AD23 Power/Other VCC AG22 Power/Other
VCC AD24 Power/Other VCC AG25 Power/Other
VCC AD25 Power/Other VCC AG26 Power/Other
VCC AD26 Power/Other VCC AG27 Power/Other
VCC AD27 Power/Other VCC AG28 Power/Other
VCC AD28 Power/Other VCC AG29 Power/Other

Datasheet 51
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VCC AG30 Power/Other VCC AK19 Power/Other

VCC AG8 Power/Other VCC AK21 Power/Other
VCC AG9 Power/Other VCC AK22 Power/Other
VCC AH11 Power/Other VCC AK25 Power/Other
VCC AH12 Power/Other VCC AK26 Power/Other
VCC AH14 Power/Other VCC AK8 Power/Other
VCC AH15 Power/Other VCC AK9 Power/Other
VCC AH18 Power/Other VCC AL11 Power/Other
VCC AH19 Power/Other VCC AL12 Power/Other
VCC AH21 Power/Other VCC AL14 Power/Other
VCC AH22 Power/Other VCC AL15 Power/Other
VCC AH25 Power/Other VCC AL18 Power/Other
VCC AH26 Power/Other VCC AL19 Power/Other
VCC AH27 Power/Other VCC AL21 Power/Other
VCC AH28 Power/Other VCC AL22 Power/Other
VCC AH29 Power/Other VCC AL25 Power/Other
VCC AH30 Power/Other VCC AL26 Power/Other
VCC AH8 Power/Other VCC AL29 Power/Other
VCC AH9 Power/Other VCC AL30 Power/Other
VCC AJ11 Power/Other VCC AL8 Power/Other
VCC AJ12 Power/Other VCC AL9 Power/Other
VCC AJ14 Power/Other VCC AM11 Power/Other
VCC AJ15 Power/Other VCC AM12 Power/Other
VCC AJ18 Power/Other VCC AM14 Power/Other
VCC AJ19 Power/Other VCC AM15 Power/Other
VCC AJ21 Power/Other VCC AM18 Power/Other
VCC AJ22 Power/Other VCC AM19 Power/Other
VCC AJ25 Power/Other VCC AM21 Power/Other
VCC AJ26 Power/Other VCC AM22 Power/Other
VCC AJ8 Power/Other VCC AM25 Power/Other
VCC AJ9 Power/Other VCC AM26 Power/Other
VCC AK11 Power/Other VCC AM29 Power/Other
VCC AK12 Power/Other VCC AM30 Power/Other
VCC AK14 Power/Other VCC AM8 Power/Other
VCC AK15 Power/Other VCC AM9 Power/Other
VCC AK18 Power/Other VCC AN11 Power/Other

52 Datasheet
Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VCC AN12 Power/Other VCC K25 Power/Other

VCC AN14 Power/Other VCC K26 Power/Other
VCC AN15 Power/Other VCC K27 Power/Other
VCC AN18 Power/Other VCC K28 Power/Other
VCC AN19 Power/Other VCC K29 Power/Other
VCC AN21 Power/Other VCC K30 Power/Other
VCC AN22 Power/Other VCC K8 Power/Other
VCC AN25 Power/Other VCC L8 Power/Other
VCC AN26 Power/Other VCC M23 Power/Other
VCC AN29 Power/Other VCC M24 Power/Other
VCC AN30 Power/Other VCC M25 Power/Other
VCC AN8 Power/Other VCC M26 Power/Other
VCC AN9 Power/Other VCC M27 Power/Other
VCC J10 Power/Other VCC M28 Power/Other
VCC J11 Power/Other VCC M29 Power/Other
VCC J12 Power/Other VCC M30 Power/Other
VCC J13 Power/Other VCC M8 Power/Other
VCC J14 Power/Other VCC N23 Power/Other
VCC J15 Power/Other VCC N24 Power/Other
VCC J18 Power/Other VCC N25 Power/Other
VCC J19 Power/Other VCC N26 Power/Other
VCC J20 Power/Other VCC N27 Power/Other
VCC J21 Power/Other VCC N28 Power/Other
VCC J22 Power/Other VCC N29 Power/Other
VCC J23 Power/Other VCC N30 Power/Other
VCC J24 Power/Other VCC N8 Power/Other
VCC J25 Power/Other VCC P8 Power/Other
VCC J26 Power/Other VCC R8 Power/Other
VCC J27 Power/Other VCC T23 Power/Other
VCC J28 Power/Other VCC T24 Power/Other
VCC J29 Power/Other VCC T25 Power/Other
VCC J30 Power/Other VCC T26 Power/Other
VCC J8 Power/Other VCC T27 Power/Other
VCC J9 Power/Other VCC T28 Power/Other
VCC K23 Power/Other VCC T29 Power/Other
VCC K24 Power/Other VCC T30 Power/Other

Datasheet 53
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VCC T8 Power/Other VID3 AL6 Power/Other Output

VCC U23 Power/Other VID4 AK4 Power/Other Output
VCC U24 Power/Other VID5 AL4 Power/Other Output
VCC U25 Power/Other VSS B1 Power/Other
VCC U26 Power/Other VSS B11 Power/Other
VCC U27 Power/Other VSS B14 Power/Other
VCC U28 Power/Other VSS B17 Power/Other
VCC U29 Power/Other VSS B20 Power/Other
VCC U30 Power/Other VSS B24 Power/Other
VCC U8 Power/Other VSS B5 Power/Other
VCC V8 Power/Other VSS B8 Power/Other
VCC W23 Power/Other VSS A12 Power/Other
VCC W24 Power/Other VSS A15 Power/Other
VCC W25 Power/Other VSS A18 Power/Other
VCC W26 Power/Other VSS A2 Power/Other
VCC W27 Power/Other VSS A21 Power/Other
VCC W28 Power/Other VSS A24 Power/Other
VCC W29 Power/Other VSS A6 Power/Other
VCC W30 Power/Other VSS A9 Power/Other
VCC W8 Power/Other VSS AA23 Power/Other
VCC Y23 Power/Other VSS AA24 Power/Other
VCC Y24 Power/Other VSS AA25 Power/Other
VCC Y25 Power/Other VSS AA26 Power/Other
VCC Y26 Power/Other VSS AA27 Power/Other
VCC Y27 Power/Other VSS AA28 Power/Other
VCC Y28 Power/Other VSS AA29 Power/Other
VCC Y29 Power/Other VSS AA3 Power/Other
VCC Y30 Power/Other VSS AA30 Power/Other
VCC Y8 Power/Other VSS AA6 Power/Other
VCC_MB_ VSS AA7 Power/Other
AN5 Power/Other Output
REGULATION
VSS AB1 Power/Other
VCC_SENSE AN3 Power/Other Output
VSS AB23 Power/Other
VCCA A23 Power/Other
VSS AB24 Power/Other
VCCIOPLL C23 Power/Other
VSS AB25 Power/Other
VID0 AM2 Power/Other Output
VSS AB26 Power/Other
VID1 AL5 Power/Other Output
VSS AB27 Power/Other
VID2 AM3 Power/Other Output

54 Datasheet
Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VSS AB28 Power/Other VSS AF3 Power/Other

VSS AB29 Power/Other VSS AF30 Power/Other
VSS AB30 Power/Other VSS AF6 Power/Other
VSS AB7 Power/Other VSS AF7 Power/Other
VSS AC3 Power/Other VSS AG10 Power/Other
VSS AC6 Power/Other VSS AG13 Power/Other
VSS AC7 Power/Other VSS AG16 Power/Other
VSS AD4 Power/Other VSS AG17 Power/Other
VSS AD7 Power/Other VSS AG20 Power/Other
VSS AE10 Power/Other VSS AG23 Power/Other
VSS AE13 Power/Other VSS AG24 Power/Other
VSS AE16 Power/Other VSS AG7 Power/Other
VSS AE17 Power/Other VSS AH1 Power/Other
VSS AE2 Power/Other VSS AH10 Power/Other
VSS AE20 Power/Other VSS AH13 Power/Other
VSS AE24 Power/Other VSS AH16 Power/Other
VSS AE25 Power/Other VSS AH17 Power/Other
VSS AE26 Power/Other VSS AH20 Power/Other
VSS AE27 Power/Other VSS AH23 Power/Other
VSS AE28 Power/Other VSS AH24 Power/Other
VSS AE29 Power/Other VSS AH3 Power/Other
VSS AE30 Power/Other VSS AH6 Power/Other
VSS AE5 Power/Other VSS AH7 Power/Other
VSS AE7 Power/Other VSS AJ10 Power/Other
VSS AF10 Power/Other VSS AJ13 Power/Other
VSS AF13 Power/Other VSS AJ16 Power/Other
VSS AF16 Power/Other VSS AJ17 Power/Other
VSS AF17 Power/Other VSS AJ20 Power/Other
VSS AF20 Power/Other VSS AJ23 Power/Other
VSS AF23 Power/Other VSS AJ24 Power/Other
VSS AF24 Power/Other VSS AJ27 Power/Other
VSS AF25 Power/Other VSS AJ28 Power/Other
VSS AF26 Power/Other VSS AJ29 Power/Other
VSS AF27 Power/Other VSS AJ30 Power/Other
VSS AF28 Power/Other VSS AJ4 Power/Other
VSS AF29 Power/Other VSS AJ7 Power/Other

Datasheet 55
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VSS AK10 Power/Other VSS AN1 Power/Other

VSS AK13 Power/Other VSS AN10 Power/Other
VSS AK16 Power/Other VSS AN13 Power/Other
VSS AK17 Power/Other VSS AN16 Power/Other
VSS AK2 Power/Other VSS AN17 Power/Other
VSS AK20 Power/Other VSS AN2 Power/Other
VSS AK23 Power/Other VSS AN20 Power/Other
VSS AK24 Power/Other VSS AN23 Power/Other
VSS AK27 Power/Other VSS AN24 Power/Other
VSS AK28 Power/Other VSS AN27 Power/Other
VSS AK29 Power/Other VSS AN28 Power/Other
VSS AK30 Power/Other VSS C10 Power/Other
VSS AK5 Power/Other VSS C13 Power/Other
VSS AK7 Power/Other VSS C16 Power/Other
VSS AL10 Power/Other VSS C19 Power/Other
VSS AL13 Power/Other VSS C22 Power/Other
VSS AL16 Power/Other VSS C24 Power/Other
VSS AL17 Power/Other VSS C4 Power/Other
VSS AL20 Power/Other VSS C7 Power/Other
VSS AL23 Power/Other VSS D12 Power/Other
VSS AL24 Power/Other VSS D15 Power/Other
VSS AL27 Power/Other VSS D18 Power/Other
VSS AL28 Power/Other VSS D21 Power/Other
VSS AL3 Power/Other VSS D24 Power/Other
VSS AL7 Power/Other VSS D3 Power/Other
VSS AM1 Power/Other VSS D5 Power/Other
VSS AM10 Power/Other VSS D6 Power/Other
VSS AM13 Power/Other VSS D9 Power/Other
VSS AM16 Power/Other VSS E11 Power/Other
VSS AM17 Power/Other VSS E14 Power/Other
VSS AM20 Power/Other VSS E17 Power/Other
VSS AM23 Power/Other VSS E2 Power/Other
VSS AM24 Power/Other VSS E20 Power/Other
VSS AM27 Power/Other VSS E25 Power/Other
VSS AM28 Power/Other VSS E26 Power/Other
VSS AM4 Power/Other VSS E27 Power/Other

56 Datasheet
Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VSS E28 Power/Other VSS K5 Power/Other

VSS E29 Power/Other VSS K7 Power/Other
VSS E8 Power/Other VSS L23 Power/Other
VSS F10 Power/Other VSS L24 Power/Other
VSS F13 Power/Other VSS L25 Power/Other
VSS F16 Power/Other VSS L26 Power/Other
VSS F19 Power/Other VSS L27 Power/Other
VSS F22 Power/Other VSS L28 Power/Other
VSS F4 Power/Other VSS L29 Power/Other
VSS F7 Power/Other VSS L3 Power/Other
VSS G1 Power/Other VSS L30 Power/Other
VSS H10 Power/Other VSS L6 Power/Other
VSS H11 Power/Other VSS L7 Power/Other
VSS H12 Power/Other VSS M1 Power/Other
VSS H13 Power/Other VSS M7 Power/Other
VSS H14 Power/Other VSS N3 Power/Other
VSS H17 Power/Other VSS N6 Power/Other
VSS H18 Power/Other VSS N7 Power/Other
VSS H19 Power/Other VSS P23 Power/Other
VSS H20 Power/Other VSS P24 Power/Other
VSS H21 Power/Other VSS P25 Power/Other
VSS H22 Power/Other VSS P26 Power/Other
VSS H23 Power/Other VSS P27 Power/Other
VSS H24 Power/Other VSS P28 Power/Other
VSS H25 Power/Other VSS P29 Power/Other
VSS H26 Power/Other VSS P30 Power/Other
VSS H27 Power/Other VSS P4 Power/Other
VSS H28 Power/Other VSS P7 Power/Other
VSS H3 Power/Other VSS R2 Power/Other
VSS H6 Power/Other VSS R23 Power/Other
VSS H7 Power/Other VSS R24 Power/Other
VSS H8 Power/Other VSS R25 Power/Other
VSS H9 Power/Other VSS R26 Power/Other
VSS J4 Power/Other VSS R27 Power/Other
VSS J7 Power/Other VSS R28 Power/Other
VSS K2 Power/Other VSS R29 Power/Other

Datasheet 57
 Land Listing and Signal Descriptions

Table 23. Alphabetical Land Table 23. Alphabetical Land

Assignments Assignments

Land Signal Buffer Land Signal Buffer

Land Name Direction Land Name Direction
# Type # Type

VSS R30 Power/Other VTT B26 Power/Other

VSS R5 Power/Other VTT B27 Power/Other
VSS R7 Power/Other VTT B28 Power/Other
VSS T3 Power/Other VTT B29 Power/Other
VSS T6 Power/Other VTT B30 Power/Other
VSS T7 Power/Other VTT A25 Power/Other
VSS U1 Power/Other VTT A26 Power/Other
VSS U7 Power/Other VTT A27 Power/Other
VSS V23 Power/Other VTT A28 Power/Other
VSS V24 Power/Other VTT A29 Power/Other
VSS V25 Power/Other VTT A30 Power/Other
VSS V26 Power/Other VTT C25 Power/Other
VSS V27 Power/Other VTT C26 Power/Other
VSS V28 Power/Other VTT C27 Power/Other
VSS V29 Power/Other VTT C28 Power/Other
VSS V3 Power/Other VTT C29 Power/Other
VSS V30 Power/Other VTT C30 Power/Other
VSS V6 Power/Other VTT D25 Power/Other
VSS V7 Power/Other VTT D26 Power/Other
VSS W4 Power/Other VTT D27 Power/Other
VSS W7 Power/Other VTT D28 Power/Other
VSS Y2 Power/Other VTT D29 Power/Other
VSS Y5 Power/Other VTT D30 Power/Other
VSS Y7 Power/Other VTT_OUT_LE
J1 Power/Other Output
FT
VSS_MB_
AN6 Power/Other Output
REGULATION VTT_OUT_RI
AA1 Power/Other Output
GHT
VSS_SENSE AN4 Power/Other Output
VTT_SEL F27 Power/Other Output
VSSA B23 Power/Other
VTTPWRGD AM6 Power/Other Input
VTT B25 Power/Other

58 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

A10 D08# Source Synch Input/Output AA28 VSS Power/Other

A11 D09# Source Synch Input/Output AA29 VSS Power/Other
A12 VSS Power/Other AA3 VSS Power/Other
A13 COMP0 Power/Other Input AA30 VSS Power/Other
A14 D50# Source Synch Input/Output AA4 A21# Source Synch Input/Output
A15 VSS Power/Other AA5 A23# Source Synch Input/Output
A16 DSTBN3# Source Synch Input/Output AA6 VSS Power/Other
A17 D56# Source Synch Input/Output AA7 VSS Power/Other
A18 VSS Power/Other AA8 VCC Power/Other
A19 D61# Source Synch Input/Output AB1 VSS Power/Other
A2 VSS Power/Other AB2 IERR# Asynch GTL+ Output
A20 RESERVED AB23 VSS Power/Other
A21 VSS Power/Other AB24 VSS Power/Other
A22 D62# Source Synch Input/Output AB25 VSS Power/Other
A23 VCCA Power/Other AB26 VSS Power/Other
A24 VSS Power/Other AB27 VSS Power/Other
A25 VTT Power/Other AB28 VSS Power/Other
A26 VTT Power/Other AB29 VSS Power/Other
A27 VTT Power/Other AB3 MCERR# Common Clock Input/Output
A28 VTT Power/Other AB30 VSS Power/Other
A29 VTT Power/Other AB4 A26# Source Synch Input/Output
A3 RS2# Common Clock Input AB5 A24# Source Synch Input/Output
A30 VTT Power/Other AB6 A17# Source Synch Input/Output
A4 D02# Source Synch Input/Output AB7 VSS Power/Other
A5 D04# Source Synch Input/Output AB8 VCC Power/Other
A6 VSS Power/Other AC1 TMS TAP Input
A7 D07# Source Synch Input/Output AC2 DBR# Power/Other Output
A8 DBI0# Source Synch Input/Output AC23 VCC Power/Other
A9 VSS Power/Other AC24 VCC Power/Other
VTT_RIGHT AC25 VCC Power/Other
AA1 Power/Other Output
_OUT
AC26 VCC Power/Other
AA2 LL_ID1 Power/Other Output
AC27 VCC Power/Other
AA23 VSS Power/Other
AC28 VCC Power/Other
AA24 VSS Power/Other
AC29 VCC Power/Other
AA25 VSS Power/Other
AC3 VSS Power/Other
AA26 VSS Power/Other
AC30 VCC Power/Other
AA27 VSS Power/Other

Datasheet 59
 Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

AC4 RESERVED AE23 VCC Power/Other

AC5 A25# Source Synch Input/Output AE24 VSS Power/Other
AC6 VSS Power/Other AE25 VSS Power/Other
AC7 VSS Power/Other AE26 VSS Power/Other
AC8 VCC Power/Other AE27 VSS Power/Other
AD1 TDI TAP Input AE28 VSS Power/Other
AD2 BPM2# Common Clock Input/Output AE29 VSS Power/Other
AD23 VCC Power/Other AE3 COMP7 Power/Other Input
AD24 VCC Power/Other AE30 VSS Power/Other
AD25 VCC Power/Other AE4 RESERVED
AD26 VCC Power/Other AE5 VSS Power/Other
AD27 VCC Power/Other AE6 RESERVED
AD28 VCC Power/Other AE7 VSS Power/Other
AD29 VCC Power/Other AE8 SKTOCC# Power/Other Output
AD3 BINIT# Common Clock Input/Output AE9 VCC Power/Other
AD30 VCC Power/Other AF1 TDO TAP Output
AD4 VSS Power/Other AF10 VSS Power/Other
AD5 ADSTB1# Source Synch Input/Output AF11 VCC Power/Other
AD6 A22# Source Synch Input/Output AF12 VCC Power/Other
AD7 VSS Power/Other AF13 VSS Power/Other
AD8 VCC Power/Other AF14 VCC Power/Other
AE1 TCK TAP Input AF15 VCC Power/Other
AE10 VSS Power/Other AF16 VSS Power/Other
AE11 VCC Power/Other AF17 VSS Power/Other
AE12 VCC Power/Other AF18 VCC Power/Other
AE13 VSS Power/Other AF19 VCC Power/Other
AE14 VCC Power/Other AF2 BPM4# Common Clock Input/Output
AE15 VCC Power/Other AF20 VSS Power/Other
AE16 VSS Power/Other AF21 VCC Power/Other
AE17 VSS Power/Other AF22 VCC Power/Other
AE18 VCC Power/Other AF23 VSS Power/Other
AE19 VCC Power/Other AF24 VSS Power/Other
AE2 VSS Power/Other AF25 VSS Power/Other
AE20 VSS Power/Other AF26 VSS Power/Other
AE21 VCC Power/Other AF27 VSS Power/Other
AE22 VCC Power/Other AF28 VSS Power/Other

60 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

AF29 VSS Power/Other AG7 VSS Power/Other

AF3 VSS Power/Other AG8 VCC Power/Other
AF30 VSS Power/Other AG9 VCC Power/Other
AF4 A28# Source Synch Input/Output AH1 VSS Power/Other
AF5 A27# Source Synch Input/Output AH10 VSS Power/Other
AF6 VSS Power/Other AH11 VCC Power/Other
AF7 VSS Power/Other AH12 VCC Power/Other
AF8 VCC Power/Other AH13 VSS Power/Other
AF9 VCC Power/Other AH14 VCC Power/Other
AG1 TRST# TAP Input AH15 VCC Power/Other
AG10 VSS Power/Other AH16 VSS Power/Other
AG11 VCC Power/Other AH17 VSS Power/Other
AG12 VCC Power/Other AH18 VCC Power/Other
AG13 VSS Power/Other AH19 VCC Power/Other
AG14 VCC Power/Other AH2 RESERVED
AG15 VCC Power/Other AH20 VSS Power/Other
AG16 VSS Power/Other AH21 VCC Power/Other
AG17 VSS Power/Other AH22 VCC Power/Other
AG18 VCC Power/Other AH23 VSS Power/Other
AG19 VCC Power/Other AH24 VSS Power/Other
AG2 BPM3# Common Clock Input/Output AH25 VCC Power/Other
AG20 VSS Power/Other AH26 VCC Power/Other
AG21 VCC Power/Other AH27 VCC Power/Other
AG22 VCC Power/Other AH28 VCC Power/Other
AG23 VSS Power/Other AH29 VCC Power/Other
AG24 VSS Power/Other AH3 VSS Power/Other
AG25 VCC Power/Other AH30 VCC Power/Other
AG26 VCC Power/Other AH4 A32# Source Synch Input/Output
AG27 VCC Power/Other AH5 A33# Source Synch Input/Output
AG28 VCC Power/Other AH6 VSS Power/Other
AG29 VCC Power/Other AH7 VSS Power/Other
AG3 BPM5# Common Clock Input/Output AH8 VCC Power/Other
AG30 VCC Power/Other AH9 VCC Power/Other
AG4 A30# Source Synch Input/Output AJ1 BPM1# Common Clock Input/Output
AG5 A31# Source Synch Input/Output AJ10 VSS Power/Other
AG6 A29# Source Synch Input/Output AJ11 VCC Power/Other

Datasheet 61
 Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

AJ12 VCC Power/Other AK18 VCC Power/Other

AJ13 VSS Power/Other AK19 VCC Power/Other
AJ14 VCC Power/Other AK2 VSS Power/Other
AJ15 VCC Power/Other AK20 VSS Power/Other
AJ16 VSS Power/Other AK21 VCC Power/Other
AJ17 VSS Power/Other AK22 VCC Power/Other
AJ18 VCC Power/Other AK23 VSS Power/Other
AJ19 VCC Power/Other AK24 VSS Power/Other
AJ2 BPM0# Common Clock Input/Output AK25 VCC Power/Other
AJ20 VSS Power/Other AK26 VCC Power/Other
AJ21 VCC Power/Other AK27 VSS Power/Other
AJ22 VCC Power/Other AK28 VSS Power/Other
AJ23 VSS Power/Other AK29 VSS Power/Other
AJ24 VSS Power/Other AK3 ITP_CLK0 TAP Input
AJ25 VCC Power/Other AK30 VSS Power/Other
AJ26 VCC Power/Other AK4 VID4 Power/Other Output
AJ27 VSS Power/Other AK5 VSS Power/Other
AJ28 VSS Power/Other AK6 FORCEPR# Asynch GTL+ Input
AJ29 VSS Power/Other AK7 VSS Power/Other
AJ3 ITP_CLK1 TAP Input AK8 VCC Power/Other
AJ30 VSS Power/Other AK9 VCC Power/Other
AJ4 VSS Power/Other AL1 THERMDA Power/Other
AJ5 A34# Source Synch Input/Output AL10 VSS Power/Other
AJ6 A35# Source Synch Input/Output AL11 VCC Power/Other
AJ7 VSS Power/Other AL12 VCC Power/Other
AJ8 VCC Power/Other AL13 VSS Power/Other
AJ9 VCC Power/Other AL14 VCC Power/Other
AK1 THERMDC Power/Other AL15 VCC Power/Other
AK10 VSS Power/Other AL16 VSS Power/Other
AK11 VCC Power/Other AL17 VSS Power/Other
AK12 VCC Power/Other AL18 VCC Power/Other
AK13 VSS Power/Other AL19 VCC Power/Other
AK14 VCC Power/Other AL2 PROCHOT# Asynch GTL+ Input/Output
AK15 VCC Power/Other AL20 VSS Power/Other
AK16 VSS Power/Other AL21 VCC Power/Other
AK17 VSS Power/Other AL22 VCC Power/Other

62 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

AL23 VSS Power/Other AM29 VCC Power/Other

AL24 VSS Power/Other AM3 VID2 Power/Other Output
AL25 VCC Power/Other AM30 VCC Power/Other
AL26 VCC Power/Other AM4 VSS Power/Other
AL27 VSS Power/Other AM5 FC11 Power/Other Output
AL28 VSS Power/Other AM6 VTTPWRGD Power/Other Input
AL29 VCC Power/Other AM7 FC12 Power/Other Output
AL3 VSS Power/Other AM8 VCC Power/Other
AL30 VCC Power/Other AM9 VCC Power/Other
AL4 VID5 Power/Other Output AN1 VSS Power/Other
AL5 VID1 Power/Other Output AN10 VSS Power/Other
AL6 VID3 Power/Other Output AN11 VCC Power/Other
AL7 VSS Power/Other AN12 VCC Power/Other
AL8 VCC Power/Other AN13 VSS Power/Other
AL9 VCC Power/Other AN14 VCC Power/Other
AM1 VSS Power/Other AN15 VCC Power/Other
AM10 VSS Power/Other AN16 VSS Power/Other
AM11 VCC Power/Other AN17 VSS Power/Other
AM12 VCC Power/Other AN18 VCC Power/Other
AM13 VSS Power/Other AN19 VCC Power/Other
AM14 VCC Power/Other AN2 VSS Power/Other
AM15 VCC Power/Other AN20 VSS Power/Other
AM16 VSS Power/Other AN21 VCC Power/Other
AM17 VSS Power/Other AN22 VCC Power/Other
AM18 VCC Power/Other AN23 VSS Power/Other
AM19 VCC Power/Other AN24 VSS Power/Other
AM2 VID0 Power/Other Output AN25 VCC Power/Other
AM20 VSS Power/Other AN26 VCC Power/Other
AM21 VCC Power/Other AN27 VSS Power/Other
AM22 VCC Power/Other AN28 VSS Power/Other
AM23 VSS Power/Other AN29 VCC Power/Other
AM24 VSS Power/Other AN3 VCC_SENSE Power/Other Output
AM25 VCC Power/Other AN30 VCC Power/Other
AM26 VCC Power/Other AN4 VSS_SENSE Power/Other Output
AM27 VSS Power/Other VCC_MB_
AN5 REGULA Power/Other Output
AM28 VSS Power/Other
TION

Datasheet 63
 Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

VSS_MB_ C10 VSS Power/Other

AN6 REGULA Power/Other Output
C11 D11# Source Synch Input/Output
TION
C12 D14# Source Synch Input/Output
AN7 FC16 Power/Other Output
C13 VSS Power/Other
AN8 VCC Power/Other
C14 D52# Source Synch Input/Output
AN9 VCC Power/Other
C15 D51# Source Synch Input/Output
B1 VSS Power/Other
C16 VSS Power/Other
B10 D10# Source Synch Input/Output
C17 DSTBP3# Source Synch Input/Output
B11 VSS Power/Other
C18 D54# Source Synch Input/Output
B12 D13# Source Synch Input/Output
C19 VSS Power/Other
B13 FC19 Power/Other Output
C2 BNR# Common Clock Input/Output
B14 VSS Power/Other
C20 DBI3# Source Synch Input/Output
B15 D53# Source Synch Input/Output
C21 D58# Source Synch Input/Output
B16 D55# Source Synch Input/Output
C22 VSS Power/Other
B17 VSS Power/Other
C23 VCCIOPLL Power/Other
B18 D57# Source Synch Input/Output
C24 VSS Power/Other
B19 D60# Source Synch Input/Output
C25 VTT Power/Other
B2 DBSY# Common Clock Input/Output
C26 VTT Power/Other
B20 VSS Power/Other
C27 VTT Power/Other
B21 D59# Source Synch Input/Output
C28 VTT Power/Other
B22 D63# Source Synch Input/Output
C29 VTT Power/Other
B23 VSSA Power/Other
C3 LOCK# Common Clock Input/Output
B24 VSS Power/Other
C30 VTT Power/Other
B25 VTT Power/Other
C4 VSS Power/Other
B26 VTT Power/Other
C5 D01# Source Synch Input/Output
B27 VTT Power/Other
C6 D03# Source Synch Input/Output
B28 VTT Power/Other
C7 VSS Power/Other
B29 VTT Power/Other
C8 DSTBN0# Source Synch Input/Output
B3 RS0# Common Clock Input
C9 RESERVED
B30 VTT Power/Other
D1 RESERVED
B4 D00# Source Synch Input/Output
D10 D22# Source Synch Input/Output
B5 VSS Power/Other
D11 D15# Source Synch Input/Output
B6 D05# Source Synch Input/Output
D12 VSS Power/Other
B7 D06# Source Synch Input/Output
D13 D25# Source Synch Input/Output
B8 VSS Power/Other
D14 RESERVED
B9 DSTBP0# Source Synch Input/Output
D15 VSS Power/Other
C1 DRDY# Common Clock Input/Output

64 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

D16 RESERVED E22 D45# Source Synch Input/Output

D17 D49# Source Synch Input/Output E23 RESERVED
D18 VSS Power/Other E24 FC10 Power/Other Output
D19 DBI2# Source Synch Input/Output E25 VSS Power/Other
D2 ADS# Common Clock Input/Output E26 VSS Power/Other
D20 D48# Source Synch Input/Output E27 VSS Power/Other
D21 VSS Power/Other E28 VSS Power/Other
D22 D46# Source Synch Input/Output E29 VSS Power/Other
D23 FC9 Power/Other Output E3 TRDY# Common Clock Input
D24 VSS Power/Other E4 HITM# Common Clock Input/Output
D25 VTT Power/Other E5 FC20 Power/Other Output
D26 VTT Power/Other E6 RESERVED
D27 VTT Power/Other E7 RESERVED
D28 VTT Power/Other E8 VSS Power/Other
D29 VTT Power/Other E9 D19# Source Synch Input/Output
D3 VSS Power/Other F10 VSS Power/Other
D30 VTT Power/Other F11 D23# Source Synch Input/Output
D4 HIT# Common Clock Input/Output F12 D24# Source Synch Input/Output
D5 VSS Power/Other F13 VSS Power/Other
D6 VSS Power/Other F14 D28# Source Synch Input/Output
D7 D20# Source Synch Input/Output F15 D30# Source Synch Input/Output
D8 D12# Source Synch Input/Output F16 VSS Power/Other
D9 VSS Power/Other F17 D37# Source Synch Input/Output
E10 D21# Source Synch Input/Output F18 D38# Source Synch Input/Output
E11 VSS Power/Other F19 VSS Power/Other
E12 DSTBP1# Source Synch Input/Output F2 FC5 Common Clock Input
E13 D26# Source Synch Input/Output F20 D41# Source Synch Input/Output
E14 VSS Power/Other F21 D43# Source Synch Input/Output
E15 D33# Source Synch Input/Output F22 VSS Power/Other
E16 D34# Source Synch Input/Output F23 RESERVED
E17 VSS Power/Other F24 TESTHI7 Power/Other Input
E18 D39# Source Synch Input/Output F25 TESTHI2 Power/Other Input
E19 D40# Source Synch Input/Output F26 TESTHI0 Power/Other Input
E2 VSS Power/Other F27 VTT_SEL Power/Other Output
E20 VSS Power/Other F28 BCLK0 Clock Input
E21 D42# Source Synch Input/Output F29 RESERVED

Datasheet 65
 Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

F3 BR0# Common Clock Input/Output G9 D16# Source Synch Input/Output

F4 VSS Power/Other H1 GTLREF0 Power/Other Input
F5 RS1# Common Clock Input H10 VSS Power/Other
F6 IMPSEL Power/Other Input H11 VSS Power/Other
F7 VSS Power/Other H12 VSS Power/Other
F8 D17# Source Synch Input/Output H13 VSS Power/Other
F9 D18# Source Synch Input/Output H14 VSS Power/Other
G1 VSS Power/Other H15 DP1# Common Clock Input/Output
G10 RESERVED H16 DP2# Common Clock Input/Output
G11 DBI1# Source Synch Input/Output H17 VSS Power/Other
G12 DSTBN1# Source Synch Input/Output H18 VSS Power/Other
G13 D27# Source Synch Input/Output H19 VSS Power/Other
G14 D29# Source Synch Input/Output H2 GTLREF1 Power/Other Input
G15 D31# Source Synch Input/Output H20 VSS Power/Other
G16 D32# Source Synch Input/Output H21 VSS Power/Other
G17 D36# Source Synch Input/Output H22 VSS Power/Other
G18 D35# Source Synch Input/Output H23 VSS Power/Other
G19 DSTBP2# Source Synch Input/Output H24 VSS Power/Other
G2 COMP2 Power/Other Input H25 VSS Power/Other
G20 DSTBN2# Source Synch Input/Output H26 VSS Power/Other
G21 D44# Source Synch Input/Output H27 VSS Power/Other
G22 D47# Source Synch Input/Output H28 VSS Power/Other
G23 RESET# Common Clock Input H29 FC15 Power/Other Output
G24 TESTHI6 Power/Other Input H3 VSS Power/Other
G25 TESTHI3 Power/Other Input H30 BSEL1 Power/Other Output
G26 TESTHI5 Power/Other Input H4 RSP# Common Clock Input
G27 TESTHI4 Power/Other Input H5 TESTHI10 Power/Other Input
G28 BCLK1 Clock Input H6 VSS Power/Other
G29 BSEL0 Power/Other Output H7 VSS Power/Other
G3 TESTHI8 Power/Other Input H8 VSS Power/Other
G30 BSEL2 Power/Other Output H9 VSS Power/Other
G4 TESTHI9 Power/Other Input VTT_OUT_L
J1 Power/Other Output
EFT
G5 FC7 Source Synch Output
J10 VCC Power/Other
G6 RESERVED
J11 VCC Power/Other
G7 DEFER# Common Clock Input
J12 VCC Power/Other
G8 BPRI# Common Clock Input
J13 VCC Power/Other

66 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

J14 VCC Power/Other K4 REQ0# Source Synch Input/Output

J15 VCC Power/Other K5 VSS Power/Other
J16 DP0# Common Clock Input/Output K6 REQ3# Source Synch Input/Output
J17 DP3# Common Clock Input/Output K7 VSS Power/Other
J18 VCC Power/Other K8 VCC Power/Other
J19 VCC Power/Other L1 LINT1 Asynch GTL+ Input
J2 COMP4 Power/Other Input L2 TESTHI13 Asynch GTL+ Input
J20 VCC Power/Other L23 VSS Power/Other
J21 VCC Power/Other L24 VSS Power/Other
J22 VCC Power/Other L25 VSS Power/Other
J23 VCC Power/Other L26 VSS Power/Other
J24 VCC Power/Other L27 VSS Power/Other
J25 VCC Power/Other L28 VSS Power/Other
J26 VCC Power/Other L29 VSS Power/Other
J27 VCC Power/Other L3 VSS Power/Other
J28 VCC Power/Other L30 VSS Power/Other
J29 VCC Power/Other L4 A06# Source Synch Input/Output
J3 FC22 Power/Other Output L5 A03# Source Synch Input/Output
J30 VCC Power/Other L6 VSS Power/Other
J4 VSS Power/Other L7 VSS Power/Other
J5 REQ1# Source Synch Input/Output L8 VCC Power/Other
J6 REQ4# Source Synch Input/Output M1 VSS Power/Other
J7 VSS Power/Other THERM
M2 Asynch GTL+ Output
TRIP#
J8 VCC Power/Other
M23 VCC Power/Other
J9 VCC Power/Other
M24 VCC Power/Other
K1 LINT0 Asynch GTL+ Input
M25 VCC Power/Other
K2 VSS Power/Other
M26 VCC Power/Other
K23 VCC Power/Other
M27 VCC Power/Other
K24 VCC Power/Other
M28 VCC Power/Other
K25 VCC Power/Other
M29 VCC Power/Other
K26 VCC Power/Other
M3 STPCLK# Asynch GTL+ Input
K27 VCC Power/Other
M30 VCC Power/Other
K28 VCC Power/Other
M4 A07# Source Synch Input/Output
K29 VCC Power/Other
M5 A05# Source Synch Input/Output
K3 A20M# Asynch GTL+ Input
M6 REQ2# Source Synch Input/Output
K30 VCC Power/Other
M7 VSS Power/Other

Datasheet 67
 Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

M8 VCC Power/Other R24 VSS Power/Other

N1 PWRGOOD Power/Other Input R25 VSS Power/Other
N2 IGNNE# Asynch GTL+ Input R26 VSS Power/Other
N23 VCC Power/Other R27 VSS Power/Other
N24 VCC Power/Other R28 VSS Power/Other
N25 VCC Power/Other R29 VSS Power/Other
N26 VCC Power/Other FERR#/
R3 Asynch GTL+ Output
PBE#
N27 VCC Power/Other
R30 VSS Power/Other
N28 VCC Power/Other
R4 A08# Source Synch Input/Output
N29 VCC Power/Other
R5 VSS Power/Other
N3 VSS Power/Other
R6 ADSTB0# Source Synch Input/Output
N30 VCC Power/Other
R7 VSS Power/Other
N4 RESERVED
R8 VCC Power/Other
N5 RESERVED
T1 COMP1 Power/Other Input
N6 VSS Power/Other
T2 COMP5 Power/Other Input
N7 VSS Power/Other
T23 VCC Power/Other
N8 VCC Power/Other
T24 VCC Power/Other
P1 TESTHI11 Power/Other Input
T25 VCC Power/Other
P2 SMI# Asynch GTL+ Input
T26 VCC Power/Other
P23 VSS Power/Other
T27 VCC Power/Other
P24 VSS Power/Other
T28 VCC Power/Other
P25 VSS Power/Other
T29 VCC Power/Other
P26 VSS Power/Other
T3 VSS Power/Other
P27 VSS Power/Other
T30 VCC Power/Other
P28 VSS Power/Other
T4 A11# Source Synch Input/Output
P29 VSS Power/Other
T5 A09# Source Synch Input/Output
P3 INIT# Asynch GTL+ Input
T6 VSS Power/Other
P30 VSS Power/Other
T7 VSS Power/Other
P4 VSS Power/Other
T8 VCC Power/Other
P5 RESERVED
U1 VSS Power/Other
P6 A04# Source Synch Input/Output
U2 AP0# Common Clock Input/Output
P7 VSS Power/Other
U23 VCC Power/Other
P8 VCC Power/Other
U24 VCC Power/Other
R1 COMP3 Power/Other Input
U25 VCC Power/Other
R2 VSS Power/Other
U26 VCC Power/Other
R23 VSS Power/Other
U27 VCC Power/Other

68 Datasheet
Land Listing and Signal Descriptions

Table 24. Numerical Land Table 24. Numerical Land

Assignment Assignment

Land Land Signal Buffer Land Land Signal Buffer

Direction Direction
# Name Type # Name Type

U28 VCC Power/Other W4 VSS Power/Other

U29 VCC Power/Other W5 A16# Source Synch Input/Output
U3 AP1# Common Clock Input/Output W6 A18# Source Synch Input/Output
U30 VCC Power/Other W7 VSS Power/Other
U4 A13# Source Synch Input/Output W8 VCC Power/Other
U5 A12# Source Synch Input/Output BOOT
Y1 Power/Other Input
SELECT
U6 A10# Source Synch Input/Output
Y2 VSS Power/Other
U7 VSS Power/Other
Y23 VCC Power/Other
U8 VCC Power/Other
Y24 VCC Power/Other
V1 MSID1 Power/Other Output
Y25 VCC Power/Other
V2 LL_ID0 Power/Other Output
Y26 VCC Power/Other
V23 VSS Power/Other
Y27 VCC Power/Other
V24 VSS Power/Other
Y28 VCC Power/Other
V25 VSS Power/Other
Y29 VCC Power/Other
V26 VSS Power/Other
Y3 COMP6
V27 VSS Power/Other
Y30 VCC Power/Other
V28 VSS Power/Other
Y4 A20# Source Synch Input/Output
V29 VSS Power/Other
Y5 VSS Power/Other
V3 VSS Power/Other
Y6 A19# Source Synch Input/Output
V30 VSS Power/Other
Y7 VSS Power/Other
V4 A15# Source Synch Input/Output
Y8 VCC Power/Other
V5 A14# Source Synch Input/Output
V6 VSS Power/Other
V7 VSS Power/Other
V8 VCC Power/Other
W1 MSID0 Power/Other Output
W2 TESTHI12 Power/Other Input
W23 VCC Power/Other
W24 VCC Power/Other
W25 VCC Power/Other
W26 VCC Power/Other
W27 VCC Power/Other
W28 VCC Power/Other
W29 VCC Power/Other
W3 TESTHI1 Power/Other Input
W30 VCC Power/Other

Datasheet 69
 Land Listing and Signal Descriptions

4.2 Alphabetical Signals Reference

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
Input/
A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source
Output synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-MB boundary. Assertion of A20M# is only supported
A20M# Input in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
Input/
ADS# agents observe the ADS# activation to begin parity checking,
Output
protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
Input/ Signals Associated Strobe
ADSTB[1:0]#
Output
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]# ADSTB1#

AP[1:0]# (Address Parity) are driven by the request initiator along

with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#.
A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. This
allows parity to be high when all the covered signals are high.
AP[1:0]# should connect the appropriate pins/lands of all processor
FSB agents. The following table defines the coverage model of these
Input/
AP[1:0]# signals.
Output
Request Signals Subphase 1 Subphase 2

A[35:24]# AP0# AP1#

A[23:3]# AP1# AP0#
REQ[4:0]# AP1# AP0#

70 Datasheet
Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All processor FSB agents must receive these signals to
BCLK[1:0] Input drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BINIT# (Bus Initialization) may be observed and driven by all
processor FSB agents and if used, must connect the appropriate
pins/lands of all such agents. If the BINIT# driver is enabled during
power-on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration,
and BINIT# is sampled asserted, symmetric agents reset their bus
Input/
BINIT# LOCK# activity and bus request arbitration state machines. The bus
Output
agents do not reset their IOQ and transaction tracking state
machines upon observation of BINIT# activation. Once the BINIT#
assertion has been observed, the bus agents will re-arbitrate for the
FSB and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a
central agent may handle an assertion of BINIT# as appropriate to
the error handling architecture of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus
Input/
BNR# agent unable to accept new bus transactions. During a bus stall, the
Output
current bus owner cannot issue any new transactions.
This input is required to determine whether the processor is
installed in a platform that supports the processor. The processor
BOOTSELECT Input
will not operate if this signal is low. This input has a weak internal
pull-up to VCC.
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
Input/
BPM[5:0]# port. PRDY# is a processor output used by debug tools to determine
Output
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to Section 2.5.2
for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
BPRI# Input priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
Input/
BR0# signal is sampled to determine the agent ID = 0.
Output
This signal does not have on-die termination and must be
terminated.

Datasheet 71
 Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

The BCLK[1:0] frequency select signals BSEL[2:0] are used to

select the processor input clock frequency. Table 18 defines the
possible combinations of the signals and the frequency associated
BSEL[2:0] Output with each combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at
the same frequency. For more information about these signals,
including termination recommendations refer to Section 2.7.2.
COMP[3:2, 1:0] must be terminated to VSS on the system board
COMP[7:6,
Analog using precision resistors. COMP[7:6, 5:4] must be terminated to VTT
5:4,3:2, 1:0]
on the system board using precision resistors.
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data
strobes and DBI#.

Quad-Pumped Signal Groups

Input/
D[63:0]# DSTBN#/
Output Data Group DBI#
DSTBP#

D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3

Furthermore, the DBI# signals determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals
are activated when the data on the data bus is inverted. If more
than half the data bits, within a 16-bit group, would have been
asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Input/
DBI[3:0]#
Output Data Bus
Bus Signal
Signals

DBI3# D[63:48]#
DBI2# D[47:32]#
DBI1# D[31:16]#
DBI0# D[15:0]#

72 Datasheet
Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

DBR# (Debug Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a
DBR# Output debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
Input/
DBSY# use. The data bus is released after DBSY# is de-asserted. This
Output
signal must connect the appropriate pins/lands on all processor FSB
agents.
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
DEFER# Input normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DP[3:0]# (Data parity) provide parity protection for the D[63:0]#
Input/ signals. They are driven by the agent responsible for driving
DP[3:0]#
Output D[63:0]#, and must connect the appropriate pins/lands of all
processor FSB agents.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
Input/
DRDY# clock data transfer, DRDY# may be de-asserted to insert idle clocks.
Output
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DBI0# DSTBN0#

Input/
DSTBN[3:0]#
Output D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DBI0# DSTBP0#

Input/
DSTBP[3:0]#
Output D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#

FC signals are signals that are available for compatibility with other
FCx Other
processors.

Datasheet 73
 Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

FERR#/PBE# (floating point error/pending break event) is a

multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
FERR#/PBE# Output
assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal
state. For additional information on the pending break event
functionality, including the identification of support of the feature
and enable/disable information, refer to volume 3 of the Intel
Architecture Software Developer's Manual and the Intel Processor
Identification and the CPUID Instruction application note.
The FORCEPR# input can be used by the platform to force the
processor (both cores) to activate the Thermal Control Circuit
FORCEPR# Input
(TCC). The TCC will remain active until the system deasserts
FORCEPR#.
GTLREF[1:0] determine the signal reference level for GTL+ input
GTLREF[1:0] Input signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
Input/
HIT# Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
HITM# Input/ be continued by reasserting HIT# and HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
IERR# Output
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.5.2
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol floating-
point instructions. If IGNNE# is de-asserted, the processor
generates an exception on a noncontrol floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
IGNNE# Input
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
IMPSEL input will determine whether the processor uses a 50 Ω or
IMPSEL Input 60 Ω buffer. This pin must be tied to GND on 50Ω platforms and left
as NC on 60 Ω platforms.

74 Datasheet
Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
INIT# Input processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the
appropriate pins/lands of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
ITP_CLK[1:0] Input
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
LINT[1:0] Input previous Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
The LL_ID[1:0] signals are used to select the correct loadline slope
LL_ID[1:0] Output
for the processor. LL_ID[1:0] = 00 for the Pentium D processor.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
Input/ end of the last transaction.
LOCK#
Output When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity
of lock.
MCERR# (Machine Check Error) is asserted to indicate an
unrecoverable error without a bus protocol violation. It may be
driven by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
Input/ • Enabled or disabled.
MCERR# • Asserted, if configured, for internal errors along with IERR#.
Output
• Asserted, if configured, by the request initiator of a bus transaction after
it observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the
IA-32 Software Developer’s Manual, Volume 3: System
Programming Guide.

Datasheet 75
 Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

MSID[1:0] (input) MSID0 is used to indicate to the processor

whether the platform supports 775_VR_CONFIG_05B processors. A
775_VR_CONFIG_05B processor will only boot if its MSID0 pin is
MSID[1:0] Input
electrically low. A 775_VR_CONFIG_05A processor will ignore this
input.
MSID1 must be electrically low for the processor to boot.
For the processor, PROCHOT# can be configured via BIOS as an
output or a bi-directional signal.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that one or both
Output
cores has reached its maximum safe operating temperature. This
or
PROCHOT# indicates that the processor Thermal Control Circuit (TCC) has been
Input/
activated, if enabled.
Output
As a bi-directional signal, assertion of PROCHOT# by the system will
activate the TCC, if enabled, for both cores. The TCC will remain
active until the system de-asserts PROCHOT#. See Section 5.2.3 for
more details.
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
PWRGOOD Input
transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable
before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
Input/
REQ[4:0]# bus owner to define the currently active transaction type. These
Output
signals are source synchronous to ADSTB0#. Refer to the AP[1:0]#
signal description for a details on parity checking of these signals.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
RESET# Input asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
RS[2:0]# Input
must connect the appropriate pins/lands of all processor FSB
agents.

76 Datasheet
Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

RSP# (Response Parity) is driven by the response agent (the agent

responsible for completion of the current transaction) during
assertion of RS[2:0]#, the signals for which RSP# provides parity
protection. It must connect to the appropriate pins/lands of all
RSP# Input processor FSB agents.
A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. While
RS[2:0]# = 000, RSP# is also high, since this indicates it is not
being driven by any agent ensuring correct parity.
SKTOCC# (Socket Occupied) will be pulled to ground by the
SKTOCC# Output processor. System board designers may use this signal to determine
if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
SMI# Input Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
STPCLK# Input The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-asserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
TCK Input
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI
TDI Input
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO Output TDO provides the serial output needed for JTAG specification
support.
TESTHI[13:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
TESTHI[13:0] Input
description) through a resistor for proper processor operation. See
Section 2.4 for more details.
THERMDA Other Thermal Diode Anode. See Section 5.2.7.
THERMDC Other Thermal Diode Cathode. See Section 5.2.7.

Datasheet 77
 Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

In the event of a catastrophic cooling failure, the processor will

automatically shut down when the silicon has reached a
temperature approximately 15°C above the maximum TC. Assertion
of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (VCC) must be removed following the
assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
THERMTRIP# Output
enabled within 10 µs of the assertion of PWRGOOD (provided
VTTPWRGD, VTT, and VCC are asserted) and is disabled on de-
assertion of PWRGOOD (if VTTPWRGD, VTT, or VCC are not valid,
THERMTRIP# may also be disabled). Once activated, THERMTRIP#
remains latched until PWRGOOD, VTTPWRGD, VTT or VCC is de-
asserted. While the de-assertion of the PWRGOOD, VTTPWRGD, VTT
or VCC signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 µs of the assertion of PWRGOOD
(provided VTTPWRGD, VTT, and VCC are asserted).
TMS (Test Mode Select) is a JTAG specification support signal used
TMS Input
by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is
TRDY# Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
TRST# Input
must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to
VCC Input
these pins is determined by the VID[5:0] pins.
VCCA Input VCCA provides isolated power for the internal processor core PLLs.
VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
VCC_SENSE Output core power (VCC). It can be used to sense or measure voltage near
the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
VCC_MB_ VCC. It is connected internally in the processor package to the sense
Output
REGULATION point land U27 as described in the Voltage Regulator-Down (VRD)
10.1 Design Guide for Desktop Socket 775.
VID[5:0] (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the Voltage
Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775
for more information. The voltage supply for these signals must be
valid before the VR can supply VCC to the processor. Conversely, the
VID[5:0] Output
VR output must be disabled until the voltage supply for the VID
signals becomes valid. The VID signals are needed to support the
processor voltage specification variations. See Table 2 for definitions
of these signals. The VR must supply the voltage that is requested
by the signals, or disable itself.
VSS are the ground pins for the processor and should be connected
VSS Input
to the system ground plane.
VSSA Input VSSA is the isolated ground for internal PLLs.

78 Datasheet
Land Listing and Signal Descriptions

Table 25. Signal Description (Sheet 1 of 9)

Name Type Description

VSS_SENSE is an isolated low impedance connection to processor

VSS_SENSE Output core VSS. It can be used to sense or measure ground near the
silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
VSS_MB_ VSS. It is connected internally in the processor package to the sense
Output
REGULATION point land V27 as described in the Voltage Regulator-Down (VRD)
10.1 Design Guide for Desktop Socket 775.
VTT Miscellaneous voltage supply.
VTT_OUT_LEFT The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
Output provide a voltage supply for some signals that require termination
VTT_OUT_RIGHT to VTT on the motherboard.

The VTT_SEL signal is used to select the correct VTT voltage level for
VTT_SEL Output
the processor.
The processor requires this input to determine that the VTT voltages
VTTPWRGD Input
are stable and within specification.

§§

Datasheet 79
 Land Listing and Signal Descriptions

80 Datasheet
Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations
5.1 Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.

A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the
Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and Intel®
Pentium® 4 Processor Thermal and Mechanical Design Guidelines.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.

5.1.1 Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 26. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system. For
more details on thermal solution design, please refer to the Intel® Pentium® D
Processor, Intel® Pentium® Processor Extreme Edition, and Intel® Pentium® 4
Processor Thermal and Mechanical Design Guidelines.

The processor uses a methodology for managing processor temperatures that is

intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed will be based on the temperature reported by the processor’s
Thermal Diode. If the diode temperature is greater than or equal to TCONTROL, then the
processor case temperature must remain at or below the temperature as specified by
the thermal profile. If the diode temperature is less than TCONTROL then the case
temperature is permitted to exceed the thermal profile, but the diode temperature
must remain at or below TCONTROL. Systems that implement fan speed control must be
designed to take these conditions in to account. Systems that do not alter the fan
speed only need to ensure the case temperature meets the thermal profile
specifications.

To determine a processor's case temperature specification based on the thermal profile,

it is necessary to accurately measure processor power dissipation. Intel has developed
a methodology for accurate power measurement that correlates to Intel test
temperature and voltage conditions. Refer to the Intel® Pentium® D Processor, Intel®

Datasheet 81
 Thermal Specifications and Design Considerations

Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and
Mechanical Design Guidelines and the Processor Power Characterization Methodology
for the details of this methodology.

The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 26 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor
feature must be enabled for the processor to remain within specification.

Table 26. Processor Thermal Specifications

Core Thermal
Minimum Maximum TC
Processor Number Frequency Design Notes
TC (°C) (°C)
(GHz) Power (W)

Extreme Edition 965 3.73 GHz 130 5 1, 2

1, 2
Extreme Edition 955 3.46 GHz 130 5
See Table 27 1, 2
960 3.60 GHz 130 5
and Figure 13
1, 2
950 3.40 GHz 130 5
1, 2
940 3.20 GHz 130 5
1, 2
960 3.60 GHz 95 5
1, 2
950/945 3.40 GHz 95 5
See Table 28 1, 2
940/935 3.20 GHz 95 5
and Figure 14
1, 2
930/925 3 GHz 95 5
1, 2
920/915 2.80 GHz 95 5
NOTES:
1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the
maximum power that the processor can dissipate.
2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP.
Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile
figure and associated table for the allowed combinations of power and TC.

82 Datasheet
Thermal Specifications and Design Considerations

Table 27. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)

Power Maximum Power Maximum Power Maximum Power Maximum
(W) TC (°C) (W) TC (°C) (W) TC (°C) (W) TC (°C)

0 43.9 34 50.4 68 56.8 102 63.3

2 44.3 36 50.7 70 57.2 104 63.7
4 44.7 38 51.1 72 57.6 106 64.0
6 45.0 40 51.5 74 58.0 108 64.4
8 45.4 42 51.9 76 58.3 110 64.8
10 45.8 44 52.3 78 58.7 112 65.2
12 46.2 46 52.6 80 59.1 114 65.6
14 46.6 48 53.0 82 59.5 116 65.9
16 46.9 50 53.4 84 59.9 118 66.3
18 47.3 52 53.8 86 60.2 120 66.7
20 47.7 54 54.2 88 60.6 122 67.1
22 48.1 56 54.5 90 61.0 124 67.5
24 48.5 58 54.9 92 61.4 126 67.8
26 48.8 60 55.3 94 61.8 128 68.2
28 49.2 62 55.7 96 62.1 130 68.6
30 49.6 64 56.1 98 62.5
32 50.0 66 56.4 100 62.9

Figure 13. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)

65.0

60.0

y = 0.19x + 43.9
Tcase (C)

55.0

50.0

45.0

40.0
0 10 20 30 40 50 60 70 80 90 100 110 120 130
Power (W)

Datasheet 83
 Thermal Specifications and Design Considerations

Table 28. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)

Maximum Maximum Maximum
Power (W) Power (W) Power (W)
TC (°C) TC (°C) TC (°C)

0 43.4 34 50.5 68 57.7

2 43.8 36 51.0 70 58.1
4 44.2 38 51.4 72 58.5
6 44.7 40 51.8 74 58.9
8 45.1 42 52.2 76 59.4
10 45.5 44 52.6 78 59.8
12 45.9 46 53.1 80 60.2
14 46.3 48 53.5 82 60.6
16 46.8 50 53.9 84 61.0
18 47.2 52 54.3 86 61.5
20 47.6 54 54.7 88 61.9
22 48.0 56 55.2 90 62.3
24 48.4 58 55.6 92 62.7
26 48.9 60 56.0 94 63.1
28 49.3 62 56.4 95 63.4
30 49.7 64 56.8
32 50.1 66 57.3

Figure 14. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)

65.0

60.0
Tcase (C)

55.0

y = 0.21x + 43.4

50.0

45.0

40.0
0 10 20 30 40 50 60 70 80 90
Power (W)

84 Datasheet
Thermal Specifications and Design Considerations

5.1.2 Thermal Metrology

The maximum and minimum case temperatures (TC) for the processor is specified in
Table 26. This temperature specification is meant to help ensure proper operation of
the processor. Figure 15 illustrates where Intel recommends TC thermal measurements
should be made. For detailed guidelines on temperature measurement methodology,
refer to the Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition,
and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines.
Figure 15. Case Temperature (TC) Measurement Location

Measure TC at this point

(geometric center of the package)
37.5 mm

37.5 mm

5.2 Processor Thermal Features

5.2.1 Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will
not be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief

Datasheet 85
 Thermal Specifications and Design Considerations

periods of TCC activation is expected to be so minor that it would be immeasurable. An

under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the Intel® Pentium® D Processor, Intel®
Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and
Mechanical Design Guidelines for information on designing a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.

5.2.2 On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor

IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.

5.2.3 PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#. Refer to the Intel Architecture Software Developer's Manuals
for specific register and programming details.

PROCHOT# can be configured via BIOS as an output or a bi-directional signal. As an

output, PROCHOT# (Processor Hot) will go active when the processor temperature
monitoring sensor detects that one or both cores has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit (TCC)
has been activated, if enabled. As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled, for both cores. The TCC will remain active until the system
de-asserts PROCHOT#.

If PROCHOT# is configured as an output only, the FORCEPR# signal can be driven from
an external source to activate the TCC. This will prevent one core from asserting the
PROCHOT# signal of the other core and unnecessarily activating the TCC of that core.
Refer to Chapter 5.2.4 for details on the FORCEPR# signal.

86 Datasheet
Thermal Specifications and Design Considerations

As a bi-directional signal, PROCHOT# allows for some protection of various components

from over-temperature situations. The PROCHOT# signal is bi-directional in that it can
either signal when the processor (either core) has reached its maximum operating
temperature or be driven from an external source to activate the TCC. The ability to
activate the TCC via PROCHOT# can provide a means for thermal protection of system
components.

Bi-directional PROCHOT# (if enabled) can allow VR thermal designs to target maximum
sustained current instead of maximum current. Systems should still provide proper
cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of
system cooling failure. The system thermal design should allow the power delivery
circuitry to operate within its temperature specification even while the processor is
operating at its Thermal Design Power. With a properly designed and characterized
thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted
for very short periods of time when running the most power intensive applications. An
under-designed thermal solution that is not able to prevent excessive assertion of
PROCHOT# in the anticipated ambient environment may cause a noticeable
performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for
Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature.

5.2.4 FORCEPR# Signal

The FORCEPR# (force power reduction) input can be used by the platform to cause the
processor (both cores) to activate the TCC. If the Thermal Monitor is enabled, the TCC
will be activated upon the assertion of the FORCEPR# signal. The TCC will remain active
until the system deasserts FORCEPR#. FORCEPR# is an asynchronous input.

FORCEPR# can be used to thermally protect other system components. To use the VR
as an example, when the FORCEPR# pin is asserted, the TCC circuit in the processor
(both cores) will activate, reducing the current consumption of the processor and the
corresponding temperature of the VR.

Note that assertion of the FORCEPR# does not automatically assert PROCHOT#. As
mentioned previously, the PROCHOT# signal is asserted when a high temperature
situation is detected. A minimum pulse width of 500 µs is recommend when the
FORCEPR# is asserted by the system. Sustained activation of the FORCEPR# pin may
cause noticeable platform performance degradation.

One application is the thermal protection of voltage regulators (VR). System designers
can create a circuit to monitor the VR temperature and activate the TCC when the
temperature limit of the VR is reached. By asserting FORCEPR# (pulled-low) and
activating the TCC, the VR can cool down as a result of reduced processor power
consumption. FORCEPR# can allow VR thermal designs to target maximum sustained
current instead of maximum current. Systems should still provide proper cooling for the
VR, and rely on FORCEPR# only as a backup in case of system cooling failure. The
system thermal design should allow the power delivery circuitry to operate within its
temperature specification even while the processor is operating at its Thermal Design
Power. With a properly designed and characterized thermal solution, it is anticipated
that FORCEPR# would only be asserted for very short periods of time when running the
most power intensive applications. An under-designed thermal solution that is not able
to prevent excessive assertion of FORCEPR# in the anticipated ambient environment
may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD)
10.1 Design Guide for Desktop Socket 775 for details on implementing the FORCEPR#
feature.

Datasheet 87
 Thermal Specifications and Design Considerations

5.2.5 THERMTRIP# Signal

Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic
cooling failure, the processor will automatically shut down when the silicon has reached
an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this
point, the FSB signal THERMTRIP# will go active and stay active as described in
Table 25. THERMTRIP# activation is independent of processor activity and does not
generate any bus cycles.

5.2.6 TCONTROL and Fan Speed Reduction

TCONTROL is a temperature specification based on a temperature reading from the
thermal diode. The value for TCONTROL will be calibrated in manufacturing and
configured for each processor. When TDIODE is above TCONTROL then TC must be at or
below TC-MAX as defined by the thermal profile in Table 27 and Figure 13; otherwise,
the processor temperature can be maintained at TCONTROL (or lower) as measured by
the thermal diode.

The purpose of this feature is to support acoustic optimization through fan speed
control. Contact your Intel representative for further details and documentation.

5.2.7 Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is
used as a thermal "diode", with its collector shorted to Ground. A thermal sensor
located on the system board may monitor the die temperature of the processor for
thermal management and fan speed control. Table 29,Table 30, Table 31 and Table 32
provide the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 29 and 30. The Diode Model parameters (Table 29) apply
to traditional thermal sensors that use the Diode Equation to determine the processor
temperature. Transistor Model parameters (Table 30) have been added to support
thermal sensors that use the transistor equation method. The Transistor Model may
provide more accurate temperature measurements when the diode ideality factor is
closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.

Table 29. Thermal “Diode” Parameters using Diode Model

Symbol Parameter Min Typ Max Unit Notes

IFW Forward Bias Current 5 — 200 µA 1

n Diode Ideality Factor 1.000 1.009 1.050 — 2, 3, 4
RT Series Resistance 2.79 4.52 6.24 Ω 2, 3, 5

NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized across a range of 50 – 80 °C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW = IS * (e qVD/nkT –1)
where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann
Constant, and T = absolute temperature (Kelvin).

88 Datasheet
Thermal Specifications and Design Considerations

5. The series resistance, RT, is provided to allow for a more accurate measurement of the
junction temperature. RT, as defined, includes the lands of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic
charge.

Table 30. Thermal “Diode” Parameters using Transistor Model

Symbol Parameter Min Typ Max Unit Notes

IFW Forward Bias Current 5 - 200 µA 1, 2

IE Emitter Current 5 200
nQ Transistor Ideality 0.997 1.001 1.005 - 3, 4, 5
Beta 0.391 0.760 3, 4
RT Series Resistance 2.79 4.52 6.24 Ω 3, 6

NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Same as IFW in Table 29
3. Characterizedacross a range of 50 – 80 °C.
4. Not 100% tested. Specified by design characterization.
5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qVBE/nQkT
–1)
Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter
junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin).
6. The series resistance, RT, provided in the Diode Model Table (Table 29) can be used for
more accurate readings as needed.

When calculating a temperature based on thermal diode measurements, a number of

parameters must be either measured or assumed. Most devices measure the diode
ideality and assume a series resistance and ideality trim value, although some are
capable of also measuring the series resistance. Calculating the temperature is then
accomplished using the equations listed under Table 29. In most temperature sensing
devices, an expected value for the diode ideality is designed-in to the temperature
calculation equation. If the designer of the temperature sensing device assumes a
perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes
are not perfect, the designers usually select an ntrim value that more closely matches
the behavior of the diodes in the processor. If the processors diode ideality deviates
from that of ntrim, each calculated temperature will be offset by a fixed amount. This
temperature offset can be calculated with the equation:

Terror(nf) = Tmeasured X (1 - nactual/ntrim)

Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured
ideality of the diode, and ntrim is the diode ideality assumed by the temperature
sensing device.

To improve the accuracy of diode based temperature measurements, a new register

containing Thermal Diode Offset data has been added to the processor. During
manufacturing each processor thermal diode will be evaluated for its behavior relative
to a theoretical diode. Using the equation above, the temperature error created by the
difference between ntrim and the actual ideality of the particular processor will be

Datasheet 89
 Thermal Specifications and Design Considerations

calculated. This Thermal Diode Offset value will be programmed into the new diode
correction MSR and when added to the Thermal Diode Base value can be used to
correct temperatures read by diode based temperature sensing devices.

If the ntrim value used to calculate the Thermal Diode Offset differs from the ntrim value
used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the
Thermal Diode Offset can be adjusted by calculating nactual and then recalculating the
offset using the actual ntrim as defined in the temperature sensor manufacturers'
datasheet.

The Diode_Base value and ntrim used to calculate the Diode_Correction_Offset are
listed in Table 31.

Table 31. Thermal “Diode” ntrim and Diode_Correction_Offset

Symbol Parameter Unit

ntrim Diode ideality used to calculate Diode_Offset 1.008

Diode_Base Diode Base 0 C

Table 32. Thermal Diode Interface

Signal
Signal Name Land Number
Description

THERMDA AL1 diode anode

THERMDC AK1 diode cathode

§ §§

90 Datasheet
Features

6 Features
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, please refer to Table 33.

The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.

Table 33. Power-On Configuration Option Signals

Configuration Option Signal1,2

Output tristate SMI#

Execute BIST INIT#
In Order Queue pipelining (set IOQ depth
A7#
to 1)
Disable MCERR# observation A9#
Disable BINIT# observation A10#
APIC Cluster ID (0–3) A[12:11]#
Disable bus parking A15#
Single Logical Processor Mode A31#3
Symmetric agent arbitration ID BR0#
RESERVED A[6:3]#, A8#, A[14:13]#, A[16:35]#

NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not be asserted
during RESET#.
3. This mode is not tested

6.2 Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 16 for a visual representation of the processor low
power states.

Datasheet 91
 Features

Figure 16. Processor Low Power State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated
Enhanced HALT or HALT State
Normal State INIT#, BINIT#, INTR, NMI, SMI#, BCLK running
Normal execution RESET#, FSB interrupts Snoops and interrupts allowed

rte K#
Snoop Snoop

se C L
d
As TP
STPCLK# STPCLK# Event Event

S
Asserted De-asserted Occurs Serviced

se #
d
as LK
rte
e- C
D TP
S
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches

Snoop Event Occurs

Stop Grant State Stop Grant Snoop State
BCLK running BCLK running
Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches

6.2.1 Normal State

This is the normal operating state for the processor.

6.2.2 HALT and Enhanced HALT Powerdown States

The processor supports the HALT or Enhanced HALT powerdown state. The Enhanced
HALT Powerdown state is configured and enabled via the BIOS. The Enhanced HALT
state must be enabled via the BIOS for the processor to remain within its
specifications.

The Enhanced HALT state is a lower power state as compared to the Stop Grant State.

6.2.2.1 HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the
HALT or MWAIT instructions. When one of the logical processors executes the HALT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to
immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.

92 Datasheet
Features

The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2 Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed
the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS.
When one of the logical processors executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating
point before entering the Enhanced HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the
processor exits the Enhanced HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.

6.2.3 Stop Grant State

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.

BINIT# will not be serviced while the processor is in Stop Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.

A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by
the processor, and only serviced when the processor returns to the Normal State. Only
one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

Datasheet 93
 Features

6.2.4 Enhanced HALT Snoop or HALT Snoop State,

Stop Grant Snoop State
The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT
state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State
entered will be the HALT Snoop State. Refer to the following sections for details on
HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State.

6.2.4.1 HALT Snoop State, Stop Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT Power Down state, as appropriate.

6.2.4.2 Enhanced HALT Snoop State

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT
state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID
operating point of the Enhanced HALT state.
While in the Enhanced HALT Snoop State, snoops are handled the same way as in the
HALT Snoop State. After the snoop is serviced the processor will return to the Enhanced
HALT state.

6.2.5 Enhanced Intel® SpeedStep® Technology

Enhanced Intel SpeedStep® technology enables the processor to switch between
frequency and voltage points, which may result in platform power savings. To support
this technology, the system must support dynamic VID transitions. Switching between
voltage/frequency states is software controlled.
Note: Not all processors are capable of supporting Enhanced Intel SpeedStep technology.
More details on which processor frequencies will support this feature will be provided in
future releases of the Intel® Pentium® D Processor 900 Sequence and Intel® Pentium®
Processor Extreme Edition 955, 965 Specification Update.
Enhanced Intel SpeedStep technology is a technology that creates processor
performance states (P states). P states are power consumption and capability states
within the Normal state as shown in Figure 16. Enhanced Intel SpeedStep technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. To
run at reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep technology:
• Voltage/Frequency selection is software controlled by writing to processor MSRs
(Model Specific Registers); thus, eliminating chipset dependency.
• If the target frequency is higher than the current frequency, Vcc is incriminated in
steps (+12.5 mV) by placing a new value on the VID signals and the processor
shifts to the new frequency. Note that the top frequency for the processor can not
be exceeded.
• If the target frequency is lower than the current frequency, the processor shifts to
the new frequency and VCC is then decremented in steps (-12.5 mV) by changing
the target VID through the VID signals.

§§

94 Datasheet
Boxed Processor Specifications

7 Boxed Processor Specifications

The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme
Edition 955, 965 will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators. Unless otherwise noted, all figures in
this chapter are dimensioned in millimeters and inches [in brackets]. Figure 17 shows a
mechanical representation of a boxed processor.

Note: Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the Intel® Pentium® D Processor, Intel® Pentium®
Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical
Design Guidelines for further guidance.
Figure 17. Mechanical Representation of the Boxed Processor

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

7.1 Mechanical Specifications

7.1.1 Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 17 shows a
mechanical representation of the boxed processor.

Datasheet 95
 Boxed Processor Specifications

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 18 (Side View), and Figure 19 (Top View).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 23 and Figure 24. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.

Figure 18. Space Requirements for the Boxed Processor (Side View: applies to all four
side views)

95.0
[3.74]

81.3
[3.2]

10.0 25.0
[0.39] [0.98]

B d P Sid Vi

Figure 19. Space Requirements for the Boxed Processor (Top View)

95.0
[3.74]

95.0
[3.74]

NOTES:
1. Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.

96 Datasheet
Boxed Processor Specifications

Figure 20. Space Requirements for the Boxed Processor (Overall View)

7.1.2 Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5
and the Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and
Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines for details on
the processor weight and heatsink requirements.

7.1.3 Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.

7.2 Electrical Requirements

7.2.1 Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 21. Baseboards
must provide a matched power header to support the boxed processor. Table 34
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open-collector output that pulses
at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.

The fan heatsink receives a PWM signal from the motherboard from the fourth pin of
the connector labeled as CONTROL.

Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.

Datasheet 97
 Boxed Processor Specifications

The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 22 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 4.33 inches from the center of the processor
socket.

Figure 21. Boxed Processor Fan Heatsink Power Cable Connector Description

Pin Signal Straight square pin, 4-pin terminal housing with

1 GND polarizing ribs and friction locking ramp.
2 +12 V
0.100" pitch, 0.025" square pin width.
3 SENSE
4 CONTROL Match with straight pin, friction lock header on
mainboard.

1 2 3 4

Table 34. Fan Heatsink Power and Signal Specifications

Description Min Typ Max Unit Notes

+12V: 12 volt fan power supply 10.2 12 13.8 V -

IC:
Peak Fan current draw — 1.1 1.5 A
-
Fan start-up current draw — — 2.2 A
Fan start-up current draw maximum duration — — 1.0 Second
pulses per
SENSE: SENSE frequency — 2 — fan 1
revolution
CONTROL 21 25 28 kHz 2,3

NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open Drain Type, Pulse Width Modulated.
3. Fan will have a pull-up resistor to 4.75 V, maximum is 5.25 V.

98 Datasheet
Boxed Processor Specifications

Figure 22. Baseboard Power Header Placement Relative to Processor Socket

R110
[4.33]
B

7.3 Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.

7.3.1 Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is found in Chapter 5 of this document. The boxed processor
fan heatsink is able to keep the processor temperature within the specifications (see
Table 26) in chassis that provide good thermal management. For the boxed processor
fan heatsink to operate properly, it is critical that the airflow provided to the fan
heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the
sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow
through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink
reduces the cooling efficiency and decreases fan life. Figure 23 and Figure 24 illustrate
an acceptable airspace clearance for the fan heatsink. The air temperature entering the
fan should be kept below 38 °C. A Thermally Advantaged Chassis with an Air Guide 1.1
is recommended to meet the 38 °C requirement. Again, meeting the processor's
temperature specification is the responsibility of the system integrator.

Note: The processor fan is the primary source of airflow for cooling the Vcc voltage regulator.
Dedicated voltage regulator cooling components may be necessary if the selected fan is
not capable of keeping regulator components below maximum rated temperatures.

Datasheet 99
 Boxed Processor Specifications

Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(Side 1 View)

Figure 24. Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(Side 2 View)

§§

100 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications

8 Balanced Technology Extended

(BTX) Boxed Processor
Specifications
The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme
Edition 955, 965 will be offered as an Intel boxed processor. Intel boxed processors are
intended for system integrators who build systems from largely standard components.
The boxed processor will be supplied with a cooling solution known as the Thermal
Module Assembly (TMA). Each processor will be supplied with one of the two available
types of TMAs — Type I or Type II. This chapter documents motherboard and system
requirements for both the TMAs that will be supplied with the boxed processor in the
775-land LGA package. This chapter is particularly important for OEMs that
manufacture motherboards for system integrators. Figure 25 shows a mechanical
representation of a boxed processor in the 775-land LGA package with a Type I TMA.
Figure 26 illustrates a mechanical representation of a boxed processor in the 775-land
LGA package with Type II TMA.

Note: Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets].

Note: Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the Intel® Pentium® D Processor, Intel® Pentium®
Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical
Design Guidelines for further guidance.

Figure 25. Mechanical Representation of the Boxed Processor with a Type I TMA

NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but
the basic shape and size will remain the same.

Datasheet 101
 Balanced Technology Extended (BTX) Boxed Processor Specifications

Figure 26. Mechanical Representation of the Boxed Processor with a Type II TMA

NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but
the basic shape and size will remain the same.

8.1 Mechanical Specifications

8.1.1 Balanced Technology Extended (BTX) Type I and Type II
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed Intel processor TMA.
The boxed processor will be shipped with an unattached TMA. Figure 27 shows a
mechanical representation of the boxed processor in the 775-land LGA package for
Type I TMA. Figure 28 shows a mechanical representation of the boxed processor in the
775-land LGA package for Type II TMA. The physical space requirements and
dimensions for the boxed processor with assembled fan thermal module are shown.

102 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications

Figure 27. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
Volumes

NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.

Datasheet 103
 Balanced Technology Extended (BTX) Boxed Processor Specifications

Figure 28. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
Volume

NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.

8.1.2 Boxed Processor Thermal Module Assembly Weight

The boxed processor thermal module assembly for Type I BTX will not weigh more than
1200 grams. The boxed processor thermal module assembly for Type II BTX will not
weigh more than 1200 grams. See Chapter 5 and the Intel® Pentium® D Processor,
Intel® Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal
and Mechanical Design Guidelines for details on the processor weight and thermal
module assembly requirements.

8.1.3 Boxed Processor Support and Retention Module (SRM)

The boxed processor TMA requires an SRM assembly provided by the chassis
manufacturer. The SRM provides the attach points for the TMA and provides structural
support for the board by distributing the shock and vibration loads to the chassis base
pan. The boxed processor TMA will ship with the heatsink attach clip assembly, duct
and screws for attachment. The SRM must be supplied by the chassis hardware vendor.

104 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications

See the Support and Retention Module (SRM) External Design Requirements
Document, Balanced Technology Extended (BTX) System Design Guide, and the Intel®
Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and Intel®
Pentium® 4 Processor Thermal and Mechanical Design Guidelines for more detailed
information regarding the support and retention module and chassis interface and
keepout zones. Figure 29 illustrates the assembly stack including the SRM.

Figure 29. Assembly Stack Including the Support and Retention Module

T he rm a l M od u le A ssem bly
• H ea tsin k & Fan
• C lip
• S tructural D uct

M othe rboard

SRM

C ha ssis P an

8.2 Electrical Requirements

8.2.1 Thermal Module Assembly Power Supply
The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power
supply. The TMA will include power cable to power the integrated fan and will plug into
the 4-wire fan header on the baseboard. The power cable connector and pinout are
shown in Figure 30. Baseboards must provide a compatible power header to support
the boxed processor. Table 35contains specifications for the input and output signals at
the TMA.

The TMA outputs a SENSE signal, which is an open- collector output that pulses at a
rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match
the system board-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should
be tied to GND.

The TMA receives a Pulse Width Modulation (PWM) signal from the motherboard from
the 4th pin of the connector labeled as CONTROL.

Datasheet 105
 Balanced Technology Extended (BTX) Boxed Processor Specifications

Note: The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not
support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the TMA power cable
to reach it. The power header identification and location should be documented in the
platform documentation, or on the system board itself. Figure 31 shows the location of
the fan power connector relative to the processor socket. The baseboard power header
should be positioned within 4.33 inches from the center of the processor socket.

Figure 30. Boxed Processor TMA Power Cable Connector Description

Pin Signal Straight square pin, 4-pin terminal housing with

1 GND polarizing ribs and friction locking ramp.
2 +12 V
0.100" pitch, 0.025" square pin width.
3 SENSE
4 CONTROL Match with straight pin, friction lock header on
mainboard.

1 2 3 4

Table 35. TMA Power and Signal Specifications

Description Min Typ Max Unit Notes

+12V: 12 volt fan power supply 10.2 12 13.8 V

IC:
Peak Fan current draw — 1.0 1.5 A
Fan start-up current draw — — 2.0 A
Fan start-up current draw maximum duration — — 1.0 Second
pulses per
SENSE: SENSE frequency — 2 — fan 1
revolution
CONTROL 21 25 28 KHz 2,3

NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open Drain Type, Pulse Width Modulated.
3. Fan will have a pull-up resistor to 4.75 V, maximum 5.25 V

106 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications

Figure 31. Balanced Technology Extended (BTX) Mainboard Power Header Placement
(Hatched Area)

8.3 Thermal Specifications

This section describes the cooling requirements of the thermal module assembly
solution used by the boxed processor.

8.3.1 Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a TMA. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
case temperature specification is in Chapter 5. The boxed processor TMA is able to
keep the processor temperature within the specifications in Table 26 for chassis that
provide good thermal management. For the boxed processor TMA to operate properly,
it is critical that the airflow provided to the TMA is unimpeded. Airflow of the TMA is into
the duct and out of the rear of the duct in a linear flow. Blocking the airflow to the TMA
inlet reduces the cooling efficiency and decreases fan life. Filters will reduce or impede
airflow which will result in a reduced performance of the TMA. The air temperature
entering the fan should be kept below 35.5°C. Again, meeting the processor's
temperature specification is the responsibility of the system integrator.

Datasheet 107
 Balanced Technology Extended (BTX) Boxed Processor Specifications

In addition, Type I TMA must be used with Type I chassis only and Type II TMA with
Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height
difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the
chassis will not seal against the Type II TMA and poor acoustic performance will occur
as a result.

8.3.2 Variable Speed Fan

The boxed processor fan will operate at different speeds over a short range of
temperatures based on a thermistor located in the fan hub area. This allows the boxed
processor fan to operate at a lower speed and noise level while thermistor
temperatures are low. If the thermistor senses a temperatures increase beyond a lower
set point, the fan speed will rise linearly with the temperature until the higher set point
is reached. At that point, the fan speed is at its maximum. As fan speed increases, so
do fan noise levels. These set points are represented in Figure 32 and Table 36. The
internal chassis temperature should be kept below 35.5ºC. Meeting the processor’s
temperature specification (see Chapter 5) is the responsibility of the system integrator.

Note: The motherboard must supply a constant +12 V to the processor’s power header to
ensure proper operation of the variable speed fan for the boxed processor (refer to
Table 36) for the specific requirements).

Figure 32. Boxed Processor TMA Set Points

Higher Set Point

Highest Noise Level

Increasing Fan
Speed & Noise

Lower Set Point

Lowest Noise Level

X Y Z

Internal Chassis Temperature (Degrees C)

108 Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications

Table 36. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed
Processors

Boxed Processor
TMA Set Point Boxed Processor Fan Speed Notes
(ºC)

When the internal chassis temperature is below or equal to this

set point, the fan operates at its lowest speed. Recommended
X ≤ 23 1
maximum internal chassis temperature for nominal operating
environment.
When the internal chassis temperature is at this point, the fan
operates between its lowest and highest speeds.
Y = 29
Recommended maximum internal chassis temperature for
worst-case operating environment.
When the internal chassis temperature is above or equal to this
Z ≥ 35.5 1
set point, the fan operates at its highest speed.

NOTES:
1. Set point variance is approximately ±1°C from Thermal Module Assembly to Thermal
Module Assembly.

If the boxed processor TMA 4-pin connector is connected to a 4-pin motherboard

header and the motherboard is designed with a fan speed controller with PWM output
(see CONTROL in Table 35) and remote thermal diode measurement capability, the
boxed processor will operate as described in the following paragraphs.

As processor power has increased, the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.

The 4-wire PWM controlled fan in the TMA solution provides better control over chassis
acoustics. It allows better granularity of fan speed and lowers overall fan speed than a
voltage-controlled fan. Fan RPM is modulated through the use of an ASIC located on
the motherboard that sends out a PWM control signal to the 4th pin of the connector
labeled as CONTROL. The fan speed is based on a combination of actual processor
temperature and thermistor temperature.

If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard
processor fan header it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.

For more details on specific motherboard requirements for 4-wire based fan speed
control see the Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme
Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines.

§§

Datasheet 109
 Balanced Technology Extended (BTX) Boxed Processor Specifications

110 Datasheet
Debug Tools Specifications

9 Debug Tools Specifications

9.1 Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging processor systems. Tektronix and Agilent should be
contacted to get specific information about their logic analyzer interfaces. The following
information is general in nature. Specific information must be obtained from the logic
analyzer vendor.

Due to the complexity of the processor systems, the LAI is critical in providing the
ability to probe and capture FSB signals. There are two sets of considerations to keep in
mind when designing a processor system that can make use of an LAI: mechanical and
electrical.

9.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI lands plug
into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processor heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.

9.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.

§§

Datasheet 111
 Debug Tools Specifications

112 Datasheet