NCP1631

Interleaved, 2-Phase Power

Factor Controller
The NCP1631 integrates a dual MOSFET driver for interleaved
PFC applications. Interleaving consists of paralleling two small
stages in lieu of a bigger one, more difficult to design. This approach
has several merits like the ease of implementation, the use of smaller www.onsemi.com
components or a better distribution of the heating.
Also, Interleaving extends the power range of Critical Conduction
MARKING DIAGRAM
Mode that is an efficient and cost−effective technique (no need for
low trr diodes). In addition, the NCP1631 drivers are 180° phase shift
for a significantly reduced current ripple. NCP1631G
SOIC−16
Housed in a SOIC16 package, the circuit incorporates all the AWLYWW
D SUFFIX
features necessary for building robust and compact interleaved PFC CASE 751B
stages, with a minimum of external components. A = Assembly Location
WL = Wafer Lot
General Features Y = Year
• Near−Unity Power Factor WW = Work Week
G = Pb−Free Package
• Substantial 180° Phase Shift in All Conditions Including Transient
Phases PIN ASSIGNMENT
• Frequency Clamped Critical Conduction Mode (FCCrM) i.e., ZCD2 ZCD1
Fixed Frequency, Discontinuous Conduction Mode Operation with 1
FB REF5V/pfcOK
Critical Conduction Achievable in Most Stressful Conditions
Rt DRV1
• FCCrM Operation Optimizes the PFC Stage Efficiency Over the
OSC GND
Load Range
Vcontrol Vcc
• Out−of−phase Control for Low EMI and a Reduced rms Current in
FFOLD DRV2
the Bulk Capacitor
BO Latch
• Frequency Fold−back at Low Power to Further Improve the Light
OVP / UVP CS
Load Efficiency
(Top View)
• Accurate Zero Current Detection by Auxiliary Winding for Valley
Turn On ORDERING INFORMATION
• Fast Line / Load Transient Compensation Device Package Shipping†
• High Drive Capability: −500 mA / +800 mA NCP1631DR2G SOIC−16 2500 / Tape & Reel
• Signal to Indicate that the PFC is Ready for Operation (“pfcOK” (Pb−Free)
Pin) †For information on tape and reel specifications,
• VCC Range: from 10 V to 20 V including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Safety Features
• Output Over and Under Voltage Protection Typical Applications
• Brown−Out Detection with a 50−ms Delay to Help • Computer Power Supplies
Meet Hold−up Time Specifications • LCD / Plasma Flat Panels
• Soft−Start for Smooth Start−up Operation • All Off Line Appliances Requiring Power Factor
• Programmable Adjustment of the Maximum Power Correction
• Over Current Limitation
• Detection of Inrush Currents

*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

March, 2019 − Rev. 8 NCP1631/D
 NCP1631

Vin

Vout Vaux2 Icoil1 L2

Rzcd2
Rbo1 Rovp1 Rout1 L1 Vaux2
1 16 Rzcd1 D1 Icoil2
Rout2
2 15 Vout
pfcOK
3 14 D2
M1
OVPin Cosc Rt 4 13
5 12 LOAD
Vcc M2
Ac lin e Ccomp2 RFF 6 11
Rbo2 Rovp2 Rcomp1
7 10
EMI 8 9
Filter Cbo2 Ccomp1 Cbulk
Cin OVPin Rocp
RCS

Iin
Figure 1. Typical Application Schematic

Table 1. MAXIMUM RATINGS

Symbol Rating Pin Value Unit
VCC(MAX) Maximum Power Supply Voltage Continuous 12 −0.3, +20 V
DRVMAX Maximum Voltage on DRV Pins 11, 14 −0.3 V, VCC V
VMAX Maximum Input Voltage on Low Power Pins 1, 2, 3, 4, 6, 7, −0.3, +9.0 V
8, 9, 10, 15,
and 16
VControl(MAX) VControl Pin Maximum Input Voltage 5 −0.3, VControl(clamp) (Note 1) V
Power Dissipation and Thermal Characteristics
PD Maximum Power Dissipation @ TA = 70°C 550 mW
RqJ−A Thermal Resistance Junction−to−Air 145 °C/W
TJ Operating Junction Temperature Range −55 to +150 °C
TJ(MAX) Maximum Junction Temperature 150 °C
TS(MAX) Storage Temperature Range −65 to +150 °C
TL(MAX) Lead Temperature (Soldering, 10s) 300 °C
ESD Capability, HBM model (Note 2) 3 kV
ESD Capability, Machine Model (Note 2) 250 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. “VControl(clamp)” is the pin5 clamp voltage.
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

www.onsemi.com
2
 NCP1631

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics Test Conditions Symbol Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage V
Startup Threshold VCC increasing VCC(on) 11 11.85 12.7
Minimum Operating Voltage VCC decreasing VCC(off) 9.5 10 10.5
Hysteresis VCC(on) – VCC(off) VCC(hyst) 1.5 1.85 −
Internal Logic Reset VCC decreasing VCC(reset) 4.0 5.75 7.5
Startup current VCC = 9.4 V ICC(start) − 35 100 mA
Supply Current mA
Device Enabled/No output load on pin6 Fsw = 130 kHz (Note 4) ICC1 − 5.0 7.0
Current that discharges VCC in latch mode VCC = 15 V, Vpin10 = 5 V ICC(latch) – 0.4 0.8
Current that discharges VCC in OFF VCC = 15 V, pin 7 grounded ICC(off) − 0.4 0.8
mode
OSCILLATOR AND FREQUENCY FOLDBACK
Clamping Charging Current Pin 6 open IOSC(clamp) mA
TJ = −40°C to +125°C 31.5 35 38.5
TJ = −55°C to +125°C (Note 6) 30 35 38.5
Charge Current with no frequency foldback Pin 6 grounded IOSC(CH1) mA
TJ = −40°C to +125°C 126 140 154
TJ = −55°C to +125°C (Note 6) 120 140 154
Charge Current @ Ipin6 = 50 mA Ipin6 = 50 mA IOSC(CH2) 76.5 85 93.5 mA
Maximum Discharge Current Pin 6 grounded IOSC(DISCH1) mA
with no frequency foldback TJ = −40°C to +125°C 94.5 105 115.5
TJ = −55°C to +125°C (Note 6) 90 105 115.5
Discharge Current @ Ipin6 = 50 mA Ipin6 = 50 mA IOSC(DISCH2) 45 50 55 mA
Voltage on pin 6 Ipin6 = 50 mA, Vpin5 = 2.5 V VFF 0.9 1.0 1.3 V
Oscillator Upper Threshold VOSC(high) − 5 − V
Oscillator Lower Threshold VOSC(low) 3.6 4.0 4.4 V
Oscillator Swing (Note 5) VOSC(swing) 0.93 0.98 1.03 V
CURRENT SENSE
Current Sense Voltage Offset Ipin9 = 100 mA VCS(TH100) −20 0 20 mV
Ipin9 = 10 mA VCS(TH10) −10 0 10
Current Sense Protection Threshold TJ = 25°C IILIM1 202 210 226 mA
TJ = −40°C to 125°C 194 210 226
TJ = −55°C to +125°C (Note 6) 173 210 226
Threshold for In−rush Current Detection TJ = −40°C to +125°C Iin−rush 11 14 17 mA
(Note 5) TJ = −55°C to +125°C 10.4 14 17

GATE DRIVE (Note 7)

Drive Resistance Ω
DRV1 Sink Ipin14 = 100 mA RSNK1 – 7 15
DRV1 Source Ipin14 = −100 mA RSRC1 – 15 25
DRV2 Sink Ipin11 = 100 mA RSNK2 – 7 15
DRV2 Source Ipin11 = −100 mA RSRC2 – 15 25
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
7. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.

www.onsemi.com
3
 NCP1631

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics Test Conditions Symbol Min Typ Max Unit
GATE DRIVE (Note 7)
Drive Current Capability (Note 5) mA
DRV1 Sink VDRV1 = 10 V ISNK1 − 800 −
DRV1 Source VDRV1 = 0 V ISRC1 − 500 −
DRV2 Sink VDRV2 = 10 V ISNK1 − 800 −
DRV2 Source VDRV2 = 0 V ISRC1 − 500 −
Rise Time ns
DRV1 CDRV1 = 1 nF, VDRV1 = 1 to 10 V tr1 − 40 −
DRV2 CDRV2 = 1 nF, VDRV2 = 1 to 10 V tr2 − 40 −
Fall Time ns
DRV1 CDRV1 = 1 nF, VDRV1 = 10 to 1 V tf1 – 20 –
DRV2 CDRV2 = 1 nF, VDRV2 = 10 to 1 V tf2 – 20 –
REGULATION BLOCK
Feedback Voltage Reference VREF 2.44 2.500 2.56 V
Error Amplifier Source Current Capability @ Vpin2 = 2.4 V IEA(SRC) −20 mA
Error Amplifier Sink Current Capability @ Vpin2 = 2.6 V IEA(SNK) +20
Error Amplifier Gain GEA 110 200 290 mS
Pin 5 Source Current when (Vout(low) TJ = −40°C to 125°C IControl(boost) 184 230 276 mA
Detect) is activated TJ = −55°C to +125°C (Note 6) 178 230 276 mA

Pin2 Bias Current Vpin2 = 2.5 V IFB(bias) −500 500 nA

Pin 5 Voltage: @ Vpin2 = 2.4 V VControl(clamp) 3.0 3.6 4.2 V
@ Vpin2 = 2.6 V VControl(MIN) 0 0.6 1.2
VControl(range) 2.7 3 3.3
Internal VREGUL Voltage @ Vpin2 = 2.6 V, Ipin6 = 90 mA VREGUL(MIN) − − 0.1 V
(measured on pin 6): @ Vpin2 = 2.4 V, Ipin6 = 90 mA VREGUL(Clamp) − 1.66 −
Ratio (Vout(low) Detect Threshold / VREF) FB falling Vout(low)/VREF 95.0 95.5 96.0 %
(Note 5)
Ratio (Vout(low) Detect Hysteresis / FB rising Hout(low)/VREF − − 0.5 %
VREF) (Note 5)

SKIP MODE
Duty Cycle Vpin2 = 3 V DMIN − − 0 %
RAMP CONTROL (valid for the two phases)
Maximum DRV1 and DRV2 On−Time Vpin7 = 1.1 V, Ipin3 = 50 mA ton1 14.5 19.5 22.5 ms
(FB pin grounded) Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5) ton2 1.10 1.35 1.60
TJ = −25°C to +125°C
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5) ton3 4.00 5.00 6.00
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5) ton4 0.35 0.41 0.48

Maximum DRV1 and DRV2 On−Time Vpin7 = 1.1 V, Ipin3 = 50 mA ton1 14.0 19.5 22.5 ms
(FB pin grounded) Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5) ton2 1.05 1.35 1.60
TJ = −40°C to +125°C
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5) ton3 3.84 5.00 6.00
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5) ton4 0.33 0.41 0.48

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
7. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.

www.onsemi.com
4
 NCP1631

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics Test Conditions Symbol Min Typ Max Unit
RAMP CONTROL (valid for the two phases)
Maximum DRV1 and DRV2 On−Time Vpin7 = 1.1 V, Ipin3 = 50 mA (Note 6) ton1 13.0 19.5 22.5 ms
(FB pin grounded) Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5) ton2 1.00 1.35 1.60
TJ = −55°C to +125°C
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5) ton3 3.70 5.00 6.00
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5) ton4 0.32 0.41 0.48

Pin 3 voltage VBO = Vpin7 = 1.1 V, Ipin3 = 50 mA VRt1 1.071 1.096 1.121 V
VBO = Vpin7 = 1.1 V, Ipin3 = 200 mA VRt2 1.071 1.096 1.121
VBO = Vpin7 = 2.2 V, Ipin3 = 50 mA VRt3 2.169 2.196 2.223
VBO = Vpin7 = 2.2 V, Ipin3 = 200 mA VRt4 2.169 2.196 2.223

Maximum Vton Voltage Not tested Vton(MAX) 5 V

Pin 3 Current Capability IRt(MAX) 1 − − mA
Pin 3 sourced current below which the IRt(off) 7 mA
controller is OFF

Pin 3 Current Range Not tested IRt(range) 20 1000 mA

ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2)
ZCD Threshold Voltage VZCD increasing VZCD(TH),H 0.40 0.50 0.60 V
VZCD falling VZCD(TH),L 0.20 0.25 0.30
ZCD Hysteresis VZCD decreasing VZCD(HYS) 0.25 V
Input Clamp Voltage V
High State Ipin1 = 5.0 mA VZCD(high) 9.0 11 13
Low State Ipin1 = −5.0 mA VZCD(low) −1.1 −0.65 −0.1
Internal Input Capacitance (Note 5) CZCD − 10 − pF
ZCD Watchdog Delay tZCD 80 200 320 ms
BROWN−OUT DETECTION
Brown−Out Comparator Threshold VBO(TH) 0.97 1.00 1.03 V
Brown−Out Current Source TJ = −40°C to 125°C IBO 6 7 8 mA
TJ = −55°C to +125°C (Note 6) 5.7 7 8

Brown−Out Blanking Time (Note 5) TJ = −40°C to 125°C tBO(BLANK) 38 50 62 ms

TJ = −55°C to +125°C 38 50 63.5

Brown−Out Monitoring Window (Note 5) tBO(window) 38 50 62 ms

Pin 7 clamped voltage if VBO < VBO(TH) Ipin7 = −100 mA VBO(clamp) − 965 − mV
during tBO(BLANK)

Current Capability of the BO Clamp IBO(clamp) 100 − − mA

Hysteresis VBO(TH) – VBO(clamp) Ipin7 = − 100 mA VBO(HYS) 10 35 60 mV
Current Capability of the BO pin Clamp IBO(PNP) 100 − − mA
PNP Transistor

Pin BO voltage when clamped by the PNP Ipin7 = − 100 mA VBO(PNP) 0.35 0.70 0.90 V
OVER AND UNDER VOLTAGE PROTECTIONS
Over−Voltage Protection Threshold VOVP 2.425 2.500 2.575 V
Ratio (VOVP / VREF) (Note 5) VOVP/VREF 99.2 99.7 100.2 %
Ratio UVP Threshold over VREF VUVP/VREF 8 12 16 %
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
7. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.

www.onsemi.com
5
 NCP1631

Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics Test Conditions Symbol Min Typ Max Unit
OVER AND UNDER VOLTAGE PROTECTIONS
Pin 8 Bias Current Vpin8 = 2.5 V IOVP(bias) −500 − 500 nA
Vpin8 = 0.3 V
LATCH INPUT
Pin Latch Threshold for Shutdown VLatch 2.375 2.500 2.625 V
Pin Latch Bias Current Vpin10 = 2.3 V ILatch(bias) −500 − 500 nA
pfcOK / REF5V
Pin 15 Voltage Low State Vpin7 = 0 V, Ipin15 = 250 mA VREF5V(low) − 60 120 mV
Pin 15 Voltage High State Vpin7 = 0 V, Ipin15 = 5 mA VREF5V(high) 4.7 4.85 5.3 V
Current Capability IREF5V 5 10 − mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSHDN 130 140 150 °C
Thermal Shutdown Hysteresis TSHDN(HYS) − 50 − °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
7. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.

www.onsemi.com
6
 NCP1631

Table 3. DETAILED PIN DESCRIPTION

Pin Number Name Function
1 ZCD2 This is the zero current detection pin for phase 2 of the interleaved PFC stage. Apply the voltage
from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET
drain source voltage
2 FB This pin receives a portion of the pre−converter output voltage. This information is used for the reg-
ulation and the “output low” detection (VOUTL) that drastically speed−up the loop response when the
output voltage drops below 95.5% of the wished level.
3 RT The resistor placed between pin 3 and ground adjusts the maximum on−time of our system for both
phases, and hence the maximum power that can be delivered by the PFC stage.

4 OSC Connect a capacitor to set the clamp frequency of the PFC stage. If wished, this frequency can be
reduced in light load as a function of the resistor placed between pin 6 and ground (frequency
fold−back). If the coil current cycle is longer than the selected switching period, the circuit delays
the next cycle until the core is reset. Hence, the PFC stage can operate in Critical Conduction Mode
in the most stressful conditions.
5 VControl The error amplifier output is available on this pin. The capacitor connected between this pin and
ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power
Factor ratios.
Pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly
(soft−start).
6 Freq. Foldback Apply a resistor between pin 6 and ground to adjust the oscillator charge current. Clamped not to
exceed 100 mA, this charge current is made proportional to the power level for a reduced switching
frequency at light load and an optimum efficiency over the load range.
7 BO Apply an averaged portion of the input voltage to detect brown−out conditions when Vpin2 drops
(Brown−out below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time re-
Protection) quirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the
“pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated
to offer a programmable hysteresis.
The pin2 voltage is internally re−used for feed−forward.
Grounding pin 7 disables the part (after the 50−ms blanking time has elapsed).
8 OVP / UVP The circuit turns off when Vpin9 goes below 480 mV (UVP) and disables the drive as long as the pin
voltage exceeds 2.5 V (OVP).

9 CS This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the
maximum coil current and protect the PFC stage in presence of in−rush currents.

10 Latch Apply a voltage higher than 2.5 V to latch−off the circuit. The device is reset by unplugging the PFC
stage (practically when the circuit detects a brown−out detection) or by forcing the circuit VCC below
VCCRST (4 V typically). Operation can then resume when the line is applied back.
11 DRV2 This is the gate drive pin for phase 2 of the interleaved PFC stage. The high current capability of the
totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power
MOSFETs.
12 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V and
turns off when VCC goes below 10 V (typical values). After start−up, the operating range is 9.5 V up
to 20 V.
13 GND Connect this pin to the pre−converter ground.
14 DRV1 This is the gate drive pin for phase 1 of the interleaved PFC stage. The high current capability of the
totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power
MOSFETs.
15 REF5V / The pin15 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low
pfcOK otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and
that hence, it can start operation.
16 ZCD1 This is the zero current detection pin for phase 1 of the interleaved PFC stage. Apply the voltage
from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET
drain source voltage.

www.onsemi.com
7
 NCP1631

Vref
pfcOK Internal
Vout low 230 mA Thermal VD D
detect Shutdown Regul Vcc
VD D
−
TS D Iref
0.955*Vref SHDN
+

Error Amplifier UVP

Vcc_OK
FB −±20 mA BO_NOK
Vref
+ IRt_low
Vcc(on)
OVLflag1 Vcc(off)
UVLO
Vcontrol
SK I P
OF F ( 0.6 V cl amp vo ltag e Fault OF F VBOcomp
BO_NOK
i s acti vated) management
5R OC P
STOP Brown−out
VREGUL detection with BO
50−ms delay
pfcOK 3V 4R OVP VBO
In−rush
IFF SKIP
OFF CLK2 Vcc
Generation of the oscillator
charge current IFF as a DT Vton In−rush
S DRV2
FFOLD function of VREGUL VBOcomp processing Q
circuitry Vpwm2 Lpwm2
(frequency fold−back) pfcOK
R Ou tpu t
STOP Buffer 2
IRt < 7 mA IRt_low DRV1 DRV2 Vton
CLK1 Vcc
In−rush
Generation of the charge S
ICH On−time control Vpwm1 Q DRV1
Rt current for the internal for the two Vpwm1 Lpwm1
timing capacitors (max phases Vpwm2 R
on−time setting for the Ou tpu t
two phases) STOP Buffer 1
CLK1
Oscillator block
VBO VDMG2 with interleaving and In−rush
CLK2 OSC
frequency foldback
Zero current VZCD2
ZCD2 detection for
phase 2 VZCD1 VZCD2
DRV2 IFF
All the RS latches are
RESET dom inant
REF5V
VDMG1
VZCD1 pfcOK
Stup OFF
Zero current pfcOK/
DT
ZCD1 detection for OFF S REF5V
phase 1 DRV1 Lstup Q
OVLflag1 R

Current Sense Block

− UVP (Building of ICS
OVP proportional to ICOIL)
12% Vr ef
+
OC P
ICS > 210 mA Ics
+ OVP
Vovp = Vref − In−rush
− CS
ICS > 14 mA +
BO_NOK
Vcc_OK QZCD1
Vcc < Vcc(r eset) QZCD2
R SHDN DRV1
L SHDN Q DRV2
Vr ef −
GND
S
Latch
+

Figure 2. Functional Block Diagram

www.onsemi.com
8
 NCP1631

Detailed Operating Description A “pfcOK” signal.

The NCP1631 integrates a dual MOSFET driver for The circuit detects when the PFC stage is in steady state
interleaved, 2−phase PFC applications. It drives the two or if on the contrary, it is in a start−up or fault condition. In
branches in so−called Frequency Clamped Critical the first case, the “pfcOK” pin (pin15) is in high state and
conduction Mode (FCCrM) where each phase operates in low otherwise. This signal is to disable the downstream
Critical conduction Mode (CrM) in the most stressful converter unless the bulk capacitor is charged and no fault
conditions and in Discontinuous Conduction Mode (DCM) is detected. Finally, the downstream converter can be
otherwise, acting as a CrM controller with a frequency optimally designed for the narrow voltage provided by the
clamp (given by the oscillator). According to the PFC stage in normal operation.
conditions, the PFC stage actually jumps from DCM to
Safety Protections.
CrM (and vice versa) with no discontinuity in operation and
The NCP1631 permanently monitors the input and
without degradation of the current shape.
Furthermore, the circuit incorporates protection features output voltages, the input current and the die temperature
to protect the system from possible over−stresses and make
for a rugged operation together with some special circuitry
the PFC stage extremely robust and reliable. In addition to
to lower the power consumed by the PFC stage in no−load
the aforementioned OVP protection, one can list:
conditions. More generally, the NCP1631 is ideal in
systems where cost−effectiveness, reliability, low stand−by Maximum Current Limit: the circuit permanently
power and high power factor are the key parameters: senses the total input current and prevents it
from exceeding the preset current limit, still
Fully Stable FCCrM and Out−Of−Phase Operation. maintaining the out−of−phase operation.
Unlike master/slave controllers, the NCP1631 utilizes an
In−rush Detection: the NCP1631 prevents the
interactive−phase approach where the two branches
power switches turn on for the large in−rush
operate independently. Hence, the two phases necessarily
currents sequence that occurs during the
operate in FCCrM, preventing risks of undesired start−up phase.
dead−times or continuous conduction mode sequences. In
addition, the circuit makes them interact so that they run Under−Voltage Protection: this feature is mainly to
out−of−phase. The NCP1631 unique interleaving prevent operation in case of a failure in the
technique substantially maintains the wished 180° phase OVP monitoring network (e.g., bad
shift between the 2 branches, in all conditions including connection).
start−up, fault or transient sequences. Brown−Out Detection: the circuit stops operating if
the line magnitude is too low to protect the
Optimized Efficiency Over The Full Power Range. PFC stage from the excessive stress that could
The NCP1631 optimizes the efficiency of your PFC damage it in such conditions.
stage in the whole line/load range. Its clamp frequency is
Thermal Shutdown: the circuit stops pulsing when
a major contributor at nominal load. For medium and light
its junction temperature exceeds 150°C
load, the clamp frequency linearly decays as a function of
typically and resumes operation once it drops
the power to maintain high efficiency levels even in very
below about 100°C (50°C hysteresis).
light load. The power threshold under which frequency
reduces is programmed by the resistor placed between pin NCP1631 Operating Modes
6 and ground. To prevent any risk of regulation loss at no The NCP1631 drives the two branches of the interleaved
load, the circuit further skips cycles when the error in FCCrM where each phase operates in Critical
amplifier reaches its low clamp level. conduction Mode (CrM) in the most stressful conditions
and in Discontinuous Conduction Mode (DCM) otherwise,
Fast Line / Load Transient Compensation.
acting as a CrM controller with a frequency clamp (given
Characterized by the low bandwidth of their regulation
by the oscillator). According to the conditions, the PFC
loop, PFC stages exhibit large over and under−shoots when
stage actually jumps from DCM to CrM (and vice versa)
abrupt load or line transients occur (e.g. at start−up). The
with no discontinuity in operation and without degradation
NCP1631 dramatically narrows the output voltage range.
of the current shape.
First, the controller dedicates one pin to set an accurate
The circuit can also transition within an ac line cycle so
Over−Voltage Protection level and interrupts the power
that:
delivery as long as the output voltage exceeds this
threshold. Also, the NCP1631 dynamic response enhancer • CrM reduces the current stress around the sinusoid top.
drastically speeds−up the regulation loop when the output • DCM limits the frequency around the line zero
voltage is 4.5% below its desired level. As a matter of fact, crossing.
a PFC stage provides the downstream converter with a very This capability offers the best of each mode without the
narrow voltage range. drawbacks. The way the circuit modulates the MOSFET
on−time allows this facility.

www.onsemi.com
9
 NCP1631

Figure 3. DCM and CRM Operation Within a Sinusoid Cycle for One Branch

NCP1631 On−time Modulation The NCP1631 operates in voltage mode. As portrayed by

Let’s study the ac line current absorbed by one phase of Figure 6, the MOSFET on time t1 is controlled by the signal
the interleaved PFC converter. Vton generated by the regulation block as follows:
The current waveform of the inductor (L) during one C tVTON
switching period (Tsw) is portrayed by Figure 5. t1 + (eq. 2)
It
The ac line current is the averaged value of the coil
current as the result of the EMI filter “polishing” action. Where:
Hence, the line current produced by one of the phase is: • Ct is the internal timing capacitor
ǒ Ǔǒt T) t ǓV
t
Iin + 1 1
2 L
1
sw
2
in
(eq. 1)
• It is the internal current source for the timing capacitor.
The It charge current is constant for a given resistor
placed on the Rt pin. Ct is also a constant. Hence, the
Where (Tsw = t1 + t2 + t3) is the switching period and Vin
condition
is the ac line rectified voltage.
Equation 1 shows that Iin is proportional to Vin if ǒt (tT) t )Ǔ
1 1
sw
2

ǒ Tsw
Ǔ
t1(t 1 ) t2)
is a constant. to be a constant for proper power factor correction can be
changed into:
Forcing ǒt (tT) t )Ǔ
1 1
sw
2
ǒ VTON(t 1 ) t2)
Ǔ is constant.
T sw
constant is what the NCP1631 does to perform FCCrM
operation that is, to operate in discontinuous or critical The output of the regulation block (VCONTROL) is
conduction mode according to the conditions, without linearly changed into a signal (VREGUL) varying between
degradation of the power factor. 0 and 1.66 V. (VREGUL) is the voltage that is injected into
the PWM section to modulate the MOSFET duty−cycle.
However, the NCP1631 inserts some circuitry that
processes (VREGUL) to form the signal (VTON) that is used
in the PWM section instead of (VREGUL) (see Figure 7).
(VTON) is modulated in response to the dead−time sensed
during the precedent current cycles, that is, for a proper
shaping of the ac line current. This modulation leads to:
T swVREGUL t1 ) t2
VTON + or: VTON + VREGUL (eq. 3)
Figure 4. Boost Converter t1 ) t2 Tsw
Substitution of Equation 3 into Equation 2 leads to the
following on−time expression:

Ctǒ TswVREGUL
t1)t2
Ǔ
t1 + (eq. 4)
It
Replacing “t1” by its expression of Equation 4,
Equation 1 simplifies as follows:
V in C tVREGUL
Iin(phase1) + I in(phase2) + (eq. 5)
2L It
Figure 5. Inductor Current in DCM

www.onsemi.com
10
 NCP1631

Given the regulation low bandwidth of the PFC systems, From this equation, we can check that if Vpin7 (BO
(VCONTROL) and then (VREGUL) are slow varying signals. voltage) is 1 V and Rt is 20 kW (Ipin3 = 50 mA) that the
Hence, the line current absorbed by each phase is: on−time is 20 ms as given by parameter Ton1.
Iin(phase1) + I in(phase2) + k V in (eq. 6) Since:

where: k + constant + ƪ ƫ
C tVREGUL
2 L It
VREGUL(max) + 1.66 V
C tVREGUL
Ton +
It
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped. 2 Ǹ2 Vin(rms)
Vpin7 + p k BO
One can note that this analysis is also valid for CrM
operation that is just a particular case of this functioning where kBO is the scale down factor of the BO sensing
where (t3=0), which leads to (t1+t2=Tsw) and network
(VTON=VREGUL). That is why the NCP1631 automatically
adapts to the conditions and jumps from DCM and CrM
(and vice versa) without power factor degradation and
ǒ k BO +
R bo2
R bo1 ) R bo2
Ǔ
without discontinuity in the power delivery.
(see Brown−out section)
The charging current It is internally processed to be
We can deduce the total input current value and the
proportional to the square of the line magnitude. Its value
average input power:
is however programmed by the pin 3 resistor to adjust the
available on−time as defined by the Ton1 to Ton4 parameters (R t)2V REGUL
Iin(rms) ^ (eq. 8)
of the data sheet. 26.9 @ 10 12 L k BO 2V in,rms
From these data, we can deduce:
(Rt)2V REGUL
Rt 2 Pin,avg ^ (eq. 9)
t1 + T on(ms) + 50 n (eq. 7) 26.9 @ 10 12 L k BO 2
Vpin7 2

timing capacitor PWM

s aw −too th comparator
+ to PWM latch
−

VREGUL Vton
OA1
+
R1 SKIP
−
S3 OV P
C1
OF F
OC P
0.5* VBOcomp
(I se nse (from BO block)
IN 1
− 210 m)
S1 pfcOK
−> V ton d u ring (t1+t2) S2 In−rus h
−> 0 V d u ring t3 (d e a d −time) DT
−> V ton *(t1+t2)/T in average (high during dead−time)

The integrator OA1 amplifies the error between VREGUL and

IN1 so that in average, (VTON*(t1+t2)/Tsw) equates VREGUL.

Figure 6. PWM Circuit and Timing Diagram Figure 7. VTON Processing Circuit

The “VTON processing circuit” is “informed” when there The output of the “VTON processing circuit” is also
is an OVP condition or a skip sequence, not to grounded when the circuit is in OFF state to discharge the
over−dimension VTON in that conditions. Otherwise, an capacitor C1 and initialize it for the next active phase.
OVP sequence or a skipped cycle would be viewed as a Finally, the “VTON” is not allowed to be further increased
“normal” dead−time phase by the circuit and VTON would compared to VREGUL when the circuit has not completed
inappropriately increase to compensate it. (Refer to the start−up phase (pfcOK low) and if VBOcomp from the
Figure 7). brown−out block is high (refer to brown−out section for
more information).

www.onsemi.com
11
 NCP1631

350,00 3,50

300,00 3,00

250,00 2,50

200,00 2,00

Ton (ms)
Vin (V)

150,00 1,50

100,00 1,00
Vin
50,00 ton 0,50

0,00 0,00
0 2 4 6 8 10 12 14 16 18 20
time (ms)
Figure 8. Input Voltage and On−time vs. Time (example with FSW = 100 kHz, Pin = 150 W, VAC = 230 V, L = 200 mH)

Regulation Block and Low Output Voltage Detection The swing of the error amplifier output is limited within
A trans−conductance error amplifier with access to the an accurate range:
inverting input and output is provided. It features a typical • It is forced above a voltage drop (VF) by the “low
trans−conductance gain of 200 mS and a typical capability clamp” circuitry. When this circuitry is activated, the
of ±20 mA. The output voltage of the PFC stage is typically power demand is minimum and the NCP1631 enters
scaled down by a resistors divider and monitored by the skip mode (the controller stops pulsating) until the
inverting input (feed−back pin – pin2). The bias current is clamp is no more active.
minimized (less than 500 nA) to allow the use of a high
• It is clamped not to exceed 3.0 V + the same VF
impedance feed−back network. The output of the error
voltage drop.
amplifier is pinned out for external loop compensation
(pin5). Typically a type−2 compensator is applied between Hence, Vpin5 features a 3 V voltage swing. Vpin5 is then
pin5 and ground, to set the regulation bandwidth below offset down by (VF) and further divided before it connects
20 Hz, as need in PFC applications (refer to application to the “Vton processing block” and the PWM section.
note AND8407). Finally, the output of the regulation is a signal (“VREGUL”
of the block diagram) that varies between 0 and 1.66 V.

pfcOK 230 m A
Vout low
detect
VDD
−

0.955*Vref
+

FB E rr o r Am p lifier
− ±20 m A
Vref
+

V control OVLflag1

OFF SKIP (0 .6 V c lamp

5R vo ltage is activated)

VREGUL
3V 4R

Figure 9. Regulation Block Figure 10. Correspondence Between

VCONTROL and VREGUL

www.onsemi.com
12
 NCP1631

Provided the low bandwidth of the regulation loop, sharp Zero Current Detection
variations of the load, may result in excessive over and While the on time is constant, the core reset time varies
under−shoots. Over−shoots are limited by the Over− with the instantaneous input voltage. The NCP1631
Voltage Protection (see OVP section). To contain the determines the demagnetization completion by sensing the
under−shoots, an internal comparator monitors the inductor voltage, more specifically, by detecting when the
feed−back signal (Vpin2) and when Vpin2 is lower than inductor voltage drops to zero.
95.5% of its nominal value, it connects a 230 mA current Practically, an auxiliary winding in flyback
source to speed−up the charge of the compensation configuration is taken off of the boost inductor and gives a
capacitor (Cpin5). Finally, it is like if the comparator scaled down version of the inductor voltage that is usable
multiplied the error amplifier gain by 10. by the controller (Figure 12). In that way, the ZCD voltage
One must note that this circuitry for under−shoots (“VAUX”) falls and starts to ring around zero volts when the
limitation, is not enabled during the start−up sequence of inductor current drops to zero. The NCP1631 detects this
the PFC stage but only once the converter has stabilized falling edge and allows the next driver on time.
(that is when the “pfcOK” signal of the block diagram, is Figure 1 shows how it is implemented.
high). This is because, at the beginning of operation, the For each phase, a comparator detects when the voltage
pin5 capacitor must charge slowly and gradually for a soft of the ZCD winding exceeds 0.5 V. When this is the case,
start−up. the coil is in demagnetization phase and the latch LZCD is
set. This latch is reset when the next driver pulse occurs.

Rzcd2

Rzcd1
1 ZCD2 16 ZCD1 D1
Vin
L1
VDMG1 AND1
Vzcd1 PWM
+ SET1 latch
Qzcd1 PH1 Vcc
Negative Negative − S
Q DRV1
LZCD S
and and QZCD Q
positive positive 0.5 V R CLK1 14 M1
R
clamp clamp (from phase
In−rush output
management buffe r 1
block)
200−ms
reset signal
delay S DT (from PH1 PWM
Q D2 Vout
comparator)
OFF R
(from Fault Vin L2
management
VDMG2 Vzcd2 PWM output
block)
SET2 buffe r 2
+ latch PH2
Vcc DRV2
− S Qzcd2 S
Q Q Cbulk
CLK2 Cbulk
R R 11 M2
0.5 V (from phase
management In−rush reset signal
block) (from PH2 PWM comparator)

Figure 11. Zero Current Detection

To prevent negative voltages on the ZCD pins (ZCD1 for At startup or after an inactive period (because of a
phase 1 and ZCD2 for phase 2), these pins are internally protection that has tripped for instance), there is no energy
clamped to about 0 V when the voltage applied by the in the ZCD winding and therefore no voltage signal to
corresponding ZCD winding is negative. Similarly, the activate the ZCD comparator. This means that the driver
ZCD pins are clamped to VZCD(high) (10 V typical), when will never turn on. To avoid this, an internal watchdog
the ZCD voltage rises too high. Because of these clamps, timer is integrated into the controller. If the driver remains
a resistor (RZCD of Figure 11) is necessary to limit the low for more than 200 ms (typical), the timer sets the LZCD
current from the ZCD winding to the ZCD pin. The clamps latch as the ZCD winding signal would do. Obviously, this
are designed to respectively source and sink 5 mA 200−ms delay acts as a minimum off−time if there is no
minimum. It is recommended not to exceed this 5 mA level demagnetization winding while it has no action if there is
within the ZCD clamps for a proper operation. a ZCD voltage provided by the auxiliary winding.

www.onsemi.com
13
 NCP1631

Figure 12. Zero Current Detection Timing Diagram

(VAUX is the Voltage Provided by the ZCD Winding)

Current Sense not to sink more than 5 mA from the CS pin for a proper
The NCP1631 is designed to monitor a negative voltage operation.
proportional to total input current, i.e., the current drawn by Two functions use ICS: the over current protection and
the two interleaved branches (Iin). As portrayed by the in−rush current detection.
Figure 13, a current sense resistor (RCS) is practically
inserted within the return path to generate a negative Over−Current Protection (OCP)
voltage (VCS) proportional to Iin. The circuit uses VCS to If ICS exceeds IILIM1 (210 mA typical), an over−current
detect when Iin exceeds its maximum permissible level. To is detected and the on−time is decreased proportionally to
do so, the circuit incorporates an operational amplifier that the difference between the sensed current IIN and the
sources the current necessary to maintain the CS pin 210 mA OCP threshold.
voltage null (refer to Figure 13). By inserting a resistor The on−time reduction is done by injecting a current Ineg
ROCP between the CS pin and RCS, we adjust the current in the negative input of the “VTON processing circuit”
that is sourced by the CS pin (ICS) as follows: OPAMP. (See Figure 7)
* [R CSICOIL] ) [ROCPI CS] + 0 (eq. 10) Ineg + 0.5(I CS * 210 m) (eq. 12)

Which leads to: This current is injected each time the OCP signal is high.
RCS The maximum coil current is:
ICS + I (eq. 11)
R OCP
R OCP COIL
ICOIL(max) + I (eq. 13)
In other words, the pin 9 current (ICS) is proportional to RCS ILIM1
the coil current.
A negative clamp protects the circuit from the possible In−rush Current Detection
negative voltage that can be applied to the pin. This When the PFC stage is plugged to the mains, the bulk
protection is permanently active (even if the circuit off). capacitor is abruptly charged to the line voltage. The
The clamp is designed to sustain 5 mA. It is recommended charge current (named in−rush current) can be very huge

www.onsemi.com
14
 NCP1631

depending on the presence or absence of an effective MOSFETs from the possible excessive stress it could suffer
in−rush limiting circuitry. If the MOSFET turns on during from if it was allowed to turn on while a huge current
this severe transient, it may be over−stressed and finally flowed through the coil as it can be the case at start−up or
damaged. That is why, the NCP1631 permanently monitors during an over−load transient.
the input current and delays the MOSFET turn on until the The propagation delay (ICS < Iin−rush) to (drive outputs
in−rush current has vanished. This is the function of the ICS high) is in the range of few ms.
comparison to the Iin−rush threshold (14 mA typical). When However when the circuit starts to operate, the NCP1631
ICS exceeds Iin−rush, the comparator output (“In−rush”) is disables this protection to avoid that the current produced
high and prevents the PWM latches from setting (see block by one phase and sensed by the circuit prevents the other
diagram). Hence, the two drivers cannot turn high and the branch from operating. Practically, some logic grounds the
MOSFETs cannot switch on. This is to guarantee that the In−rush protection output when it detects the presence of
MOSFETs remain off as long as if the input current exceeds current cycles with a zero current detection signal provided
10% of its maximum value. This feature protects the by the auxiliary winding (Figure 13).
Vaux2
VIN IIN D2 VOUT
EMI
Filter Vaux1 L2
D1
Ac lin e

Curr e nt ICS OC P
CIN Mirror L1
IILIM1 = 210 mA

The pin voltage M2

ICS (ICS is proportional to the coil current)
is maintained ICS (from ZCD DRV 2
to 0 V ICS block) M1
CS In−r ush
QZCD1
ICS 9 DRV 1 CBULK
Iin−rush = 14 mA QZCD2
Negative clamp

LOAD
DRV 1
DRV 2
ROCP

RCS IIN
The CS block performs the over−current protection and the in−rush current detection.
Figure 13. Current Sense Block

Over−Voltage Protection
While PFC circuits often use one single pin for both the allows the implementation of two separate feed−back
Over−Voltage Protection (OVP) and the feed−back, the networks (see Figure 15):
NCP1631 dedicates one specific pin for the under−voltage 1. One for regulation applied to pin 2.
and over−voltage protections. The NCP1631 configuration 2. Another one for the OVP function (pin 8).

Vout (bulk voltage) Vout (bulk voltage)

Rout1 Rout1
1 16 1 16
FB FB 2
15 15
2
3 14 3 14
Rout3 Rovp1 Rout2
4 13 4 13

5 12 5 12

6 11 6 11
Rout2 Rovp2
7 10 7 10
OVP OVP
9 9
8 8

Figure 14. Configuration with One Feed−back Figure 15. Configuration with Two
Network for Both OVP and Regulation Separate Feed−back Networks

www.onsemi.com
15
 NCP1631

The double feed−back configuration offers some should be used to allow operation of the downstream
up−graded safety level as it protects the PFC stage even if converter.
there is a failure of one of the two feed−back arrangements.
However, if wished, one single feed−back arrangement Oscillator Section – Phase Management
is possible as portrayed by Figure 14. The regulation and The oscillator generates the clock signal that dictates the
OVP blocks having the same reference voltage, the maximum switching frequency for the global system (fosc).
resistance ratio Rout2 over Rout3 adjusts the OVP threshold. In other words, each of the two interleaved branches cannot
More specifically, operate above the clamp frequency that is half the oscillator
frequency (fosc/2). The oscillator frequency (fosc) is
The bulk regulation voltage (“Vout(nom)”) is: adjusted by the capacitor applied to pin 4. Typically, a
R out1 ) R out2 ) R out3 440 pF capacitor approximately leads to a 120−kHz
Vout(nom) + @ V ref (eq. 14)
R out2 ) R out3 operating frequency, meaning a 60−kHz clamp frequency
for each branch. The oscillator frequency should be kept
The OVP level (“Vout(ovp)”) is:
below 500 kHz (which corresponds to a pin4 capacitor in
R out1 ) R out2 ) R out3 the range of 100 pF).
Vout(ovp) + @ V ref (eq. 15)
R out2 As shown by Figure 16, two current sources IOSC(clamp)
The ratio OVP level over regulation level is: (35 mA typical) and IOSC(CH) (105 mA typical) charge the
pin 4 capacitor until its voltage exceeds VOSC(high) (5 V
Vout(ovp) Rout3
+1) (eq. 16) typically). At that moment, the output of the COMP_OSC
Vout(nom) Rout2 comparator (“SYNC” of Figure 16) turns high and changes
For instance, (Vout(nom) = 105% x Vout(nom)) leads to: the COMP_OSC reference threshold that drops from
(Rout3 = 5% x Rout2). VOSC(high) down to VOSC(low) (hysteresis). The system
When the circuit detects that the output voltage exceeds enters a discharge phase where the ICH current source is
the OVP level, it maintains the power switch open to stop disabled and instead a sink current IOSC(DISCH) (105 mA
the power delivery. typ.) discharges the pin 4 capacitor. This sequence lasts
As mentioned previously, the “VTON processing circuit” until Vpin4 goes below VOSC(low) when the “SYNC” signal
is “informed” when there is an OVP condition, not to turns low and a new charging phase starts. A divider by two
over−dimension VTON in that conditions. Otherwise, an uses the “SYNC” information to manage the phases of the
OVP sequence would be viewed as a dead−time phase by interleaved PFC: the first SYNC pulse sets “phase 1”, the
the circuit and VTON would inappropriately increase to second one, “phase 2”, the third one phase 1 again... etc...
compensate it (refer to Figure 7). According to the selected phase, the “SYNC” signal sets
the relevant “Clock generator latch” that will generate the
PfcOK / REF5V Signal clock signal (“CLK1” for phase 1, “CLK2” for phase 2)
The NCP1631 can communicate with the downstream when SYNC drops to zero (falling edge detector). So, the
converter. The signal “pfcOK/REF5V” is high (5 V) when drivers are synchronized to SYNC falling edge.
the PFC stage is in normal operation (its output voltage is Actually, the drivers cannot turn on at this very moment
stabilized at the nominal level) and low otherwise. if the demagnetization of the coil is not yet complete (CrM
More specifically, “pfcOK/REF5V” is low: operation). In this case, the clock signal is maintained high
− During the PFC stage start−up, that is, as long as until the driver turns high (the clock generator latches are
the output voltage has not yet stabilized at the reset by the corresponding driver is high − reset on rising
right level. The start−up phase is detected by edge detector). Also, the discharge time can be prolonged
the latch “LSTUP” of the block diagram in if when Vpin4 drops below VOSC(low), the driver of the
Figure 2. “LSTUP” is set during each “off” phase cannot turn on because the core is not reset yet (CrM
phase so that its output (“STUP“) is high when operation). In this case, Vpin4 decreases until the driver
the circuit enters an active phase. The latch is turns high. The further discharge of Vpin4 below VOSC(low)
reset when the error amplifier stops charging helps maintain a substantial 180° phase shift in CrM that is
its output capacitor, that is, when the output in essence, guaranteed in DCM. In the two conditions (CrM
voltage of the PFC stage has reached its or DCM), operation is stable and robust.
desired regulation level. At that moment, Figure 17 portrays the clock signal waveforms in
“STUP” falls down to indicate the end of the different cases:
start−up phase. − In fixed frequency operation (DCM), the cycle
− Any time, the circuit is off or a fault condition is time of the coil current is shorter than an
detected as described by the “Fault oscillator period. Hence, as soon as the clock
management and OFF mode” section signal goes high, the driver can turn on and
Finally, “pfcOK/REF5V” is high when the PFC output reset the clock generator latch. The clock
voltage is properly and safely regulated. “pfcOK/REF5V” signal is then a short pulse.

www.onsemi.com
16
 NCP1631

− However, the coil current can possibly be non current has totally vanished. In other words,
zero when the clock signal turns high. The critical conduction mode (CrM) operation is
circuit would enter Continuous Conduction obtained.
Mode (CCM) if the MOSFET turned on in that The clamp frequency can be computed using the
moment. In order to avoid CCM operation, the following equation:
clock is prevented from setting the PWM latch 60 m
until the core is reset (that is as low as “VZCD” fosc ^ (eq. 17)
C OSC ) 10 p
of Figure 8 is low). The clock signal remains
high during this waiting phase (refer to where COSC is the pin 4 external capacitor and Cpin the pin
Figure 12). Hence the next MOSFET 4 parasitic capacitance (about 10 pF).
conduction time occurs as soon as the coil

105 mA
Current
FFOLD IFF Mirror

VREGUL
RFF
VREGUL
IFF
pfcOK

Circuitry for
Frequency Foldback

SYNCbar CL K1
DRV 1

SYNCbar R
CLK1
IOSC(CH) = IFF IOSC(clamp) Ge nera tion
latch
Q_ph1
OS C Co mp _OSC Q
SYNC S

COSC
P h ase1

VOSC(high)/
VOSC(low) DRV 2

divider
by tw o R Q_ph2

IOSC(DISCH) = IFF CLK2

Ge nera tion
latch
P hase2

Q CL K2
S
Q_ph2
Q_ph1
SYNCbar

Figure 16. Oscillator Block

www.onsemi.com
17
 NCP1631

Figure 17. Typical Waveforms (Tdelay not shown here for the sake of simplicity)

Frequency Foldback “VREGUL” is the signal derived from Vcontrol that is

In addition, the circuit features the frequency fold−back effectively used to modulate the MOSFET on−time.
function to improve the light load efficiency. Practically, VREGUL is buffered and applied to pin 6 (“Frequency
the oscillator charge and discharge currents (IOSC(CH) and fold−back” pin). A resistor RFF is to be connected to pin 6
IOSC(DISCH) of Figure 16) are not constant but dependent on to sink a current proportional to VREGUL

ǒ Ǔ
the power level. More specifically, IOSC(CH) and
V REGUL
IOSC(DISCH) linearly vary as a function of Vcontrol output of Ipin6 + I FF + .
R FF
the regulation block that thanks to the feed−forward
featured by the NCP1631, is representative of the load. This current is clamped not to exceed 105 mA and copied
The practical implementation is portrayed by Figure 16. by a current mirror to form IOSC(CH) and IOSC(DISCH).
As a matter of fact, the oscillator charge current is:

IOSC(CH) + I OSC(clamp) )
V REGUL
R FF
if ǒ VREGUL
RFF
Ǔ
v 105 mA
(eq. 18)

IOSC(CH) + I OSC(clamp) ) I OSC(CH1) + I OSC(CHT1) + 140 mA otherwise

The oscillator charge current is then an increasing function of VREGUL and is clamped to 140 mA.
The oscillator discharge current is:

IOSC(DISCH) +
V REGUL
R FF
if ǒ VREGUL
RFF
Ǔ
v 105 mA
(eq. 19)

IOSC(DISCH) + I OSC(DISCH1) + 105 mA otherwise

The oscillator discharge current is also an increasing value for (IFF = 105 mA). If we consider the clamp
function of VREGUL and is clamped to105 mA. frequency fOSC computed by Equation 17 as the nominal
As a consequence, the clamp frequency is also an value obtained at full load and if we name it “fOSC(nom)”:
increasing function of VREGUL until it reaches a maximum

www.onsemi.com
18
 NCP1631

fOSC + f OSC(nom) if ǒVREGUL w R FF @ 105 mAǓ

(eq. 20)
VREGUL(R FFIOSC(clamp) ) VREGUL)
fOSC + @ f OSC(nom) if ǒVREGUL v R FF @ 105 mAǓ
60 m R FF(RFFI OSC(clamp) ) 2V REGUL)
Let’s illustrate this operation on an example. If one decides to start to reduce the clamp frequency
VREGUL is the control signal that varies between 0 and when the power goes below (Pin)HL/2, the oscillator charge
1.66 V, (VREGUL = 1.66 V) corresponding to the maximum current should start to decrease when VREGUL is 0.83 V.
power (Pin)HL that can virtually be delivered by the PFC Hence, the pin 6 resistor (“RFF”) must be selected so that
stage as selected by the timing resistor (for more details, pin 6 sources 105 mA when VREGUL equates 0.83 V:
you can refer to the application note AND8407). 0.83 V
RFF + + 7.9 kW (eq. 21)
105 mA
Let’s take (RFF = 8.2 kW) which is a normalized value.
This selection leads to:
fOSC + f OSC(nom) if ǒVREGUL w 8.2 k @ 105 m + 860 mVǓ
(eq. 22)
V REGUL(RFFI OSC(clamp) ) V REGUL)
fOSC + @ f OSC(nom) if ǒVREGUL v 860 mVǓ
492 m(RFFI OSC(clamp) ) 2V REGUL)
For instance, if the nominal frequency (fOSC(nom)) is 120 kHz, the following characteristic is obtained.

150

100
fOSC(nom) = 120 kHz
Fosc (kHz)

50

0
0 0.5 1 1.5
VREGUL (V)
Figure 18. Fold−back Characteristic of the Clamp Frequency with RFF = 8.2 kW and fOSC(nom) = 120 kHz

If pin6 is grounded (accidently or not), the circuit operates A transistor pulls the pin 6 down during startup to disable
properly with a constant 140 mA oscillator charge current and the frequency fold−back function.
a 105 mA discharge current. The clamp frequency equates its
nominal value over the whole load range. Skip Mode
If pin6 is open, the oscillator charge current is equal to The circuit features the frequency fold−back that leads to
IOSC(clamp) but the oscillator discharge current is null and a very efficient stand−by mode. In order to ensure a proper
hence the PFC stage cannot operate. regulation in no load conditions even if this feature is not
A minimum discharge current and hence a minimum used (pin 6 grounded), the circuit skips cycles when the
clamp frequency can be forced by placing a resistor error amplifier output is at its minimum level. The error
between pin 4 and ground. For instance, a 1.5−MW resistor amplifier output is maintained between about 0.6 V and
forces a 3.3−mA discharge current when the oscillator 3.6 V thanks to active clamps. A skip sequence occurs as
capacitor is fully charged and about 2.6 mA when it is near long as the 0.6 V clamp circuitry is triggered and switching
the oscillator low threshold (4 V). operation is recovered when the clamp is inactive.

www.onsemi.com
19
 NCP1631

Brown−Out Protection
The brown−out pin receives a portion of the input voltage (VIN). As VIN is a rectified sinusoid, a capacitor must integrate
the ac line ripple so that a voltage proportional to the average value of (VIN) is applied to the brown−out pin.

IRt_ low
IRt < 7 mA Current M irror

Rt IRt
VBO
RRt
Vin VBO IRt

Feed−forward
Ac line
circuitry

EM I Rbo1
Filter Cin 1V VBOcomp BO_NOK
BO s1

Tdelay
RCS Cbo Rbo2 S
s2 50-ms 50-ms
LBO Q delay delay
Vdd R This voltage
980 mV reset res et
(“VBOcomp”) is
7 mA Clamp high when Vpin7
This PNP transistor
maintains the BO pin is below 1 V
below the BO threshold
when the circuit is not fed Ci r c uitr y fo r
enough to control the brown−out detection
state of the BO block
Figure 19. Brown−out Block

The main function of the BO block is to detect too low can be detected. This is the role of the second 50−ms timer
input voltage conditions. A 7−mA current source lowers the of Figure 19:
BO pin voltage when a brown−out condition is detected. • if the output of OPAMP is high at the end of the first
This is for hysteresis purpose as required by this function. delay (50−ms blanking time) and before the second
In nominal operation, the voltage applied to pin7 must be 50−ms delay time is elapsed, a brownout condition is
higher than the 1 V internal voltage reference. In this case, detected
the output of the comparator BO_Comp (VBOcomp) is low • if the output of OPAMP remains low for the duration
(see Figure 19). of the second delay, no fault is detected.
Conversely, if Vpin7 goes below 1 V, the BO_Comp
output turns high and a 965 mV voltage source is connected When the “BO_NOK” signal is high:
to the BO pin to maintain the pin level near 1 V. Then, a − The drivers are disabled, the “Vcontrol” pin is
50−ms blanking delay is activated during which no fault is grounded to recover operation with a soft−start
detected. The main goal of the 50−ms lag is to help meet when the fault has gone and the “pfcOK”
the hold−up requirements. In case of a short mains voltage turns low to disable the downstream
interruption, no fault is detected and hence, the “pfcOK” converter.
signal remains high and does not disable the downstream − The OPAMP output is separated from pin7
converter. In addition, pin7 being kept at 965 mV, there is (Figure 19) to prevent the operational
almost no extra delay between the line recovery and the amplifier from maintaining 1 V on pin7 (as
occurrence of a proper voltage applied to pin2, that done by the switches s1 and s2 in the
otherwise would exist because of the large capacitor representation of Figure 19). Instead, Vpin2
typically placed between pin7 and ground to filter the input drops to the value that is externally forced (by
voltage ripple. As a result, the NCP1631 effectively Vin, Rbo1, Rbo2 and Cbo2 in Figure 19). As a
“blanks” any mains interruption that is shorter than 25 ms consequence, the OPAMP output remains high
(minimum guaranteed value of the 50−ms timer). and the “BO_NOK” signal stays high until the
At the end of this 50−ms blanking delay, another timer is line recovers.
activated that sets a 50−ms window during which a fault

www.onsemi.com
20
 NCP1631

− The 7−mA current source is enabled that lowers temperature exceeds 140°C typically. The output stage is
the pin7 voltage for hysteresis purpose. then enabled once the temperature drops below about 80°C
A short delay (Tdelay) is added to get sure that these three (60°C hysteresis).
actions are properly done before the PFC driver is disabled The temperature shutdown keeps active as long as the
and the “Vcontrol” and “pfcOK” pins are grounded. circuit is not reset, that is, as long as VCC keeps higher than
At startup (and in UVLO situations that is when the Vcc VCCRESET. The reset action forces the TSD threshold to
voltage is not sufficient for operation), a pnp transistor be the upper one (140°C). This ensures that any cold
ensures that the BO pin voltage remains below the 1 V start−up will be done with the right TSD level.
threshold until VCC reaches VCC(on). This is to guarantee
that the circuit starts operation in the right state, that is, Under−Voltage Lockout Section
“BONOK” high. When VCC exceeds VCC(on), the pnp The NCP1631 incorporates an Under−Voltage Lockout
transistor turns off and the circuit enables the 7−mA current block to prevent the circuit from operating when the power
source (IBO). supply is not high enough to ensure a proper operation. An
Also, (IBO) is enabled whenever the part is in off−mode, UVLO comparator monitors the pin 12 voltage (VCC) to
but at startup, IBO is disabled until VCC reaches VCC(on). allow the NCP1631 operation when VCC exceeds 12 V
typically. The comparator incorporates some hysteresis
Brown−out Resistors Calculation (2.0 V typically) to prevent erratic operation as the VCC
The BO resistors can be calculated with the following crosses the threshold. When VCC goes below the UVLO
equations (for more details, refer to the application note comparator lower threshold, the circuit turns off.
AND8407) The circuit off state consumption is very low: < 50 mA.
This low consumption enables to use resistors to charge
ȡ ȡ f10 ȣȣ line
the VCC capacitor during the start−up without the penalty
(V in,avg)boH *ȧ(V ȧ1 * 3f ȧȧ
in,avg) boL of a too high dissipation.
Ȣ Ȣ ȤȤline

Output Drive Section

Rbo1 + (eq. 23)
IHYST The circuit embeds two drivers to control the two
Rbo1
interleaved branches. Each output stage contains a totem
Rbo2 + (eq. 24) pole optimized to minimize the cross conduction current
ǒ (Vin,avg)boL
VBO(th)
ǒ f
1 * BO
3fline
ǓǓ *1
during high frequency operation. The gate drive is kept in
a sinking mode whenever the Under−Voltage Lockout
(UVLO) is active or more generally whenever the circuit
is off. Its high current capability (−500 mA/+800 mA)
Feed−forward
allows it to effectively drive high gate charge power
As shown by Figure 19, The BO circuit also generates an
MOSFET.
internal current proportional to the input voltage average
value (IRt). The pin7 voltage is buffered and made available Reference Section
on pin 3. Placing a resistor between pin 3 and ground, The circuit features an accurate internal reference
enables to adjust a current proportional to the average input voltage (VREF). VREF is optimized to be ±2.4% accurate
voltage. This current (IRt) is internally copied and squared over the temperature range (the typical value is 2.5 V).
to form the charge current for the timing capacitor of each VREF is the voltage reference used for the regulation and
phase. Since this current is proportional to the square of the the over−voltage protection. The circuit also incorporates
line magnitude, the conduction time is made inversely a precise current reference (IREF) that allows the
proportional to the line magnitude. This feed−forward Over−Current Limitation to feature a ±6% accuracy over
feature makes the transfer function and the power delivery the temperature range.
independent of the ac line level. Only the regulation output
(VREGUL) controls the power amount. If the IRt current is Fault Management and OFF Mode
too low ( below 7 mA), the controller goes in OFF mode to The circuit detects a fault if the Rt pin is open (Figure 20).
avoid damaging the MOSFETs with too long conduction Practically, if the pin sources less than 7 mA, the “IRt_Low”
time. signal sets a latch that turns off the circuit if its output
(Rt(open)) is high. A 30−ms blanking time avoids parasitic
Thermal Shutdown (TSD) fault detections. The latch is reset when the circuit is in
An internal thermal circuitry disables the circuit gate UVLO state (too low VCC levels for proper operation).
drive and then keeps the power switch off when the junction

www.onsemi.com
21
 NCP1631

Internal Vref
Thermal
Shutdown
VDD Vcc
TSD Regul
Iref
Stdwn
UVP

Vcc_OK
BO_NOK UVLO

12 V / 10 V
Rt(open)
Q R

30−ms IRt_Low
S blanking (Ipin3 < 7 mA)
time
OF F
Fault
management

Figure 20. Fault Management Block

When any of the following faults is detected: − The pin5 capacitor (Vcontrol) is discharged and kept
− brown−out (“BO_NOK”) grounded along the OFF time, to initialize it for the
− Under−Voltage Protection (“UVP”) next operating sequence, where it must be slowly and
− Latch−off condition (“Stdwn”) gradually charged to offer some soft−start.
− Die over−temperature (“TSD”) − The “pfcOK” pin is grounded.
− Too low current sourced by the Rt pin (“Rt(open)”) − The output of the “VTON processing block” is
− “UVLO” (improper Vcc level for operation) grounded
The circuit turns off. In this mode, the controller stops When the circuit recovers after a fault, the first watchdog
operating. The major part of the circuit sleeps and its time is around 20 ms instead of 200 ms to allow a faster
consumption is minimized (< 500 mA). More specifically, re−start.
when the circuit is in OFF state: In OFF mode at startup, the consumption is very low (<
− The two drive outputs are kept low 50 mA). The brown−out block is initialized not to allow
− The 7−mA current source of the brown−out block is operation (“BO_NOK” high) by default. The PNP clamp is
enabled to set the proper start−up BO threshold if Vcc active and maintains the BO pin level below 1 V. The 7−mA
is high enough for proper operation. If not, the current source is enabled only when VCC reaches VCC(on)
brown-out pin is pulled down by a pnp transistor for a threshold.
proper input voltage sensing when the circuit recovers
operation (see brown-out section).

www.onsemi.com
22
 NCP1631

Figure 21. Start−up and Brown Out Conditions

www.onsemi.com
23
 NCP1631

PACKAGE DIMENSIONS

SOIC−16
CASE 751B−05
ISSUE K
−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
−B− P 8 PL SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 8
0.25 (0.010) M B S PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F
K R X 45 _ F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
C K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
−T− SEATING P 5.80 6.20 0.229 0.244
PLANE
M J R 0.25 0.50 0.010 0.019
D 16 PL

0.25 (0.010) M T B S A S

SOLDERING FOOTPRINT
8X
6.40
16X 1.12
1 16

16X
0.58

1.27
PITCH

8 9

DIMENSIONS: MILLIMETERS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent− Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your loca
Email: orderlit@onsemi.com Sales Representative

◊ www.onsemi.com NCP1631/D
24