INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4516B
MSI
Binary up/down counter
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
DESCRIPTION Information on P0 to P3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
The HEF4516B is an edge-triggered synchronous
MR which must be LOW. When PL and CE are LOW, the
up/down 4-bit binary counter with a clock input (CP), an
counter changes on the LOW to HIGH transition of CP.
up/down count control input (UP/DN), an active LOW
Input UP/DN determines the direction of the count, HIGH
count enable input (CE), an asynchronous active HIGH
for counting up, LOW for counting down. When counting
parallel load input (PL), four parallel inputs (P0 to P3), four
up, TC is LOW when O0 and O3 are HIGH and CE is LOW.
parallel outputs (O0 to O3), an active LOW terminal count
When counting down, TC is LOW when O0 to O3 and
output (TC), and an overriding asynchronous master reset
CE are LOW. A HIGH on MR resets the counter (O0 to
input (MR).
O3 = LOW) independent of all other input conditions.
Fig.2 Pinning diagram.
HEF4516BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4516BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4516BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Fig.1 Functional diagram.
PINNING
PL parallel load input (active HIGH)
P0 to P3 parallel inputs
CE count enable input (active LOW)
CP clock pulse input (LOW to HIGH,
edge triggered)
UP/DN up/down count control input
MR master reset input
TC terminal count output (active LOW)
O0 to O3 parallel outputs
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995 2
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995 3
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995 4
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
FUNCTION TABLE
MR PL UP/DN CE CP MODE
L H X X X parallel load
L L X H X no change
L L L L count down
L L H L count up
H X X X X reset
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
Fig.5 State diagram.
Logic equation for terminal count:
TC = CE ⋅ { ( UP/DN ) ⋅ O 0 ⋅ O 1 ⋅ O 2 ⋅ O 3 + UP/DN ⋅ O 0 ⋅ O 1 ⋅ O 2 ⋅ O 3 }
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 1000 fi + ∑ (foCL) × VDD2 where
dissipation per 10 4500 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz)
package (P) 15 11 200 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995 5
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD TYPICAL EXTRAPOLATION
SYMBOL MIN. TYP. MAX.
V FORMULA
Propagation delays
CP → On 5 145 290 ns 118 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 60 120 ns 49 ns + (0,23 ns/pF) CL
15 45 90 ns 37 ns + (0,16 ns/pF) CL
5 155 310 ns 128 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 65 130 ns 54 ns + (0,23 ns/pF) CL
15 45 90 ns 37 ns + (0,16 ns/pF) CL
CP → TC 5 260 525 ns 233 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 105 210 ns 94 ns + (0,23 ns/pF) CL
15 75 150 ns 67 ns + (0,16 ns/pF) CL
5 180 360 ns 153 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 75 150 ns 64 ns + (0,23 ns/pF) CL
15 55 115 ns 47 ns + (0,16 ns/pF) CL
PL → On 5 125 255 ns 98 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 55 110 ns 44 ns + (0,23 ns/pF) CL
15 40 85 ns 32 ns + (0,16 ns/pF) CL
5 170 340 ns 143 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 70 140 ns 59 ns + (0,23 ns/pF) CL
15 50 105 ns 42 ns + (0,16 ns/pF) CL
PL → TC 5 250 500 ns 223 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 110 220 ns 99 ns + (0,23 ns/pF) CL
15 80 160 ns 72 ns + (0,16 ns/pF) CL
5 250 500 ns 223 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 110 220 ns 99 ns + (0,23 ns/pF) CL
15 80 160 ns 72 ns + (0,16 ns/pF) CL
CE → TC 5 165 330 ns 138 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 65 135 ns 54 ns + (0,23 ns/pF) CL
15 50 100 ns 42 ns + (0,16 ns/pF) CL
5 145 290 ns 118 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 60 125 ns 49 ns + (0,23 ns/pF) CL
15 45 95 ns 37 ns + (0,16 ns/pF) CL
MR → On, TC 5 205 405 ns 178 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 65 130 ns 54 ns + (0,23 ns/pF) CL
15 45 85 ns 37 ns + (0,16 ns/pF) CL
MR → TC 5 225 450 ns 198 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 75 150 ns 64 ns + (0,23 ns/pF) CL
15 50 100 ns 42 ns + (0,16 ns/pF) CL
January 1995 6
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD TYPICAL
V SYMBOL MIN. TYP. MAX. EXTRAPOLATION
FORMULA
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
January 1995 7
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
VDD TYPICAL
V SYMBOL MIN. TYP. MAX. EXTRAPOLATION
FORMULA
Minimum clock 5 95 45 ns
pulse width; LOW 10 tWCPL 35 20 ns
15 25 15 ns
Minimum PL 5 105 55 ns
pulse width; HIGH 10 tWPLH 45 25 ns
15 35 15 ns
Minimum MR 5 120 60 ns
pulse width; HIGH 10 tWMRH 50 25 ns
15 40 20 ns
Recovery time 5 130 65 ns
for MR 10 tRMR 45 20 ns
15 30 15 ns
Recovery time 5 150 75 ns
for PL 10 tRPL 50 25 ns
15 30 15 ns
Set-up times 5 100 50 ns
see also waveforms
Pn → PL 10 tsu 50 25 ns
Figs 6 and 7
15 40 20 ns
5 250 125 ns
UP/DN → CP 10 tsu 100 50 ns
15 75 35 ns
5 120 60 ns
CE → CP 10 tsu 40 20 ns
15 25 10 ns
Hold times 5 10 −40 ns
Pn → PL 10 thold 5 −20 ns
15 0 −20 ns
5 35 −90 ns
UP/DN → CP 10 thold 15 −35 ns
15 15 −25 ns
5 20 −40 ns
CE → CP 10 thold 5 −15 ns
15 5 −10 ns
Maximum clock 5 3 6 MHz
pulse frequency 10 fmax 7 14 MHz
15 9 18 MHz
January 1995 8
Philips Semiconductors Product specification
HEF4516B
Binary up/down counter
MSI
Fig.6 Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP.
Fig.7 Waveforms showing minimum pulse width for PL and MR, recovery time for PL and MR and set-up and
hold times for Pn to PL.
January 1995 9
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January 1995
Philips Semiconductors
Binary up/down counter
10
Fig.8 Timing diagram.
Product specification
HEF4516B
MSI
