DESIGN GUIDE

NVIDIA® TEGRA™ 2
Interface Design Guide

Abstract
This document contains recommendations and guidelines for engineers to follow to create a product that is optimized
® ™
to achieve the best performance from the common interfaces supported by NVIDIA Tegra 2 processors.
® ™
Tegra 2 processors incorporate a low-power, high performance Dual-core ARM Cortex-A9 MPCore processor and
includes dedicated 2D, 3D, audio and HD video processing capabilities. These are accessed through a full set of
interfaces including multiple memory, storage, video, audio and peripheral interfaces.

Document Change History

Version Date Description
v01 JUL 4, 2010 Initial Release: This document replaces all versions of both:
Tegra_200_Series_Design_Guide_DG04753001
AP20_Design_Guide_DG04485001

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Table of Contents
1.0 Introduction .............................................................................................................................................................................5
1.1 Abbreviations and Definitions ............................................................................................................................................5
1.2 Signal Name Conventions.................................................................................................................................................6
1.3 Routing Guidelines ............................................................................................................................................................6
1.4 Signal Routing Conventions ..............................................................................................................................................7
1.5 Routing Guideline Format .................................................................................................................................................7
1.6 Features & Functions ........................................................................................................................................................8
1.7 Block Diagram...................................................................................................................................................................9
2.0 Power ...................................................................................................................................................................................10
2.1 Power Solution Requirements .........................................................................................................................................10
2.2 Optimal Power Solution...................................................................................................................................................10
2.3 Power Sequencing ..........................................................................................................................................................11
2.4 System Power States ......................................................................................................................................................11
2.5 Power Saving Features ...................................................................................................................................................12
2.6 Power Management Controller .......................................................................................................................................12
2.7 Adjustable Core & CPU Voltages ....................................................................................................................................13
2.7.1 Interface & Miscellaneous Power Control .................................................................................................................................... 13
2.8 Power Routing Guidelines...............................................................................................................................................14
2.9 Core Voltage Sense Signals ...........................................................................................................................................14
2.9.1 Routing guidelines for Core/CPU Sense signals: ........................................................................................................................ 14
2.10 5.2.4. Power Decoupling Guidelines .............................................................................................................................15
3.0 Interface Routing Guidelines.................................................................................................................................................17
3.1 Clocks .............................................................................................................................................................................18
3.1.1 32.768kHz Clock ........................................................................................................................................................................ 18
3.1.2 Oscillator Clock........................................................................................................................................................................... 18
3.2 DRAM Memory Configurations .......................................................................................................................................21
3.2.1 DDR2 Design Guidelines ............................................................................................................................................................ 21
3.2.2 8-bit Memory Configurations ....................................................................................................................................................... 21
3.2.3 16-bit Memory Configurations ..................................................................................................................................................... 27
3.2.4 LPDDR2 PoP (on PCB) or Discrete Design Guidelines ............................................................................................................... 34
3.3 NAND ..............................................................................................................................................................................38
3.3.1 NAND/NOR Design Guidelines ................................................................................................................................................... 39
3.4 USB.................................................................................................................................................................................41
3.4.1 Force Recovery .......................................................................................................................................................................... 41
3.4.2 Mini-Card .................................................................................................................................................................................... 42
3.4.3 USB Design Guidelines .............................................................................................................................................................. 42
3.5 ULPI ................................................................................................................................................................................43
3.5.1 ULPI Design Guidelines .............................................................................................................................................................. 43
3.6 HSIC ...............................................................................................................................................................................44
3.6.1 HSIC Design Guidelines ............................................................................................................................................................. 44
3.7 PCIE (Tegra 250 Only)....................................................................................................................................................45
3.7.1 PCIE Design Guidelines ............................................................................................................................................................. 45

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3.8 Internal (LCD) Display Interfaces ....................................................................................................................................47

3.8.1 Parallel RGB (Dumb) Display Interface ....................................................................................................................................... 47
3.8.2 Parallel Host (Smart) Display Interface ....................................................................................................................................... 48
3.8.3 Parallel RGB to LVDS Transmitter LCD Interface ....................................................................................................................... 48
3.8.4 MIPI DSI ..................................................................................................................................................................................... 50
3.9 External Display Interfaces .............................................................................................................................................51
3.9.1 HDMI .......................................................................................................................................................................................... 51
3.9.2 RGB DAC Interface .................................................................................................................................................................... 52
3.10 Video Input ....................................................................................................................................................................55
3.10.1 MIPI CSI Imager Connections ................................................................................................................................................... 55
3.10.2 YUV Imager Connections ......................................................................................................................................................... 56
3.10.3 Bayer Imager Connections........................................................................................................................................................ 56
3.10.4 Parallel VI Design Guidelines .................................................................................................................................................... 57
3.11 SDIO .............................................................................................................................................................................58
3.11.1 SD/MMC Card Connections ...................................................................................................................................................... 58
3.11.2 eMMC Device Connections....................................................................................................................................................... 59
3.11.3 SDIO Device Connections ........................................................................................................................................................ 59
3.11.4 SD/MMC Design Guidelines ..................................................................................................................................................... 60
3.12 Audio .............................................................................................................................................................................61
3.12.1 I2S Design Guidelines .............................................................................................................................................................. 61
3.13 Multi-purpose interfaces ................................................................................................................................................62
3.13.1 I2C............................................................................................................................................................................................ 62
3.13.2 SPI ........................................................................................................................................................................................... 63
3.13.3 UART........................................................................................................................................................................................ 64
3.14 Miscellaneous ...............................................................................................................................................................65
3.14.1 Keyboard .................................................................................................................................................................................. 65
3.14.2 Thermal Diode (Temperature Sensor)....................................................................................................................................... 66
3.14.3 JTAG ........................................................................................................................................................................................ 67
3.14.4 Strapping Pins .......................................................................................................................................................................... 68
3.14.5 EFUSE ..................................................................................................................................................................................... 69

4.0 Pad Configuration .................................................................................................................................................................70

4.1 POR (Power-on Reset) Default .......................................................................................................................................70
4.2 SFIO (Special Function I/O) Pad Control ........................................................................................................................70
4.3 GPIO Capability ..............................................................................................................................................................71
4.4 General Pin Selection Considerations ............................................................................................................................71
4.5 Considerations for Deep Sleep .......................................................................................................................................72
4.5.1 Input & Unconnected Pins in Deep Sleep ................................................................................................................................... 72

5.0 Substrate Trace Length ........................................................................................................................................................73

5.1 Tegra 250 Substrate Trace Lengths ...............................................................................................................................73
5.2 AP20 Substrate Trace Lengths .......................................................................................................................................77
6.0 Unused Interface Terminations .............................................................................................................................................80

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6.1 Unused Muxed Standard CMOS Pad Interfaces .............................................................................................................80

6.2 Unused DSI & CSI Interfaces..........................................................................................................................................80
6.3 Unused JTAG Interface...................................................................................................................................................81
6.4 Unused HDMI Interface...................................................................................................................................................81
6.5 Unused VDAC Interface ..................................................................................................................................................81
6.6 Unused USB Interfaces...................................................................................................................................................81
6.7 Unused HSIC Interface ...................................................................................................................................................82
6.8 Unused IC-USB Interface................................................................................................................................................82
6.9 Unused PCI Express Interface ........................................................................................................................................82
7.0 PCB Pad Layout Recommendations ....................................................................................................................................83

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1.0 INTRODUCTION

1.1 Abbreviations and Definitions

Table 2 lists abbreviations that may be used throughout this document and their definitions.

Table 1. Abbreviations and Definitions

Abbreviation Definition
AVP Audio/Video Processor
BT Bluetooth
CRT Cathode Ray Tube
DDR2 Double Data Rate SDRAM, Second-generation
EMC External Memory Controller
GPS Global Positioning Satellite
HDMI High Definition Multimedia Interface
HSIC High Speed IC Interface
I2C Inter IC
I2S Inter IC Sound Interface
IRAM Internal Random Access Memory
ISP Image Signal Processor
KBC Keyboard Controller
L1 / L2 Level 1 / Level 2 (cache)
LCD Liquid Crystal Display
LDO Low Dropout (voltage regulator)
LPDDR2 Low Power Double Data Rate SDRAM, Second-generation
LVDS Low Voltage Differential Signaling Interface
MC Memory Controller
MMC/ HSMMC/ eMMC Multi-Media Card / High Speed MMC / Embedded MMC
PCIe PCI Express
PCM Pulse Code Modulation
PHY Physical Interface (i.e. USB PHY)
PMC Power Management Controller
PMIC Power Management IC
RF Radio Frequency
RTC Real Time Clock
SDIO Secure Digital I/O Interface
SPI Serial Peripheral Interface
TD Three D (3D)
UART Universal Asynchronous Receive-Transmit
ULPI Ultra Low Pin-count Interface
USB Universal Serial Bus
VD Video Decoder
VDAC Video Digital to Analog Converter
VE Video Encoder
VGA Video Graphics Array
WLAN Wireless Local Area Network

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1.2 Signal Name Conventions

The following conventions are used in describing the signals for Tegra 2:
 Signal names use a mnemonic to represent the function of the signal. For example, Digital Audio Master Clock 1
signal is represented as DAP_MCLK1, written in bold to distinguish it from other text. All active low signals are
identified by an underscore followed by capitol N (_N) after the signal name. For example, SYS_RESET_N indicates
an active low signal. Active high signals do not have the underscore-N (_N) after the signal names. For example,
SDIO_CMD indicates an active high signal. Differential signals are identified as a pair with the same names that end
with _P and _N or in most cases just P and N (for positive and negative, respectively). For example, USB1_DP and
USB1_DN indicate a differential signal pair. One exception is the differential DDR clock which doesn’t use the P or
_P to indicate the positive signal (DDR_CLK & DDR_CLK_N).
 I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the signal. Table 2
lists the I/O codes used in the signal description tables.

Table 2. Signal Type Codes

Code Definition
A Analog
DIFF I/O Bidirectional Differential Input/Output
DIFF IN Differential Input
DIFF OUT Differential Output
I/O Bidirectional Input/Output
I Input
O Output
OD Open Drain Output
P Power

1.3 Routing Guidelines

Pay close attention when routing high speed interfaces, such as DDR2/LPDDR2, HDMI, USB/HSIC, DSI/CSI and PCI
Express. Each of these interfaces has strict routing rules for the trace impedance, width, spacing, total length, and length/flight
time matching. The following guidelines provide an overview of the routing guidelines and notations used in this document.
 Controlled Impedance
Each interface has a different trace impedance requirement and spacing to other traces. It is up to the designer to
calculate the trace width and spacing required to achieve the specified single-ended (SE) and differential (Diff)
impedances.
 Trace Length/Flight Time Matching
Flight time of a signal is the time it takes for a signal to propagate from one end (the driver) to the other end (the
receiver). One way to get the same flight time for a signal within a signal group is to match the trace within a specified
length in the signal group. Typically, this works for a four-layer board where the signal velocity is the same for the top
and bottom layers where signal traces are routed. However, for stack-up greater than four layers, we recommend
calculating trace length based on flight time (unless otherwise specified).
- Unless otherwise stated, always include Tegra 2 substrate trace length or propagation delay in all trace length or
flight time matching calculations.
- Total trace length = substrate trace length + motherboard trace length. Do not exceed the maximum trace length
specified.
- For a four-layer board stack-up, it is recommended using just the trace length matching, because the signal
velocity for top and bottom layers is the same.
- For six layers and above, it is recommended to match trace lengths based on the flight time of the signals. For
example, outer layer signal velocity could be 150psi (ps/inch) and inner layer 180psi. If one signal is routed 10
inches on the outer layer and the second signal is routed 10 inches in the inner layer, the difference in the flight
time between the two signals will be 300ps! That is a big difference if the required matching is 15ps (100 mil
trace length matching). To fix this, the inner trace needs to be 1.7 inches shorter or the outer trace needs to be 2
inches longer.
- In this design guide, terms such as intra-pair and inter-pair are used when describing differential pair length.
Intra-pair refers to matching traces within a differential pair (for example, the true to complement trace matching).
Inter-pair matching refers to matching the differential pair’s average length to other differential pairs’ average
lengths.

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1.4 Signal Routing Conventions

Throughout this document, the following signal routing conventions are used:

SE Impedance (/ Diff Impedance) at x× Dielectric Height Spacing

 The single-ended impedance of the trace (along with the differential impedance for diff pairs) is followed by a spacing
requirement. The spacing is a multiple of the dielectric height. The dielectric height is different for microstrip and
stripline (for example, it is 2.8 mil for microstrip and 3.0 mil for stripline on a typical six-layer board). Note: 1 mil =
1/1000th of an inch.
 Example: “50Ω and 5× dielectric height spacing” means that the trace should be routed at 50Ω single-ended and at
least (5 * 2.8 mil), or 14 mil spacing to adjacent signals (or 5 * 3.0 mil = 15 mil spacing for stripline traces).
 Example: “50Ω SE / 100Ω differential and 3× dielectric height spacing” means the trace should be routed at 50Ω
single-ended, 100Ω differential, and at least (3 * 2.8 mil), or 8.4 mil spacing to adjacent signals (or 3 * 3.0 mil = 9 mil
spacing for stripline traces).

1.5 Routing Guideline Format

The routing guidelines use in this chapter has the following format to specify how a signal should be routed. Refer to the
applicable Tegra 2 platform specific Design Guides for nominal impedance values for some sample board stack-ups.
 Breakout: Breakout traces are traces that are routed from the BGA ball outward to the rest of the board. The breakout
trace length is limited to 500 mil unless otherwise specified.
 After Breakout or Routing: After the breakout, the signal should be routed according to the specified impedance for
differential, single-ended, or even both (for example: PCIE). Trace spacing to other signals is also specified.
 Minimum/Maximum Length: Follow the maximum and minimum trace lengths where specified. The trace lengths are
shown in inches (or mils) or in terms of signal delay in pico-seconds (ps).

Note: For differential signals, the trace spacing to other signals must be the larger of the specified × dielectric height or the intra-
pair spacing. In other words, the spacing to other signals/pairs cannot be smaller than the spacing between the
complementary signals (intra-pair).
The total trace length depends on signal velocity which is different between the outer (microstrip) and inner layers (stripline)
of a PCB.
Unless otherwise specified, all trace length calculations (for matching and min/max) must include Tegra 2 substrate trace
length or delay (refer to the substrate trace length/delay chapter).

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1.6 Features & Functions

Dual-core ARM® Cortex -A9 MPCore™ Processor, up to 1.0 GHz Clocks
 L1 caches (each core)  System clock: 12, 13, 19.2, or 26 MHz
- 32KB L1 I-cache  Sleep clock: 32 KHz
- 32KB L1 D-cache  Dynamic clock scaling & clock source selection
 1MB L2 unified cache Boot Sources
Memory Subsystem  Raw SLC or MLC NAND (ONFI 2.1, Async. mode only)
 32-bit LPDDR2-600  eMMC, eSD, Sync-NOR, SPI serial flash
 32-bit DDR2-667 (Tegra 250 only)  MuxOneNAND / Flex-MuxOneNAND, LBA/mobile LBA
 Supports Up to 1 GB  USB (Recovery Mode)

HD Video Decode Security

 H.264 up to 1080p  Secure memories to store 2x8 keys, 128-bit eFuse
 WMV9/VC-1, MPEG-4 – 1080p  Hardware acceleration for AES encryption/decryption for secure boot & MM DRM
 DiVX, XviD – 1080p Storage Interfaces
 H.263, MPEG-2 – D1  4 SD/MMC controllers (supporting SD, MMC, HS-MMC, & SDIO)
 JPEG – up to 80 Mpixel per second  NAND flash, Up to eight chip selects, ECC corrections
HD Video Encode  EIDE, NOR flash
 H.264 – 1080p Peripheral Interfaces
 MPEG-4 – 720p  2 USB 2.0 interfaces with integrated PHY
 H.263 – D1  1 USB 2.0 interface supporting ULPI or HSIC
 JPEG – up to 80 Mpixel per second  5 High-speed UART interfaces
Audio Processor  4 SPI interfaces
 Audio Formats Supported (decode)  4 I2C controllers:
- AAC-LC, AAC+, eAAC+, AMR-WB, AMR-NB, WMA7,  2 enhanced audio controllers supporting

- WMA8, WMA9, and WMA10, MP3, PCM/WAV, SBC - I2S, left/right-justified, PCM, TDM (multi-slot mode)

 Audio Formats Supported (encode)  S/PDIF (Sony-Philips Digital Interface I/O)

- AAC-LC, AMR-WB, AMR-NB, PCM/WAV, SBC  5 DAP ports

- I/F to external audio devices, Crossbar between DAPs & internal controllers
Ultra-low Power NVIDIA® GeForce® GPU
 AC’97 controller
 ®
OpenGL ES 2.0
 PCI Express (PCIe) 4 lanes: 1x4, 2x2, 2x1 (Tegra 250 only)
 Peak Triangle Rate (million triangles per second):
 PWM Controllers (4 channels and up to 8 bits)
o Tegra 250: 71, AP20: 59
 Peak Fill Rate (with Z-reject - million pixels per second):  TWC (three-wire controller)
o Tegra 250: 1200, AP20: 1100  One-wire interface
 Programmable pixel shader & vertex/lighting  Keypad scan matrix (up to 16 x 8 – Tegra 250, up to 11 x 6 – AP20)
 CSAA support, 2K x 2K texturs & 4K x 4K render resolutions Baseband Interfaces
 Advanced 2D and vector engine  HSIC, ULPI. MIPI-HSI
Display Controller Subsystem  SPI (master and slave), HS-UART
 Two independent display controllers  PCM support
 LCD: Tegra 250 to 1680 x 1050, AP20 to 1024 x 600
Package
 HDMI 1.3 up to 1080p
 CRT: T2gra 250 to 1600 x 1200, AP20 to 1280x1024
 Tegra 250: 664 Ball FCBGA, 23x23 mm, 0.8 mm pitch

 SPI-based smart-panel interface

 AP20: 481 Ball Package-on-Package (PoP)

 MIPI DSI interface with 2-lane support  Process: 40 nm LPG TSMC

 HF and RoHS Compliant
Imaging System
 Integrated ISP
Applications
 Raw (Bayer) input up to 12 Mpixels  Smartbooks, Tablets, Potable Media Players, Portable Navigation Devices, Internet
TV, and more
 2 MIPI CSI interfaces (1 with 2-lane support)
 8-bit/10-bit/12-bit digital video input port

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1.7 Block Diagram

USB1
PHY
TEGRA 2 CSI A

SIM Dual Cortex-A9 PAR. VI

IC-USB
CPU COMPLEX
USB3 HD AUDIO, VIDEO ISP & VIDEO INPUT
PHY
CSI B
PROCESSOR (AVP) CONTROLLER
MPCORE
ULPI + L2 CACHE CAM I2C
USB2
HSIC
BASE- GEN1 Touch
BAND/ HSI Additional Controllers I2C Screen
MODEM
PCIE PWM LED
UART1 SPI2 Driver

LCD
DAP3 SDIO3 2ND
SPI3 Main
LCD
DSI LCD
DISPLAY
WiFi SDIO1 SPI4
UART5 CONTROLLERS
1&2
HDMI
UART3 HD TV
BLUE-
TOOTH
DDC
DAP4
TV/
VDAC CRT
DAP5 AUDIO
FM PMC
CONTROLLER
RADIO Keypad
UART4
Keybrd

GPS UART2 SD/MMC

SDIO2
Card
GEN1 PWR SPI NAND/
ACCEL DAP2 DAP1 SPI1 OSC EMC SDIO4
I2C I2C FLASH GMI

Ref
Temp SPI
32 Clock eMMC
Sensor KHZ FLASH
DRAM NAND/
Out
DDR2, NOR
Speaker LDOs & POWER LPDDR2 FLASH
AUDIO DC-DCs SOLUTION
Mic
CODEC 32
Headset Charger Battery KHZ

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2.0 POWER

2.1 Power Solution Requirements

The system power solution typically includes a PMU to handle many of the Tegra 2 power rails. Additional DC/DC and LDOs
may be required to power other rails, such as the USB Host VBUS. In addition, a separate battery management/charging
subsystem may be required. The following are some of the items to look for in a power/clocking solution for a design built
around Tegra 2:

32.768KHz Clock This must be on before Tegra 2 reset (SYS_RESET_N) is de-asserted and remain on as long as Tegra 2 is
powered
Reference clock 12MHz, 13MHz, 19.2MHz or 26MHz clock connected to Tegra 2 XTAL_OUT pin if provided externally. This
clock can also be generated internally by connecting a Crystal to the XTAL_IN/OUT pins.
Note: If the PEX (PCI Express) interface is implemented in a design, the reference clock or crystal must be
12MHz. This frequency is required to generate the PEX 100MHz internal clock
System Reset Reset output connected to the SYS_RESET_N pin. This is low during the power-on sequence until all
required powers/clocks are stable
DC/DC and LDO Adequate number of supplies at voltage/power levels needed, including programmable RTC, Core and CPU
Supplies voltages
Power Sequencing Power, clock and reset sequences that meet Tegra 2 and peripheral requirements
Power Control I2C & SPI supported for control I/F
Over-voltage protection Required for USB1_VBUS if standard USB Device connector would allow Charger connection
Battery management monitoring and charging as required by design

2.2 Optimal Power Solution

RTC LDO 1.0-1.2V nominal voltage range with 25mV to 50mV steps
Separate LDO for RTC domain allowing Deep Sleep mode support – Tegra 2 lowest power mode
Switch RTC domain down as low as 1.0V (should be programmable) before entering Deep Sleep mode
Switch RTC domain automatically back to 1.2V when wake-up event occurs & CORE_PWR_REQ
asserted

CORE Switcher 1.0-1.2V nominal voltage range with 25mV steps

CORE and RTC domains must track each other within 170mV
Tracking can be ensured in software but tracking control in power solution is best
Turn off if CORE_PWR_REQ de-asserted – on at 1.2V when CORE_PWR_REQ asserted

CPU Switcher 0.75 -1.0V nominal voltage range with 25mV steps
VDD_CORE must be ≥ VDD_CPU + 100mV
Turn off if CPU_PWR_REQ de-asserted – on at 1.0V when CPU_PWR_REQ asserted

PLL LDO Use 1.1V LDO from 1.8V DC/DC switcher to optimize efficiency and noise
Very good line regulation ensured using DC/DC switcher as LDO source
Turn off in when entering Deep Sleep mode when CORE_PWR_REQ is de-asserted

Host Interface Supply all signals between PMU and Tegra 2 (SYSTEM domain)
Optimized when Host rail is connected to 1.8V switcher

Power Sequence Power Up/Down sequence programmable by OTP ensures flexibility for any system design
Power-down sequence is reverse order of Power-up sequence

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2.3 Power Sequencing

The Power solution, including the PMU and any external supplies/logic, must be able to meet the power sequence requirements
of Tegra 2 and system peripherals. These requirements are detailed in the Tegra 2 EMT Datasheets.

2.4 System Power States

Various events and software operate to transition Tegra between the different power states.

Figure 1. Power States

Power DVFS
Source
Valid
ULVO OFF ACTIVE IDLE

SUSPEND

DEEP
SLEEP

Table 3. Power Rail State Descriptions

State Status of Voltage Rails Note
UVLO No power available – all rails OFF (Under-voltage Lockout) – Absence of main battery or dead
battery
OFF All Tegra 2 rails OFF Mobile device is powered OFF, except the RTC running in the
PMU
ACTIVE VDD_CORE, VDD_RTC, VDDIO_SYS, AVDD_PLLx, AVDD_OSC, Device running and controlled by active power management
VDDIO_DDR, VDD_DDR_RX ON (DVFS)
VDD_CPU optional (depending on need)
All other rails optional (depending on functionality required)
DRAM in normal operating mode
IDLE VDD_CORE, VDD_RTC, VDDIO_SYS, AVDD_PLLx, AVDD_OSC, Lowest power state with CPU powered off, but DDR not in self-
VDDIO_DDR, VDD_DDR_RX ON refresh..Idle is overall name for various scalable states
VDD_CPU OFF supporting low power use cases (A/V Playback, Simple display
refresh, etc.). AVP provides processing power in IDLE
All others optional (depending on functionality required)
DRAM in normal operating mode
SUSPEND VDD_CORE, VDD_RTC, VDDIO_SYS, AVDD_PLLx, AVDD_OSC, Lowest power state with CORE on (voice call, USB suspend)
VDDIO_DDR, VDD_DDR_RX ON
VDD_CPU OFF
All others optional (depending on functionality required)
DRAM in self-refresh mode
DEEP SLEEP VDD_RTC, VDDIO_SYS, VDDIO_DDR, VDD_DDR_RX ON Deepest sleep state, requiring specific wake-up events
VDD_CORE, VDD_CPU, AVDD_USB, AVDD_USB_PLL,
AVDD_IC_USB, VPP_FUSE and all PCIE (PEX) rails OFF
All other rails optional (Recommend OFF)
DRAM in self-refresh mode

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2.5 Power Saving Features

Tegra 2 utilizes a variety of means to provide an efficient power management solution for a complex environment. Hardware
and software work together to deliver an optimized system to monitor and control power use: raising voltages or clock
frequencies when demand requires, lowering them when less is sufficient, and removing them when none is needed. Following
is a brief discussion about power domains and power islands, as these are key to power management.

Tegra 2 is partitioned into power domains and power islands to optimize mobile device standby time (by limiting leakage current)
and to reduce power consumption for different use cases.

Table 4. RTC and Core Power Domains

Power Domain Power Islands in Domain Modules in Power Island
RTC (Always On) N/A PMC (Power Management Controller)
KBC (Keyboard Controller)
RTC (Real Time Clock)
Core NPG (Non Power Gated) AVP, 2D, Display, IRAM, MC (Memory Controller), L2 Cache RAM
TD (Power Gated) 3D
VD and VE (Power Gated) Video Decoder, Video Encoder, ISP, VI, CSI
CPU CPU Dual MPCores, MSelect, L1/L2 Controllers, L1 Cache RAM

Power gating cuts an unused power island’s leakage current. There are two core power-gated islands and one non-power-gated
island. The L2 cache, which is located on the Core domain, is not powered off if the CPU domain is off. This allows it to
maintain its contents while Tegra 2 is in a suspend state. The NPG blocks are clock-gated (Off) when not used, to reduce
unnecessary power consumption and consist of the 2D, Display, AVP, IRAM, and MC modules.

2.6 Power Management Controller

Tegra 2 power management controller (PMC) interacts with the external Power Management Unit IC (PMU) to achieve the
various power states. The PMC primarily acts as a controller, transitioning Tegra 2 to/from different low power modes while the
2
PMU acts as a slave, receiving commands via an I C or SPI interface as well as dedicated power/clock request signals. Other
power-management functions, such as clock gating, are inherent to Tegra 2 and are not controlled by the PMC.

The PMC contains logic for maintaining the state and control of power domains. It also signals the PMU to provide power to
Tegra 2 CPU and/or Core rails, and is part of the RTC power domain. The PMC manages the interface with the PMU including:
 PWR_I2C – Main control interface between PMC and PMU. Alternately, SPI is supported if PMU does not support I2C
control interface. PMC is the master and PMU the slave.
 CORE_PWR_REQ – Driven by the PMC to request VDD_CORE power be removed or asserted when transitioning
between ON and Deep Sleep states
 CPU_PWR_REQ – Driven by the PMC to request VDD_CPU power be removed or asserted when transitioning
between ON and either CPU Idle or Deep Sleep states
 SYS_CLK_REQ – Driven by the PMC to request an external reference clock be disabled or enabled when transitioning
between different power states

Note: CORE_PWR_REQ, CPU_PWR_REQ and SYS_CLK_REQ default to tri-state once VDDIO_SYS is applied and should therefore be
pulled-up to VDDIO_SYS or down to GND to ensure the PMU and/or clock source will provide core power and reference clock
during power-up. Alternately, the source of VDD_CORE and VDD_CPU can be designed to ignore the state of these pins during a
Power-on sequence.

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2.7 Adjustable Core & CPU Voltages

Tegra 2 DVFS software can dynamically adjust its core voltages (VDD_CORE & VDD_RTC) and CPU voltage (VDD_CPU) by
communicating with a PMU and/or other dedicated supplies using I2C or SPI commands. This allows a reduction in power
consumption depending on processing requirements (workload). The Power Management (PM) software monitors the workload
and scales the Core and CPU rails up or down to the lowest voltage that can sustain the workload at any point. In addition, the
CPU rail (VDD_CPU) can be powered off or on as needed to minimize power consumption while still allowing the system to
process audio, video, etc.

Note: Depending on Tegra 2 device & application, adjustable core voltage may have to be implemented to meet Thermal Design Power
(TDP) limits

The power design should support the following:

 VDD_CORE & VDD_RTC adjustments from 1.2V down to 1.0V or lower
 VDD_CPU adjustments from 1.0V down to 0.75V or lower
 Adjustments should be in 25mV to 50mV increments
 Each step must meet DC tolerance (refer to applicable Tegra Datasheet for requirements)
 In addition, transition slew-rate of these rails must meet the requirements found in the EMT Datasheet

Additionally, the Core & CPU rails need to maintain the following relationships:
 VDD_CORE – VDD_CPU >/= 100mV
 VDD_CORE must stay within 170mV of VDD_RTC when VDD_CORE is powered

Table 5 Default Power-up Voltages

VDD_CORE & VDD_RTC Voltage (V) VDD_CPU Voltage (V)
1.2V Determined by DVFS (From 0.9V – 1.0V)
1.2V Determined by DVFS (From 0.9V – 1.0V)

Note: VDD_CPU should be brought up by the DVFS software (running on the AVP) which will determine the correct voltages

2.7.1 Interface & Miscellaneous Power Control

In addition to controlling the Core and CPU rails to save power, other rails can be enabled or disabled as needed to minimize
power. The rails that must be powered whenever Tegra 2 is in any state except off include:

VDD_RTC Must always be powered – Contains PMC, & allows core logic to communicate with IO pins
VDDIO_SYS Rail associated with SYS_RESET_N, CLK_32K_IN, PWR_I2C, CORE/CPU_PWR_REQ & SYS_CLK_REQ
VDDIO_DDR Powers the Tegra 2 DRAM interface – required even in Deep Sleep for DRAM Self-refresh mode. VDD_DDR_RX is not
VDD_DDR_RX required, but leakage current is reduced if it is left powered along with VDDIO_DDR
VDD_DDR_1 Powers LPDDR2 Cores when AP20 (PoP) is used. These are also required to support Self-refresh mode
VDD_DDR_2

Power rails that can be off in Deep Sleep, but must return under hardware control (using CORE_PWR_REQ) are:

VDD_CORE Powers Boot ROM, AVP & IO controllers

AVDD_OSC Rail associated with XTAL_IN/OUT - Required to provide Reference clock
AVDD_PLLA_P_C PLLA, PLLM & PLLU are used by Boot ROM to provide clock to AVP, perform DRAM initialization routines & to
AVDD_PLLM execute certain USB PHY initialization routines
AVDD_PLLU
AVDD_USB These rails must be powered down during Deep Sleep and must be brought back on before SYS_RESET_N
AVDD_USB_PLL goes high

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Other rails can be left disabled or enabled during Deep Sleep, Suspend or one of the active states, depending on need. This
includes the following power rails:

VDD_CORE_NAND (AP20 Only), AVDD_PLLX, VDDIO_NAND, VDDIO_LCD, VDDIO_AUDIO, VDDIO_VI, VDDIO_BB,

VDDIO_UART, VDDIO_SDIO, AVDD, AVDD_HDMI, AVDD_HDMI_PLL, AVDD_VDAC, AVDD_DSI_CSI, VDDIO_HSIC

Rails should be powered if:

 Pins on an interface need to be driven as SFIOs (Special Function I/Os) or GPIOs
 Pin is used as a Wake event
 Internal Pullup/pulldown functionality is required
 Pins are connected to a powered interface or circuit

2.8 Power Routing Guidelines

High frequency decoupling capacitors (usually 0.1μF) should be placed as close as possible to the Tegra 2 package. In addition,
bottom-side capacitors can be placed under the Tegra 2 package. Any deviation from this strategy should be simulated and
tested in a four-corner environment to ensure proper power delivery.

The following guidelines should be used when routing the connection between the Tegra 2 package and the filter capacitors.
 Run thick trace (at least 16 mils wide) from power ball & drop via to power plane as soon as possible.
 After via, continue running thick trace to decoupling capacitor or mount capacitor on underside of board & connect to
via.
 Use thick trace (at least 16 mils wide) on GND side of decoupling capacitor to connect with GND plane via.
 Position decoupling capacitors no more than 150 mils away from Tegra 2 package & keep trace length between
capacitor SMT pads & power/GND vias to a minimum.
 Place all 0.1 μF capacitors within 100 mil of power balls & ≤ 2.2μF capacitors near power balls (& under Tegra 2).
4.7μF capacitors can be somewhat further from the power balls, but for critical interfaces such as DRAM, keep as close
as possible.
 If space is limited, PLL power balls within a group can share one 0.1μF capacitor provided capacitor is within 100 mils
of all power balls.

2.9 Core Voltage Sense Signals

Tegra 2 has two pairs of power remote sensing signals, one for VDD_CORE (VDD_CORE_SENSE, GND_CORE_SENSE) and
the other for VDD_CPU (VDD_CPU_SENSE, GND_CPU_SENSE). These provide a more accurate view of the actual voltages
the Core and CPU are seeing. They can optionally be used with compatible Core & CPU supplies to keep the internal voltage
levels at the proper levels.

2.9.1 Routing guidelines for Core/CPU Sense signals:

If the Core and/or CPU supplies support differential remote sense, run a pseudo differential pair (4/4/4 mil or wider) from these
balls back to the supply remote sense pins. These traces should have 3× dielectric height spacing away from other traces. If the
supplies only supports single-ended remote sensing, then connect the GND_CORE_SENSE and/or GND_CPU_SENSE balls to
GND and route the VDD_CORE_SENSE and/or VDD_CPU_SENSE back to the supplies.

Table 6 Core/CPU Remote Sensing Signals

Ball Name Description
VDD_CORE_SENSE Used for CORE voltage remote sensing. If not used, connect to VDD_CORE or leave NC
GND_CORE_SENSE Used for CORE voltage remote sensing. If not used, connect to GND or leave NC
VDD_CPU_SENSE Used for CPU voltage remote sensing. If not used, connect to VDD_CORE or leave NC
GND_CPU_SENSE Used for CPU voltage remote sensing. If not used, connect to GND or leave NC

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2.10 5.2.4. Power Decoupling Guidelines

There are two different packages for Tegra 2. Each package requires different filters and decouplings. The following tables show
the filter and decoupling guidelines for each of the package. Refer to the appropriate figure for filter configurations (topology).
Note that the voltage level may be different from the ball name and/or supply rail name.

Note: Refer to corresponding Datasheet for package type used by Tegra 2.

All Tegra 2 power rails must not ramp faster than 20 μs (from 10% to 90%). See Tegra 2 EMT Datasheets for full details on
power rail ramp requirements.
Voltage level is nominal. Refer to Tegra 2 Datasheets for tolerances & DC-current requirements.
Ferrite bead DCR must be low enough for voltage at ball to meet tolerance requirement

Figure 2: Filter Topology A

Table 7 Power Supply Capacitor Recommendations for Tegra 2

Ball Name Package Voltage Description Decoupling Topology
Powers Tegra 2 Core including AVP, 2D, Display, IRAM, 2 x 4.7uF
VDD_CORE Both Variable A
Memory Controller, L2 Cache RAM 3 x 0.1uF
Powers Tegra 2 Dual MPCores, MSelect, L1/L2 Cache 3 x 4.7uF
VDD_CPU Both Variable A
Controllers, L1 Cache RAM 1 x 0.1uF
VDD_RTC Both Variable Power for Always On Domain including PMC, KBC & RTC 1 x 0.1uF A
Includes AVDD_PLLA_P_C, AVDD_PLLM, AVDD_PLLU,
1 x 0.1uF
AVDD_PLLn1 Both 1.1V AVDD_PLLD. Power rails for PLLX, PLLA, PLLP, PLLC, PLLD, A
(each PLL rail)
PLLU, PLLS
AVDD_DSI_CSI Both 1.2V Powers DSI & CSI I/O (D-PHY) 1 x 0.1uF A
AVDD_OSC Both 1.8V Power for internal Oscillator logic 1 x 4.7uF A
AVDD_USB Both 3.3V Powers both USB1 & USB3 PHYs 1 x 4.7uF A
AVDD_USB_PLL Both 3.3V Power for dedicated USB PLL (within USB block) 1 x 0.1uF A
1.8V or Powers IC-USB PHY 1 x 4.7uF
AVDD_IC_USB Both A
3.0V 1 x 0.1uF
2.8V to
AVDD_VDAC Both Powers VDAC pads 1 x 0.1uF A
3.3V
AVDD_HDMI Both 3.3V Powers HDMI I/O 1 x 0.1uF A
AVDD_HDMI_PLL Both 1.8V Power for HDMI logic & dedicated PLL (within block) 1 x 0.1uF A
Tegra 250 1.8V Powers DDR2 or LPDDR2 I/O pads. 6 x 4.7uF
VDDIO_DDR A
AP20 1.2V 12 x 4.7uF
2.8V to
VDDIO_DDR_RX Both Powers internal DDR2/LPDDR2 reference logic 1 x 4.7uF A
3.3V
1 x 4.7uF
Tegra 250 1.8V, 2.8V- Powers NAND block I/Os. Pins referenced to this rail are
VDDIO_NAND 1 x 0.1uF A
3.3V muxed & various functions are supported
AP20 3 x 0.1uF
Powers System block I/Os. Most pins referenced to this rail
VDDIO_SYS Tegra 250 1.8V 1 x 0.1uF A
are muxed & various functions are supported
Powers System block I/Os. Most pins on this rail are muxed &
VDDIO_SYS_
AP20 1.8V support various functions. This is also connected to 1 x 0.1uF A
DDR_1
VDD_DDR_1 rail (see below)

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Ball Name Package Voltage Description Decoupling Topology

Tegra 250 1 x 4.7uF
1.8V, 2.8V- Powers Baseband block I/Os. Pins on this rail are muxed &
VDDIO_BB 1 x 4.7uF A
AP20 3.3V support various functions
1 x 0.1uF
1.8V, 2.8V- Powers SDIO block I/Os. Pins on this rail are muxed & support 1 x 4.7uF
VDDIO_SDIO Both A
3.3V various functions 1 x 0.1uF
Tegra 250 1.8V, 2.8V- Powers LCD block I/Os. Pins on this rail are muxed & support 1 x 0.1uF
VDDIO_LCD A
AP20 3.3V various functions 3 x 0.1uF
1.8V, 2.8V- Powers UART block I/Os. Pins on this rail are muxed & support
VDDIO_UART Both 1 x 0.1uF A
3.3V various functions
1 x 4.7uF
VDDIO_HSIC Both 1.2V Powers HSIC I/O A
1 x 0.1uF
1.8V, 2.8V- Powers Video Input block I/Os. Pins on this rail are muxed & 1 x 4.7uF
VDDIO_VI Both A
3.3V support various functions 1 x 0.1uF
1.8V, 2.8V- Powers Audio block I/Os. Pins on this rail are muxed & support
VDDIO_AUDIO Both 1 x 0.1uF A
3.3V various functions
AVDD_PEX Tegra 250 1.05V Powers Analog PCI-Express logic 1 x 0.1uF A
AVDD_PEX_PLL Tegra 250 1.05V Powers dedicated PCI-Express PLL (within block) 1 x 4.7uF A
Powers PLLE which provides reference 100MHz clock for PCI-
AVDD_PLLE Tegra 250 1.05V 1 x 0.1uF A
Express logic
VDD_PEX Tegra 250 1.05V Power for Digital PCI-Express I/Os 1 x 4.7uF A
VDDIO_PEX_CLK Tegra 250 3.3V Power for PCI-Express Clock 1 x 0.1uF A
Powers DDR1 core of stacked LPDDR2 devices. This rail
connects from AP20 Bottom Balls to Balls on package Top for 2 x 4.7uF
VDD_DDR_1 AP20 1.8V A
use on PoP Module. This rail is also connected to 5 x 0.1uF
VDDIO_SYS_DDR_1 (above)
Powers DDR2 core of stacked LPDDR2 devices. This rail only
3 x 4.7uF
VDD_DDR_2 AP20 1.2V connects from AP20 Bottom Balls to Balls on package Top for A
6 x 0.1uF
use on PoP Module
Powers Core of stacked NAND devices if needed. This rail only
1 x 4.7uF
VDD_NAND_CORE AP20 Note connects from AP20 Bottom Balls to Balls on package Top for A
2 x 0.1uF
use on PoP Module

Note: 1. Tegra 250 requires fewer external capacitors due to on-package capacitors in these cases

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3.0 INTERFACE ROUTING GUIDELINES

This chapter contains the PCB routing and other guidelines for the following Tegra 2 interfaces.
 Clocks
 DDR2 / LPDDR2
 NAND/GMI
 USB
 ULPI
 HSIC
 PCIE
 LCD
 HDMI
 VGA / TV Out
 Video Input
 HSMMC / SDIO
 Audio
 I2C
 SPI
 UART
 Keyboard
 JTAG
 Strapping Pins
 EFuse
 Thermal Diode

Note: Unless otherwise noted, all resistor values are ±5%

Unless otherwise specified, all trace impedance values are ±15%

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3.1 Clocks
Tegra 2 has a large number of internal functional blocks as well as supports a broad range of interfaces. Each of these has its
own clocking requirements. The RTC (Real Time Clock) and PMC (Power Management Controller) require a 32.768KHz clock,
to be provided externally. In addition, a higher frequency reference clock (OSC) is required. This can come from a crystal or an
external source, and feeds several integrated PLLs that provide a variety of clocking options for the core and I/O blocks. The
Tegra 2 clocking scheme is shown in Figure 3.

Figure 3. Tegra 2 Clocking Block Diagram (External clock source shown, but Crystal connection supported as well)

PMU Tegra 2
RTC

CLK_32K_IN
32KHz RTC PLLS

PLLC
PMC
SYS_CLK_REQ
PLLM

XTAL_IN PLLP Clock sources

OSC for internal
OSC
XTAL_OUT PLLA core & I/F
EN OUT blocks
PLLU
12MHz, 13MHz, 1.8V AVDD_OSC
19.2MHz, 26MHz 120R@100MHz
Reference Clock PLLD
1.1V AVDD_PLLA_P_C
AVDD_PLLX PLLX
AVDD_PLLM
AVDD_PLLU (& PLLD)
0.1uf PLL_S_PLL_LF

3.1.1 32.768kHz Clock

The 32.768kHz clock is provided externally, typically by the PMU (Power Management Unit). This clock is input on the
CLK_32K_IN pin which is referenced to the VDDIO_SYS rail. See the appropriate Tegra 2 Datasheet for details on the
requirements for this clock.

3.1.2 Oscillator Clock

Tegra 2 supports two methods of generating the internal Oscillator clock. Normal Oscillation Mode (on-chip oscillator) with
crystal connected to XTAL_IN and XTAL_OUT, and Bypass Mode (external clock source). In both modes, the frequencies
supported are 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz unless PEX (PCIe) interface is implemented (Tegra 250 only) in which
case, only 12MHz is allowed.

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3.1.2.1 Normal Oscillator Mode

A crystal is connected to XTAL_OUT and XTAL_IN to generate the reference clock internally. A reference circuit is shown in
Figure 4. Table 8 contains the requirements for the crystal used, the value of the parallel bias resistor and information to
calculate the values of the two external load capacitors (C L1 and CL2) shown in the circuit.

Figure 4. Crystal Connection Example

Tegra 2

XTAL_IN XTAL_OUT

RBIAS
CL1 CL2

Table 8 Crystal and Circuit Requirements

Symbol Parameter Min Typ Max Unit
FP Parallel resonance crystal Frequency 12, 13, 19.2, 26 MHz
FTOL Frequency Tolerance ±50 ppm
CL Load Capacitance for crystal parallel resonance 5 7 10 pf
Typical values used for CL1/CL2 12
DL Crystal Drive Level 300 uW
RBIAS External Bias Resistor 2 MΩ
ESR Equivalent Series Resistance
12 or 13MHz Crystal 100 Ω
19.2 or 26MHz Crystal 80
Start Time (From AVDD_OSC on or SYS_CLK_REQ active
TSTART <3 10 mS
coming out of Deep Sleep)

Notes: FP, FTOL, CL and DL are found in the Xtal Datasheet

ESR = RM * (1 + C0/CL)/2 where RM = Motional Resistance, C0 =Shunt Capacitance from Xtal datasheet. Datasheets may
specify ESR directly – consult manufacturer if unclear whether ESR or RM are specified.
Load capacitor values (CLx) can be found with formula CL = [(CL1xCL2)/(CL1+CL2)]+CPCB Or since CL1 and CL2 are
typically of equal value, CL = (CLx/2)+CPCB. or CLx = (CL – CPCB) x 2
CL = Load capacitance (Xtal datasheet). CPCB is PCB capacitance (trace, via, pad, etc.)

3.1.2.2 Crystal Design Guidelines

Table 9. Crystal Interface Signal Routing Requirements

Parameter Requirement Notes
Topology Point to Point
Number of loads 1 load
Reference plane GND (including Crystal itself)
Breakout Region Max Length Minimum width & spacing
Trace Impedance 100Ω differential, 55Ω single-ended (±20%) 1
Trace Spacing (to other nets) Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length <400ps – As short as possible
Max Trace Intra-pair Skew <6ps (~40mil)

Notes: 1: Routing as differential pair provides immunity and easier to reach target impedance.

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3.1.2.3 Bypass Mode

Select bypass mode when external clock source is used.
 Provide clock input to XTAL_OUT
 Tie XTAL_IN to GND
 Check input clock requirements in the appropriate Tegra 2 Datasheet
 SYS_CLK_REQ can be used by the PMC to enable/disable external oscillator when transitioning to different power
modes. This pin is tri-state at initial power-on, so will need a pull-up or pull-down resistor to enable the reference clock
initially.

Figure 5. External Reference Clock Connection Example

1.8V
External Tegra 2
OSC
EN OUT XTAL_OUT

VDDIO_SYS XTAL_IN
100KΩ

1.8V AVDD_OSC

SYS_CLK_REQ

1.8V VDDIO_SYS

Table 10. XTAL_IN/OUT Signal Connections

Ball Name Type Termination Description
XTAL_IN A For Crystal Connection: Crystal Input and Output: Used to connect either a
XTAL_OUT Load capacitors from XTAL_IN & XTAL_OUT to GND. Crystal, or external clock source.
Typically 12pf, but depends on PCB loading & Crystal Specs.
Bias resistor between XTAL_IN & XTAL_OUT closer to Tegra
2 2 than capacitors.
see Crystal Connection Example
External Clock Connection:
XTAL_IN tied to GND
see External Reference Clock Connection Example
SYS_CLK_REQ O 100K to GND or VDDIO_SYS to enable external clock source System Clock Request: Connect to enable of
external clock source if clock to be disabled during
Deep Sleep.

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3.2 DRAM Memory Configurations

Tegra 2 supports standard DDR2 and LPDDR2 SDRAM up to 1GB total memory. The maximum frequency supported is
333MHz (666MT/s) for DDR2 and 300MHz (600MT/s) for LPDDR2

3.2.1 DDR2 Design Guidelines

DDR2 SDRAM support described in this document is limited to these configurations and topologies up to 333MHz (666MT/s)
unterminated:
 Single Rank (4 devices), x8 SDRAMs in Starburst (T-T) topology.
 Dual Rank (8 devices ), x8 SDRAMs in Starburst (T-T-T) topology.
 Single Rank (2 devices), x16 SDRAMs in T-Branch topology.
 Dual Rank (4 devices ), x16 SDRAMs in Starburst (T-T) topology.

The topology for each signal must be followed exactly as shown in the following figures. Starburst topology for 8 SDRAM (Dual
Rank) assumes four devices on the top layer and four on the bottom.

3.2.2 8-bit Memory Configurations

3.2.2.1 Four, 8-bit DDR2 devices

 Four devices are routed in parallel to form single 32-bit memory rank (1 Chip Select, 1 Clock Enable)
 CLK/CLK_N, A[14:0], BA[2:0], RAS_N/CAS_N/WR_N, ODT0, CKE0 and CS0_N are routed to all devices (4 loads)
 DQ[31:0], DQS[3:0]P/N, DQM[3:0] are routed to one device each (1 load)

Figure 6. Single Rank, 8-bit DDR2 Configuration

Rank 0 (Single Rank Example)

DDR_CLK CLK+ DDR2 CLK+ DDR2 CLK+ DDR2 CLK+ DDR2
Tegra 2 DDR_CLK_N
DDR_CS0_N
CLK-
CS
(x8)
CLK-
CS
(x8)
CLK-
CS
(x8)
CLK-
CS
(x8)
DDR_A[14:0] ADDRESS ADDRESS ADDRESS ADDRESS
DDR_BA[2:0] BANK BANK BANK BANK
DDR_RAS_N RAS_N RAS_N RAS_N RAS_N
DDR_CAS_N CAS_N CAS_N CAS_N CAS_N
DDR_WE_N WE_N WE_N WE_N WE_N
DDR_CKE0 CKE CKE CKE CKE
DDR_ODT0 ODT ODT ODT ODT

DDR_DQS0P DQS+ #1 #2 #3 #4
DDR_DQS0N DQS-
DDR_DQM0 DQM
DDR_DQ[7:0] DATA
VDDQ

VSSQ
VDDL
VREF

VSSL
VDD

VSS

DDR_DQS1P
DDR_DQS1N
DDR_DQM1
DDR_DQ[15:8]

DDR_DQS2P
DDR_DQS2N
DDR_DQM2
DDR_DQ[23:16]

DDR_DQS3P
DDR_DQS3N
DDR_DQM3
DDR_DQ[31:24]

DDR_QUSE0
2.8V –
VDD_RX_DDR DDR_QUSE1
3.3V
DDR_QUSE2
1.8V VDDIO_DDR DDR_QUSE3

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Table 13. Single & Dual Rank, 8-bit DDR2 Addr/Cmd/Ctl Signal Routing Requirements
Parameter Requirement (Single Rank) Requirement (Dual Rank)
Topology Starburst (T-T) Starburst (T-T-T)
Operational Constraints Address / Command = 1T Address / Command = 1T
Configuration / Device Organization 4 loads 8 loads (4 for Control – See Note)
Maximum Loading (per pin) 2pf 2pf
Reference plane GND GND
Breakout Region Impedance Minimum width & spacing Minimum width & spacing
Max PCB breakout length 48ps (~0.3”) 48ps (~0.3”)
Trace Impedance 47-50Ω ±15% 47-50Ω ±15%
Trace Spacing Microstrip 4x dielectric 4x dielectric
Stripline 3x dielectric 3x dielectric
Max Trace Length: Package+PCB main trunk ≤480ps ≤480ps
Max Trace Length: Seg 1 ≤167ps ≤167ps
Max Trace Length: Seg 2 ≤89ps ≤89ps
Max Trace Length: Seg 3 (Dual Rank) na ≤45ps
Max Trace Length Skew in Seg 1 ≤13ps ≤13ps
Max Trace Length Skew in Seg 2 ≤15ps ≤15ps
Max Trace Length Skew in Seg 3 (Dual Rank) na ≤6ps
Max Trace Length Skew between Addr/Cmd/Ctl & Clk
Single Rank:
Package + PCB Main Trunk +Seg1 + Seg2 (Addr/Cmd)
compared w/Package + PCB Main Trunk + Seg1 + Seg2 (Clk) <160ps
Dual Rank:
Package + PCB Main Trunk +Seg1 + Seg2 + Seg3 (Addr/Cmd)
<160ps
compared w/Package + PCB Main Trunk + Seg1 + Seg2 + Seg3 (Clk)

Notes: Command includes DDR_RAS_N, DDR_CAS_N, DDR_WE_N & DDR_ODT0

Control includes DDR_CS[1:0]_N & DDR_CKE[1:0]. See Single Rank Starburst (T-T) Topology for Control requirements
All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified

Table 14. Single & Dual Rank, 8-bit DDR2 Addr/Cmd/Ctl Signal Group Connections
Ball Name Type Termination Description
DDR_A[14:0] O None Address: Connect DDR_A to A pins of all SDRAM
DDR_BA[2:0] O None Bank Address: Connect DDR_BA to BA pins of all SDRAM
DDR_CAS_N O None Column Address Strobe
Connect DDR_CAS_N to CAS_N pins of all SDRAMs
DDR_RAS_N O None Row Address Strobe:
Connect DDR_RAS_N to RAS_N pins of all SDRAMs
DDR_WE_N O None Write Enable:
Connect DDR_WE_N to WE_N pins of all SDRAMs
DDR_CS[1:0]_N O None Chip Select:
Connect DDR_CS0_N to CS_N pins of all SDRAM on Rank 0
Connect DDR_CS1_N to CS_N pins on all SDRAM on Rank 1
DDR_CKE[1:0] O None Clock Enable
Connect DDR_CKE0 to CKE pins of all SDRAM on Rank 0
Connect DDR_CKE1 to CKE pins on all SDRAM on Rank 1
DDR_ODT0 O None On-Die Termination Control
Connect DDR_ODT0 to ODT pins of all SDRAMs

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Figure 12. Single Rank, 8-bit DDR2 Clock [Starburst (T-T) Topology]

Figure 13. Dual Rank, 8-bit DDR2 Clock [Starburst (T-T-T) Topology)

Table 15. Single & Dual Rank, 8-bit DDR2 Clock Routing Requirements
Parameter Requirement (Single Rank) Requirement (Dual Rank)
Clock
Topology Starburst Starburst
Configuration / Device Organization 4 loads 8 loads
Maximum Loading (per pin) 2pf 2pf
Reference plane GND GND
Breakout Region Impedance Minimum width & spacing Minimum width & spacing
Max PCB breakout length 48ps (~0.3”) 48ps (~0.3”)
Trace Impedance 90Ω diff pair ±15% 90Ω diff pair ±15%
Trace Spacing Microstrip 4x dielectric 4x dielectric
Stripline 3x dielectric 3x dielectric
Max Trace Length: Package+PCB main trunk ≤480ps ≤480ps

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T-Branch Topology: 16-bit DDR2 Address, Command & Control (Single Rank), Control (Dual Rank)

Figure 18. T-Branch Topology: 16-bit DDR2 Address, Command & Control (Single Rank), Control (Dual Rank)

Rank 0
Branch A DDR2
Package Main trunk #1
Tegra 2
Branch B DDR2
#2

Table 19. T-Branch Topology: 16-bit DDR2 Addr, Cmd & Ctl (Single Rank), Ctl (Dual Rank) Group Signal Routing Requirements
Parameter Requirement (Add/Cmd/Ctl Single Rank, Ctl Dual Bank)
Address/Command/Control
Topology T-Branch
Operational Constraints Address / Command = 1T
Configuration / Device Organization 2 loads
Maximum Loading (per pin) 2pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance 47-50Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length: Package+PCB main trunk ≤560ps
Max Trace Length: Branch A/B ≤100ps
Max Trace Length Skew between Addr/Cmd/Ctl & Clk <160ps
Package + PCB Main Trunk +Branch A/B (Addr/Cmd/Ctl)
compared with Package + PCB Main Trunk + Branch A/B (Clk)
Max Trace Length Skew (Addr/Cmd) in Branch A/B ≤30ps

Notes: Command includes DDR_RAS_N, DDR_CAS_N, DDR_WE_N & DDR_ODT0

Control includes DDR_CS[1:0]_N & DDR_CKE[1:0]
All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified

Starburst (T-T) Topology: 16-bit DDR2 Address & Command (Dual Rank)

Figure 19. Starburst (T-T) Topology: 16-bit DDR2 Address & Command (Dual Rank)

Rank 0
Seg 2 DDR2
Seg 1 #1
Rank 1
DDR2
Package Main Trunk #3
Tegra 2 Rank 0
DDR2
#2
Rank 1
DDR2
#4

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Table 20. Dual Rank, 16-bit DDR2 Addr & Cmd Group Signal Routing Requirements
Parameter Requirement (Dual Rank)
Address/Command
Topology Starburst (T-T)
Operational Constraints Address / Command = 1T
Configuration / Device Organization 4 loads: Address & Command
2 loads: Control (See Note)
Maximum Loading (per pin) 2pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance 47-50Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length: Package+PCB main trunk ≤480ps
Max Trace Length: Seg 1 ≤167ps
Max Trace Length: Seg 2 ≤89ps
Max Trace Length Skew in Seg 1 ≤13ps
Max Trace Length Skew in Seg 2 ≤15ps
Max Trace Length Skew between Addr/Cmd/Ctl & Clk <160ps
Package + PCB Main Trunk +Seg1 + Seg2 (Addr/Cmd)
compared w/Package + PCB Main Trunk + Seg1 + Seg2 (Clk)

Notes: Command includes DDR_RAS_N, DDR_CAS_N, DDR_WE_N & DDR_ODT0

Control includes DDR_CS[1:0]_N & DDR_CKE[1:0]. See Single Rank T-Branch topology for Control requirements
All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified

Table 21. Single & Dual Rank, 16-bit DDR2 Addr, Cmd & Ctl Group Connections
Ball Name Type Termination Description
DDR_A[14:0] O None Address: Connect DDR_A to A pins of all SDRAMs
DDR_BA[2:0] O None Bank Address: Connect DDR_BA to BA pins of all SDRAMs
DDR_CAS_N O None Column Address Strobe: Connect DDR_CAS to CAS_N pins of all SDRAMs
DDR_RAS_N O None Row Address Strobe: Connect DDR_RAS to RAS_N pins of all SDRAMs
DDR_WE_N O None Write Enable: Connect DDR_WE_N to WE_N pins of all SDRAMs
DDR_CS[1:0]_N O None Chip Select:
Connect DDR_CS0 to CS_N pins of all SDRAM on Rank 0
Connect DDR_CS1 to CS_N pins on all SDRAM on Rank 1
DDR_CKE[1:0] O None Clock Enable
Connect DDR_CKE0 to CKE pins of all SDRAM on Rank 0
Connect DDR_CKE1 to CKE pins on all SDRAM on Rank 1
DDR_ODT0 O None On-Die Termination Control: Connect DDR_ODT0 to ODT pins of all
SDRAMs

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Figure 20. Single Rank, 16-bit DDR2 Clock (T-Branch Topology)

Branch A Rank 0
+ DDR2
Package Main trunk -- #1
CLK
Tegra 2 + +
CLK_N
-- -- Branch B
+ DDR2
-- #2

Figure 21. Dual Rank, 16-bit DDR2 Clock (Starburst (T-T) Topology)

Seg 2 Rank 0
+ DDR2
Seg 1 -- #1
+
-- Rank 1
+ DDR2
Package Main Trunk -- #3
CLK
Tegra 2 + +
CLK_N
-- -- Rank 0
+ DDR2
-- #2
+
-- Rank 1
+ DDR2
-- #4

Table 22. Single & Dual Rank, 16-bit DDR2 Clock Routing Requirements
Parameter Requirement (Single Rank) Requirement (Dual Rank)
Clock
Topology T-Branch Starburst (T-T)
Configuration / Device Organization 2 loads 4 loads
Maximum Loading (per pin) 2pf 2pf
Reference plane GND GND
Breakout Region Impedance Minimum width & spacing Minimum width & spacing
Max PCB breakout length 48ps (~0.3”) 48ps (~0.3”)
Trace Impedance 90Ω diff pair ±15% 90Ω diff pair ±15%
Trace Spacing Microstrip 4x dielectric 4x dielectric
Stripline 3x dielectric 3x dielectric
Max Trace Length: Package+PCB main trunk ≤605ps ≤480ps
Max Trace Length: Branch A/B (Single Rank) ≤115ps na
Max Trace Length Skew in Branch A/B (Single Rank) <30ps na
Max Trace Length Skew CLK/CLK_N (Single Rank) <1ps na
(Package + Main Trunk + T-Branch A/B)
Max Trace Length: Seg 1 (Dual Rank) na ≤167ps
Max Trace Length: Seg 2 (Dual Rank) na ≤89ps
Max Trace Length Skew CLK/CLK_N (Dual Rank) na <1ps
Package + Main Trunk + Seg1 + Seg2

Note: All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified.

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Table 23. Single & Dual Rank, 16-bit DDR2 Clock Connections
Ball Name Type Termination Description
DDR_CLK DIFF None Clock
DDR_CLK_N OUT Connect DDR_CLK to CLK pins of all SDRAM
Connect DDR_CLK_N to CLK_N pins of all SDRAM

Table 24. Miscellaneous DDR2 Connections

Ball Name Type Termination Description
DDR_COMP_PU A 49.9Ω, 1% to VDDIO_DDR SDRAM Compensation Pull-up
Connect to termination resistor
Connect other end of resistor to VDDIO_DDR
DDR_COMP_PD A 49.9Ω, 1% to GND SDRAM Compensation Pull-down
Connect to termination resistor
Connect other end of resistor to GND

Table 25. DDR2 SDRAM PWR/GND Connections

DDR2 Ball Name Type Termination Description
VREF A DDR2 SDRAM Voltage Reference: Connect to rails = 0.5 * VDDIO_DDR
VDD P DDR2 SDRAM Power Rails: Connect to same power source as
VDDQ VDDIO_DDR
VDDL
VSS P DDR2 SDRAM Ground pins: Connect to GND
VSSQ
VSSL

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3.2.4 LPDDR2 PoP (on PCB) or Discrete Design Guidelines

LPDDR2 SDRAM support described in this document is either a PoP module mounted on the PCB alongside Tegra 2, or
discrete LPDDR2 devices (x32 at the package level). Configurations up to 1GB are supported and up to 300MHz (600MT/s).

Note: LPDDR2 PoP (on PCB) or discrete devices contain from 1 to 4 memory devices stacked inside

The topology for each signal must be followed exactly as shown in the following figures.

Figure 22. PoP Module or Discrete LPDDR2 Configuration

VDDIO_DDR

Tegra 2 LPDDR2 1.8V

(1.2V)

DDR_CLK CK_T VDD1

DDR_CLK_N CK_C VDD2

2.94KΩ,1%

2.94KΩ,1%
VDDIO_DDR DDR_A[9:0] CA[9:0] VDDQ
DDR_CS[1:0]_N CS[1:0]_N VDDCA
DDR_CKE[1:0] CKE[1:0]
49.9Ω,1%

VREF(CA)
DDR_DQS[3:0]P DQS[3:0]_T VREF(DQ)
DDR_DQS[3:0]N DQS[3:0]_C

2.94KΩ,1%

2.94KΩ,1%
DDR_COMP_PU DDR_DQM[3:0] DQM[3:0] ZQ0
DDR_COMP_PD DDR_DQ[31:0] DQ[31:0] ZQ1
49.9Ω,1%

VSS

243Ω,1%

243Ω,1%
VSSQ
VSSCA

Trace length out from DDR_QUSE0 & back to

2.8V – DDR_QUSE1 must match trace length of
VDD_RX_DDR DDR_QUSE0
3.3V DDR_DQS1 & DDR_DQS3 separately (+/-
DDR_QUSE1
100ps).
1.2V VDDIO_DDR DDR_QUSE2
DDR_QUSE3
Trace length out from DDR_QUSE 2 & back to
DDR_QUSE3 must match DDR_DQS0 &
DDR_DQS2 separately (+/-100ps)

Figure 23. LPDDR2 DQ, DQS, DQM & Address/Control (Point-Point) Topology

Package Main trunk

Tegra
250
LPDDR2

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Table 26. LPDDR2 Data Signal Group Routing Requirements

Parameter Requirement (PoP) Requirement (Discrete)
DQ/DQS/DM
Topology Point-Point
Max Number of Loads 1 (Up to 2 internal loads)
Minimum Loading (per pin) 1.25pf
Maximum Loading (per pin) 2.5pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance DQ/DM 50Ω ±15%
DQS 90Ω diff pair ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length: Package+PCB main trunk <375ps <565ps
Max Trace Length Skew between DQ & DQS (Package + PCB Main Trunk) <20ps
Max Trace Length Skew between DQSP & DQSN (Package + PCB Main Trunk) <1ps
Max Trace Length Skew between DQS & CLK (Package + PCB Main Trunk) <75ps
Max Trace Length Skew between DQS1 & QUSE0 + QUSE1 <100ps
Max Trace Length Skew between DQS3 & QUSE0 + QUSE1 <100ps
Max Trace Length Skew between DQS0 & QUSE2 + QUSE3 <100ps
Max Trace Length Skew between DQS2 & QUSE2 + QUSE3 <100ps

Note: All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified.

Table 27. LPDDR2 Data Signal Group Connections

Ball Name Type Termination Description
DDR_DQ[31:0] I/O No Termination required Data: Connect to DQ pins of all SDRAMs (see table below)
Data Mask: Connect to DM pins on SDRAMs (see table below)
DDR_DM[3:0] O Data Strobes: Connect to DQSP/DQSN pins of all SDRAMs (See below)
Byte Lanes (Groupings)
DDR_DQS[3:0]P DIFF I/O Data Data Mask Data Strobe
DDR_DQS[3:0]N DQ[7:0] DM0 DQS0P/N
DQ[15:8] DM1 DQS1P/N
DQ[23:16] DM2 DQS2P/N
DQ[31:24] DM3 DQS3P/N

LPDDR2 Address, Command & Control

Table 28. LPDDR2 Cmd/Addr & Ctl Group Signal Routing Requirements
Parameter Requirement (PoP) Requirement (Discrete)
Command/Address & Control
Topology Point-Point
Operational Constraints Address / Command = 1T
Max Number of Loads 1 (up to 4 internal address & 2 control loads)
Minimum Loading (per pin) 1pf
Maximum Loading (per pin) 2pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance 50Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length: Package+PCB main trunk ≤445ps ≤565ps
Max Trace Length Skew between Addr/Cmd/Ctl & Clk (Package + PCB Main Trunk) <10ps

Notes: Command/Address includes DDR_A[9:0]. DDR_A[14:10] are not used

Control includes DDR_CS[1:0]_N & DDR_CKE[1:0]
All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified

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Table 29. LPDDR2 Cmd/Addr & Ctl Group Connections

Ball Name Type Termination Description
DDR_A[9:0] O None Address: Connect DDR_A to A pins of all SDRAMs
DDR_CS[1:0]_N O None Chip Select:
Connect DDR_CS0 to CS_N pins of all SDRAM on Rank 0
Connect DDR_CS1 to CS_N pins on all SDRAM on Rank 1
DDR_CKE[1:0] O None Clock Enable: Connect DDR_CKE pin(s) to to CKE pin(s) of SDRAM. If only
one CKE pin, leave DDR_CKE1 as NC
DDR_A[14:10] O None Unused SDRAM pins LPDDR2: Leave NC
DDR_BA[2:0]
DDR_RAS_N
DDR_CAS_N
DDR_WE_N
DDR_ODT0

Figure 24. LPDDR2 Clock (Point-Point Topology)

Package Main trunk

Tegra CLK
+ +
250 CLK_N LPDDR2
-- --

Table 30. LPDDR2 Clock Routing Requirements

Parameter Requirement (PoP) Requirement (Discrete)
Clock
Topology Point-Point
Max Number of Loads 4 (Module will include up to 4 devices)
Minimum Loading (per pin) 1pf
Maximum Loading (per pin) 2pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance 90Ω diff pair ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length: Package+PCB main trunk ≤445ps ≤565ps
Max Trace Length Skew CLK/CLK_N (Package + Main Trunk + T-Branch A/B) <1ps

Note: All Max Trace Length Skew matching must include substrate pin delays unless otherwise specified.

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Table 31. LPDDR2 Clock Connections

Ball Name Type Termination Description
DDR_CLK DIFF None Clock
DDR_CLK_N OUT Connect DDR_CLK to CLK pins of all SDRAM
Connect DDR_CLK_N to CLK_N pins of all SDRAM

Table 32. Miscellaneous Tegra 250 LPDDR2 Connections

Ball Name Type Termination Description
DDR_COMP_PU A 49.9Ω, 1% to VDDIO_DDR SDRAM Compensation Pull-up
Connect to termination resistor
Connect other end of resistor to VDDIO_DDR
DDR_COMP_PD A 49.9Ω, 1% to GND SDRAM Compensation Pull-down
Connect to termination resistor
Connect other end of resistor to GND

Table 33. Miscellaneous Non-Tegra 250 LPDDR2 Connections

Ball Name Type Termination Description
VREF(CA) A Resistor Voltage Divider for each ref pin: LPDDR2 Command/Address & Data Voltage References: Connect
VREF(DQ) Single device Module/Discrete: VREF(CA) and VREF(DQ) pins of module each to center of voltage divider
11.9KΩ, 1% resistor to VDDIO_DDR described in Termination column.
11.9KΩ, 1% resistor to GND
Dual device Module/Discrete:
5.9KΩ, 1% resistor to VDDIO_DDR
5.9KΩ, 1% resistor to GND
Quad device Module/Discrete:
2.94KΩ, 1% resistor to VDDIO_DDR
2.94KΩ, 1% resistor to GND
VDD1 P LPDDR2 Core 1: Connect VDD1 pins of module to 1.8V supply (see LPDDR
device spec. for tolerance).
VDD2 P LPDDR2 Core 2:
VDDCA LPDDR2 Command/Address I/O power rail:
VDDQ LPDDR2 Data I/O power rail:
Connect VDD2, VDDCA and VDDQ pins of module to same 1.2V supply (±
5%) as used for VDDIO_DDR on Tegra 250.
ZQ0 A 243Ω, 1% to GND LPDDR2 Zero Compensation pins: Connect each ZQ[1:0] pin to a
ZQ1 separate resistor and then to GND as described in Termination column
VSS P LPDDR2 Core, Command/Address and Data Ground pins: Connect VSS,
VSSQ VSSQ and VSSCA to GND.
VSSCA

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3.3 NAND
Tegra 2 contains a Raw NAND and GMI (General Memory Interface) controller. Between these two blocks, Tegra 2 supports a
broad range of devices including a variety of NAND and NOR devices and configurations.
 Raw NAND (SLC, MLC - Up to 8 devices/8 chip selects)
 OneNAND / Mux OneNAND / Flex Mux OneNAND
 mLBA NAND
 NOR, Sync NOR

Figure 25. Multiple 8-bit Raw NAND Example

External resistor if stronger pull-up is VDDIO_NAND
required than weak internal resistor

10KΩ
NAND_ALE
Tegra 2 GMI_ADV_N
NAND_CLE
ALE NAND
GMI_CLK
NAND_RE_N
CLE 1
GMI_OE_N
NAND_WE_N
RE_N 2
GMI_WE_N
NAND_D[7:0]
WE_N 3
GMI_AD[7:0]
NAND_BSY0
D[7:0] 4
GMI_WAIT BSY 5
GMI_WP_N WP 6
100KΩ 7
NAND_CE0_N
8
GMI_CS2_N CE0_N
NAND_CE1_N
GMI_CS3_N CE1_N
NAND_CE2_N
GMI_CS4_N CE2_N
NAND_CE3_N
GMI_IORDY CE3_N
NAND_CE4_N
GMI_CS6_N CE4_N
NAND_CE5_N CE5_N
GMI_CS5_N
NAND_CE6_N
GMI_CS0_N CE6_N
1.8V, 2.8V- NAND_CE7_N
VDDIO_NAND GMI_CS1_N CE7_N
3.3V

Figure 26. Single 16-bit Raw NAND Connection Example

External resistor if stronger VDDIO_NAND
pull-up is required than weak
internal resistor
10KΩ
NAND_ALE
Tegra 2 GMI_ADV_N
NAND_CLE
ALE NAND
GMI_CLK CLE
NAND_CE0_N
GMI_CS2 CE_N
NAND_RE_N
GMI_OE_N RE_N
NAND_WE_N
GMI_WE_N WE_N
NAND_D[15:0]
GMI_AD[15:0] D[15:0]
NAND_BSY0
GMI_WAIT BSY0
1.8V, 2.8V-
VDDIO_NAND GMI_WP_N WP
3.3V
100KΩ

Figure 27. Flex Mux OneNAND Connection Example

VDDIO_NAND
100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

Tegra 2 GMI_CS0_N CE1 Flex Mux

GMI_CS1_N CE2
GMI_CLK CLK
OneNAND
GMI_ADV_N AVD_N
GMI_AD[15:0] AD[15:0]
GMI_OE_N OE_N
GMI_WR_N WE_N
GMI_WAIT RDY

GMI_INT1
GMI_WP_N INT1
GMI_INT2
GMI_AD16 INT2
1.8V VDDIO_NAND GMI_RST_N RP_N

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Figure 28. mLBA NAND Connection Example

100KΩ VDDIO_NAND
100KΩ
NAND_ALE
Tegra 2 GMI_ADV_N
NAND_CLE
ALE mLBA
GMI_CLK CLE
GMI_CSx_N
NAND_CEx_N
CE_N
NAND
NAND_RE_N
GMI_OE_N RE_N
NAND_WE_N
GMI_WR_N WE_N
NAND_D[15:0]
GMI_AD[15:0] D[16:1]
NAND_BSY
GMI_WAIT R/B
1.8V, NAND_WP_N
VDDIO_NAND GMI_WP_N WP_N
2.8V-3.3V
100KΩ

Figure 29. Synchronous NOR Connection Example

100KΩ VDDIO_NAND
Tegra 2 100KΩ
SYNC NOR
GMI_CSx_N CE_N
GMI_CLK CLK
GMI_ADV_N ADV_N
GMI_AD[15:0] AD[15:0]
GMI_A[24:16] A[24:16]
GMI_OE_N OE_N
GMI_WR_N WE_N
GMI_WAIT RY/B
100KΩ
GMI_WP_N WP_N
GMI_DPD DPD
1.8-3.3V VDDIO_NAND GMI_RST_N RST_N

3.3.1 NAND/NOR Design Guidelines

Table 34. NAND/GMI Interface Signal Routing Requirements

Parameter Requirement (Asynchronous) Requirement (Synchronous)
Maximum Frequency 133MHz 133MHz
Maximum Loading (per pin) - Cmd, Data, CE/CS 3.5pf (ALE/CLE/WE_N) na
4pf (DQ)
5pf (CE[7:0]_N)
Maximum Loading (per pin) - Cmd, Data, Cld, CE/CS 7.8pf (ALE/CLE/WE_N) 4pf
9pf (Data)
10pf (CE[7:0]_N)
Maximum Number of Loads 4 (Requirements for 8 loads TBD) 1
Reference plane GND, Power (see note) GND, Power (see note)
Breakout Region Impedance Minimum width & spacing Minimum width & spacing
Breakout Region Max Length 45ps (~30 mils) 45ps (~30 mils)
Trace Impedance 50Ω ±15% 50Ω ±15%
Trace Spacing Microstrip 3x dielectric 4x dielectric
Stripline 2x dielectric 1.5x dielectric
Max Trace Length < 965pf (~6.0”) < 965pf (~6.0”)
Max Trace Length Skew:
Cmd to DATA (Async), CLK to Data/Cmd/Add/CS (Sync) <100ps <100ps

Notes: If PWR reference, use 0.01uf decoupling cap between PWR and GND for return current

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Table 35. Raw NAND Signal Connections

Function Name Type Termination Description
NAND_D[15:0] I/O NAND Data: Connect NAND_D[15:0] to D[15:0] pins of all NAND devices
NAND_CE[7:0] O NAND Chip Enables: Connect NAND_CE[7:0]_N to CE_N pins each NAND device
O NAND Address Latch Enable: Connect NAND_ALE to ALE pins of all NAND
NAND_ALE devices
O NAND Command Latch Enable: Connect NAND_CLE to CLE pins of all NAND
NAND_CLE devices
NAND_RE_N O NAND Read Enable: Connect NAND_RE_N to RE_N pins of all NAND devices
NAND_WE_N O NAND Write Enable: Connect NAND_WE_N to WE_N pins of all NAND devices
I 10KΩ to VDDIO_NAND or NAND Busy: Connect NAND_BSY0 to BSY (R/B) pins of all NAND devices in
VDDIO_SYS depending on wired or configuration.
NAND_BSY0 location of pin
O 100KΩ to GND General Memory I/F Write Protect: Connect GMI_WP to WP_N pins of all
NAND devices. If GMI_WP_N is used for NAND_CS5_N, connect to
GMI_WP_N SYS_RESET_N or Tegra 2 GPIO pulled low (internally or externally) at boot

Notes: Ball location can be on NAND (Primary) or SYSTEM (Secondary) interface blocks. Refer to Tegra 2 EMT Datasheet “Signal List
and Multiplexing Functions” section for actual Ball Names.

Table 36. NOR/GMI Signal Connections

Function Name Type Termination Description
O GMI dedicated Address lines: For use with non-muxed (add/data) memory
devices. Connect GMI_A[27:0] to A[27:0] (or whatever subset required) pins on
GMI_A[27:0] all Memory devices.
I/O GMI Address/Data: For 16-bit wide devices, connect GMI_AD[15:0] to D[15:0]
pins of all Memory device(s). For 32-bit wide devices (or two 16-bit wide devices
in parallel), connect GMI_AD[27:0] to D[27:0] pins of appropriate Memory
GMI_AD[27:00] device(s). The upper data bits are shown below.
I/O GMI Upper Data: Connect GMI _D[31:28] to D[31:28] of appropriate Memory
GMI_D[31:28] device(s)
O 100KΩ to VDDIO_NAND GMI Chip Selects: Connect GMI_CS[7:0]_N to CS_xN pins of corresponding
GMI_CS[7:0]_N depending on location of pin memory device(s)
GMI_CLK O GMI Clock: Connect GMI_CLK to CLK pins on all memory devices
GMI_ADV_N O GMI Address Valid: Connect GMI_ADV_N to ADV pins on all memory devices
GMI_OE_N O GMI Output Enable: Connect GMI _OE_N to OE_N pins on all memory devices
GMI_WE_N O GMI Write Enable: Connect GMI _WE_N to WE_N pins on all memory devices
O GMI Deep Power Down: Connect GMI_DPD to DPD pins (if supported) on all
GMI_DPD memory devices
I 100KΩ to VDDIO_NAND GMI Wait: Connect GMI_WAIT to WAIT, RDY, R/B pins on all memory devices
GMI_WAIT depending on location of pin
O GMI Reset: Connect GMI_RST_N to RST pins (if supported) for all memory
GMI_RST_N devices
O 100KΩ to GND General Memory I/F Write Protect: Connect GMI_WP to WP_N pins of all
NAND devices. If GMI_WP_N is used for NAND_CS5_N, connect to
GMI_WP_N SYS_RESET_N or Tegra 2 GPIO pulled low (internally or externally) at boot
I GMI Interrupts: Connect GMI_INT[2:1] to INT pins (if supported) for all memory
devices. GMI_INT1 uses the same ball as GMI_WP_N, so if GMI_INT1 is used,
another GPIO will need to be assigned for WP_N if required. GMI_INT2 uses the
same ball as GMI_AD16, so if GMI_INT2 is used, the interface is limited to 16-
GMI_INT[2:1] bits wide.

Notes: Depending on what signals are used, the ball locations can be on NAND, UART and AUDIO interface blocks. Refer to Tegra 2
EMT Datasheet “Signal List and Multiplexing Functions” section for actual Ball Names.

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3.4 USB
Tegra 2 has three USB controllers which can be brought out on a variety of interfaces including USB PHY, ULPI, HSIC and
IC_USB.

Note: USB VBUS overvoltage protection: VBUS must be protected until AVDD_USB is powered as shown in Figure 30.

Controller #1
 Routed to integrated PHY (USB1) and supports low, full and high speed mode
 Both Host and Device modes are supported. VBUS available to support Type A, B or A/B connectors
 USB1 required for Recovery mode and must be configurable as a USB Device (See Force Recovery section below)
Controller #2
 Used for either ULPI or HSIC (Only one can be used per design)
 ULPI is a 12-pin I/F used to connect to compatible external USB PHYs, Baseband or other compatible devices
- Example connection to SMSC USB3315 ULPI to USB PHY shown in ULPI section
 HSIC is a 2-pin I/F for high-speed chip-to-chip communications to compatible external PHYs, hubs, Basebands, etc.
Controller #3
 Either routed to second integrated USB PHY (USB3) or to IC_USB interface. Only one can be used per design.
 USB3 supports low, full and high speed and Host mode. VBUS provided.
- Typical Smartbook designs use USB3 to interface to USB Hub
 IC_USB interface is used to connect to compatible SIM Cards

3.4.1 Force Recovery

The USB1 PHY interface is required to be available as a Device for Force Recovery mode which is used to download new
firmware. The example in Figure 30 shows a USB Micro B connector as the mechanism to connect to a Host system. Force
Recovery mode is entered by keeping the FORCE_RECOVERY pin low when the system is first powered up (until
SYS_RESET_N goes high. This is accomplished by pressing the momentary push button shown during power-on.

Figure 30 Force Recovery Connections

VDDIO_NAND
Tegra 2 ForceRecovery
47KΩ Button
NAND
GMI_OE_N 47KΩ

1.8V,
VDDIO_NAND
2.8-3.3V

USB1 VBUS
1
90R@100MHz DN
USB1_DN 2
DP USB
USB1_DP 3
ACC1_DET
ID
4
Micro B
USB1_VBUS 5
220R@100MHz PWR 6
3.3V 1 DM
2 DP 4
NC 5
NC
3 ID 7
AVDD_USB
GND
AVDD_USB_PLL

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3.4.2 Mini-Card
Figure 31 shows USB & SMB (I2C) from Tegra 2 connected to a Mini-Card socket. The Mini-Card socket is one method for
supporting Baseband modules (currently using only the USB interface portion of the Mini-Cards). A SIM socket is provided off
one of the Mini-Card connectors for this purpose..

Figure 31. Example USB / I2C to Mini-Card Socket Connections

1 6
5
3 4

2
SIM
GND VCC
UIM_VPP UIM_RESET
VPP RST
UIM_DATA UIM_CLK
IO CLK
UIM_IC_DM UIM_IC_DP
DN DP
NC NC
1 6
5
3 4

2
3.3V
3.3V VDDIO_UART
1 2
WAKE_N 3.3VAUX 1.5V
3 RESERVED GND 4
5 RESERVED 1.5V 6
7 8
2.2KΩ

2.2KΩ

2.2KΩ

2.2KΩ
CLKREQ_N UIM_PWR
9
11
GND
REFCLKn
UIM_DATA
UIM_CLK
10
12 Tegra 2
13 REFCLKp UIM_RESET 14
15 GND UIM_VPP 16
17 18
19
RES/UIM_C8 GND
20
3.3V VDDIO_UART UART
RES/UIM_C4 RESERVED
21 22
GND PERST_N VCCB VCCA
23 PERn0 24
25 PERp0 Mini 3.3VAUX
GND 26 B1 Level A1 GEN1_I2C_SCL
27 GND 1.5V 28 B2 Shifter A2 GEN1_I2C_SDA VDDIO_UART 1.8V
29
31
GND Card SMB_CLK 30
32
DIR GND
PETn0 SMB_DATA
33 PETp0 GND 34
3.3V 35 GND USB_Dn 36 USB
37 GND USB_Dp 38
39 3.3VAUX GND 40
41 42 USB3_DN AVDD_USB
3.3VAUX LED_WWAN_N
43 GND LED_WLAN_N 44 USB3_DP AVDD_USB_PLL 3.3V
45 RESERVED LED_WPAN_N 46
47 RESERVED 1.5V 48
49 RESERVED GND 50
51 RESERVED 3.3VAUX 52

3.4.3 USB Design Guidelines

Table 37. USB Interface Signal Routing Requirements

Parameter Requirement
Max Frequency (High Speed) 480Mb/s, UI=2.083ns (240MHz)
Max Loading 10pf (High Speed), 150pf (Full Speed), 600pf (Low Speed)
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Trace Impedance 90Ω diff pair ±15%, 50Ω Single Ended ±15%
Max Trace Length Microstrip: max 15’’, Stripline: max 13”
Max Intra-Pair Skew between USBx_DP & USBx_DN <7.5ps

Table 38. USB Signal Connections

Ball Name Type Termination Description
USB1_DP, USB3_DP DIFF I/O 90Ω common-mode chokes close USB Differential Data Pair: Connect to USB connector, Mini-Card Socket,
USB1_DP, USB3_DN to connector. Internal 19.5 kΩ to Hub or other device on the PCB.
GND. Internal 45Ω termination to
GND on each pad (90Ω diff.)
USB1_VBUS A 220Ω choke in series with VBUS USB Bus 5V Supply from Host/Hub: Connect VBUS from connector to
from connector. USB1_VBUS choke, then to gating device input (FET, LDO, etc.). Connect enable of
gated with AVDD_USB Gating device to AVDD_USB. Connect output of gating device to
USB1_VBUS pin.
ACC1_DETECT A 1KΩ series resistors Accessory Detect: Connect to ID pin on USB connector if applicable (i.e.
ACC3_DETECT Micro A/B or proprietary conn.) & Tegra 2 Host mode supported.
USB_REXT A 1KΩ, 1% to GND External Reference: Connect through 1K resistor to GND

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3.5 ULPI
Tegra 2 supports ULPI (UMTI+ Low Pin Interface) as an option for the USB Controller #2. This can be used to connect to
external USB PHYs, or other compatible devices. Figure 32 shows Tegra 2 connecting to ULPI-USB PHY. The PHY can then
interface to a compatible Baseband, USB Hub, etc. The ULPI Interface supports an 8-bit SDR data interface only – 4-bit DDR
data I/F is not supported.

Figure 32. Example ULPI connection to External SMSC USB3315 USB PHY

Tegra 2 SMSC USB3315

BASEBAND ULPI_CLK ULPI CLKOUT USB_DP

ULPI_DIR ULPI DIR USB_DN
ULPI_NXT ULPI NXT VBUS
ULPI_STP ULPI STP ID
ULPI_DATA[7:0] ULPI DATA
VBAT
1.8V VDDIO_BB GPIO_PV1 RESET VDD3V3
VDD1V8
24MHz VDDIO
AUDIO DAP_MCLK2 REFCLK
CPEN
1.8V VDDIO_AUDIO RBIAS 8.06KΩ,1%
GND_TP

3.5.1 ULPI Design Guidelines

Table 39. ULPI Interface Signal Routing Requirements

Parameter Requirement
Frequency / Topology 60MHz / Point to point (480Mbps)
Max Loading 10pf
Reference plane GND or PWR (see note)
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length < 45ps
Trace Impedance 90Ω diff pair ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 1.5x dielectric
Max Trace Length < 650ps
Max Trace Length Skew between DATA & CLK <100ps

Notes: If PWR reference, use 0.01uf decoupling cap between PWR and GND for return current

Table 40. ULPI Signal Connections

Ball Name Type Termination Description
ULPI_DATA[7:0] I/O ULPI Data.: Connect to DATA pin of ULPI device
ULPI_CLK I/O Optional 10Ω series resistor near ULPI Clock.: Connect to CLK pin of ULPI device
ULPI device CLK pin
ULPI_DIR I/O ULPI Direction: Connect to DIR pin of ULPI device
ULPI_NXT I/O ULPI Next: Connect to NXT pin of ULPI device
ULPI_STP I/O ULPI Stop.: Connect to STP pin of ULPI device
DAP_MCLK2 O DAP Master Clock 2: Optionally clock for some ULPI devices that require
a reference clock. Connect DAP_MCLK2, set to output OSC to REFCLK pin
of ULPI device if REFCLK not provided elsewhere. Frequency will equal to
Tegra 2 reference frequency (Crystal or external source on XTAL_IN/OUT)
or 2x reference frequency. Choose frequency based on ULPI device
requirements for REFCLK.

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3.6 HSIC
An alternative for the USB Controller #2 is to support HSIC (High Speed Inter-Chip). This 2-pin, 1.2V CMOS I/F can connect to
compatible USB PHYs, hubs, peripherals, etc. Figure 33 shows Tegra 2 as the Host interfacing with an external HSIC-USB
Hub.

Figure 33. Example HSIC connection to USB Hub

Tegra 2 HSIC_STROBE STROBE USB HUB

(HSIC Host) HSIC_DATA DATA (HSIC Device)
1.2V VDDIO_HSIC HSIC_REXT 1.2KΩ,1%

3.6.1 HSIC Design Guidelines

Table 41. HSIC Interface Signal Routing Requirements

Parameter Requirement
Frequency / Topology 480Mb/s, UI=2.083ns (240MHz). Point to Point topology
Max Loading 14pf
Reference plane GND
Trace Impedance 50Ω ±15%
Trace Spacing Microstrip Not tested
Stripline 3x dielectric
Max Trace Length < 4”
Max Trace Length Skew between HSIC_STROBE & HSIC_DATA <15ps

Table 42. HSIC Signal Connections

Ball Name Type Termination Description
HSIC_STROBE I/O HSIC Strobe: Connect HSIC_STROBE to STROBE pin on HSIC device
HSIC_DATA I/O HSIC Data: Connect HSIC_DATA to DATA pin on HSIC device
HSIC_REXT A 1.2KΩ, 1% to GND HSIC External Reference Resistor. Connect as described in termination
column

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3.7 PCIE (Tegra 250 Only)

Tegra 2 contains a PCIe controller that can be brought out as two, 2-lane or one 4-lane interfaces. This narrow, high-speed
interface can be used to connect to a variety of high bandwidth devices.

Figure 34. Example PCIe Connections

Tegra 2
PEX PEX_CLK_OUT1_N
PEX_CLK_OUT1_P
PEX_CLK_OUT2_N
PEX_CLK_OUT2_P

0.1uf
PEX_L0_TXN
0.1uf
PEX_L0_TXP
PEX_L0_RXN
PEX_L0_RXP

0.1uf
PEX_L1_TXN
0.1uf
PEX_TERMP PEX_L1_TXP
PEX_L1_RXN
2.49KΩ,1%

PEX_L1_RXP

0.1uf
PEX_L2_TXN
0.1uf
PEX_L2_TXP
PEX_L2_RXN To PCIE Mini-Card,
direct to peripheral or
PEX_L2_RXP proprietary connector
3.3V VDDIO_PEX_CLK
0.1uf
PEX_L3_TXN
1.05V 0.1uf
PEX_L3_TXP
PEX_L3_RXN
VDD_PEX
PEX_L3_RXP
AVDD_PCIE
AVDD_PEX PEX_REFCLKP
AVDD_PEX_PLL PEX_REFCLKN
120R@100MHz
100KΩ 3.3V
PEX_WAKE_N
SDIO SDIO3_DAT1
PEX_CLKREQ0_N
GPIO_PV6
PEX_CLKREQ1_N
SDIO3_DAT0
PEX_RST0_N
GPIO_PV5
PEX_RST1_N
3.3V VDDIO_SDIO SDIO3_DAT4
PEX_PRSNT0_N
GPIO_PV4
PEX_PRSNT1_N
SDIO3_DAT5

3.7.1 PCIE Design Guidelines

Table 43. PCIE Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 2.5Gb/s, UI=400ps (1.25GHz)
Topology Point to point, unidirectional, differential
Configuration / Device Organization 1 load
Max Load (per pin) 0.5 pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Trace Impedance 100Ω diff pair ±10%, 55Ω Single Ended ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length 15.5 inches
Max Intra-Pair Trace Length Skew 1ps
Max Inter-Pair Trace Length Skew (Within Link) 1.6ns

Note: Void region under BGA pads. Remove slivers between BGA pads and feedthru to vias
Do trace length matching before the vias to transition to different layers
For PCIE Mini-Card: 100nF discrete 0402 on PCB halfway between Tegra 2 & socket pins

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Table 44. PCIE Signal Connections

Ball Name Type Termination Description
PEX_CLK_OUT[2:1]_P O PEX Clock Output: Connect PEX_CLK_OUT[2:1]_P/N pins to
PEX_CLK_OUT[2:1]_N Device/Connector REFCLKP/N pins.
PEX_L[3:0]_TXP DIFF OUT Series 0.1uf Capacitor Differential Transmit Data Pair: Connect to PETN/P/pins of
PEX_L[3:0]_TXN corresponding PCIe device/Mini-Card socket according to supported
configuration.

If not used: Leave NC.

PEX_L[3:0]_RXP DIFF IN Refer to other device, or specific Differential Receive Data Pair: Connect to PERN/P pins of corresponding
PEX_L[3:0]_RXN connector’s spec. for series AC- PCIe device/Mini-Card socket according to supported configuration.
coupling capacitor requirement.
If not used: Connect to GND
PEX_CLKREQ[1:0]_N I PEX Clock Request: Connect to CLKREQ pins on device or connectors
PEX_WAKE_N I 100KΩ pullup to 3.3V PEX Wake: Connect to WAKE pins on device or connector
PEX_PRSNT[1:0]_N I PEX Present: Connect to Present pins on connector(s) if supported
PEX_TERMP A 2.49KΩ, 1% to GND PCIe Calibration: Routing: nominal impedance and 2× dielectric height
spacing.
Max PCB trace length 1 inch.
VDDIO_PEX_CLK P PEX Clock I/O Power Rail: Connect to 3.3V supply
VDD_PEX P PEX Digital Power Rail: Connect to 1.05V supply
AVDD_PLLE P PEX PLL (for 100MHz reference): Connect to 1.05V supply
AVDD_PEX P PEX Analog Power Rail: Connect to 1.05V supply
AVDD_PEX_PLL P 120R@100MHz ferrite bead to PEX PHY PLL Power Rail: Connect to 1.05V supply through bead listed in
3.3V termination column
PEX_REFCLKP DIFF OUT PEX Reference Clock: Unused, connect to GND
PEX_REFCLKN
PEX_TSTCLKP DIFF OUT PEX Test Clock: Unused, connect to GND
PEX_TSTCLKN

Note: If PCIe (PEX) is supported, Tegra 2 reference clock must be 12MHz.

Table 45. PCIE Configurations

PCIE Signal Supported Configurations
1, x4 2, x2
1, x2 1, x2
PEX_CLK_OUT1_N √ √
PEX_CLK_OUT2_N √
PEX_L0_TXN/P √ √
PEX_L1_TXN/P √ √
PEX_L2_TXN/P √ √
PEX_L3_TXN/P √ √
PEX_CLKREQ0_N √ √
PEX_CLKREQ1_N √
PEX_RST0_N √ √
PEX_RST1_N √
PEX_PRSNT0_N √ √
PEX_PRSNT1_N √
PEX_WAKE_N √ √ √

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3.8 Internal (LCD) Display Interfaces

A broad range of interfaces for LCD displays are supported by Tegra 2. Two separate display controllers can drive up to two
displays simultaneously. Or, one of the displays can be an LCD while the other an HDMI display, standard CRT or SDTV.
Alternately, a number of dual LCD combinations are supported.
 Simple (Dumb) Parallel RGB interfaces (16-bit, 18-bit or 24-bit color)
 Parallel Host interfaces from 6 to 24-bits wide (16-bit, 18-bit or 24-bit color)
 Parallel RGB to LVDS Transmitter Interface
 Serial (SPI) initialization Interface
 MIPI DSI Interface

3.8.1 Parallel RGB (Dumb) Display Interface

This type of interface typically has a Pixel clock, Vertical/Horizontal Syncs and a Display Enable. In addition, from 8 to 24 pixel
data lines complete the interface. These types of displays typically do not have their own display buffer memory and require
Tegra 2 to refresh them continuously out of the SDRAM memory.

Figure 35. 18-bit RGB LCD Connection Example

Tegra 2 18-bit RGB LCD

LCD_PCLK PIX_CLK
LCD_VSYNC VSYNC
LCD_HSYNC HSYNC
LCD_DE DATA_EN

LCD_D[17:12] R[5:0]
LCD_D[11:6] G[5:0]
LCD_D[5:0] B[5:0]

1.8V,
VDDIO_LCD
2.8V-3.3V

Figure 36 shows a 24-bit Parallel RGB interface with serial (SPI like) interface for control/register programming. SPI3 is routed
to LCD_CS0, LCD_SCK, LCD_SDOUT and LCD_SDIN. Tegra 2 can write or read from the LCD display driver. RGB data is
still transferred over the parallel interface. Note that the lower two bits of Red, Green and Blue to the panel come from the upper
6-bits (LCD_D[23:18]) of the 24-bit LCD interface on the Tegra 2.

Figure 36. 24-bit RGB+SPI LCD Connection Example

Tegra 2 24-bit RGB+SPI LCD

LCD_PCLK PIX_CLK
LCD_VSYNC VSYNC
LCD_HSYNC HSYNC
LCD_DE DATA_EN
Parallel
LCD_D[17:12] R[7:2]
RGB
Data I/F LCD_D[23:22] R[1:0]
LCD_D[11:6] G[7:2]
LCD_D[21:20] G[1:0]
LCD_D[5:0] B[7:2]
LCD_D[19:18] B[1:0]

LCD_CS0 SPI_CS
Optional LCD_SCK SPI_CLK
Control
LCD_SDOUT SPI_DIN
I/F (SPI)
LCD_SDIN SPI_DOUT

1.8V,
VDDIO_LCD
2.8V-3.3V

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3.8.2 Parallel Host (Smart) Display Interface

Another interface type supported is the Parallel Host. This is used with displays that contain integrated display controllers and
typically frame buffers as well. Both commands and pixel data are transferred over this type of interface.
 Typically Chip Select, Write Enable and Data/Control signals
 Data bus widths of 6, 8, 9, 16, 18 or 24-bits
 Narrow Interfaces require multiple transfers per command or pixel data

Figure 37 shows basic connections to a 16-bit Host type LCD display. Since these devices usually have their own frame
buffers, they can optionally perform self-refresh of the display so the Tegra 2 does not have to always drive the pixel data. This
can be useful to lower power or signal noise in some situations.
Figure 37. 16-bit Host I/F LCD Connection Example

Tegra 2 16-bit Host LCD

LCD_CS0 Chip Select
LCD_PCLK Write Enable
LCD_DC0 Data/Control

LCD_D[15:11] R[4:0]
LCD_D[10:5] G[5:0]
LCD_D[4:0] B[4:0]

1.8V,
VDDIO_LCD
2.8V-3.3V

3.8.3 Parallel RGB to LVDS Transmitter LCD Interface

An 18-bit interface to an external LVDS Transmitter to connect to common Tablet or Smartbook panels is described. Other
interface options are possible. The example assumes an SPWG 18bpp single channel LVDS panel interface. 24bpp solution is
also supported.

Figure 38. Example LVDS Connections

Tegra 2 LVDS LVDS Panel

Transmitter
LCD_PCLK CLKIN Y0M
LCD_VSYNC D25 Y0P
LCD_HSYNC D24 Y1M
LCD_DE D26 Y1P
Y2M
RED[4:0]
LCD_D[16:12] D[4:0] Y2P
RED5
LCD_D17 D6 CLKOUTM
GREEN[2:0]
LCD_D[8:6] D[9:7] CLKOUTP
GREEN[5:3]
LCD_D[11:9] D[14:12]
BLUE0
LCD_D0 D15 IOVCC VDDIO_LCD
BLUE[5:1]
LCD_D[5:1] D[22:18] 120R@100MHz
PLLVCC VDD_LVDS
120R@100MHz
VDDIO_LCD CLKSEL
LVDSVCC
VCC
LCD_PWR0 SHTDN
PLLGND
10KΩ
LVDSGND
1.8V VDDIO_LCD GND

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Figure 39. Single Channel LVDS Signal Mapping

Previous Data Current Data

LVDS_CLKOUTP/N

LVDS_Y0P/M R1 R0 G0 R5 R4 R3 R2 R1 R0 G0

LVDS_Y1P/M G2 G1 B1 B0 G5 G4 G3 G2 G1 B1

LVDS_Y2P/M B3 B2 DE VS HS B5 B4 B3 B2 De

Table 46. LCD Interface Signal Routing Requirements (External LVDS Transmitter)
Parameter Requirement
Max Frequency 50MHz – Flex display, 133MHz – External transceiver
Topology Point to Point
Configuration / Device Organization 1 load
Max Loading 40pf (Flex display), 20pf (External transceiver)
Reference plane GND or PWR (In case of PWR reference, use decoupling cap (0.01uf)
between PWR and GND for return current)
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 45ps (~0.3”)
Trace Impedance 90Ω diff pair ±15% / 90Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 2x dielectric
Max Trace Length <900ps (Flex display), <450ps (External transceiver)
Max Trace Length Skew between CLK & Data <100ps

Table 47. LCD Signal Connections

Ball Name Type Termination Description
LCD_PCLK O None LCD Pixel Clock (Primary LCD Display): Connect to Pixel (Dot) Clock pins
on panel connector or Onboard Transmitter if present (I.E. LVDS)
LCD_VSYNC O None LCD Vertical/Horizontal Syncs: Connect to Vsync/Hsync pins on panel
LCD_HSYNC connector or Onboard Transmitter if present (I.E. LVDS)
LCD_DE O None LCD Display Enable: Connect to DE pin of panel connector or Onboard
Transmitter if present (I.E. LVDS)
LCD_D[23:0] O None LCD Data: Connect to Data (RGB) pins of panel connector or Onboard
Transmitter if present (I.E. LVDS). Check the example diagrams for correct
connection to 16-bit, 18-bit or 24-bit devices.
LCD_CS[1:0]_N O None LCD Chip Selects (CS0 – Primary LCD, CS1 - Secondary Display): Connect
to CS pin of panel connector. Typically used for Host type interfaces
(parallel or serial)
LCD_SCK O None LCD Serial Shift Clock: Connect to Serial Clock pin of panel connector
LCD_SDOUT O None LCD Serial Data Out: Connect to Serial data in pin of panel connector
LCD_SDIN I None LCD Serial Data In: Connect to Serial data out pin of panel connector
LCD_PWR[2:0] O None LCD Power Control: Typically used as GPIOs to control power/shutdown
features on panel, backlight, etc.
LCD_DC[1:0] O None LCD Data Command Select (DC0 – Primary LCD, DC1 - Secondary
Display): Connect to DC/RS pin of panel connector. Typically used for
Host type interfaces (parallel or serial)
LCD_WR_N O None LCD Write Strobe (Secondary Display): Connect to WR pin of panel
connector. Typically used for parallel Host type interfaces

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3.8.4 MIPI DSI

In addition to the digital interfaces described in the LCD Display section, Tegra 2 also supports a high-speed serial differential
MIPI DSI interface to connect to compatible displays. One or two data lanes are supported, each capable of up to 1Gbps data
rate. Lane 1 is bidirectional (High Speed Out, Low Power/speed In from display).

Figure 40: DSI Single/Dual Connection Example

Tegra 2 DSI LCD

DSI_CLKAP
Clock
DSI_CLKAN
DSI_D1AP
Channel 1
DSI_D1AN
DSI_D2AP
Channel 2
DSI_D2AN

DSI_CSI_RUP 453Ω,1% AVDD_DSI_CSI

DSI_CSI_RDN 49.9Ω,1%

AVDD_DSI_CSI 1.2V

3.8.4.1 MIPI DSI and CSI Design Guidelines

Table 48. MIPI DSI Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 500MHz (1GT/S per data lane)
Configuration / Device Organization 1 load
Max Loading (per pin) 10pf
Reference plane GND or PWR (In case of PWR reference, use decoupling cap (0.01uf)
between PWR and GND for return current)
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 48ps (~0.3”)
Trace Impedance 90Ω diff pair, 50Ω Single Ended, 25 Ω Common-mode (±20%)
Trace Spacing (pair to pair) Microstrip 2x dielectric
Stripline 2x dielectric
Max Trace Length < 1.62ns
Max Intra-pair Skew <1ps
Max Inter-pair Skew <10ps

Table 49. MIPI DSI Signal Connections

Ball Name Type Termination Description
DSI_CLKAN O DSI Differential Clock: Connect to CLKn & CLKp pins of receiver
DSI_CLKAP
DSI_D[2:1]AN I/O DSI Differential Data Lanes: Connect to Dn & Dp pins of receiver
DSI_D[2:1]AP
CSI_CLKAN I CSI A Differential Clock: Connect to CLKn & CLKp pins of Transmitter
CSI_CLKAP (Main camera)
CSI_CLKBN I CSI B Differential Clock: Connect to CLKn & CLKp pins of Transmitter
CSI_CLKBP (Secondary camera)
CSI_D[2:1]AN I CSI A Differential Data Lanes: Connect to Dn & Dp pins of Transmitter
CSI_D[2:1]AP (Main camera)
CSI_D1BN I CSI B Differential Data Lanes: Connect to Dn & Dp pins of Transmitter
CSI_D1BP (Secondary camera)
DSI_CSI_RDN A 49.9Ω, 1% to GND DSI/CSI Voltage Reference Pulldown:
DSI_CSI_RUP A 453Ω, 1% to 1.2V DSI/CSI Voltage Reference Pull-up:

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3.9 External Display Interfaces

 HDMI
 CRT (VGA)
 SDTV (TV Out)

3.9.1 HDMI
A standard 3-lane HDMI V1.3 interface is supported as one option for an external display.
 DDC_SCL/SDA pins are 5V tolerant (no level shifter required). Lines pulled up to 5V supply.
 HP_DET drives HDMI_INT on Tegra 2 (Also 5V tolerant - no level shifter required).

Figure 41: HDMI Connection Example

1.8KΩ 5V
5V
TYPE A CONNECTOR
Tegra 2 1.8KΩ
120R@100MHz
HDMI_DDC_CLOCK
LCD DDC_SCL 33Ω
120R@100MHz HP_DET
HDMI_DDC_DATA 0.1pf 19
DDC_SDA 33Ω +5V_F
120R@100MHz 18
1.8, HDMI_INT DDC/CEC_GND
VDDIO_LCD HDMI_INT 1KΩ 17
2.8-3.3V 220pf DDC_DATA
16
100KΩ DDC_CLOCK
15
RSRVD
4.7pf 4.7pf 14
CEC
13
CK-
12
HDMI CK_SHIELD
11
CK+
10
D0-
HDMI_TXCN 9
3.3V D0_SHIELD
HDMI_TXCP 8
D0+
AVDD_HDMI HDMI_TXD0N 7
D1-
HDMI_TXD0P 6
1MΩ

D S D1_SHIELD
HDMI_TXD1N 5
G D1+
HDMI_TXD1P 4
1.8V D2-
HDMI_TXD2N 3
D D2_SHIELD
HDMI_TXD2P 2
D2+
G 1
S
HDMI_RSET
1 5
1KΩ,1%

PWR +5V_F
3 2
AVDD_HDMI_PLL 4 NC
6 7
GND
SHIELD GND

3.9.1.1 HDMI Design Guidelines

Table 50. HDMI Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 165MHz
Configuration / Device Organization 1 load
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Trace Impedance 90Ω diff pair ±15%, 45-55Ω Single Ended ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length 11”: Microstrip, 9”: Stripline
Max Intra-Pair Skew < 5ps
Max Inter-Pair Skew < 150ps (see note below for EMI)

Notes: Routing Over void not allowed (Anti-pad at connector pins causes voids. Route traces w/min. void references)
If signals switch ref. layers, add symmetrical stitching via close to signal vias. Max GND via distance = 1x diff pair via pitch
EMI: It is recommended that the length of the data pairs be skewed 50ps – 75ps from each other to reduce EMI (all data
pairs should have different lengths)

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Table 51. HDMI Signal Connections

Ball Name Type Termination Description
HDMI_TXCN O ESD protection diodes (to GND) HDMI Differential Clock: Connect HDMI_TXCN/TXCP to CP-/CP+ pins on
HDMI_TXCP HDMI Connector
HDMI_TXD[2:0]N O ESD protection diodes (to GND) HDMI Differential Data: Connect HDMI_TXCN/TXCP to CP-/CP+ pins on
HDMI_TXD[2:0]P HDMI Connector
HDMI_INT_N I Place the following in order from Tegra 2: HDMI Interrupt (Hot Plug Detect): Connect to HP_DET pin on HDMI
1000KΩ to GND Connector
1KΩ series resistor
220pF to GND
ESD protection diodes (to +5V & GND)
HDMI_RSET A 1KΩ, 1% to GND HDMI Current Reverence: Route at nominal impedance and 2× dielectric
height spacing to resistor.
DDC_SCL I/OD The following apply to each DDC line in HDMI/VGA DDC Interface – Clock and Data: Connect to DDC_SCL and
DDC_SDA order from Tegra 2: DDC_SDA pins (respectively) of HDMI connector.
1.8kΩ to +5V
33Ω series resistor Routing: Route at nominal impedance and 1× dielectric height spacing. No
length restrictions.
120R@100MHz Bead in series
ESD protection diodes (to +5V & GND) Note: DDC is used by both HDMI and VGA. If both are implemented in a
4.7pF to GND system, only a single set of series and pull-up resistors should be used.

3.9.2 RGB DAC Interface

Tegra 2 RGB DAC interface can be used to connect to a VGA monitor or an SDTV (Composite, S-Video or Component).

Below is an example of a connection between Tegra 2 and the various components to implement a VGA (CRT) connection.

Figure 42. VGA (CRT) Output Connection Example

+5V

Tegra 2 GND-R
68nH
R ID0 SHIELD
VDAC_R
VDAC 68nH
GND-G
G DDC_DATA
VDAC_VREF VDAC_G
68nH GND-B
B HSYNC
VDAC_RSET VDAC_B
0.1uf 5V
1KΩ, 1%

10pf 10pf 10pf 10pf 10pf 10pf 1D2 VSYNC

150 Ω

150 Ω

150 Ω
150 Ω

150 Ω

150 Ω

GND
GND DDC_CLOCK

VDDIO_LCD +5V
SHIELD
2.8V –
AVDD_VDAC Level Shifter 220R@100MHz
3.3V
VCAA VCCB 33Ω
A1 B1 220R@100MHz
LCD CRT_VSYNC A2 B2 33Ω
47pf 47pf
CRT_HSYNC DIR GND
0.1uf
1.8KΩ +5V 0.1uf

1.8KΩ 220R@100MHz
DDC_SCL 33Ω +5V
220R@100MHz
1.8, 2.8V
VDDIO_LCD DDC_SDA 33Ω
– 3.3V 4.7pf 4.7pf 1 5
3 PWR
2
4 NC
6 7
GND

For TV Output, VDAC_R, VDAC_G and VDAC_B carry Composite Video or S-Video. Composite Video can be programmed to
come out on any of the 3 but the example below shows it coming out on VDAC_B.

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Figure 43. Composite Connection Example

100nH
Composite
Tegra 2 VDAC_B
Video
VDAC_R
8pf 12pf

150 Ω

150 Ω
VDAC_G

0.1uf
VDAC_VREF

2.8V –
AVDD_VDAC VDAC_RSET 1KΩ, 1%
3.3V

Figure 44. Combined S-Video/Composite Connection Example

S-Video (both VDAC_R & VDAC-G)
100nH Composite Video (Only VDAC-G)
Tegra 2 VDAC_R
VDAC_B 100nH
VDAC_G

0.1uf 8pf 8pf 12pf 12pf

150 Ω

150 Ω
150 Ω

150 Ω
VDAC_VREF

2.8V –
AVDD_VDAC VDAC_RSET 1KΩ, 1%
3.3V

Termination Placement
 Two 150 Ω terminations (to GND) are needed for each of the three RGB lines. One should be placed near Tegra 2
(within 600 mils) and the other near the connector.
 The three-pole filter should be placed within 600 mil of the connector, using values 8pF/100nH / 12pF (see Figure 45
for more detail).
 ESD protection diodes (place-holders) should be placed close to the connector, preferably between the 150Ω
termination and the three-pole filter. Connect to +3.3V and GND vias with >15 mil trace width and no longer than 75 mil.
Routing
Unless otherwise specified, follow these guidelines for routing RGB signals:
Tegra 2 BGA Breakout (< 150 mil):
 Route nominal impedance and 1.5× dielectric height spacing
After Breakout:
 RGB signals should be routed at specified impedance for each segment, 15 mil spacing to each other, and 20 mil
spacing to other signals.
 All three RGB signals should be matched as close as possible with a maximum length of 10 inches.
 Keep RGB signals >250 mil away from any areas of the board that experience high switching currents, such as
switching voltage regulator FETs and inductors, and CPU signals. Keep >50 mil away from clocks, high current power
traces, and vias.
 RGB signals should reference a solid GND plane for the entire route. If this is not possible, vias should be kept to a
minimum.
 Ground elements of the filter and terminations can be routed together and tied to a single point grounded to a quiet
area of the digital plane.
 Optionally, a trace tied to GND at several points can encircle the RGB signals on each layer to assist in keeping them
quiet. Highly recommended for signal length ~ 10 inches.

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Figure 45: Placement of VDAC Three-Pole Filter

L1
DAC A B C C D To Connector

Diodes
150 Ω

150 Ω
C1 C2

ESD
Figure 2-6. Placement of RGB Three-Pole Filter

Note: For VGA Output: L1 = 68nH C1 = C2 = 10pF

For TV Output: L1 = 100nH C1 = 8pF, C2 = 12pF

Table 52. RGB DAC Connections

Ball Name Type Termination Description
VDAC_R O Refer to Figure 45 RGB DAC Output
VDAC_G 150Ω to GND within 600 mil of Tegra 2 Connect to respective R, G, B pins of VGA connector.
VDAC_B Three-pole filter within 600 mil of connector
Routing:
Another 150Ω to GND near the connector
Section Z Max Delay Spacin
ESD protection diodes placed before three-pole
g
filter and connected to +3.3V and GND
A 37.5 Ω 600 mil (100 ps) 15 mil
B 50 Ω 6000 mil (1 ns) 15 mil
Note: RGB signal balls meet the ESD standard
IEC_61000_4_2 at 2 kV. If more stringent ESD C 50 Ω 120 mil (20 ps) 15 mil
protection is needed, external diodes should be D 75 Ω * 600 mil (100 ps) 15 mil
used.
* If 75 Ω impedance on a 4 layer PCB is not achievable, it is OK to
One 75Ω resistor (instead of two 150Ω) to GND
change to an achievable impedance (around 50 Ω).
can be used if the trace is short.
CRT_HSYNC O Need a 3.3V-to-5V buffer/Level shifter before RGB Horizontal/Vertical Sync: Connect to respective HSYNC and
CRT_VSYNC going to VGA connector. VSYNC pins of VGA connector.
Series 33Ω resistor and 220R@100MHz inductor
at the output of buffer. Routing: Route at nominal impedance and 4× dielectric height
spacing.
47pF Capacitors to GND
ESD protection diodes connected to +5V and
GND.
Note: Filter component values are dependent on
the 3.3V-to-5V buffer used. Listed values are as
implemented on an NVIDIA reference design.
Each design must be verified to meet the VGA
connector specification.
VDAC_RSET A 1KΩ 1% to GND within 750 mils of Tegra 2 Current Reference:
Routing: Route at nominal impedance and 2× dielectric height
spacing to resistor.
VDAC_VREF A 0.01μF to GND within 500 mils of Tegra 2 Voltage Referenc:
Routing: Route at nominal impedance and 2× dielectric height
spacing to capacitor.
DDC_SCL OD • 33Ω series resistor, then 2.2kΩ to +5V (both close to VGA DDC Interface – Clock and Data
DDC_SDA VGA connector). • Connect to SCL and SDA pins (respectively) of VGA connector
• 470pF to GND at connector
• ESD protection diodes to +5V and GND Routing: Route at nominal impedance and 1× dielectric height
spacing. No length restrictions.

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3.10 Video Input

The Video Input block in the Tegra 2 supports both a both a 10-bit digital interface as well as two MIPI CSI interfaces, allowing a
variety of device types and combinations to be supported.
MIPI CSI Interfaces
 Two MIPI CSI I/Fs – One with dual data lane, one with single lane.
 Each data channel has peak bandwidth up to 1Gbps
Digital Parallel Interfaces
 8-bit YUV digital I/F with external or embedded syncs (ITU601, ITU656)
 10-bit Bayer digital I/F
 Supports clock rates up to 125MHz
 Provides Master reference clock (MCLK) to imager up to 80MHz
2
 I C available plus 5 dedicated GPIOs

3.10.1 MIPI CSI Imager Connections

The TEGRA 2 can interface to one or two MIPI CSI imagers. Figure 46 shows connections to two CSI imagers. The upper
imager has one or two data channels. Two channels may be required for larger resolution imagers to keep the data rate lower
on each. Some items to note:
 CAM_I2C interface shown connected as this is still used for configuration/control
 Resistors required on DSI_CSI_RUP/ DSI_CSI_RND and the same described in the MIPI DSI section. Only one set is
required and serve both the CSI and DSI interfaces.
 MCLK available for imager to use as reference clock if needed
 GPIOs for imager reset/power-down shown similar to previous examples but with two imagers, an additional GPIO
(VI_GP0) allows one or both imagers to be placed in reset. A single GPIO is used for power-down, although it would
be possible to have separate power-down control if necessary.

Figure 46: Dual MIPI CSI Imager Connection Example

VDDIO_VI

Tegra 2 100KΩ
2.2KΩ
2.2KΩ
VI VI_MCLK REFCLOCK
CAM_I2C_SCL I2C_SCL
CAM_I2C_SDA I2C_SDA
CAM_RST_N
VI_GP5 RESET
VI_GP4 CAM_PDWN
PWRDOWN
CAM_AF_PDWN_N
1.8V–3.3V VDDIO_VI VI_GP0 AF_PDWN
100KΩ
100KΩ
CSI CSI_CLKAP
Clock A
CSI_CLKAN
CSI_D1AP
Channel 1A
CSI_D1AN
CSI_D2AP
Channel 2A
CSI_D2AN

REFCLOCK
I2C_SCL
I2C_SDA
AVDD_DSI_CSI RESET
PWRDOWN
453Ω,1% DSI_CSI_RUP CSI_CLKBP
Clock B
CSI_CLKBN
49.9Ω,1% DSI_CSI_RDN
CSI_D1BP
Channel 1B
1.2V AVDD_DSI_CSI CSI_D1BN

3.10.1.1 CSI Design Guidelines

CSI and DSI both use the MIPI D-PHY for the physical interface. The routing and connection requirements can be found in the
MIPI DSI section.

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3.10.2 YUV Imager Connections

The Example in Figure 47 shows a typical connection to a YUV imager:
 CCIR601 type interface (external syncs) shown.
 8-bits of data connect to imager (Note VI_D[9:2] used for YUV data)
 MCLK available for imager to use as reference clock eliminating need for external source

Note: If two imagers are implemented, both using the digital parallel interface, only one at a time can be driving the imager clock, sync
and data lines. The other must tri-state these pins. Separate resets are often used for this purpose.

Figure 47: YUV Imager Connection Example

4.7KΩ VDDIO_VI
4.7KΩ
Tegra 2 VI_MCLK REF_CLK
VI_PCLK PIX_CLK
VI_HSYNC HSYNC
VI_VSYNC VSYNC
VI_D[9:2] PIX_DATA
CAM_I2C_SCL I2C_SCL
CAM_I2C_SDA I2C_SDA
VI_GP5 RESET
1.8,
VDDIO_VI VI_GP4 PWRDOWN
2.8-3.3V

3.10.3 Bayer Imager Connections

A connection to a Bayer style imager is shown in Figure 48:
 TEGRA 2 supports up to 10-bit interface for Bayer imagers
 10-bits of data connect to imager (VI_D[9:0] to Imager Data[9:0]). For imagers with less than 10-bits, connect to upper
bits of VI_D[9:0]. Those with more should connect VI_D[9:0] to upper bits of imager interface.
 MCLK available for imager reference clock eliminating need for external source
 CAM_I2C_SCL and CAM_I2C_SDA used to configure/control imager

Figure 48: Bayer Imager Connection Example

4.7KΩ VDDIO_VI
4.7KΩ
Tegra 2 VI_MCLK REF_CLK
VI_PCLK PIX_CLK
VI_HSYNC HSYNC
VI_VSYNC VSYNC
VI_D[9:0] PIX_DATA
CAM_I2C_SCL I2C_SCL
CAM_I2C_SDA I2C_SDA
VI_GP5 RESET
1.8,
VDDIO_VI VI_GP4 PWRDOWN
2.8-3.3V

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3.10.4 Parallel VI Design Guidelines

Table 53. Parallel VI Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 125MHz (Input only)
Topology Point to point
Configuration / Device Organization 1 load @ Max Frequency. 2 Loads at reduced frequencies
Max Loading (per imager) 10pf
Reference plane GND or PWR (In case of PWR reference, use decoupling cap (0.01uf)
between PWR and GND for return current)
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 45ps (~0.3”)
Trace Impedance 50Ω, ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length <450ps
Max Trace Length Skew between PCLK & VI_D[9:0] <100ps

Table 54. Parallel VI Signal Connections

Ball Name Type Termination Description
VI_MCLK O VI Master Clock: Connect to Reference clock input on camera(s)
VI_PCLK I VI Pixel Clock: Connect to Pixel CLK input on camera(s)
VI_VSYNC I VI Vertical Sync: Connect to Vsync on camera(s)
VI_HSYNC I VI Horizontal Sync: Connect to Hsync on camera(s)
VI_D[11:0] I VI Pixel Data: Connect to Data pins on camera(s)

Camera I/F Type Camera Pins Tegra Pins

YUV D[7:0] VI_D[9:2]
Bayer 8-bit D[7:0] VI_D[9:2]
GND VI[1:0]
Bayer 10-bit D[9:0] VI_D[9:0]
Bayer 12-bit D[11:2] VI_D[9:0]
GND D[1:0]
VI_GP[6:0] O 100KΩ to VDDIO_VI or GND VI General Purpose Outputs: Used to control various functions. Typically
typically placed on Reset & used for Reset, Imager Powerdown, Autofocus Powerdown, Flash
Powerdown pins to keep these Enable, etc. Connect to appropriate pins.
active when camera not used
CAM_I2C_SCL I/OD 2.2KΩ – 10KΩ depending on Camera I2C Interface: Connect CAM_I2C_SCL/SDA to SCL/SDA on
CAM_I2C_SDA loading to VDDIO_VI camera (s). If to cameras supported, or camera and other I2C device
(Autofocus unit, etc), ensure I2C addresses are different from each other
and from others in the design.

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3.11 SDIO
Tegra 2 has four SD/MMC controllers: SDIO1, SDIO2, SDIO3 and HSMMC (SDIO4). These are all capable of supporting a
variety of devices and protocols including SD/MMC Memories, eSD and MMC devices and SDIO peripherals. SD/eSD/SDIO
can be supported up to 4-bits and at standard or High Speed. MMC/eMMC supports 4 or 8-bit devices Standard or High Speed
devices.

3.11.1 SD/MMC Card Connections

Figure 49 shows an 8-bit MMC & 4-bit SDIO combo socket. Here, the SDIO3 controller on the SDIO domain is used.

Figure 49. Tegra 2 SD/MMC Card Socket Connection Example

VDDIO_SDIO

0.1uf
CMD_PU
DAT_PU
DAT_PU
DAT_PU
DAT_PU
DAT_PU
DAT_PU
DAT_PU
DAT_PU
CMD_PU & DAT_PU: See Termination
Tegra 2 recommendations in SD / MMC Card Socket
Signal Connections table D4
D5
SDIO3_CLK
D2
SDIO3_CMD
D3
CMD
SDIO3_DAT0
GND
SDIO3_DAT1
VDD
SDIO3_DAT2
CLK
SDIO3_DAT3
GND
SDIO3_DAT4
D0
SDIO3_DAT5
D1
SDIO3_DAT6
D6
SDIO3_DAT7
D7
SDIO CD_N
GPIO_PV6
SDIO WP_N
GPIO_PV5
D2
VDDIO_SD
D3
5 1 CMD
PWR 3
2 GND
NC 4
7 6 VDD
GND
CLK
5 1 GND
PWR 3
2 D0
NC 4 0.1uf
7 6 D1
GND

5 1 C_DETECT_N
PWR 3
2.8V – 2 WP_N
VDDIO_SDIO NC 4
3.3V 7
GND 6

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3.11.2 eMMC Device Connections

The SD/MMC interface supports eMMC devices. If the eMMC will be a boot device, it must be connected to one of the HSMMC
(SDIO4) interface positions on the NAND domain. Two locations are supported for eMMC boot:

1. Primary: Shown in Figure 50 below

2. Secondary: CLK – GMI_CLK, CMD – GMI_WAIT, DAT[7:0] – GMI AD[3, 11, 2, 10, 1, 9, 0, 8]

The Primary boot location for eMMC can be selected with Fuses or Straps (see section on Strapping Pins). The Secondary boot
location can only be selected with Fuses. The Secondary boot location is usually only used for the AP20 PoP configuration with
eMMC on the PoP module. Figure 50 shows a typical eMMC external connection.

Figure 50. HSMMC (SDIO4) Connection Example to eMMC Device

VDDIO_NAND

CMD_PU & DAT_PU: See

Termination recommendations in
CMD_PU

DAT_PU

DAT_PU

DAT_PU

DAT_PU

DAT_PU

DAT_PU

DAT_PU

DAT_PU
SD / MMC Card Socket Signal
Connections table
Tegra 2
HSMMC_CLK
GMI_CS5_N
HSMMC_CMD
CLK eMMC
GMI_DPD CMD

HSMMC_DAT7
GMI_AD27 DATA7
HSMMC_DAT6
GMI_AD26 DATA6
HSMMC_DAT5
GMI_AD25 DATA5
HSMMC_DAT4
GMI_AD24 DATA4
HSMMC_DAT3
GMI_AD23 DATA3
HSMMC_DAT2
GMI_AD22 DATA2
HSMMC_DAT1
GMI_AD21 DATA1
1.8V, HSMMC_DAT0
VDDIO_NAND GMI_AD20 DATA0
2.8V-3.3V

3.11.3 SDIO Device Connections

An SDIO controller I/F is often used to interface to medium bandwidth peripherals such as a WiFi controller.

Figure 51. Tegra 2 SDIO WiFi Connection Example

Tegra 2 WiFi
BB SDIO1_CLK SDIO_CLK
SDIO1_CMD SDIO_CMD
SDIO1_DAT0 SDIO_DAT0
SDIO1_DAT1 SDIO_DAT1
SDIO1_DAT2 SDIO_DAT2
SDIO1_DAT3 SDIO_DAT3

GPIO_PVx WLAN_SYS_RST_N
1.8V VDDIO_BB GPIO_PVx WLAN_PWD_N
100KΩ 100KΩ

UART UART3_TXD BT_UART_RX

UART3_RXD BT_UART_TX
UART3_CTS_N BT_UART_RTS
UART3_RTS_N BT_UART_CTS

DAP4_SCLK BT_PCM_CLK
DAP4_FS BT_PCM_SYNC
DAP4_DOUT BT_PCM_IN
DAP4_DIN BT_PCM_OUT

GPIO_PU6 BT_IRQ_N
GPIO_PU0 BT_RST_N
1.8V VDDIO_UART GPIO_PU1 BT_WAKEUP

SYSTEM
1.8V VDDIO_SYSTEM CLK_32K_OUT WLAN_CLK_32K_IN

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3.11.4 SD/MMC Design Guidelines

Table 55. SD / MMC Interface Signal Routing Requirements

Parameter Requirement
Maximum Frequency
SD/SDIO 50MHz
MMC 52MHz
Configuration / Device Organization 1 load
Max Loading 10pf
Reference plane GND or PWR (In case of PWR reference, use decoupling cap (0.01uf)
between PWR and GND for return current)
Breakout Region Impedance 45-50Ω ±15%
Max PCB breakout length 45 ps (~0.3 inches)
Trace Impedance 45-50Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 2.5x dielectric
Max Trace Length < 1100ps
Max Trace Length Skew in/between CLK & CMD/DAT <100ps

Table 56. SD / MMC Card Socket Signal Connections

Ball Name Type Termination Description
SDIO1_CLK O SDIO/MMC Clock: Connect to CLK pin of device or socket
SDIO2_CLK
SDIO3_CLK
HSMMC_CLK
SDIO1_CMD I/O MMC/eMMC SDIO/MMC Command: Connect to CMD pin of device or socket
SDIO2_CMD (1.8V): 10KΩ – 50KΩ to VDDIO_xxx
SDIO3_CMD (2.8V-3.3V): 10KΩ – 100KΩ to VDDIO_xxx
HSMMC_CMD
SD/SDIO
10KΩ – 100KΩ to VDDIO_xxx

Notes:
10KΩ strongly recommended for
MMC/eMMC to ensure CMD reaches
High level during Card ID Mode
xxx is I/O block where I/F resides)
SDIO1_DAT[3:0] I/O MMC/eMMC SDIO/MMC Data: Connect to Data pins of device or socket
SDIO2_DAT[7:0] (1.8V): 10KΩ – 50KΩ to VDDIO_xx
SDIO3_DAT[7:0] (2.8V-3.3V): 10KΩ – 100KΩ to VDDIO_xxx
HSMMC_DAT[7:0]
SD/SDIO
10KΩ – 100KΩ to VDDIO_xxx

Note: xxx is I/O block SDIO I/F resides

SD/MMC Card Detect I SDIO/MMC Card Detect: For an SD/MMC socket, connect GPIO to
Card Detect pin on socket. If card insertion should wake the device
from Deep Sleep mode, make sure to use a Wake capable pin such
as GPIO_PV6 used in the SD/MMC Card Socket Connection
Example
SD/MMC Write I SDIO/MMC Write Protect: For an SD/MMC socket, connect GPIO
Protect to Write Protect pin on socket. The SD/MMC Card Socket
Connection Example uses GPIO_PV5.

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3.12 Audio
Tegra 2 supports PCM, I2S and AC97 digital audio interfaces and includes a flexible audio port switching architecture. The
example below shows a typical connection for a Smartbook design. This includes interfacing to a single Codec using I2S
protocol as well as the I2C for control (PWR_I2C I/F shown in example). A master audio reference clock is provided on the
Tegra 2 DAP_MCLK1 pin and an interrupt on the SPI2_CS0_N pin configured as GPIO_PX3. Other configurations are
possible.

Table 57. DAP Pin Muxing Options

Function Interface Block Typical Usage
DAP1 AUDIO HiFi Audio
DAP2 AUDIO Auxiliary Audio
DAP3 BB Baseband
DAP4 UART Bluetooth Audio
DAP5 NAND FM - Unavailable if eMMC used

Note: A limit of two Tegra 2 device DAPs can be masters at any time.
If the Tegra 2 device is the master, the Master Clock should be provided to the Codec on DAP_MCLK[2:1].

Figure 52. Simple Audio Codec Connection Example and Audio DAP Connections

Tegra 2 (Master) Audio Device

(Slave)
Tegra 2 Audio Codec DAPn_SCLK SCLK
AUDIO DAP4_SCLK BCLK DAPn_FS FS
DAP4_FS LRC DAPn_DOUT DIN
DAP4_DOUT DACDAT DAPn_DIN DOUT
DAP4_DIN ADCDAT

DAP_MCLK1 MCLK
SPI2_CS0_N
1.8V VDDIO_AUDIO INTERRUPT
(GPIO_PX3)
Tegra 2 (Slave) Audio Device
(Master)
SYSTEM
PWR_I2C_SCL SCLK DAPn_SCLK SCLK
1.8V VDDIO_SYSTEM PWR_I2C_SDA SDIN DAPn_FS FS
DAPn_DOUT DIN
DAPn_DIN DOUT

3.12.1 I2S Design Guidelines

Table 58. I2S Interface Signal Routing Requirements

Parameter Requirement
Configuration / Device Organization 1 load
Max Loading 8pf
Topology Point to Point
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Trace Impedance 50Ω ±20%
Trace Spacing Microstrip 2x dielectric
Stripline 2x dielectric
Max Trace Length <3.6ns (~20”)
Max Trace Length Skew between SCLK & DOUT/DIN <250ps

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Table 59. I2S Signal Connections

Ball Name Type Termination Description
DAP1_SCLK I/O DAP Serial Clock: Connect to I2S/PCM CLK pin of audio device.
DAP2_SCLK
DAP3_SCLK
DAP4_SCLK
DAP5_SCLK
DAP1_FS I/O DAP Field Select (Word Select for I2S): Connect to WS (I2S) or FS/SYNC
DAP2_FS (PCM) pin of audio device.
DAP3_FS
DAP4_FS
DAP5_FS
DAP1_DOUT O DAP Data Output: Connect to Data Input pin of audio device.
DAP2_DOUT
DAP3_DOUT
DAP4_DOUT
DAP5_DOUT
DAP1_DIN I DAP Data Input: Connect to Data Output pin of audio device.
DAP2_DIN
DAP3_DIN
DAP4_DIN
DAP5_DIN
DAP_MCLK1 O DAP Master Clock: Connect to MCLK pin of Audio device if reference
DAP_MCLK2 clock required.

3.13 Multi-purpose interfaces

3.13.1 I2C
2
Tegra 2 has four I C controllers: PWR_I2C, I2C1 (GEN1_I2C), I2C2 (GEN2_I2C/DDC) and I2C3 (CAM_I2C). PWR_I2C is only
2
available on the System I/O block and mostly used to control the PMU and other power related devices. The Audio Codec (if I C
control is used) and Temperature Sensor may also use PWR_I2C. The I2C3 (CAM_I2C) controller is brought out on the VI
interface as CAM_I2C_SCL/SDA and is typically used to control a camera device. Controllers I2C1 (GEN1_I2C) and I2C2
(GEN2_I2C/DDC) can be brought out on several interfaces, and are more general purpose. The I2C2 controller is used
primarily to implement the DDC interface if HDMI and/or VGA Out are implemented.
2
Table 60 shows the I C controllers and where they are available on the Tegra 2 pins. The function is shown in the left column
2
and the Location column contains the I/O Blocks where the I C functions can be located. See the appropriate Tegra 2
Datasheet for complete Multiplexing tables. Work closely with your NVIDIA support team when choosing the locations of the
various interfaces to ensure there are no conflicts and the configurations are fully supported by the software.

Table 60. I2C Pin Muxing Options

Function Location (Interface Block)
PWR_I2C SYSTEM
I2C1 (GEN1_I2C) UART, AUDIO
I2C2 (GEN2_I2C) LCD, NAND
I2C3 (CAM_I2C) VI

3.13.1.1 Design Guidelines

2
 Voltage Level shifters are required when interfacing I C devices that are powered at a different voltage than Tegra 2
2
interface where the I C pins reside. Pull-up resistors are required on either side of the level shifters.
2 2
 Care must be taken to ensure I C peripherals on same I C bus connected to Tegra 2 do not have duplicate addresses.
 GEN1_I2C & GEN2_I2C, each are available on two sets of pins. Either controller should only be used from a single set
of pins per design. Multiple devices can be connected to the single set of pins in wired OR fashion.

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Table 61. I2C Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 100KHz (Standard Mode), 400KHz (Fast Mode)
Topology Single ended, bi-directional, multiple masters/slaves
Max Loading (total of all loads) 400pf (Standard Mode), 100pf (Fast Mode)
Reference plane GND or PWR (no requirement for decoupling caps for PWR reference)
Trace Impedance 50 – 60Ω ±15%
Trace Spacing 1x dielectric
Max Trace Length 20 Inches (Standard Mode), 10 Inches (Fast Mode)

Table 62. I2C Signal Connections

Function Name Type Termination Description
PWR_I2C_SCL OD 1.8kΩ to 4.7KΩ to VDDIO_SYS (1.8V) Power I2C Clock & Data. Connect to CLK & Data pins of other devices on
PWR_I2C_SDA this bus
GEN1_I2C_SCL OD 1.8kΩ to 4.7KΩ to VDDIO_UART or Generic I2C 1 Clock & Data. Connect to CLK & Data pins of other devices
GEN1_I2C_SDA VDDIO_AUDIO depending on which I/O on this bus
block the I2C pins are being used (1.8V,
2.8V to 3.3V)
GEN2_I2C_SCL OD 1.8kΩ to 4.7KΩ to VDDIO_NAND Generic I2C 2 Clock & Data. Connect to CLK & Data pins of other devices
GEN2_I2C_SDA (GEN2_I2C) or VDDIO_LCD (DDC) on this bus
DDC_SCL depending on which I/O block the I2C
DDC_SDA pins are being used (1.8V, 2.8V to 3.3V)
CAM_I2C_SCL OD 1.8kΩ to 10KΩ to VDDIO_VI (1.8V, 2.8V Camera I2C Clock & Data. Connect to CLK & Data pins of other devices
CAM_I2C_SDA to 3.3V) on this bus

3.13.2 SPI
Tegra 2 has four SPI controllers. Table 63 shows the SPI controllers and where they are available on the Tegra 2 pins. The
function is shown in the left column & the Location column shows the I/O Blocks where the SPI functions can be located. See
the appropriate Tegra 2 Datasheet for complete Multiplexing tables. Work closely with your NVIDIA support team when
choosing the locations of the various interfaces to ensure there are no conflicts and the configurations are fully supported by the
software.

Table 63. SPI Pin Muxing Options

Function Location (Interface Block)
SPI1 (1 x CS) BB, VI, AUDIO
SPI2 (4 x CS) BB, AUDIO, SDIO
SPI3 (4 x CS) GMI, BB, AUDIO, LCD
SPI4 (2 x CS) GMI, UART, SDIO

3.13.2.1 SPI Interconnection Examples

Tegra 2 supports both Master and Slave operation. The figures below are simple examples of the connections used in both
modes.

Figure 53. SPI Connections

Tegra 2 SPIn_CSx_N CS SPI Slave Tegra 2 SPIn_CSx_N CS SPI Master

Master SPIn_SCK CLK Device Slave SPIn_SCK CLK Device
SPIn_MOSI MOSI SPIn_MOSI MOSI
SPIn_MISO MISO SPIn_MISO MISO

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3.13.2.2 SPI Design Guidelines

Table 64. SPI Interface Signal Routing Requirements

Parameter Requirement
Max Frequency 50MHz
Configuration / Device Organization 4 loads
Max Loading (total of all loads) 15pf
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length 75ps (~0.5 inches)
Trace Impedance 50 – 60Ω ±15%
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length 5 Inches
Max Trace Length Skew between SI/SO to SCLK <30ps

Table 65. SPI Signal Connections

Ball Name Type Termination Description
SPI1_SCK I/O None SPI Clock.: Connect to Peripheral CLK pin(s)
SPI2_SCK
SPI3_SCK
SPI4_SCK
SPI1_MOSI I/O None SPI Master Out / Slave In: Connect to Peripheral MOSI pin(s)
SPI2_MOSI
SPI3_MOSI
SPI4_MOSI
SPI1_MISO I/O None SPI Master In / Slave Out: Connect to Peripheral MISO pin(s)
SPI2_MISO
SPI3_MISO
SPI4_MISO
SPI1_CS0_N I/O None SPI Chip Selects.: Connect one CS_N pin per SPI controller to each
SPI2_CS[3:0]_N Peripheral CS pin on the interface
SPI3_CS[3:0]_N
SPI4_CS[1:0]_N

3.13.3 UART
Tegra 2 has five UARTs. Table 66 shows the UARTs and where they are available on the Tegra 2 pins. The pin function is
shown in the left column and the Location column shows the I/O Blocks where the UART functions can be located. See the
Tegra 2 Datasheet for complete Multiplexing tables. Work closely with your NVIDIA support team when choosing the locations
of the various interfaces to ensure there are no conflicts and the configurations are fully supported by the software.

Table 66. UART Pin Muxing Options

Function Location (Interface Block)
UART1 BB, UART, SDIO
UART2 UART
UART3 UART
UART4 BB, NAND
UART5 NAND

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Interconnection Examples
Figure 54 below shows a simple example of a 4-wire UART on Tegra 2 connecting to a UART on a peripheral. UART1 supports
up to four additional handshake signals, but these are not typically used as part of the UART interface in a Smartbook design.

Figure 54. UART Connection Example

Tegra 2 UART Peripheral UART

UARTn_TXD RXD – Recieve Data
UARTn_RXD TXD – Transmit Data
UARTn_CTS_N RTS_N – Request to Send
UARTn_RTS_N CTS_N – Clear to Send

Table 67. UART Signal Connections

Ball Name Type Termination Description
UART1_TXD O None UART Transmit: Connect to Peripheral RXD pin of device
UART2_
UART3_
UART4_
UART5_
UART1_RXD I None UART Receive: Connect to Peripheral TXD pin of device
UART2_
UART3_
UART4_
UART5_
UART1_CTS_N I None UART Clear to Send: Connect to Peripheral RTS_N pin of device
UART2_
UART3_
UART4_
UART5_
UART1_RTS_N O None UART Request to Send: Connect to Peripheral CTS pin of device
UART2_
UART3_
UART4_
UART5_
UART1_DCD_N I/O None UART Data Carrier Detect
UART1_DSR_N UART Data Set Ready
UART1_DTR_N UART Data Terminal Ready
UART1_RI_N UART Ring Indicator

When these UART1 pins are available (not used for ULPI, SPI2 or HSI on
Baseband interface block), they are typically used as GPIOs for signal
handshaking between Tegra 2 and a Baseband when direct Baseband
interfaces are used.

3.14 Miscellaneous
3.14.1 Keyboard
Tegra 2 keyboard controller eliminates the requirement for de-bounce capacitors and pull up resistors. It can handle any two
button key press ghosting without diodes or any unique key press combination if diodes are present. If only certain keys may be
pressed at once (such as direction keys) these can be placed on a single Row or Column and eliminate the need for diodes. The
Row and Column pins can be configured for a keyboard matrix of up to 16-by-8.

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3.14.2 Thermal Diode (Temperature Sensor)

Nvidia strongly recommends the thermal diode in Tegra 2 be connected to a Thermal Sensor (shown in Figure 55 & Figure 56
below). The Thermal Sensor should be integrated in the system such that hardware will automatically shutdown (Power-off)
without software involvement in a catastrophic situation. A second output from the Thermal Sensor (Alert) is routed to a GPIO
configured as interrupt and is used to provide a warning to the NVidia Resource Management software that the Tegra 2 die
temperature is high and steps need to be taken to lower the temperature to a safe level.
Figure 55: Thermal Diode Connection Example (Using ADT7461A Thermal Sensor)
VDDIO_SYS 3.3V VDDIO ON/OFF
3.3V _LCD 1.8V D (To Power Off)
2.2KΩ

2.2KΩ

10KΩ

10KΩ
G
VDDIO_SYS 3.3V
Tegra 2 S

200Ω
ADT7461AARMZ

100KΩ

100KΩ
DDR THERMD_P 100Ω D+ Temp Sensor
1000pf D- VDD
1.8V VDDIO_DDR THERMD_N 100Ω Level Shifter
THERM TEMP ALERT
VCAA VCCB
ALERT (LCD_DC0/
SYSTEM PWR_I2C_SCL SCL1 SCL2 SCL GPIO_PN6)
PWR_I2C_SDA SDA1 SDA2 SDA GND
0.1uf
1.8V VDDIO_SYS DIR GND
0.1uf 0.1uf

Figure 56: Thermal Diode Connection Example (Using NCT8001 Thermal Sensor)

VDDIO_SYS VDDIO_LCD
ON/OFF
3.3V 1.8V D (To Power Off)
2.2KΩ

2.2KΩ

Tegra 2 S

200Ω
NCT8001

100KΩ

100KΩ
DDR THERMD_P 100Ω D+ Temp Sensor
1000pf VDD
1.8V VDDIO_DDR THERMD_N 100Ω D-
THERM TEMP ALERT
ALERT (LCD_DC0/
SYSTEM PWR_I2C_SCL SCL GPIO_PN6)
PWR_I2C_SDA SDA GND
0.1uf
1.8V VDDIO_SYS

Table 68. Thermal Diode / Temperature Sensor (ADT074xx) Interface Signal Routing Requirements
Parameter Requirement
Configuration / Device Organization 1 loads
Reference plane GND
Breakout Region Impedance Minimum width & spacing
Max PCB breakout length < 0.6 inch, minimum spacing rules
Trace Impedance 90 Ω differential, nominal single-end impedance
Trace Spacing Microstrip 4x dielectric
Stripline 3x dielectric
Max Trace Length 10 inch / >= 4 mil
Max Trace Intra-pair Skew 5 ps (between all discontinuity and overall)

Notes: 1: Keep switch-mode supply as distant as possible

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Table 69. Thermal Diode Signal Connections

Ball Name Type Termination Description
THERMD_P DIFF IN 1000pf cap between signal pair. Thermal Diode: Connect to a thermal sensor (ADT-7461A or NCT1008)
THERMD_N Optional 100 ohm Series resistors for
High Frequency noise filtering
PWR_I2C_SCL OD 2.2 kΩ to VDDIO_SYS (1.8V) if direct I2C Clock & Data: Connect to I2C interface on Thermal Sensor for
connect to Thermal Sensor configuration and to read temperature data.
PWR_I2C_SDA I/OD
2.2KΩ to 10KΩ if Level shifter used The ADT-7461 requires a 3.3V CMOS compatible I2C interface. A
between PWR_I2C and the Sensor. level shifter is required as the PWR_I2C I/F is powered by
VDDIO_SYS (1.8V only).
The NCT1008 is a 3.3V device, but its I2C interface is 1.8V CMOS
level compatible. A level shifter is not required.

3.14.3 JTAG
Implementing JTAG functionality in a system is not required, but may be useful when bringing up a new design. The pull-up and
pull-down resistors shown in Figure 57 are required.

For designs that do implement a JTAG connector for connection to an In-Circuit-Emulator or similar debugging device, note that
the JTAG_TRST_N line is not connected to Tegra 2. This pin instead selects whether the JTAG interface is to be used for
communicating with the Tegra 2 CPU complex, or for Test/Scan purposes. When JTAG_TRST_N is pulled low, the JTAG
interface is enabled for access to the CPU complex. When high, it is in Test/Scan mode. In order to reset the JTAG block, a
reset command is used rather than toggling the JTAG_TRST_N pin.

Figure 57. JTAG Connections

VDDIO_SYS
VDDIO_SYS

Resistor stuffing option to allow JTAG_TRST

to be driven high for Boundary Scan Mode –
10KΩ

10KΩ

Tegra 2 Do not install for normal operation or JTAG

connection to CPUs/AVP/AHB VCC 1 2 VCC
TRST_N 3 4 GND
JTAG_TRST_N 0Ω
TDI 5 6 GND
JTAG_TDI
TMS 7 8 GND
JTAG_TMS
JTAG_TCK TCK 9 10 GND
RTCK 11 12 GND
JTAG_RTCK
TDO 13 14 GND
JTAG_TDO
From System reset – Same as RST 15 16 GND
SYS_RESET_N or equivalent PD 17 18 GND
VDDIO_SYS 1.8V
PD 19 20 GND
100KΩ

100KΩ

100KΩ

100KΩ
10KΩ

Table 70. JTAG Signal Connections

Ball Name Type Termination Description
JTAG_TMS I 10kΩ to VDDIO_SYS (1.8V) JTAG Mode Select: Connect to TMS pin of connector
JTAG_TCK I 100kΩ to GND JTAG Clock: Connect to TCK pin of connector
JTAG_TDO O JTAG Data Out: Connect to TDO pin of connector
JTAG_TDI I 10kΩ to VDDIO_SYS (1.8V) JTAG Data In: Connect to TDI pin of connector
JTAG_RTCK I 10kΩ to GND JTAG Return Clock: Connect to RTCK pin of connector
JTAG_TRST_N I 100kΩ to GND JTAG Reset (Repurposed to select Normal JTAG or Scan mode):
For normal system operation, or when connecting to CPU/AVP/AHB bus, leave
NC or pulldown.nect to TMS pin of connector
To support Scan test mode, place pads for 0Ω resistor or other shorting
mechanism to connect JTAG_TRST_N to TRST_N pin of JTAG connector.

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3.14.4 Strapping Pins

The straps need to be at a valid logic level from the rising edge of SYS_RESET_N and must remain valid for at least 12.5uS.
During this period, the BootROM reads the values of the strap settings.

Figure 58. Power-on Strapping Connections

VDDIO_NAND VDDIO_NAND

ForceRecovery
47KΩ Button

Tegra 2

100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

100KΩ
FORCE_RECOVERY_N
GMI_OE_N 47KΩ
JTAG_ARM1
GMI_CLK
JTAG_ARM0
GMI_ADV_N
RAM_CODE3
GMI_AD07
RAM_CODE2
GMI_AD06 Install either the
RAM_CODE1 pullup or pulldown
GMI_AD05
RAM_CODE0 resistor in location
GMI_AD04
BOOT_SELECT CODE3 indicated by dotted
GMI_AD15 outlines to select
BOOT_SELECT CODE2
GMI_AD14 desired strapping
BOOT_SELECT CODE1
GMI_AD13
BOOT_SELECT CODE0
GMI_AD12
100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

100KΩ

10KΩ

10KΩ

10KΩ

10KΩ
VDDIO_NAND 1.8V-3.3V

Note that stronger 10KΩ pulldown resistors are required for the
Boot Select straps at GMI_AD[15:12] due to active internal pull-ups

Table 71. Power-on Strapping Breakdown

Strap Options Strap Pins Description
USB_RECOVERY GMI_OE_N 0: USB Recovery Mode
1: Boot from secondary device
JTAG_ARM1 GMI_CLK 00: Serial JTAG chain, MPCORE and AVP
JTAG_ARM0 GMI_ADV_N 01: MPCore only JTAG
10: AVP only JTAG
11: Reserved
RAM_CODE[3:0] GMI_AD[7:4] [3:2] Selects secondary boot device configuration set within the BCT
[1:0] Selects SDRAM configuration set within the BCT
BOOT_SELECT_CODE[3:0] GMI_AD[15:12] Software reads value and determines Boot device to be configured and used
0000 = eMMC primary x4
0001 = eMMC primary x8
0010 = eMMC primary x4, high voltage
0011 = NAND
0100 = NAND (42nm NAND)
0101 = mobile LBA NAND
0110 = FlexMuxOneNAND
0111 = eSD x4
1000 = SPI Flash
1001 = SNOR (Muxed, x16)
1010 = SNOR (Muxed, x32)
1011 = SNOR (Non-Muxed, x16)
1100 = MuxOneNAND
1101 = Reserved
1110 = Reserved
1111 = Use fuse data

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3.14.5 EFUSE
Designs must provide a way to supply a 3.3V power source to the VPP_FUSE pin on Tegra 2 to allow fuses to be burned
(unless fuses are burned before assembly). This supply is only required when fuses are burned and should be powered off
during normal operation. VPP_FUSE must be powered OFF when Tegra 2 is in Deep Sleep mode. VPP_KFUSE must be
always low.

The supply for VPP_FUSE can be provided using a test point for external supply, output of on-board LDO controlled by the
Tegra 2 GPIO or output of PMU, controlled by PWR_I2C from Tegra 2. The power source must provide a nominal voltage of
3.3V and be able to supply a minimum of 100mA. When not powered, a 10KΩ pull-down resistor on VPP_FUSE is required. A
0.1uf bypass capacitor is also recommended on this line.

Figure 59. EFUSE Connections

From Dedicated LDO

Tegra 2 or External supply

VPP_FUSE
0.1uf
10KΩ

VPP_KFUSE 10KΩ

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4.0 PAD CONFIGURATION

4.1 POR (Power-on Reset) Default

The POR value indicates the state the pins will be in once the I/O rail is powered and SYS_RESET_N is low and has
propagated through the core & I/O logic. This state is maintained when SYS_RESET_N goes high until software reconfigures
the pad in some way. The pads can be Tri-state, pulled up/down w/internal ~100KΩ resistors or actively driven high/low. The
POR value for each pin is listed in the Tegra Datasheets, in the “Signal List and Multiplexing Functions” section.
 Most pins default to tri-state (z) and many have internal pull-ups (pu) or pull-downs (pd) enabled
 Some pins default to driving high, low or toggling (T)
 The pins used for strapping options on the NAND I/F default to inputs so the state of the pin (pulled up/down externally)
can be determined during power-on (just after SYS_RESET_N goes high)

4.2 SFIO (Special Function I/O) Pad Control

For nearly every digital I/O signal pad, the following controls are available. These controls each affect a group of pins. The
exception is the SFIO/GPIO choice, which is on a pin-by-pin basis. The grouping is shown in the Tegra 2 Datasheets in the
same section as the POR information listed above, under Pin Group (for example, pins DAP4_FS, DAP4_DIN, DAP4_DOUT
and DAP4_SCLK are all in the dap4 Pin Group and if Pull-ups were enabled, all four pins would be affected). The pad control
options are described below and shown in Figure 60.

SFIO Option Pin multiplexor programmed to select Primary, Alternate 1, Alternate 2 or Alternate 3 function
SFIO / GPIO Multiplexor set to select SFIO or GPIO functionality
Tristate Controls the enable of the output buffer in the I/O pad.
Pull-up / Pulldown Selects whether internal Pull-up or Pulldown resistor is active. These are roughly in the range of
75KΩ to 150KΩ

Figure 60. Pad Diagram

Pull-up Control (by Pin Group)
Tri-State Control (by Pin Group) I/F Rail

GPIO Tri-State (Input) / Driven (Output) – (Pin by pin)

~75KΩ-
GPIO
100KΩ

SFIO / GPIO Selection (Pin by pin) 150KΩ

Control GPIO Input/Output Data (Pin by Pin)

SFIO Output
Control in HW
Primary SFIO

Alternate 1 SFIO Pad

Alternate 2 SFIO

~75KΩ-
100KΩ

Alternate 3 SFIO 150KΩ

SFIO Select (by Pin Group) Pull-down Control (by Pin Group)

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4.3 GPIO Capability

Tegra 2 provides GPIO capability on nearly all the standard CMOS (1.8-3.3V) I/Os. The one exception is the DDR interface
which has no GPIO pin options. The GPIO control options are:

Pad mode SFIO / GPIO

Pad Direction Tristate (Input) / Driven (Output)
Output Value (output mode): High / Low
Input Read Value Reflects state of pin (High / Low)
Interrupt options Status, Enable, Edge/Level, Set/Clear, Masks
Tristate, PU/PD Same control available to tristate and/or apply internal Pull-up/down resistors as described in SFIO section.
Since the Tristate control (using Tristate registers) is closer to the actual pin output, this will take
precedence over any other output drive setting (SFIO or GPIO)

See the Tegra 2 Datasheets for the GPIO mapping for each capable pin. This information (like the POR & SFIO above) can be
found in the tables in the “Signal List and Multiplexing Functions” section. In addition, this section contains a table of the Wake
capable pins for Tegra 2. Note that several pins are different between Tegra 250 and AP20, so use the document that matches
the Tegra 2 device to be used.

4.4 General Pin Selection Considerations

In order to avoid unnecessary power consumption, or I/O contention, ensure POR (Power-on Reset) default is compatible with
usage.
 Not pulled up or down when GPIO needs to default to opposite level
 Not driven high/low and connected to peripheral device output or directly to GND or a PWR rail

This is most critical in the period after initial Power-on, before the pins can be re-programmed to the desired functionality with
Pull-up/down, Tristate, Output Enable/Disable, etc. set.

Some of the pad controls, such as Pull-up/down and Tri-State selection are by Pin Group (Except Pull-up/Down control for LCD
Pins as described below), so GPIOs should be chosen such that other pins in the Pin Group are not adversely effected if these
controls need to be changed.

For the LCD pins, the Pull-up/down controls are not simply grouped by Pin Group but are combined together as follows:

Table 72. LCD PU/PD Pin Groups

LCD PU/PD Pin Group Pins in Group
LC LCD_PCLK, LCD_DE, LCD_HSYNC, LCD_VSYNC, LCD_CS1_N, LCD_M1, LCD_DC1, HDMI_INT
LS LCD_PWR1, LCD_PWR2, LCD_SDIN, LCD_SDOUT, LCD_WR_N, LCD_CS0_N, LCD_DC0, LCD_SCK, LCD_PWR0
LCD_D[17:0] LCD_D[17:0]
LCD_D[19:18] LCD_D[19:18]
LCD_D[21:20] LCD_D[21:20]
LCD_D[23:22] LCD_D[23:22]

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4.5 Considerations for Deep Sleep

The CMOS pads have keeper circuits that maintain the output level of the pads during Deep Sleep. If a specific level is needed
during Deep Sleep other than what the pad is already driving, the pad can be configured as GPIO and set to drive out the
desired level. This includes setting the outputs to drive high/low or Tristate.

For most of the Digital CMOS pins that support internal Pull-up/down control, this functionality is disabled during Deep Sleep.
The following pins are exceptions – they retain their internal Pull-up/down capabilities during Deep Sleep:

Table 73. Thermal Diode / Temperature Sensor (ADT074xx) Design Guidelines

Type I/F Partition Comments
Keyboard (KB_ROWx/COLx) SYSTEM
Wake Capable Various Can be found in “Signal List & Multiplexing Functions” in Datasheets
SDIO1 BB (Baseband)
SDIO3 SDIO
Miscellaneous System SYSTEM Pins: PWR_I2C, 32K_CLK_OUT, SYS_CLK_REQ, CPU_PWR_REQ, CLK_32K_IN, JTAG_RTCK,
JTAG_TDO

Note: If other GPIOs require pull-up/down during Deep Sleep, external resistors are required

4.5.1 Input & Unconnected Pins in Deep Sleep

Input Receivers Disabled during Deep Sleep (except Wake pins). Do not require internal or external pull-up/down
resistors
Unused CMOS Pads Left unconnected. For lowest power, they can be set as GPIOs and configured as outputs, but
with Tristate enabled

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5.0 SUBSTRATE TRACE LENGTH

Unless otherwise specified, the substrate trace length should be included for all trace length matching and total trace length
requirements. For multilayer board stack up, where high speed traces are routed in the inner layer, the propagation delays
should be used for all time matching calculations. This is because the propagation delays for the inner layers are different from
that for the outer layers. Typical propagation delay for the inner layers is 180 ps/in and for the outer layers, 150 ps/in.
 Table 74 & Table 75 list Tegra 2 substrate trace propagation delay as well as length (at 150 ps/in).
 For four-layer boards, use substrate trace lengths for trace length matching calculation.
 For stack-ups more than four layers, use substrate trace propagation delays for trace length matching calculation.

5.1 Tegra 250 Substrate Trace Lengths

Table 74. Tegra 250 Package Substrate Trace Length
Ball Name Ball # Delay (ps) Length (mils) Ball Name Ball # Delay (ps) Length (mils)
CAM_I2C_SCL H28 112.79 751.9 HSIC_DATA AC15 140.08 933.9
CAM_I2C_SDA H27 111.55 743.7 HSIC_REXT AE15 49.45 329.7
CLK_32K_IN B14 135.99 906.6 HSIC_STROBE AD15 142.50 950.0
CORE_PWR_REQ G14 71.83 478.9 IC_DN AF14 117.54 783.6
CPU_PWR_REQ C14 88.92 592.8 IC_DP AG14 112.63 750.9
CRT_HSYNC Y22 78.64 524.3 IC_REXT AE13 37.69 251.3
CRT_VSYNC AC23 121.39 809.3 JTAG_TCK B17 59.86 399.1
CSI_CLKAN AH26 137.16 914.4 JTAG_TDI B15 105.22 701.5
CSI_CLKAP AG26 139.59 930.6 JTAG_TDO C15 110.31 735.4
CSI_CLKBN AB20 135.49 903.3 JTAG_TMS C17 87.37 582.5
CSI_CLKBP AC20 139.49 930.0 JTAG_TRST_N A15 116.58 777.2
CSI_D1AN AD20 88.25 588.3 KB_COL0 A6 180.16 1201.1
CSI_D1AP AE20 94.76 631.8 KB_COL1 D6 131.45 876.3
CSI_D1BN AH24 124.94 832.9 KB_COL2 A5 164.64 1097.6
CSI_D1BP AG24 131.41 876.0 KB_COL3 B5 155.05 1033.7
CSI_D2AN AH23 106.11 707.4 KB_COL4 C5 147.86 985.7
CSI_D2AP AG23 113.36 755.8 KB_COL5 B3 157.67 1051.1
DAP_MCLK1 P27 99.29 661.9 KB_COL6 A3 200.73 1338.2
DAP_MCLK2 R24 104.77 698.4 KB_COL7 C3 186.24 1241.6
DAP1_DIN R26 125.33 835.5 KB_ROW0 C12 119.18 794.5
DAP1_DOUT R28 102.46 683.1 KB_ROW1 B12 115.47 769.8
DAP1_FS R27 114.32 762.1 KB_ROW10 D8 166.22 1108.1
DAP1_SCLK P25 89.86 599.0 KB_ROW11 A8 157.71 1051.4
DAP2_DIN T25 85.64 570.9 KB_ROW12 B8 144.32 962.2
DAP2_DOUT T23 83.02 553.5 KB_ROW13 C8 178.24 1188.3
DAP2_FS R22 106.90 712.7 KB_ROW14 C6 127.35 849.0
DAP2_SCLK R23 83.13 554.2 KB_ROW15 B6 164.98 1099.9
DAP3_DIN L2 135.07 900.5 KB_ROW2 A12 143.99 959.9
DAP3_DOUT L1 96.19 641.3 KB_ROW3 D11 129.43 862.9
DAP3_FS J3 99.50 663.4 KB_ROW4 A11 135.48 903.2
DAP3_SCLK M4 120.47 803.1 KB_ROW5 B11 139.65 931.0
DAP4_DIN H1 136.97 913.2 KB_ROW6 C11 122.72 818.1
DAP4_DOUT J4 105.21 701.4 KB_ROW7 C9 162.49 1083.3
DAP4_FS H3 117.70 784.7 KB_ROW8 B9 129.08 860.5
DAP4_SCLK H2 142.86 952.4 KB_ROW9 A9 121.31 808.8
DDC_SCL W23 87.15 581.0 VPP_KFUSE AB14 27.95 186.4
DDC_SDA Y23 123.93 826.2 LCD_CS0_N V24 108.45 723.0
DDR_A0 A20 256.70 1711.4 LCD_CS1_N AC25 111.89 745.9
DDR_A1 C24 239.15 1594.3 LCD_D0 AA26 101.51 676.8
DDR_A10 D23 224.50 1496.6 LCD_D1 AC26 104.39 695.9

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Ball Name Ball # Delay (ps) Length (mils) Ball Name Ball # Delay (ps) Length (mils)
DDR_A11 C20 252.10 1680.7 LCD_D10 AA28 102.58 683.8
DDR_A12 C18 232.00 1546.6 LCD_D11 AA27 137.60 917.4
DDR_A13 E28 247.30 1648.7 LCD_D12 U25 115.29

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5.2 AP20 Substrate Trace Lengths

Table 75. AP20 Package Substrate Trace Length
Ball Name Ball # Delay (ps) Length (mils) Ball Name Ball # Delay (ps) Length (mils)
ACC1_DETECT W5 36.86 245.7 KB_ROW5 P24 79.31 528.7
CAM_I2C_SCL AB26 80.65 537.7 KB_ROW6 U25 73.66 491.1
CAM_I2C_SDA AA23 52.38 349.2 KB_ROW7 K26 96.86 645.7
CLK_32K_IN L25 87.70 584.7 KB_ROW8 J27 78.49 523.3
CLK_32K_OUT L29 115.64 770.9 KB_ROW9 R27 59.41 396.0
CORE_PWR_REQ W27 60.71 404.7 KB_ROW10 N29 96.62 644.2
CPU_PWR_REQ M26 52.05 347.0 LCD_CS0_N AG17 75.61 504.1
CRT_HSYNC AJ5 75.65 504.3 LCD_CS1_N AC13 66.23 441.5
CRT_VSYNC AB18 64.11 427.4 LCD_D0 AG9 63.43 422.8
CSI_CLKAN AC7 86.85 579.0 LCD_D1 AF14 58.25 388.4
CSI_CLKAP AD6 89.78 598.5 LCD_D10 AJ9 74.70 498.0
CSI_CLKBN AG3 112.30 748.7 LCD_D11 AH12 102.11 680.7
CSI_CLKBP AH2 119.19 794.6 LCD_D12 AJ13 98.99 659.9
CSI_D1AN AE5 63.57 423.8 LCD_D13 AD10 82.92 552.8
CSI_D1AP AF4 69.13 460.9 LCD_D14 AF10 103.62 690.8
CSI_D1BN AD4 81.75 545.0 LCD_D15 AA15 61.13 407.6
CSI_D1BP AE3 85.68 571.2 LCD_D16 AC15 60.48 403.2
CSI_D2AN Y8 63.27 421.8 LCD_D17 AE17 54.82 365.5
CSI_D2AP AA7 71.60 477.3 LCD_D18 AG13 77.65 517.7
DAP_MCLK1 AF22 63.47 423.1 LCD_D19 AG7 72.68 484.5
DAP_MCLK2 AL21 89.79 598.6 LCD_D2 AK4 104.46 696.4
DAP1_DIN AJ19 90.47 603.2 LCD_D20 AJ7 68.29 455.3
DAP1_DOUT AJ25 76.26 508.4 LCD_D21 AC11 82.79 551.9
DAP1_FS AL27 81.88 545.9 LCD_D22 AB14 69.75 465.0
DAP1_SCLK AE23 60.17 401.1 LCD_D23 AL5 86.55 577.0
DAP2_DIN AD22 48.83 325.5 LCD_D3 AG15 47.17 314.4
DAP2_DOUT AF24 63.65 424.3 LCD_D4 AL9 112.40 749.3
DAP2_FS AB20 79.99 533.3 LCD_D5 AF18 91.65 611.0
DAP2_SCLK AL23 75.51 503.4 LCD_D6 AH14 66.70 444.7
DAP3_DIN L21 74.87 499.1 LCD_D7 AD18 71.62 477.5
DAP3_DOUT F22 45.78 305.2 LCD_D8 AJ11 80.60 537.3
DAP3_FS K20 61.43 409.6 LCD_D9 AF16 54.00 360.0
DAP3_SCLK J19 96.94 646.3 LCD_DC0 AC17 60.85 405.7
DAP4_DIN G27 90.60 604.0 LCD_DC1 AD12 68.13 454.2
DAP4_DOUT F28 57.52 383.5 LCD_DE AJ17 87.02 580.1
DAP4_FS H26 80.18 534.5 LCD_HSYNC AJ15 91.01 606.7
DAP4_SCLK L23 81.01 540.1 LCD_M1 AE15 71.54 477.0
DDC_SCL AH6 88.76 591.7 LCD_PCLK AF12 53.68 357.9
DDC_SDA AG11 84.55 563.7 LCD_PWR0 AE9 71.91 479.4
DDR_COMP_PD J31 16.95 113.0 LCD_PWR1 AL17 74.84 499.0
DDR_COMP_PU E31 29.56 197.0 LCD_PWR2 AD14 42.15 281.0
DSI_CLKAN AB6 108.17 721.1 LCD_SCK AH8 106.25 708.3
DSI_CLKAP AB8 101.50 676.7 LCD_SDIN AH18 89.67 597.8
DSI_CSI_RDN AC3 16.18 107.8 LCD_SDOUT AA13 78.91 526.1
DSI_CSI_RUP AC5 20.62 137.4 LCD_VSYNC AB12 64.94 432.9
DSI_D1AN Y6 66.87 445.8 LCD_WR_N AE11 87.67 584.4
DSI_D1AP AA5 72.76 485.0 OWR N23 80.41 536.0
DSI_D2AN W9 105.28 701.9 PLL_S_PLL_LF M22 10.81 72.1
DSI_D2AP Y10 110.76 738.4 PWR_I2C_SCL R29 21.84 145.6
GEN1_I2C_SCL F24 84.90 566.0 PWR_I2C_SDA N27 43.68 291.2
GEN1_I2C_SDA F26 81.83 545.5 PWR_INT_N U27 29.22 194.8

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Ball Name Ball # Delay (ps) Length (mils) Ball Name Ball # Delay (ps) Length (mils)
GEN2_I2C_SCL L11 76.58 510.5 SDIO1_CLK F20 73.94 492.9
GEN2_I2C_SDA F10 63.63 424.2 SDIO1_CMD C21 53.96 359.7
GMI_AD0 A11 74.35 495.6 SDIO1_DAT0 C23 84.64 564.2
GMI_AD1 C9 48.67 324.5 SDIO1_DAT1 A21 76.78 511.9
GMI_AD10 A9 76.24 508.3 SDIO1_DAT2 J21 60.01 400.1
GMI_AD11 D6 54.53 363.6 SDIO1_DAT3 G21 83.63 557.5
GMI_AD12 E3 80.05 533.7 SDIO3_CLK J15 72.61 484.0
GMI_AD13 G5 56.80 378.7 SDIO3_CMD F14 55.11 367.4
GMI_AD14 J5 95.86 639.1 SDIO3_DAT0 D14 42.61 284.1
GMI_AD15 J1 88.56 590.4 SDIO3_DAT1 G15 93.84 625.6
GMI_AD16 F6 76.54 510.3 SDIO3_DAT2 E13 63.50 423.4
GMI_AD17 E11 82.35 549.0 SDIO3_DAT3 C13 56.15 374.3
GMI_AD18 G9 53.05 353.7 SDIO3_DAT4 J13 80.76 538.4
GMI_AD19 E9 55.20 368.0 SDIO3_DAT5 E15 62.52 416.8
GMI_AD2 C7 70.32 468.8 SDIO3_DAT6 C15 88.92 592.8
GMI_AD20 G11 62.04 413.6 SDIO3_DAT7 H14 72.91 486.1
GMI_AD21 F8 74.47 496.4 SPDIF_IN AE21 65.76 438.4
GMI_AD22 J11 84.70 564.6 SPDIF_OUT AG21 85.74 571.6
GMI_AD23 K6 88.93 592.9 SPI1_CS0_N AH20 58.43 389.5
GMI_AD24 H8 77.19 514.6 SPI1_MISO AC19 75.74 504.9
GMI_AD25 H10 85.68 571.2 SPI1_MOSI AJ23 65.90 439.3
GMI_AD26 K8 63.74 424.9 SPI1_SCK AF20 47.26 315.1
GMI_AD27 E7 52.03 346.9 SPI2_CS0_N AG25 126.95 846.3
GMI_AD3 C5 89.29 595.2 SPI2_CS1_N AJ21 87.11 580.7
GMI_AD4 D2 81.76 545.1 SPI2_CS2_N AH24 103.83 692.2
GMI_AD5 G3 88.88 592.5 SPI2_MISO AD20 47.70 318.0
GMI_AD6 H4 66.29 441.9 SPI2_MOSI AG23 109.11 727.4
GMI_AD7 J3 72.56 483.7 SPI2_SCK AG19 71.40 476.0
GMI_AD8 D12 64.30 428.6 SYS_CLK_REQ L27 24.53 163.6
GMI_AD9 C11 111.14 740.9 SYS_RESET_N P26 25.55 170.3
GMI_ADV_N N9 108.94 726.3 TEST_MODE_EN Y30 33.70 224.6
GMI_CLK B4 56.25 375.0 THERMD_N G29 17.58 117.2
GMI_CS0 J7 63.28 421.9 THERMD_P H28 15.35 102.3
GMI_CS1 H6 99.72 664.8 UART2_CTS_N D26 67.92 452.8
GMI_CS2 L5 79.49 529.9 UART2_RTS_N C27 87.17 581.1
GMI_CS3 F12 88.13 587.5 UART2_RXD J25 72.53 483.5
GMI_CS4 D8 50.02 333.4 UART2_TXD H22 53.50 356.7
GMI_CS5 L7 88.51 590.0 UART3_CTS_N H24 65.68 437.9
GMI_DPD J9 65.49 436.6 UART3_RTS_N A27 107.36 715.7
GMI_IORDY F4 89.30 595.3 UART3_RXD G23 60.13 400.9
GMI_OE_N L9 116.23 774.9 UART3_TXD C25 110.53 736.9
GMI_RST_N M10 69.65 464.4 ULPI_CLK C19 60.21 401.4
GMI_WAIT E5 78.09 520.6 ULPI_DATA0 H20 75.51 503.4
GMI_WP_N M8 113.12 754.2 ULPI_DATA1 J17 89.68 597.9
GMI_WR_N L3 69.66 464.4 ULPI_DATA2 D20 55.68 371.2
GPIO_PU0 D24 95.44 636.3 ULPI_DATA3 A23 81.50 543.4
GPIO_PU1 E23 85.46 569.7 ULPI_DATA4 K18 85.59 570.6
GPIO_PU2 J23 67.74 451.6 ULPI_DATA5 E21 103.27 688.4
GPIO_PU3 K24 108.71 724.8 ULPI_DATA6 G17 72.38 482.5
GPIO_PU4 B28 70.48 469.9 ULPI_DATA7 H18 87.82 585.4
GPIO_PU5 E25 80.75 538.4 ULPI_DIR E19 63.45 423.0
GPIO_PU6 E27 59.04 393.6 ULPI_NXT F18 86.80 578.7
GPIO_PU7 V26 110.91 739.4 ULPI_STP D18 85.81 572.1
GPIO_PV0 C17 102.69 684.6 USB_REXT Y4 41.94 279.6
GPIO_PV1 F16 105.67 704.4 USB1_DN N3 63.38 422.5

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Ball Name Ball # Delay (ps) Length (mils) Ball Name Ball # Delay (ps) Length (mils)
GPIO_PV2 H16 74.02 493.5 USB1_DP P4 58.33 388.9
GPIO_PV3 E17 92.87 619.1 USB3_DN P8 83.82 558.8
GPIO_PV6 H12 89.59 597.3 USB3_DP P6 76.62 510.8
HDMI_INT_N AD16 90.75 605.0 VDAC_B W11 40.66 271.1
HDMI_RSET AA3 24.75 165.0 VDAC_G U7 42.39 282.6
HDMI_TXCN T6 73.44 489.6 VDAC_R V6 46.67 311.2
HDMI_TXCP U5 70.82 472.2 VDAC_RSET U9 8.99 59.9
HDMI_TXD0N V4 60.64 404.3 VDAC_VREF T8 14.44 96.3
HDMI_TXD0P W3 57.49 383.3 VI_D0 AE29 66.96 446.4
HDMI_TXD1N V8 55.98 373.2 VI_D1 AC31 78.61 524.0
HDMI_TXD1P V10 51.42 342.8 VI_D10 AA27 62.33 415.5
HDMI_TXD2N R7 62.85 419.0 VI_D11 AC29 75.21 501.4
HDMI_TXD2P R9 69.76 465.1 VI_D2 AB24 89.67 597.8
HSIC_DATA R3 126.15 841.0 VI_D3 AC27 92.37 615.8
HSIC_REXT U3 37.05 247.0 VI_D4 Y22 60.44 402.9
HSIC_STROBE R5 116.90 779.3 VI_D5 Y24 63.68 424.6
IC_DN M6 80.66 537.7 VI_D6 Y26 90.75 605.0
IC_DP M4 69.60 464.0 VI_D7 AF28 116.04 773.6
IC_REXT N5 10.83 72.2 VI_D8 AK28 88.28 588.6
JTAG_TCK U29 30.93 206.2 VI_D9 AD28 121.53 810.2
JTAG_TDI V28 65.14 434.2 VI_GP0 AG31 73.10 487.4
JTAG_TDO W29 70.40 469.3 VI_GP3 AC25 92.77 618.4
JTAG_TMS Y28 54.93 366.2 VI_GP4 AA29 110.96 739.7
JTAG_TRST_N W23 82.02 546.8 VI_GP5 AH30 96.64 644.3
KB_COL0 M28 103.87 692.5 VI_GP6 AA25 58.70 391.3
KB_COL1 J29 66.44 443.0 VI_HSYNC AH26 85.67 571.1
KB_COL2 V22 52.29 348.6 VI_MCLK AE27 83.84 559.0
KB_COL3 M24 76.06 507.0 VI_PCLK AG29 74.13 494.2
KB_COL4 V24 48.48 323.2 VI_VSYNC AJ27 87.09 580.6
KB_COL5 U23 58.56 390.4 VREF_CA AG1 23.34 155.6
KB_ROW0 R23 69.18 461.2 VREF_DQ R31 7.74 51.6
KB_ROW1 R25 58.38 389.2 XTAL_IN E29 78.69 524.6
KB_ROW2 T24 101.02 673.5 XTAL_OUT D30 71.87 479.1
KB_ROW3 T26 75.63 504.2 ZQ AC1 14.96 99.7
KB_ROW4 P28 79.74 531.6

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6.0 UNUSED INTERFACE TERMINATIONS

6.1 Unused Muxed Standard CMOS Pad Interfaces

The following interfaces use the I/O pins that support multiple special functions (SFIO) and GPIO capabilities. Any unused
interfaces or portions of these interfaces that are not used can be left unconnected or used for other SFIO functions or as
GPIOs. Any of the power rails associated with these interfaces that are not used for any other purpose can be left as no
connects, or connected to GND.
 NAND
 GMI (General Memory I/F)
 SFLASH (Serial Flash)
 SPI[4:1]
 I2C[3:1]
 DAP[5:1] (Digital Audio Port)
 LCD
 SPDIF (Sony/Philips Digital I/F)
 SDIO[4:1]
 ULPI
 HSI
 UART[5:1]
 TWC (Three Wire Controller)
 VI (Video I/F)

6.2 Unused DSI & CSI Interfaces

Table 76. Unused DSI & CSI Interface Terminations
Ball Name Termination
DSI_CLKAN Leave NC if DSI interface is not used
DSI_CLKAP
DSI_D1AN
DSI_D1AP
DSI_D2AN Leave NC if DSI interface is not used, or only used with single lane
DSI_D2AP
CSI_CLKAN Leave NC if CSI interface A is not used
CSI_CLKAP
CSI_D1AN
CSI_D1AP
CSI_D2AN Leave NC if CSI interface A is not used, or only used with single lane
CSI_D2AP
CSI_CLKBN Leave NC if CSI interface B is not used
CSI_CLKBP
CSI_D1BN
CSI_D1BP
DSI_CSI_RDN Leave NC if neither DSI or CSI interface is used
DSI_CSI_RUP
AVDD_DSI_CSI Leave NC if neither DSI or CSI interface is used

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6.3 Unused JTAG Interface

Table 77. Unused JTAG Interface Terminations
Ball Name Termination
JTAG_TCK 100KΩ to GND
JTAG_TDI 10KΩ to VDDIO_SYS (1.8V)
JTAG_TDO Leave NC
JTAG_TMS 10KΩ to VDDIO_SYS (1.8V)
JTAG_TRST_N 100KΩ to GND
JTAG_RTCK Leave NC

6.4 Unused HDMI Interface

Table 78. Unused HDMI Interface Terminations
Ball Name Termination
HDMI_TXCN Leave NC
HDMI_TXCP
HDMI_TXD[2:0]N Leave NC
HDMI_TXD[2:0]P
HDMI_INT_N Leave NC or use as GPIO_PN7
HDMI_RSET Leave NC
AVDD_HDMI Leave NC
AVDD_HDMI_PLL

6.5 Unused VDAC Interface

Table 79. Unused VDAC Interface Terminations
Ball Name Termination
VDAC_R, VDAC_G, VDAC_B Leave any unused VDAC_x pin NC if not used or all if CRT / TV Out not implemented
CRT_HSYNC Leave NC if CRT I/F not implemented
CRT_VSYNC
VDAC_RSET Leave NC
VDAC_VREF Leave NC
DDC_SCL Leave NC if CRT I/F and HDMI not implemented
DDC_SDA
AVDD_VDAC Leave NC

6.6 Unused USB Interfaces

Table 80. Unused USB Interface Terminations
Ball Name Termination
USB3_DP Leave NC
USB3_DN
ACC1_DETECT Leave NC
ACC3_DETECT (200 Series only)

Note: USB1 related pins are not shown as this interface is required for Recovery Mode in all standard designs

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6.7 Unused HSIC Interface

Table 81. Unused HSIC Interface Terminations
Ball Name Termination
HSIC_DATA Leave NC
HSIC_STROBE Leave NC
HSIC_REXT Leave NC
VDDIO_HSIC Leave NC

6.8 Unused IC-USB Interface

Table 82. Unused IC-USB Interface Terminations
Ball Name Termination
IC_DP Leave NC
IC_DN
IC_REXT Leave NC
AVDD_IC_USB Leave NC

6.9 Unused PCI Express Interface

Table 83. Unused Analog PCIE Interface Signal & Power Rail Terminations
Ball Name Termination
PEX_CLK_OUT[2:1]_N Leave NC
PEX_CLK_OUT[2:1]_P
PEX_L[3:0]_RXN Connect to GND
PEX_L[3:0]_RXP
PEX_L[3:0]_TXN Leave NC
PEX_L[3:0]_TXP
PEX_REFCLKN Connect to GND
PEX_REFCLKP
PEX_TSTCLKN Leave NC
PEX_TSTCLKP
PEX_TERMP Leave NC
AVDD_PEX Connect to GND
AVDD_PEX_PLL
VDD_PEX Connect to GND
AVDD_PLLE Connect to GND
VDDIO_PEX_CLK Connect to GND

Table 84. Unused Digital PCIE Interface Terminations

Ball Name Termination
PEX_CLKREQ[1:0]_N Leave NC unless used as GPIO_PB7/PV6 or other SFIO
PEX_WAKE_N Leave NC unless used as GPIO_PB6 or other SFIO
PEX_RST[1:0]_N Leave NC unless used as GPIO_PD1/PV5 or other SFIO
PEX_PRSNT[1:0]_N Leave NC unless used as GPIO_PD0/PV4 or other SFIO

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7.0 PCB PAD LAYOUT RECOMMENDATIONS

Table 85 Pad Size Recommendations for Tegra 250
Recommended Pad, etc. sizes
15 mil round PAD
19 mil round SOLDERMASK
16 mil square PASTEMASK w/3 mil corner radius

Pad Size Soldermask Pastemask

Pad
15.00 mils 19.00 mils 16.00 mils
Pastemask

16.00 mils Soldermask

Table 86 Pad Size Recommendations for AP20

Recommended Pad, etc. sizes
10 mil round PAD
14 mil round SOLDERMASK
10 mil square PASTEMASK w/3 mil corner radius

Pad Size Soldermask Size Pastemask Size

10.00 Pad
14.00 mils 10.0
mils Pastemask
mils

10.00 mils Soldermask

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