Lecture 3
EO 101
Basic Electrical Engineering
Instructor: Dr. Subhendu Dutta
(sd.eee@iitbhu.ac.in)
• Circuit
• Branch
• Node
• Loop
• Mesh
• Electrical network
• Active element
• Passive element
• Active network
• Passive network
• Bilateral element
• Unilateral element
• Meaning of response
• Liner circuit
• Nonlinear circuit
• Potential energy difference
Kirchoff’s Current Law:
• Algebraic sum of currents entering a node
is zero for every instant of time
Current entering dot is considered as positive
I1 – I2 + I3 – I4 + I5 – I6 = 0
Current leaving dot is considered as positive
- I1 + I2 - I3 + I4 - I5 + I6 = 0
Implication of KCL :
• Forbids series connection of two unequal
current sources
Important points
• Don’t open circuit the terminals of a current
source.
• Don’t connect two current sources (having
unequal current values) in series.
KCL holds for closed curves or surfaces
i 1 (t)
i 2(t)
i1 (t ) i2 (t ) i3 (t ) 0
i (t)
3
Algebraic sum of the currents entering a closed curve or
a surface is zero at every instant of time.
Kirchhoff’s Voltage Law (KVL):
It states that in a closed circuit, the algebraic sum of
all source voltages must be equal to the algebraic
sum of all the voltage drops.
Voltage drop is encountered when current flows in
an element (resistance or load) from the higher-
potential terminal toward the lower potential
terminal.
Voltage rise is encountered when current flows in an
element (voltage source) from lower potential
terminal (or negative terminal of voltage source)
toward the higher potential terminal (or positive
terminal of voltage source).
For any pair of points j and m in a circuit, the
voltage drop vjm from point j to point m is
given by
v jm v j vm
Where vj and vm are voltages of the point j
and m respectively with respect to a common
point named as Reference or Ground.
V1 – IR1 – IR2 – V2 – IR3 – IR4 + V3 – IR5 – V4 = 0,
V1 – V2 + V3 – V4 = IR1 + IR2 + IR3 + IR4 + IR5
Implication of KVL: Two unequal voltage
sources cannot be
connected in parallel
Important points
• Don’t short circuit the terminals of a voltage
source.
• Don’t connect two voltage sources (having
unequal voltage values) directly in parallel.
Circuit Analysis:
Mesh or Loop analysis (application of KVL)
Nodal analysis (application of KCL)
Mesh or Loop analysis (application of KVL)
Step-I: Draw the circuit on a flat surface with no conductor
crossovers.
Step-2: Label the mesh currents carefully in a clockwise
direction.
Step-3: Write the mesh equations by inspecting the circuit
Loop analysis
R1
R2 R3
R4
+ +
V _
1 V2
_
R6
R5
Loop analysis
R1
R2 R3
I2
R4
+ +
V _
1 V2
_
R6
I1 I3
R5
Loop analysis
R1
I
1
R2 I R3
2
R4
+
+
V _
1 V2
_
R6
I
3
R5
Essential notes:
• If possible, convert current source to voltage source.
• Otherwise, define the voltage across the current source
and write the mesh equations as if these source voltages
were known. Augment the set of equations with one
equation for each current source expressing a known mesh
current or difference between two mesh currents.
• Mesh analysis is valid only for circuits that can be drawn in
a two-dimensional plane in such a way that no element
crosses over another.
Loop analysis
Calculate voltage across 4 ohm resistance.
1
Loop 2
4 2
I2
Loop 1
+ + 2
28 V _ 12V
_ Loop 3 8A
I1 I3
1
Mesh equations:
Consider voltage, Vx appears across 8 A current source.
For Loop 1: 28 - 1xI1 - (I1 - I2)x4 - (I1 - I3)x1 - 12 = 0 (1)
For Loop 2: - (I2 - I1)x4 – 2xI2 - (I2 - I3)x2 - 12 = 0 (2)
For Loop 3: 12 – (I3 – I2)x2 – Vx – (I3 – I1)x1 = 0 (3)
I3 = 8 A,
Solve the equations to calculate current flowing through 4
ohm resistance. Later calculate voltage drop from V = IR.
Nodal Analysis : Computation of all node
voltages of a ckt by applying
KCL.
• Assign a node to be the reference node
- arbitrarily ?
• Leave the node at which a voltage
source is directly connected with respect
to the reference node
• Leave also the reference node
G5
_
Va + Vx Vb Vc
G2 G4
+
G1 G3
Is Vd
_
G5
_
Va + Vx Vb Vc
G2 G4
+
G1 G3
Is Vd
_
Reference Node
Reference node is also called ground
G5
_
At node-A Va + Vx Vb Vc
G2 G4
G2 (Va Vb ) G5 (Va Vd ) I s 0
+
G1
GV
1 a
Is
G3
_
Vd
Reference Node
At node-B
G2 (Vb Va ) G3Vb G4 (Vb Vd ) 0
G1 G2 G5 G2 Va I s G5Vd
G2 G2 G3 G4 Vb G4Vd
With floating voltage sources
0.2 S
_
3A
440 V
_+
0.15 S
_
8A
0.05 S 25 A
0.25 S
0.2 S
_
3A
Supernode
Va 440 V
Vb Vc
_+
0.15 S
_
8A
0.05 S 25 A
0.25 S
Reference node
0.2 S
_
3A
Nodal eqns at a Supernode
440 V
8 0.15(Va Vb ) 3 0.2(Va Vc ) 0 Va Vb
_+ Vc
0.15 S
or
_
8A
0.35Va 0.15Vb 0.2Vc 11 (1) 0.05 S
0.25 S
25 A
Reference node
Nodal eqns at supernode
3 0.15(Vb Va ) 0.05Vb 0.25Vc 25 0.2(Vc Va ) 0
or
0.35Va 0.2Vb 0.45Vc 28 (2)
Relation between node voltages within supernode
Vb Vc 440 (3)
0.35Va 0.15Vb 0.2Vc 11 (1)
0.35Va 0.2Vb 0.45Vc 28 (2)
Vb Vc 440 (3)
0.35 0.15 0.2 Va 11
0.35 0.2 0.45 V 28
b
0 V 440
1 1 c
v1 v2
+ iy gmvx iy
G1 G2 vx G4 G6
_ v3
+
vin
_ G5
Ref Node
Node - 1 v1 v2
G1 (V1 Vin ) G2 (V1 V3 ) iy 0 + iy gmvx iy
G1 G2 vx G4 G6
iy G4 (V2 V3 ) _ v3
(G1 G2 )V1 G4V2 (G2 G4 )V3 GV
+
1 in v
_ in G5
Node - 2
Ref Node
G6V2 G4 (V2 V3 ) g mvx 0
gmvx gm (V1 V3 )
gmV1 (G6 G4 )V2 (G4 g m )V3 0
Node - 3
G2 (V3 V1 ) G4 (V3 V2 ) G5V3 iy g mvx 0
G2 (V3 V1 ) G4 (V3 V2 ) G5V3 G4 (V2 V3 ) g m (V1 V3 ) 0
