Lab Workbook Debugging Using Hardware Analyzer

Debugging Using Hardware Analyzer

Introduction
Software and hardware interact with each other in an embedded system. The Xilinx SDK includes both
GNU and the Xilinx Microprocessor Debugger (XMD) as software debugging tools. The hardware
analyzer tool allows for hardware debugging by providing access to the internal signals without
necessarily bringing them out via the package pins using several types of cores. These powerful cores
may reside in the programmable logic (PL) portion of the device and can be configured with several
modes that can monitor signals within the design. Vivado provides capabilities for marking any nets for
debug at different stages of the design flow. In this lab you will be introduced to various debugging cores.
Vivado and SDK include cross-triggering capability which allows software exceptions (breakpoints) to
trigger the logic analyzer, and a hardware condition detected by the logic analyzer can interrupt the
software execution.

Objectives
After completing this lab, you will be able to:
 Add the VIO core in the design
 Use VIO to insert stimulus and monitor the response
 Mark nets to debug so the AXI transactions can be monitored
 Add the ILA core in Vivado
 Perform hardware debugging using the hardware analyzer
 Perform software debugging using the SDK
 Perform cross-triggering between the hardware analyzer and the software debugger

Procedure
This lab is separated into steps that consist of general overview statements providing information on the
subsequent detailed instructions. Follow the (step-by-step) detailed instructions to progress through the lab.

Design Description
In this lab, you will add a custom core that performs a simple 8-bit addition function. The core used was
developed previously using the IP Packager capability of Vivado and is provided as part of the lab source
files. The core has additional ports so that stimuli can be brought in and the response can be monitored.
This way the core can be tested independently without using the PS or software application. The following
block diagram represents the completed design (Figure 1).

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Figure 1. Completed Design

General Flow for this Lab

Step 1: Step 2: Step 3: Step 4:

Open the Add the Add the Create HDL
Vivado Custom IP Hardware Wrapper and
Project Cores Mark Debug

Step 5: Step 6: Step 7:

Generate Generate an Test and
Bitstream Application in Debug in
SDK Hardware

1Open the Project Step 1

1-1. Open Vivado. Open the lab4 project you created in the previous lab or use
the lab4 project from the labsolution directory, and save the project as
lab5. Set Project Settings to point to the IP repository provided in the
<2015_2_zynq_sources>\lab5_zed\math_ip for the ZedBoard or
<2015_2_zynq_sources>\lab5_zybo\math_ip for the Zybo directory.

References to <2015_2_zynq_labs> means c:\xup\sys_design\2015_2_zynq_labs and

<2015_2_zynq_sources> means c:\xup\sys_design\2015_2_zynq_sources directories.

1-1-1. Start the Vivado if necessary and open either the lab4 project you created in the previous lab or
the lab4 project in the labsolution directory using the Open Project link in the Getting Started
page.

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1-1-2. Select File > Save Project As … to open the Save Project As dialog box. Enter lab5 as the
project name. Make sure that the Create Project Subdirectory option is checked, the project
directory path is c:\xup\sys_design\labs\ and click OK.

This will create the lab5 directory and save the project and associated directory with lab5 name.

1-1-3. Click Project Settings in the Flow Navigator pane.

1-1-4. Select IP in the left pane of the Project Settings form.

1-1-5. Click on the Green Plus button, browse to <2015_2_zynq_sources>\lab5_zed\math_ip for the
ZedBoard or <2015_2_zynq_sources>\lab5_zybo\math_ip for the Zybo and click Select.

1-1-6. The math_ip_v1_0 IP will appear the IP in Selected Repository window.

Figure 2. Specify IP Repository for ZedBoard

Figure 2. Specify IP Repository for Zybo

1-1-7. Click OK.

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2Add the Custom IP Step 2

2-1. Open the Block Design and add the custom IP to the system.

2-1-1. Click Open Block Design in the Flow Navigator pane, and select system.bd to open the block
diagram.

2-1-2. Click the Add IP icon and search for math in the catalog.

2-1-3. Double-click the math_ip_v1_0 to add an instance of the core to the design

2-1-4. Click on Run Connection Automation, and select /math_ip_0/S_AXI.

The custom IP consists of a hierarchical design with the lower-level module performing the
addition. The higher-level module includes the two slave registers.

Figure 3. Custom Core’s Main Functional Block

2-1-5. Click OK to connect the IP.

3Add the ILA and VIO Cores Step 3

3-1. Configure the processor to enable the cross-triggering.

3-1-1. Double-click the processing_system7_0 instance to open the PS block diagram.

3-1-2. Select the PS-PL Configuration entry in the Page Navigator.

3-1-3. Click on the PS-PL Cross Trigger interface check box to Enable PL cross trigger signals to PS
and vice-versa.

3-1-4. Expand the PS-PL Cross Trigger interface and select CPU0 DBG REQ for Cross Trigger Input0
under the Input Cross Trigger section, and CPU0 DBG ACK for Cross Trigger Output0 under the
Output Cross Trigger section.

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Figure 4. Enabling cross-triggering in PS configuration wizard

3-1-5. Click OK.

Notice that the TRIGGER_IN_0 and TRIGGER_OUT_0 interfaces are added on the processor
block.

Figure 5. Trigger in and out interfaces added on the processor block

3-2. Add the ILA core in the native mode with the cross trigger capability
enabled and connect it to the LED output port.

3-2-1. Click the Add IP icon and search for ila in the catalog.

3-2-2. Double-click on the ILA (Integrated Logic Analyzer) to add an instance of it. The ila_0 instance
will be added with the AXI slot interface.

The AXI slot interface allows you to monitor any AXI4Lite or AXI4 interface. We will not use it for
this lab.

3-2-3. Double-click on the ila_0 instance and select the Monitor Type as Native.

3-2-4. Click on the check boxes of Trigger Out Port, and Trigger In Port as we want to perform cross-
triggering.

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Figure 6. Selecting cross-triggering and storage settings

3-2-5. Select the Probe Ports tab.

3-2-6. Set the Probe Width of PROBE0 to 8 for the ZedBoard or 4 for the Zybo, and click OK.

3-2-7. Using the drawing tool perform the following connections:

PROBE0 of the ila_0 instance -> LED of the led_ip instance

CLK of the ila_0 instance -> FCLK_CLK0 of the processing_system7_0 instance
TRIG_IN of the ila_0 instance -> TRIGGER_OUT_0 of the processing_system7_0 instance
TRIG_OUT of the ila_0 instance -> TRIGGER_IN_0 of the processing_system7_0 instance

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Figure 7. ILA connections for ZedBoard

Figure 7. ILA connections for Zybo

3-3. Add the VIO core and connect it to the math_ip ports.

3-3-1. Click the Add IP icon and search for vio in the catalog

3-3-2. Double-click on the VIO (Virtual Input/Output) to add an instance of it. The vio_0 instance will
be added.

3-3-3. Double-click on the vio_0 instance to open the configuration form.

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3-3-4. Set the Output Probe Count to 3 and the Input Probe Count to 1 in the General Options tab.

3-3-5. Select the PROBE_IN Ports tab and set the PROBE_IN0 width to 9.

3-3-6. Select the PROBE_OUT Ports tab and set PROBE_OUT0 width to 1, PROBE_OUT1 width to 8,
and PROBE_OUT2 width to 8.

3-3-7. Click OK.

3-3-8. Connect the VIO instance’s ports to the math instance ports as follows:

PROBE_IN -> result

PROBE_OUT0 -> sel
PROBE_OUT1 -> ain_vio
PROBE_OUT2 -> bin_vio

3-3-9. Connect the CLK port of the vio_1 to FCLK_CLK0 port of the processing_system7_0 instance.

3-3-10. The block diagram should look similar to shown below.

Figure 8. VIO instance added and connections made for ZedBoard

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Figure 8. VIO instance added and connections made for Zybo

3-4. Mark Debug the S_AXI connection between the AXI Interconnect and
math_0 instance. Validate the design.

3-4-1. Select the S_AXI connection between the AXI Interconnect and the math_ip_0 instance.

3-4-2. Right-click and select Mark Debug to monitor the AXI4Lite transactions.

3-4-3. Select Tools > Validate Design to run the design rules checker.

Verify that there are no unmapped addresses shown in the Address Editor tab.

3-4-4. Click OK.

4Create Wrapper, Synthesize, and Assign Nets for Debugging Step 4

4-1. Update the output product and regenerate the output product which will
also update the top-level wrapper. Run the synthesis.

4-1-1. In the sources view, right-click on the block diagram file, system.bd, and select Generate
Output Products… to generate the IP-level HDL and associated files. Click Generate.

It will also update the HDL wrapper file, if necessary.

4-1-2. Click OK.

4-1-3. Click Run Synthesis.

4-1-4. Click OK to run the synthesis process (click Save to save the project if prompted).

4-1-5. When the synthesis is completed, select the Open Synthesized Design option and click OK.

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4-2. Assign nets for debugging.

4-2-1. The synthesized design will be opened in the Auxiliary pane and the Debug tab will be opened in
the Console pane.

If the Debug tab is not open then select Window > Debug.

Notice that the nets which can be debugged are grouped into Assigned and Unassigned groups.
The assigned net groups include nets associated with the VIO and ILA cores, whereas the
unassigned nets group includes S_AXI related nets.

Figure 9. The Debug tab

4-2-2. Right-click on the Unassigned Debug Nets and select the Set up Debug… option.

4-2-3. Click Next.

The nets are listed.

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Figure 10. Nets to debug for ZedBoard

Figure 10. Nets to debug for Zybo

4-2-4. Click Find Nets to Add… In the dropdown menu, select MARK_DEBUG and click OK.

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4-2-5. Select system_i/ila_0_TRIG_OUT_ACK, system_i/ila_0_TRIG_OUT_TRIG,

system_i/processing_system7_0_TRIGGER_OUT_0_TRIG,
system_i/processing_system7_0_TRIGGER_OUT_0_ACK from the listed nets and click OK.

4-2-6. Right click on the BRESP and RRESP (which are marked as undefined and driven by GND) and
select Remove Nets.

4-2-7. Click Next twice.

4-2-8. Click Finish.

4-2-9. Select File > Save Constraints and then OK.

5Generate the Bitstream Step 5

5-1. Generate the bitstream.

5-1-1. Click on the Generate Bitstream to run the implementation and bit generation processes.

5-1-2. Click Yes to run the processes.

5-1-3. When the bitstream generation process has completed successfully, a box with three options will
appear. Click Cancel.

6Generate an Application in SDK Step 6

6-1. Lauch the SDK after exporting the implemented design.

6-1-1. If it is not already open, click Open Block Design (under IP Integrator in the Flow Navigator)

6-1-2. Select File > Export > Export Hardware

6-1-3. Make sure that Include Bitstream option is selected and click OK, leaving the target directory set
to local project directory.

6-1-4. Click Yes to overwrite the existing project.

6-1-5. Select File > Launch SDK

6-1-6. Click OK.

Note that system_wrapper.hdf file will be updated in the lab5.sdk directory and
system_wrapper_hw_platform_2 (since system_wrapper_hw_platform_1 folder already was present)
folder will be created when the SDK program opens. The system_wrapper_hw_platform_2 folder will
have the latest design (including led_ip) whereas system_wrapper_hw_platform_1 has the previous
design (lab4).

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6-2. Close the lab4, lab4_bsp and the system_wrapper_hw_platform_1 projects.

Create an empty application project named lab5, and import the provided
lab5.c file either from <2015_2_zynq_sources>\lab5_zed for the ZedBoard
or from <2015_2_zynq_sources>\lab5_zybo for the Zybo.

6-2-1. To tidy up the workspace and save unnecessary building of a project that is not being used, right
click on the lab4, lab4_bsp and the system_wrapper_hw_platform_1 projects from the
previous lab, and click Close Project, as these projects will not be used in this lab. They can be
reopened later if needed.

6-2-2. Select File > New > Application Project.

6-2-3. Enter lab5 as the Project Name, choose system_wrapper_hw_platform_2 as the Target
Hardware since that has the latest hardware, for Board Support Package choose Create New
(lab5_bsp will be displayed).

6-2-4. Click Next, and select Empty Application and click Finish

The lab5 project will be created in the Project Explorer window of the SDK.

6-2-5. Select lab5 > src in the project view, right-click, and select Import.

6-2-6. Expand the General category and double-click on File System.

6-2-7. Browse to either the <2015_2_zynq_sources>\lab5_zed for the ZedBoard or

<2015_2_zynq_sources>\lab5_zybo for the Zybo and click OK..

6-2-8. Select lab5.c and click Finish.

A snippet of part of the source code is shown in the following figure. It shows that we write
operands to the custom core, read the result, and print it. We will use the write transaction as a
trigger condition in the Vivado Hardware Analyzer.

Figure 11. Source Code snippet

6-2-9. Right click and select Toggle Breakpoint in the left border on line where xil_printf(“result=%x\r\
n”,i); appears to set a breakpoint.

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7Test in Hardware Step 7

7-1. Connect and power up the board. Establish serial communications using
the SDK’s Terminal tab. Download the bitstream into the target device.
Start the debug session on lab5 project.

7-1-1. Connect and power up the board.

7-1-2. Select the tab. If it is not visible then select Window > Show view > Terminal.

7-1-3. Click on and select the appropriate COM port.

7-1-4. Select Xilinx Tools > Program FPGA.

7-1-5. Click Program making sure that the appropriate hardware platform is being selected (in this case
it would be system_wrapper_hw_platform_2).

7-1-6. Select the lab5 project in Project Explorer, right-click and select Debug As > Debug
Configurations...

7-1-7. Double-click on the (TCF) Xilinx C/C++ application (System Debugger) entry in the left pane to
create the lab5 Debug configuration. Click on the Enable Cross-Triggering option, and click
Debug.

Enabling Cross-Trigger is important if a breakpoint in SDK needs to trigger ILA. You can do this only
when you create Debug Configurations. It is not done when you execute <app_name> > Debug As
Launch on Hardware (GDB/System Debugger).

Figure 12. Creating debug configuration

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The application will be downloaded, execute ps7_init, and display a dialog box asking to switch
the perspective to the Debug perspective.

7-1-8. Click Yes if prompted to change the perspective. The program execution starts and suspends at
the entry point.

7-1-9. Click on the Step Over ( ) button to execute the first statement.

7-2. Start the hardware session from Vivado.

7-2-1. Switch to Vivado.

7-2-2. Click on Open Hardware Manager from the Program and Debug group of the Flow Navigator
pane to invoke the analyzer.

7-2-3. Click on the Open target link and then click Auto Connect to establish the connection with the
board.

The hardware session will open showing the Debug Probes tab. If the Debug Probes tab isn’t
open, click Window > Debug Probes

Figure 13. Debug probes for ZedBoard

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Figure 13. Debug probes for Zybo

The hardware session status window also opens showing that the FPGA is programmed (we did
it in SDK), there are three cores, and the two ila cores with the idle state.

Figure 14. Hardware session status for ZedBoard

Figure 14. Hardware session status for Zybo

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7-2-4. Select either XC7Z010_1 for ZedBoard or XC7Z010_1 for Zybo, and click on the Run Trigger
Immediate button to see the signals in the waveform window.

Figure 15. Opening the waveform window

Two waveform windows will be updated, one for each ila; one ila (hw_ila_1) is of the instantiated
ILA core and another (hw_ila_2) for the MARK DEBUG method.

7-2-5. Select all the signals under the hw_ila_2 probe in the Debug Probes window, right click, and
select Add Probes to Waveform.

7-3. Setup up for the cross-triggering, where a breakpoint in SDK will trigger the
Vivado logic analyzer.

7-3-1. Select the hw_ila_1 tab (if don’t see it then right-click on the hw_ila_1 in the Debug Probes
window and select Open Hardware Dashboard), and

Set the Trigger Mode Settings as follows:

Set Trigger mode to TRIG_IN_ONLY
Set TRIG_OUT mode to TRIG_IN_ONLY
Under Capture Settings, change the Trigger position in window to 512

Figure 16. Setting hw_ila_1 settings for the SDK triggering ILA

7-3-2. Select the hw_ila_2 tab, and

Set the Trigger Mode Settings as follows:

Under Capture Settings, change the Trigger position in window to 512

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Figure 17. Setting hw_ila_2 settings

7-3-3. Add system_i/processing_system7_0_TRIGGER_OUT_0_TRIG signal from the hw_ila_2

signals group in the Debug Probes window by selecting the signal, right-clicking, and selecting
Add Probes to Basic Trigger Setup.

Figure 18. Adding a probe in the trigger setup for ZedBoard

Figure 18. Adding a probe in the trigger setup for Zybo

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7-3-4. Click on X value of the just added probe and set it to 1.

At this stage the settings of hw_ila_2 would look like as shown in the figure below.

Figure 19. Setting ILA – hw_ila_2 settings for the SDK triggering ILA

7-3-5. Arm both ILAs by selecting either the xc7z020_1 for the ZedBoard or the xc7z010_1 for the Zybo
in the Hardware window and clicking on the Run Trigger button.

Notice that the Idle states changes to Waiting For Trigger for both hw_ila_1 and hw_ila_2.

Figure 20. Arming both ILAs for ZedBoard

Figure 20. Arming both ILAs for Zybo

7-3-6. In SDK, click on the Resume ( ) button to continue executing the program.

Note that the program will execute till the breakpoint and stop. The ILAs also triggered. Zoom in
at the trigger point in the Waveform - hw_ila_2 window and observe various signals. Also
observe that there are activities on the interface after about sample 520 as the processor has
stopped executing.

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Figure 21. The hw_ila_2 waveform for ZedBoard

Figure 21. The hw_ila_2 waveform for Zybo

7-3-7. Look at the left of the trigger position and observe the write address, write data, read address,
and read data signals. You will notice the values corresponding to the statements executed
before the breakpoint was encountered.

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Figure 22. The hw_ila_2 waveform window showing pre-trigger activities and the
relationship between the processor’s trigger out and ILA trigger out for ZedBoard.

Figure 22. The hw_ila_2 waveform window showing pre-trigger activities and the
relationship between the processor’s trigger out and ILA trigger out for Zybo.

7-4. In Vivado, select the VIO Core in the Debug Probes window, add the signals
to the VIO_hw_vio_1 window, and set the vio_0_probe_out0 so math_ip’s
input can be controlled manually through the VIO core. Try entering
various values for the two operands and observe the output on the
math_ip_0_result port in the Console pane.

7-4-1. In the Debug Probes window, select hw_vio_1, right-click and select Add Probes to VIO Window
to add the signals to the VIO - hw_vio_1 window.

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7-4-2. Select vio_0_probe_out0 and change its value to 1 so the math_ip core input can be controlled
via the VIO core.

Figure 23. VIO probes

7-4-3. Click on the Value field of vio_0_probe_out1 and change the value to 55 (in Hex). Similarly, click
on the Value field of vio_0_probe_out2 and change the value to 44 (in Hex). Notice that for a brief
moment a blue-colored up-arrow will appear in the Activity column and the result value changes
to 099 (in Hex).

Figure 24. Input stimuli through the VIO core’s probes

7-4-4. Try a few other inputs and observe the outputs.

7-4-5. Once done, set the vio_0_probe_out0 to 0 to isolate the vio interactions with the math_ip core.

This is not required in this exercise but normally you would do.

7-5. Setup up for the cross-triggering, where a desired condition in ILA stops
the execution of the program in SDK. Setup the hw_ila_1 trigger condition
to either 01010101 (x55) for ZedBoard or 0101 (x5) for Zybo. Set the
hw_ila_1 to BASIC_OR_TRIG_IN as the Trigger mode,
TRIGGER_OR_TRIG_IN as the TRIG_OUT mode. Setup the hw_ila_2 trigger
condition to system_i/ila_0_TRIG_OUT_TRIG being 1. Make sure that the
switches on the ZedBoard are not set at x55 or on the Zybo are not set at
x5. Arm the trigger. Click on the Resume button in the SDK to continue
executing the program. Change the switches and observe that the
hardware core triggers when the preset condition is met.

7-5-1. In the Debug Probes window, select hw_ila_1, right-click and select Add Probes to Basic Trigger
Setup.

7-5-2. Set the trigger condition of the hw_ila_1 to trigger at LED output value equal to 55 (hex) for
ZedBoard or 5 for Zybo.

7-5-3. Change the Trigger mode to BASIC_OR_TRIG_IN and TRIG_OUT mode to

TRIGGER_OR_TRIG_IN.

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Figure 25.Setting up Trigger for hw_ila_1 for ZedBoard

Figure 25.Setting up Trigger for hw_ila_1 for Zybo

7-5-4. Select hw_ila_2, remove the processing_system7_0_TRIGEER_OUT_0_TRIG entry in the Basic

Trigger Setup window by selecting the entry and click on the button.

7-5-5. Right-click on the system_i/ila_0_TRIG_OUT_TRIG under hw_ila_2 in the Debug Probes window
and select Add Probes to Basic Trigger Setup.

7-5-6. Set the trigger condition of the system_i/ila_0_TRIG_OUT_TRIG to 1.

7-5-7. In the SDK window, click on the Resume button.

7-5-8. Arm both ILAs by selecting either xc7z020_1 on the ZedBoard or xc7z010_1 on the Zybo in the
Hardware window and clicking on the Run Trigger button.

Notice that the Idle states changes to Waiting For Trigger for both hw_ila_1 and hw_ila_2.

7-5-9. Change the slide switches and see the corresponding LED turning ON and OFF.

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7-5-10. When the condition (0x55 for ZedBoard or 0x5 for Zybo) is met, the waveform will be displayed in
Vivado Logic Analyzer. In SDK, the program will stop executing at the delay loop after writing to
LED.

Figure 26. ILA_1 waveform window after Trigger for ZedBoard

Figure 26. ILA_1 waveform window after Trigger for Zybo

7-5-11. Observe the activities in the ILA_2 waveform.

Figure 27. ILA_2 waveform showing the relationship between the ILA trigger out and the
processor’s trigger out as well as the interface activities for ZedBoard

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Figure 27. ILA_2 waveform showing the relationship between the ILA trigger out and the
processor’s trigger out as well as the interface activities

7-5-12. Click on the Dissconect button ( ) in the SDK to terminate the execution.

7-5-13. Close the SDK by selecting File > Exit.

7-5-14. In Vivado, close the hardware session by selecting File > Close Hardware Manager. Click OK.

7-5-15. Close Vivado program by selecting File > Exit. Click OK.

7-5-16. Turn OFF the power on the board.

Conclusion
In this lab, you added a custom core with extra ports so you can debug the design using the VIO core.
You enabled the processor block for cross triggering and then instantiated the ILA and the VIO cores into
the design. You used Mark Debug feature of Vivado to debug the AXI transactions on the custom
peripheral. You then opened the hardware session from Vivado, setup various cores, and verified the
design and core functionality, including cross-triggering, using SDK and the hardware analyzer.
.

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